WO2021078280A1 - 一种开关半导体器件及其制备方法、固态移相器 - Google Patents
一种开关半导体器件及其制备方法、固态移相器 Download PDFInfo
- Publication number
- WO2021078280A1 WO2021078280A1 PCT/CN2020/123374 CN2020123374W WO2021078280A1 WO 2021078280 A1 WO2021078280 A1 WO 2021078280A1 CN 2020123374 W CN2020123374 W CN 2020123374W WO 2021078280 A1 WO2021078280 A1 WO 2021078280A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor layer
- layer
- intrinsic
- pin diode
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 394
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 25
- 239000002245 particle Substances 0.000 claims description 18
- 230000008859 change Effects 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000004891 communication Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 230000010354 integration Effects 0.000 abstract description 6
- 238000004088 simulation Methods 0.000 description 33
- 235000012431 wafers Nutrition 0.000 description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 17
- 239000010931 gold Substances 0.000 description 17
- 229910052737 gold Inorganic materials 0.000 description 17
- 238000002360 preparation method Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 16
- 230000000694 effects Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- PMRMTSSYYVAROU-UHFFFAOYSA-N [Ti].[Ni].[Au] Chemical compound [Ti].[Ni].[Au] PMRMTSSYYVAROU-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 229910001258 titanium gold Inorganic materials 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000013400 design of experiment Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- FHUGMWWUMCDXBC-UHFFFAOYSA-N gold platinum titanium Chemical compound [Ti][Pt][Au] FHUGMWWUMCDXBC-UHFFFAOYSA-N 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- UUWCBFKLGFQDME-UHFFFAOYSA-N platinum titanium Chemical compound [Ti].[Pt] UUWCBFKLGFQDME-UHFFFAOYSA-N 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/10—Auxiliary devices for switching or interrupting
- H01P1/15—Auxiliary devices for switching or interrupting by semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
- H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
- H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means
- H01Q3/36—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means with variable phase-shifters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/18—Phase-shifters
- H01P1/185—Phase-shifters using a diode or a gas filled discharge tube
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
- H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
- H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means
- H01Q3/36—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means with variable phase-shifters
- H01Q3/38—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means with variable phase-shifters the phase-shifters being digital
Definitions
- This application relates to the technical field of diodes, and in particular to a switching semiconductor device, a manufacturing method thereof, and a solid-state phase shifter.
- the mainstream PIN diode device form in the industry is currently a discrete device, that is, each device package contains a single PIN die.
- the use of discrete devices to achieve the goal of linearity optimization causes still many difficulties in terms of device cost, size, and component matching.
- the use of PIN diodes in series and parallel connection requires that the discrete diode components have accurate matching parameters.
- the comprehensive error range of its parameters is as high as ⁇ 20%. The effect of improving the linearity of the circuit caused by the configuration will be significantly reduced.
- the application provides a switching semiconductor device, a preparation method thereof, and a solid-state phase shifter, which are used to improve the performance of the switching semiconductor device.
- a switching semiconductor device in a first aspect, includes a first semiconductor layer, an intrinsic layer, and a second semiconductor layer stacked in a sandwich structure; wherein the number of the intrinsic layer is at least two , The at least two intrinsic layers have the same thickness, and the materials used have the same doping concentration coefficient; and when the second semiconductor is provided, the number of the second semiconductor is the same as the number of the intrinsic layer
- the numbers are in one-to-one correspondence, and each second semiconductor layer is stacked on the side of the corresponding intrinsic layer away from the first semiconductor layer; the polarities of the first semiconductor layer and the second semiconductor layer are opposite, as in the first semiconductor layer
- the second semiconductor layer is a P+ semiconductor layer; when the first semiconductor layer is a P+ semiconductor layer, the second semiconductor layer is an N+ semiconductor layer.
- the switching semiconductor device provided in this application includes at least two PIN diodes, such as the above-mentioned first semiconductor layer and each first intrinsic layer and each second semiconductor layer forming a PIN diode; When there are at least two intrinsic layers, there are two corresponding PIN diodes, and any two adjacent PIN diodes are electrically isolated. Based on the switching semiconductor device provided by the present application, there will be no process difference when the intrinsic layer is epitaxially and the first and second semiconductor layers are grown. The self-matching of parameters of different PIN diodes can be realized, and the self-matching of the parameters of two PIN diodes can be realized. Thereby improving linearity. In addition, the structure of the entire switching semiconductor device is compact, the chip packaging area is smaller, and the cost is lower.
- each second semiconductor and its corresponding intrinsic layer is a center-symmetric shape.
- the shape of the second semiconductor layer and the corresponding intrinsic layer are the same, and can be symmetrical shapes such as a circle or a square.
- the number of the PIN diodes is at least two, and the at least two PIN diodes include at least one first PIN diode and at least one second PIN diode.
- the structure of the entire switching semiconductor device is made compact.
- the area ratio of the first surface of each first PIN diode to the second surface of each second PIN diode is 1:N, where N is a rational number greater than or equal to 1, such as Different positive rational numbers such as 1, 2, 3, or 5.
- the first surface is the effective area of the doped particles in the surface of the second semiconductor layer of the first PIN diode away from the first semiconductor layer; the second surface is the second surface of the second PIN diode
- the semiconductor layer is away from the effective area of the doped particles in the surface of the first semiconductor layer. The linearity of the circuit applied to the semiconductor switching device is improved through the set proportional area.
- the switching semiconductor device further includes a first insulating layer embedded in the first semiconductor layer, and the first insulating layer electrically isolates any adjacent PIN diodes.
- the adjacent PIN diodes are electrically isolated by the first insulating layer.
- the material used for the first insulating layer can be silicon dioxide, silicon nitride, or other insulating materials.
- the semiconductor switching device is protected by the provided insulating layer.
- it further includes a second insulating layer, and the second insulating layer is connected to the first insulating layer and wraps the intrinsic layer of any PIN diode and the sidewall of the second semiconductor layer. The safety of semiconductor switching devices is improved.
- a back gold layer is provided on the side of the first semiconductor layer that faces away from the intrinsic layer.
- the back gold layer can be made of titanium nickel gold, titanium platinum, titanium gold, aluminum, or other materials.
- the PIN diode is electrically connected to the outside through the pad.
- the present application provides a solid-state phase shifter
- the solid-state phase shifter includes any one of the above-mentioned switching semiconductor devices on a plurality of branches, and each branch has at least one of the switching semiconductor devices , By turning on or turning off the switching semiconductor device, a phase difference is generated between the radio frequency signals respectively transmitted on the plurality of branches.
- a switching semiconductor device with a geometrically symmetrical figure centered on the two PIN diodes the parameters of the two PIN diodes are self-matched, thereby improving linearity. In turn, the effect of the solid-state phase shifter is improved.
- a massive MIMO (Massive MIMO) antenna array includes the above-mentioned solid-state phase shifter and a plurality of antenna units.
- the solid-state phase shifter is used to change the plurality of antennas.
- the switching semiconductor device in the used solid-state phase shifter adopts a geometrically symmetrical pattern centered on the two PIN diodes to realize the self-matching of the parameters of the two PIN diodes, thereby improving linearity. In turn, the use effect of the antenna array is improved.
- a communication device in a fourth aspect, includes the large-scale multiple-input multiple-output antenna array and a radio frequency signal transceiver, and the large-scale multiple-input multiple output antenna array is used to receive the radio frequency signal transceiver.
- a method for manufacturing a switching semiconductor device includes the following steps:
- first semiconductor layer and each first intrinsic layer and each second semiconductor layer form a PIN diode; any two adjacent PIN diodes are electrically isolated;
- the first semiconductor layer is an N+ semiconductor layer, and the second semiconductor layer is a P+ semiconductor layer; or,
- the first semiconductor layer is a P+ semiconductor layer
- the second semiconductor layer is an N+ semiconductor layer.
- the switching semiconductor device provided by the present application, there will be no process difference when the intrinsic layer is epitaxially, the first and second semiconductor layers are grown, and the self-matching of different PIN diode parameters can be realized, and two PINs can be realized.
- the parameters of the diode are self-matched, thereby improving linearity.
- the structure of the entire switching semiconductor device is compact, the chip packaging area is smaller, and the cost is lower.
- the electrical isolation between any two adjacent PIN diodes specifically includes: filling a gap between any adjacent PIN diodes with a first insulating layer, and the first insulating layer Any adjacent intrinsic layer is electrically isolated; and any adjacent second semiconductor layer is electrically isolated.
- the adjacent PIN diodes are electrically isolated by the provided first insulating layer.
- the shapes of the intrinsic layer and the second semiconductor layer formed by the etching are both centrally symmetrical.
- the first semiconductor layer and each first intrinsic layer and each second semiconductor layer to form a PIN diode specifically includes:
- the number of the PIN diodes is at least two, and the at least two PIN diodes include at least one first PIN diode and at least one second PIN diode.
- the preparation method further includes: the area ratio of the first surface of each first PIN diode to the second surface of each second PIN diode is 1:N, wherein,
- N is a rational number greater than or equal to 1;
- the first surface is the effective area of the doped particles in the surface of the second semiconductor layer of the first PIN diode away from the first semiconductor layer;
- the second surface is the effective area of the doped particles in the surface of the second semiconductor layer of the second PIN diode away from the first semiconductor layer.
- FIG. 1a is a top view of a switching semiconductor device provided by an embodiment of the application.
- Figure 1b is a cross-sectional view at A-A in Figure 1a;
- Figure 2a is a harmonic simulation circuit of a single PIN tube in a forward bias state
- Fig. 2b shows a harmonic simulation circuit of the switching semiconductor device in the forward bias state in the embodiment of the present application
- Figure 3a shows the Harmonic Balance simulation result of a single PIN tube
- Figure 3b shows the change trend of the single PIN tube in the second harmonic with the forward bias current
- FIG. 4a shows the simulation result of the harmonic balance of the switching semiconductor device of the embodiment of the present application
- FIG. 4b shows the change trend of the forward bias current in the second harmonic of the switching semiconductor device of the embodiment of the present application
- Figure 5a shows the harmonic simulation circuit of the single PIN tube in the reverse bias state
- FIG. 5b shows the harmonic simulation circuit of the switching semiconductor device in the reverse bias state in the embodiment of the present application
- Figure 6a shows the simulation result of a single PIN tube in the harmonic balance
- Figure 6b shows the change trend of the single PIN tube in the second harmonic with the reverse bias voltage
- FIG. 7a shows the simulation result of the harmonic balance of the switching semiconductor device of the embodiment of the present application
- Fig. 7b shows the change trend of the reverse bias voltage at the second harmonic of the switching semiconductor device of the embodiment of the present application
- FIG. 8 shows a harmonic simulation circuit of the switching semiconductor device provided by an embodiment of the present application in the case of a mismatch of the forward bias bias current
- Figure 9 shows the change trend of the reverse bias voltage of the switching semiconductor device at the second harmonic
- Figure 10 shows a harmonic simulation circuit that improves linearity through the PIN junction size ratio when the forward bias current is mismatched
- Figures 12a to 12g are flow charts for preparing a switching semiconductor device according to an embodiment of the application.
- Figures 13a to 13f are flow charts for preparing another switching semiconductor device according to an embodiment of the application.
- 15 is a top view of another switching semiconductor device provided by an embodiment of the application.
- FIG. 16 is a top view of another switching semiconductor device provided by an embodiment of the application.
- the switching semiconductor device is used as a control switch and applied to a solid-state phase shifter for signal transmission and reception. in.
- FIG. 1a shows a top view of a switching semiconductor device provided by an embodiment of the present application
- FIG. 1b shows a cross-sectional view at A-A in FIG. 1a.
- the switching semiconductor device is arranged in a stacked structure, and two electrically isolated PIN diodes are formed.
- the two PIN diodes are named the first PIN diode 100 and the second PIN diode 200, respectively.
- the first PIN diode 100 and the second PIN diode 200 are stacked in a sandwich structure;
- the first PIN diode 100 includes: a stacked first semiconductor layer 10, an intrinsic layer, and a second semiconductor layer a102 .
- the intrinsic layer of the first PIN diode 100 is named the first intrinsic layer 103.
- the first intrinsic layer 103 is located between the first semiconductor layer 10 and the second semiconductor layer a102.
- the first semiconductor layer 10 and the second semiconductor layer a102 are two semiconductor layers with opposite polarities.
- the first semiconductor layer 10 is a P+ semiconductor layer
- the second semiconductor layer a102 is an N+ semiconductor layer
- the first semiconductor layer 10 It is an N+ semiconductor layer
- the second semiconductor layer a102 is a P+ semiconductor layer.
- the second PIN diode 200 is arranged side by side with the first PIN diode 100.
- the second PIN diode 200 includes: a first semiconductor layer 10, an intrinsic layer, and a second semiconductor layer b202 stacked in a sandwich structure, and the intrinsic The layer is located between the first semiconductor layer 10 and the second semiconductor layer b202.
- the intrinsic layer of the second PIN diode 200 is named the second intrinsic layer 203.
- the second semiconductor layer b202 and the second semiconductor layer a102 have the same polarity and are opposite to the polarity of the first semiconductor layer 10, for example, the first semiconductor layer 10 is a P+ semiconductor layer ,
- the second semiconductor layer b202 is an N+ semiconductor layer; or, when the first semiconductor layer 10 is an N+ semiconductor layer, the second semiconductor layer b202 is a P+ semiconductor layer.
- FIG. 1b the second PIN diode 200 and the first PIN diode 100 share the same first semiconductor layer 10, but the first intrinsic layer 103 and the second intrinsic layer 203 are electrically isolated, and the second semiconductor layer a102 It is electrically isolated from the second semiconductor layer b202.
- the first intrinsic layer 103 and the second intrinsic layer 203 are located in the same layer and are disposed on the same surface of the first semiconductor layer 10, and the second semiconductor layer b202 and the second semiconductor layer a102 are located in the same layer. Floor.
- the first intrinsic layer 103 and the second intrinsic layer 203 have the same thickness, and the materials used have the same doping concentration coefficient.
- the materials used in the first intrinsic layer 103 and the second intrinsic layer 203 have the same doping concentration, and the doping concentration varies with the thickness of the intrinsic layer. Variety.
- the shape of the second semiconductor layer a102 and the corresponding first intrinsic layer 103 of the first PIN diode 100 is a symmetrical circle
- the second semiconductor layer b202 of the second PIN diode 200 and the corresponding The shape of the second intrinsic layer 203 is a symmetrical circle.
- FIG. 1a is only an example.
- the intrinsic layer 203 is not limited to a circle, and can also be other geometric shapes with a center symmetry, such as a square, a regular polygon, or other shapes with a center symmetry.
- the shapes of the second semiconductor layer a102 and the corresponding first intrinsic layer 103 of the first PIN diode 100 are centrosymmetric, and the shapes and sizes of the second semiconductor layer a102 and the first intrinsic layer 103 are the same;
- the shapes of the second semiconductor layer b202 and the corresponding second intrinsic layer 203 of the two PIN diodes 200 are also centrally symmetrical, and the shape and size of the second semiconductor layer b202 and the second intrinsic layer 203 may be the same.
- the second semiconductor layer a102 and the second semiconductor layer b202 are illustrated in FIG. 1a as being circular, the embodiment of the present application does not limit the shape of the second semiconductor layer a102 and the second semiconductor layer b202 to be the same.
- the second semiconductor layer a102 is circular and the second semiconductor layer b202 is square; or the second semiconductor layer a102 is square and the second semiconductor layer b202 is a regular pentagon.
- the shapes of the second semiconductor layer a102 and the corresponding first intrinsic layer 103 of the first PIN diode 100 are centrosymmetric shapes, and the shapes of the second semiconductor layer b202 and the corresponding second intrinsic layer 203 of the second PIN diode 200 When the shape is also center symmetric, the correspondingly formed first PIN diode 100 and second PIN diode 200 have a center symmetric structure, respectively.
- the first intrinsic layer 103 and the second intrinsic layer 203 are specifically arranged, the first intrinsic layer 103 and the second intrinsic layer 203 are located on the same surface of the first semiconductor layer 10. Both intrinsic layers are from the same wafer, thereby eliminating the impact of wafer batch differences.
- the reasons for the differences in the parameters of the wafers used in the prior art include differences between batches and differences between different wafers in the same batch.
- Traditional methods cannot guarantee that the chips come from the same wafer in the same batch.
- Even if complex and expensive precise material control is used to select dies on the same wafer, it cannot overcome the differences between dies at different locations on the same wafer, so circuit mismatch and performance degradation cannot be avoided.
- the wafers in the first PIN diode 100 and the second PIN diode 200 side by side are from the same wafer. Therefore, the difference between wafer batches and the difference between wafers can be reduced.
- the generated parameter difference is offset, so that the parameters of the first PIN diode 100 and the second PIN diode 200 are kept consistent, and a match is automatically formed, thereby solving the problem of the first PIN diode 100 and the second PIN diode 200 when they are matched.
- the area ratio corresponds to the area ratio of the first surface and the second surface, where the first surface is the surface of the second semiconductor layer a102 of the first PIN diode 100 that faces away from the first semiconductor layer 10
- the effective area of the doped particles among them, when the second semiconductor layer a102 is an N+ semiconductor layer, the doped particles are N+ particles, and when the second semiconductor layer a102 is a P+ semiconductor layer, the doped examples are P+ particles .
- the second surface is the effective area of the doped particles in the surface of the second semiconductor layer b202 of the second PIN diode 200 away from the first semiconductor layer 10; wherein, when the second semiconductor layer b202 is an N+ semiconductor layer, the doped particles It is N+ particles. When the second semiconductor layer b202 is a P+ semiconductor layer, the doped example is P+ particles.
- the ratio of the first surface to the second surface is 1:N, where N is a rational number greater than or equal to 1, such as different positive rational numbers such as 1, 2, 3, and 5. In order to facilitate understanding, the following simulation processing is performed on the case of the first PIN diode 100 and the second PIN diode 200 with different area ratios.
- FIG. 3a shows the simulation result of the single PIN tube in the harmonic balance
- Fig. 3b shows the single PIN tube in the second harmonic with the forward bias
- FIG. 4a shows the harmonic balance simulation result of the switching semiconductor device of the embodiment of the present application
- FIG. 4b shows the change trend of the second harmonic with the forward bias current of the switching semiconductor device of the embodiment of the present application.
- Figure 5a shows the harmonic simulation circuit of the single PIN tube in the reverse bias state
- Figure 5b shows the switch in the embodiment of the application.
- Harmonic simulation circuit of semiconductor device in reverse bias state After the simulation, the simulation structure of Fig. 6a ⁇ Fig. 7b is obtained, among which, Fig. 6a shows the simulation result of the single PIN tube in the harmonic balance, and Fig. 6b shows the reverse bias of the single PIN tube in the second harmonic. Trend of voltage change.
- FIG. 7a shows the simulation result of the harmonic balance of the switching semiconductor device of the embodiment of the present application
- FIG. 7b shows the change trend of the second harmonic with the reverse bias voltage of the switching semiconductor device of the embodiment of the present application. Comparing Fig. 6a and Fig. 7a, and Fig. 6b and Fig. 7b, it can be seen from the simulation results that the switching semiconductor device provided by the embodiment of this application is 170-200dB lower than the even harmonics of the single PIN tube, especially the second harmonic. To the software floating-point calculation of the rounding error, the result means that the even harmonic products have been perfectly canceled.
- the switching semiconductor device provided in the embodiments of the application achieves a 20dB improvement with the PIN tube in the prior art, and achieves non-linearity. The essence of offset is improved.
- the above-mentioned specific ratio of the area of the first PIN diode 100 and the second PIN diode 200 can be precisely controlled during the manufacturing process. This ratio can be used as a free factor to adjust the nonlinear compensation coefficient of the device, thereby increasing the overall switching semiconductor device Flexibility in design.
- the determination of the N value depends on the application scenario of the switching semiconductor device. Specifically, the value of N is finally determined according to the experimental data of Design of Experiments (DoE, Design of Experiments). By setting an appropriate value of N, it is possible to obtain better linearity even when the parameters of other parts of the circuit are mismatched.
- FIG. 8 shows a harmonic simulation circuit of the switching semiconductor device provided by an embodiment of the present application in the case of a mismatch of the forward bias bias current.
- the reference value of the PIN junction bias current is set to 10 mA, but There are two PIN diodes (the first PIN diode 100 and the second PIN diode 200, and the ratio of the first PIN diode 100 to the second PIN diode 200 is 1:1) the ratio difference (Iratio) of the bias current, the simulation scan
- the range of is set to 1.0 ⁇ 2.0 (the value of Iratio).
- Figure 9 shows the change trend of the reverse bias voltage in the second harmonic of the switching semiconductor device. In the simulation, when the Iratio deviates from 1.0, that is, when there is a bias current mismatch, the linearity improvement benefit will quickly decrease.
- the second-order harmonic is -54dBm, although it is still nearly 20dB better than the -45dB of a 10mA bias single PIN tube (that is, a traditional form of single PIN tube).
- Fig. 10 shows a harmonic simulation circuit that improves the linearity through the PIN junction size ratio in the case of the forward bias current mismatch.
- the second-order harmonic variation trend of scanning the area ratio of the first PIN diode 100 and the second PIN diode 200 is simulated.
- the optimal second-order harmonic is -dBm, which is about 5dB better than the reference value -54dBm (the area ratio is equal to 1.0).
- the distance between the first PIN diode 100 and the second PIN diode 200 is 0.1-5000 ⁇ m to ensure that the distance between the first PIN diode 100 and the second PIN diode 200
- the switching semiconductor device provided by the embodiment of the present application further includes a first insulating layer 40 embedded in the first semiconductor layer 10.
- An insulating layer 40 electrically isolates any adjacent PIN diodes.
- the first insulating layer 40 is partially inserted into the first semiconductor layer 10, and the depth of insertion is h.
- the size of h can be 0-1000 ⁇ m, such as 0 ⁇ m, 10 ⁇ m, 100 ⁇ m, 500 ⁇ m, 800 ⁇ m, 1000 ⁇ m. Equal depths to ensure the isolation between the first intrinsic layer 103 and the second intrinsic layer 203.
- the width d of the first insulating layer 40 is between 0.1-5000 ⁇ m, such as 0.1 ⁇ m, 10 ⁇ m, 50 ⁇ m, 100 ⁇ m, 50 ⁇ m, 1000 ⁇ m, 3000 ⁇ m, 5000 ⁇ m, and other different widths.
- the first insulating layer 40 is an optional component, which can be selected or not provided.
- the switching semiconductor device provided by the embodiment of the present application is further provided with a second insulating layer 30, and the second insulating layer 30 is connected to the first insulating layer 40 and envelops any PIN diode.
- the first insulating layer 40 and the second insulating layer 30 may be an integral structure or a separate structure.
- the first insulating layer 40 and the second insulating layer 30 are collectively referred to as an insulating layer.
- the material of the insulating layer can be made of different materials, such as silicon dioxide, or silicon dioxide and silicon nitride.
- a window may be opened on the insulating layer.
- the area ratio of the insulating layer corresponding to the opening of the first PIN diode 100 and the second PIN diode 200 is also different.
- the side of the second semiconductor layer a102 away from the first intrinsic layer 103 is provided with a first pad 101 and a second semiconductor layer.
- a second pad 201 is provided on the side of b202 that is away from the second one, and a back gold layer 20 is provided on the side of the first semiconductor layer 10 that is away from the first intrinsic layer 103 and the second intrinsic layer 203; the first pad 101
- the second pad 201 and the back gold layer 20 are led out as electrodes, so that the switching semiconductor device forms a common cathode or common anode three-port die, and then undergoes a packaging process to finally form an overall three-port component product form.
- the first pad 101, the second pad 201 and the back gold layer 20 can be made of titanium nickel gold, titanium platinum gold, titanium gold, aluminum materials, or other conductive materials.
- packaging forms can also be used, such as surface mount type (such as QFN, DFN), flip chip type and beam lead type, etc.
- the packaging form can realize the packaging of the first PIN diode 100 and the second PIN diode 200 and the electrical connection with the outside.
- the switching semiconductor device provided by the embodiments of the present application is used to form a three-port device structure.
- the switching semiconductor device provided by the embodiments of the present application is used to form a three-port device structure.
- the switching semiconductor device provided by the embodiments of the present application is used to form a three-port device structure.
- the switching semiconductor device provided by the embodiments of the present application is used to form a three-port device structure.
- the side-by-side arrangement of the first PIN diode 100 and the second PIN diode 200 The matching effect of the first PIN diode 100 and the second PIN diode 200 is improved.
- this overall integration method is adopted, compared with the discrete or multi-die components in the prior art, the integration is improved. Degree and reduce costs.
- the embodiment of the present application also provides a method for manufacturing a switching semiconductor device.
- the preparation method includes the following steps:
- the first semiconductor layer and the intrinsic layer are prepared, and the first semiconductor layer is laminated with the intrinsic layer; in specific preparation, the first semiconductor layer can be prepared first, and then the intrinsic layer is prepared on the surface of the first semiconductor layer ; It is also possible to prepare the intrinsic layer, and then prepare the first semiconductor layer on the surface of the intrinsic layer;
- the second semiconductor layer and the intrinsic layer are etched to form at least two intrinsic layers and a second semiconductor layer corresponding to each intrinsic layer; wherein, at least two intrinsic layers have the same thickness, and the materials used are The same doping concentration coefficient;
- first semiconductor layer and each first intrinsic layer and each second semiconductor layer form a PIN diode; any two adjacent PIN diodes are electrically isolated;
- the first semiconductor layer is an N+ semiconductor layer, and the second semiconductor layer is a P+ semiconductor layer; or,
- the first semiconductor layer is a P+ semiconductor layer
- the second semiconductor layer is an N+ semiconductor layer.
- the correspondingly formed switching semiconductor devices are also different, which will be described below.
- the first semiconductor is an N+ semiconductor as an example.
- Step 1 Prepare the first semiconductor layer 10; wherein, the first semiconductor layer 10 is an N+ semiconductor layer;
- an N-type wafer is used for the preparation of the substrate.
- An N+ doped layer is formed by doping phosphorus elements, thereby obtaining the first semiconductor layer 10.
- Step 2 Prepare the intrinsic layer 50
- a low-doped single crystal N-type intrinsic layer 50 is formed by chemical vapor deposition, diffusion or molecular beam epitaxy, and the thickness of the intrinsic layer 50 needs to be precisely controlled.
- Step 3 Form a second semiconductor layer 60 on the first intrinsic layer 103;
- the intrinsic layer 50 is formed by chemical vapor deposition at a high temperature to form a layer of polysilicon, and then at a high temperature, a B 2 O 3 material is used to diffuse boron into the wafer to form a P+ doped layer.
- the second semiconductor layer 60 is formed by diffusion or epitaxial growth on the intrinsic layer 50. It can be seen from the above description that the second semiconductor layer 60 and the first semiconductor layer 10 are opposite semiconductor layers, and the process realization method may be, but not limited to, diffusion and epitaxial growth.
- Step 4 Use an etching method to open windows in the intrinsic layer and the second semiconductor layer
- an etching method is used to open a window 70 in the intrinsic layer and the second semiconductor layer, and the window needs to be slightly over-etched on the first semiconductor layer 10, and over-etched on the first semiconductor layer 10. It can be 0-1000 microns, and the etching method can be dry etching or wet etching.
- the intrinsic layer is divided into a first intrinsic layer 103 and a second intrinsic layer 203 by the window, and the second semiconductor layer is divided into a second semiconductor layer a102 and a second semiconductor layer b202 by the window.
- the first semiconductor layer 10, the first intrinsic layer 103 and the second semiconductor layer a102 constitute a first PIN diode; the first semiconductor layer 10, the second intrinsic layer 203 and the second semiconductor layer b202 constitute a second PIN diode diode.
- the etched window should ensure the electrical isolation between the first PIN diode and the second PIN diode.
- Step 5 Deposit an insulating layer on the window
- the lift-off method can be used to deposit silicon dioxide or silicon nitride at the window, or the insulating layer can be formed by brushing with glass powder.
- the insulating layer includes a first insulating layer 40 for separating the first PIN diode 100 and the second PIN diode 200 and a second insulating layer 30 for protecting the exposed sidewalls of the first PIN diode 100 and the second PIN diode 200.
- step 5 is an optional step.
- an insulating layer is not necessary.
- Step 6 Depositing pads on the window above the second semiconductor layer
- the bonding pads are deposited by evaporation, magnetron sputtering, or electroplating, and annealed at a high temperature in a mixed gas of nitrogen and hydrogen.
- the pad corresponding to the first PIN diode is the first pad 101
- the pad corresponding to the second PIN diode is the second pad 201.
- Step 7 Depositing back gold on the bottom of the first semiconductor layer 10;
- a titanium nickel gold or titanium gold or aluminum or other metal layer is deposited on the bottom of the first semiconductor layer 10 (the side away from the intrinsic layer) to form a back gold layer 20
- the thickness can be different.
- the thickness of titanium is 0-500 nanometers
- the thickness of nickel is 0-100 nanometers
- the thickness of gold is 0-500 micrometers.
- the prepared switching semiconductor device adopts a geometrically symmetrical pattern centered on the two PIN diodes to achieve self-matching of the parameters of the two PIN diodes, thereby improving linearity.
- the entire switching semiconductor device has a compact structure, a smaller chip packaging area and a lower cost.
- the intrinsic layer of the PIN diode of the present application is epitaxial, there will be no process difference when the first and second semiconductor layers are grown, and the two PIN diode parameters are self-matched, thereby improving linearity.
- the effect of the solid-state phase shifter is improved.
- it is slightly more complicated and has certain requirements for process equipment parameters.
- the process scheme of the PIN diode of the present application is simpler, compatible with the production process of a single PIN tube, lower production cost, and can also achieve the purpose of improving the linearity of the PIN diode and the solid-state phase shifter.
- an embodiment of the present application also provides another semiconductor manufacturing method, which specifically includes:
- the first semiconductor being an N+ semiconductor as an example.
- Step 1 Prepare the first semiconductor layer 10; wherein, the first semiconductor layer 10 is an N+ semiconductor layer;
- an N-type wafer is used for the preparation of the substrate.
- An N+ doped layer is formed by doping phosphorus elements, thereby obtaining the first semiconductor layer 10.
- Step 2 Deposit an insulating layer on the surface of the first semiconductor layer 10; open a reserved PIN tube window on the insulating layer;
- a thicker silicon dioxide insulating layer is formed by the thermal chemical vapor deposition method. Using a mask and photoresist, in the area where the intrinsic layer needs to be formed, the silicon dioxide is selectively removed to open the window.
- the insulating layer is divided into a first insulating layer 40 for isolating the first PIN diode and the second PIN diode.
- a second insulating layer 30 for protecting the exposed sidewalls of the first PIN diode and the second PIN diode.
- Step 3 Prepare the intrinsic layer in the window
- a layer of low-doped single crystal is formed in the two windows of the insulating layer by chemical vapor deposition, diffusion, or molecular beam epitaxy.
- the intrinsic layer of the N-type layer The thickness of the intrinsic layer needs to be precisely controlled.
- the intrinsic layer corresponding to the first PIN diode is the first intrinsic layer 103
- the intrinsic layer corresponding to the second PIN diode is the second intrinsic layer 203.
- Step 4 forming a second semiconductor layer on the intrinsic layer
- the intrinsic layer (the first intrinsic layer 103 and the second intrinsic layer 203) is formed by chemical vapor deposition at a high temperature to form a layer of polysilicon, and then used at a high temperature
- the B2O3 material diffuses boron into the wafer to form a P+ doped layer.
- the second semiconductor layer is formed by diffusion or epitaxial growth on the intrinsic layer (the first intrinsic layer 103 and the second intrinsic layer 203).
- the second semiconductor layer and the first semiconductor layer 10 are opposite semiconductor layers, and the process realization method can be but not limited to diffusion and epitaxial growth; wherein, the second semiconductor layer corresponding to the first PIN diode is the second semiconductor layer a102 , The semiconductor layer corresponding to the second PIN diode is the second semiconductor layer b202.
- Step 5 Depositing a pad on the window above the second semiconductor layer
- the first pad 101 and the second pad 201 are deposited by evaporation, magnetron sputtering or electroplating, and annealed at a high temperature in a mixed gas of nitrogen and hydrogen.
- the first pad 101 is deposited on the side of the second semiconductor layer a102 away from the first intrinsic layer 103
- the second pad 201 is deposited on the side of the second semiconductor layer b202 away from the second intrinsic layer 203.
- Step 6 Depositing back gold on the bottom of the first semiconductor layer 10;
- a titanium nickel gold or titanium gold or aluminum or other metal layer is deposited on the bottom of the first semiconductor layer 10 (the side away from the intrinsic layer) to form a back gold layer 20
- the thickness can be different.
- the thickness of titanium is 0-500 nanometers
- the thickness of nickel is 0-100 nanometers
- the thickness of gold is 0-500 micrometers.
- the first semiconductor being an N+ semiconductor as an example.
- Step 1 Prepare the first semiconductor layer 10; wherein, the first semiconductor layer 10 is an N+ semiconductor layer;
- an N-type wafer is used for the preparation of the substrate.
- An N+ doped layer is formed by doping phosphorus elements, thereby obtaining the first semiconductor layer 10.
- Step 2 Deposit an intrinsic layer 50 on the surface of the first semiconductor layer 10;
- a low-doped single crystal N-type intrinsic layer 50 is formed in the insulating layer window by chemical vapor deposition, diffusion, or molecular beam epitaxy.
- the thickness of the intrinsic layer 50 needs to be precisely controlled.
- Step 3 Form a second semiconductor layer 60 on the intrinsic layer 50;
- the intrinsic layer 50 forms a layer of polysilicon by chemical vapor deposition at a high temperature, and then uses B 2 O 3 to diffuse boron into the wafer at a high temperature to form a P+ doped layer.
- the second semiconductor layer 60 is formed on the intrinsic layer 50 by diffusion, epitaxial growth or ion implantation. It can be seen from the above description that the second semiconductor layer 60 and the first semiconductor layer 10 are opposite semiconductor layers, and the process realization method may be, but not limited to, diffusion and epitaxial growth.
- Step 4 Use post-lift-off etching to open windows 70 on the second semiconductor layer 60 and the intrinsic layer 50 to form the first PIN diode and the second PIN diode;
- the second semiconductor layer and the intrinsic layer are etched at the window after lift-off (the intrinsic layer can be over-etched, and the depth of over-etching is 0-1000 ⁇ m), and the etching method can be Dry etching can also be wet etching.
- the intrinsic layer is divided into the first intrinsic layer 103 and the second intrinsic layer 203 by the window 70, and the second semiconductor layer is divided into the second semiconductor layer a102 and the second semiconductor layer b202 by the window 70.
- the first semiconductor layer 10, the first intrinsic layer 103 and the second semiconductor layer a102 constitute a first PIN diode;
- the first semiconductor layer 10, the second intrinsic layer 203 and the second semiconductor layer b202 constitute a second PIN diode diode.
- the etched window 70 should ensure electrical isolation between the first PIN diode 100 and the second PIN diode 200.
- Step 5 forming an insulating layer 80 on the surface of the switching semiconductor device, and then opening a window with reserved pads on the surfaces of the first PIN diode and the second PIN diode by lift-off and etching on the surfaces of the two PIN tubes;
- an insulating layer 80 is formed on the surface of the switching semiconductor device by thermal oxidation or chemical vapor deposition, and then the surface of the two PIN diodes is lift-off and etched on the first PIN diode. A window reserved for depositing pads is opened on the surface of the second PIN diode.
- the insulating layer composition can be SiO 2 , Si 3 N 4 or a multilayer structure of SiO 2 and Si 3 N 4 .
- step 5 is an optional step.
- an insulating layer is not necessary.
- Step 6 Deposit pads on the window above the first PIN diode and the second PIN diode;
- the first pad 101 and the second pad 201 are formed on the surface of the first PIN diode and the second PIN diode by evaporation, magnetron sputtering or electroplating, and Annealing is performed at high temperature in a mixed gas of nitrogen and hydrogen.
- Step 7 Depositing back gold on the bottom of the first semiconductor layer 10;
- a titanium-nickel-gold or titanium-gold or aluminum or other metal layer is deposited on the bottom of the first semiconductor layer 10 (the side away from the intrinsic layer) to form a back gold layer 20
- the thickness can be different.
- the thickness of titanium is 0-500 nanometers
- the thickness of nickel is 0-100 nanometers
- the thickness of gold is 0-500 micrometers.
- the area ratio of the first surface of each first PIN diode to the second surface of each second PIN diode is 1:N, where , N is a rational number greater than or equal to 1; the first surface is the effective area of the doped particles in the surface of the second semiconductor layer of the first PIN diode away from the first semiconductor layer; the second surface is the second surface of the second PIN diode
- the semiconductor layer is away from the effective area of the doped particles in the surface of the first semiconductor layer.
- the switching semiconductor device provided by the embodiments of the present application is used to form a three-port device structure.
- the first PIN diode and the second PIN diode are arranged side by side. In this way, the matching effect of the first PIN diode and the second PIN diode is improved.
- this overall integration method is adopted, compared with the discrete or multi-die components in the prior art, the integration is improved. This reduces the cost.
- the present application also provides a solid-state phase shifter.
- the solid-state phase shifter includes the switching semiconductor device described in any one of the above on a plurality of branches, and each branch has at least one switching semiconductor device, When two or more switching semiconductor devices are used, the two or more switching semiconductor devices may be connected in series, in parallel, or partly connected in series and partly connected in parallel, which is not specifically limited herein. And by turning on or turning off the switching semiconductor device, a phase difference is generated between the radio frequency signals respectively transmitted on the plurality of branches.
- a switching semiconductor device with a geometrically symmetrical figure centered on the two PIN diodes the parameters of the two PIN diodes are self-matched, thereby improving linearity. In turn, the effect of the solid-state phase shifter is improved.
- the protection scope of the present application is not limited to this, and the protection scope of the present application may also be multiple array structure PIN diodes.
- multiple PIN diodes with an array structure at least two intrinsic layers are provided on the same surface of the first semiconductor layer, and a second semiconductor layer is provided on each intrinsic layer; wherein, at least two intrinsic layers
- the layers have the same thickness, and the materials used have the same doping concentration coefficient; the number of the second semiconductor layer corresponds to the number of intrinsic layers, and each corresponding second semiconductor layer and intrinsic layer corresponds to the first semiconductor layer
- the layers form a PIN diode.
- the embodiments of the present application also provide a massive MIMO antenna array.
- the antenna array includes the above-mentioned solid-state phase shifter and a plurality of antenna elements.
- the solid-state phase shifter is used to change the The phase relationship between multiple antenna elements.
- the switching semiconductor device in the used solid-state phase shifter adopts a geometrically symmetrical pattern centered on two or more PIN diodes to achieve self-matching of multiple PIN diode parameters, thereby improving linearity. In turn, the use effect of the antenna array is improved.
- the PIN diode can be in an array pattern, such as the integration of 2, 4, 8 and multiple PIN diodes.
- the top view of the PIN diode is shown in FIG. 15.
- Figure 15 is a four-PIN diode mode, in which the opening areas of a and d, b and c are equal, and the ratio of the opening areas of a and b, d and c is 1:N, and N is a positive real number;
- Figure 16 is an eight-pin secondary Tube mode, where the opening areas of a and d, b and c, e and h, f and g are equal, and the ratio of the opening areas of a and b, d and c, e and f, h and g is 1: N, and N is positive Real number.
- An embodiment of the present application provides a communication device that includes the large-scale multiple-input multiple-output antenna array and a radio frequency signal transceiver, and the large-scale multiple-input multiple output antenna array is used to receive the radio frequency signal transceiver.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (14)
- 一种开关半导体器件,其特征在于,包括呈三明治结构堆叠的第一半导体层、本征层及第二半导体层;其中,所述本征层的个数至少为两个,所述至少两个本征层具有相同的厚度,且使用的材料具有相同的掺杂浓度系数;所述第二半导体的个数与所述本征层的个数一一对应,且每个第二半导体层层叠在对应的本征层背离所述第一半导体层的一面;所述第一半导体层与每个第一本征层及每个第二半导体层形成一个PIN二极管;且任意相邻的两个PIN二极管之间电隔离;其中,所述第一半导体层为N+半导体层,且所述第二半导体层为P+半导体层;或,所述第一半导体层为P+半导体层,且所述第二半导体层为N+半导体层。
- 根据权利要求1所述的开关半导体器件,其特征在于,每个第二半导体层及其对应的本征层的形状均为中心对称的形状。
- 根据权利要求1所述的开关半导体器件,其特征在于,所述PIN二极管的个数至少为两个,且所述至少两个PIN二极管包括至少一个第一PIN二极管及至少一个第二PIN二极管。
- 根据权利要求1或2所述的开关半导体器件,其特征在于,每个第一PIN二极管的第一表面与每个第二PIN二极管的第二表面的面积比例为1:N,其中,N为大于或等于1的有理数;所述第一表面为所述第一PIN二极管的第二半导体层背离所述第一半导体层的表面内所掺杂粒子的有效面积;所述第二表面为所述第二PIN二极管的第二半导体层背离所述第一半导体层的表面内所掺杂粒子的有效面积。
- 根据权利要求1~4任一项所述的开关半导体器件,其特征在于,所述开关半导体器件还包括镶嵌在所述第一半导体层的第一绝缘层,且所述第一绝缘层电隔离任意相邻的PIN二极管。
- 根据权利要求5所述的开关半导体器件,其特征在于,还包括第二绝缘层,且所述第二绝缘层与所述第一绝缘层连接并包裹任意一个PIN二极管的本征层及第二半导体层的侧壁。
- 一种固态移相器,其特征在于,包括位于多个支路上的多个如权利要求1~6任一项所述的开关半导体器件,每一支路上具有至少一个所述开关半导体器件,通过开通或关断所述开关半导体器件,使分别在所述多个支路上传输的射频信号之间产生相位差。
- 一种大规模多输入多输出(Massive MIMO)天线阵列,其特征在于,包括如权利要求7所述的固态移相器和多个天线单元,所述固态移相器用于改变所述多个天线单元之间的相位关系。
- 一种通信设备,其特征在于,包括权利要求8所述的大规模多输入多输出天线阵列和射频信号收发机,所述大规模多输入多输出天线阵列用于接收所述射频信号收发机发送的射频信号,或者,用于向所述射频信号收发机发送射频信号。
- 一种开关半导体器件制备方法,其特征在于,包括:制备第一半导体层及本征层,且所述第一半导体层与所述本征层层叠;在所述本征层背离所述第一半导体层的表面上形成第二半导体层;刻蚀所述第二半导体层及所述本征层,形成至少两个本征层及与每个本征层对应的第二半导体层;其中,所述至少两个本征层具有相同的厚度,且使用的材料具有相同的掺杂浓度系数;且所述第一半导体层与每个第一本征层及每个第二半导体层形成一个PIN二极管;任意相邻的两个PIN二极管之间电隔离;其中,所述第一半导体层为N+半导体层,且所述第二半导体层为P+半导体层;或,所述第一半导体层为P+半导体层,且所述第二半导体层为N+半导体层。
- 如权利要求10所述的制备方法,其特征在于,所述任意相邻的两个PIN二极管之间电隔离具体为:在任意相邻的PIN二极管之间的间隙内填充第一绝缘层,且第一绝缘层将任意相邻的本征层电隔离;并将任意相邻的第二半导体层电隔离。
- 如权利要求11所述的制备方法,其特征在于,所述刻蚀形成的本征层及第二半导体层的形状均为中心对称的形状。
- 如权利要求11所述的制备方法,其特征在于,所述第一半导体层与每个第一本征层及每个第二半导体层形成一个PIN二极管具体包括:所述PIN二极管的个数至少为两个,且所述至少两个PIN二极管包括至少一个第一PIN二极管及至少一个第二PIN二极管。
- 如权利要求13所述的制备方法,其特征在于,每个第一PIN二极管的第一表面与每个第二PIN二极管的第二表面的面积比例为1:N,其中,N为大于或等于1的有理数;所述第一表面为所述第一PIN二极管的第二半导体层背离所述第一半导体层的表面内所掺杂粒子的有效面积;所述第二表面为所述第二PIN二极管的第二半导体层背离所述第一半导体层的表面内所掺杂粒子的有效面积。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20878129.4A EP4036972A4 (en) | 2019-10-24 | 2020-10-23 | SEMICONDUCTOR SWITCHING DEVICE AND METHOD OF FABRICATION THEREOF, AND SEMICONDUCTOR PHASE SHIFTER |
KR1020227016894A KR20220086635A (ko) | 2019-10-24 | 2020-10-23 | 반도체 스위치 장치, 이의 제조 방법 및 고체 상태 위상 시프터 |
JP2022524009A JP7436648B2 (ja) | 2019-10-24 | 2020-10-23 | 半導体スイッチデバイス、その製造方法、およびソリッドステート移相器 |
US17/727,258 US20220247055A1 (en) | 2019-10-24 | 2022-04-22 | Semiconductor Switch Device, Manufacturing Method Thereof, and Solid-State Phase Shifter |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911019107.XA CN112713145A (zh) | 2019-10-24 | 2019-10-24 | 一种开关半导体器件及其制备方法、固态移相器 |
CN201911019107.X | 2019-10-24 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/727,258 Continuation US20220247055A1 (en) | 2019-10-24 | 2022-04-22 | Semiconductor Switch Device, Manufacturing Method Thereof, and Solid-State Phase Shifter |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2021078280A1 true WO2021078280A1 (zh) | 2021-04-29 |
Family
ID=75540349
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2020/123374 WO2021078280A1 (zh) | 2019-10-24 | 2020-10-23 | 一种开关半导体器件及其制备方法、固态移相器 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20220247055A1 (zh) |
EP (1) | EP4036972A4 (zh) |
JP (1) | JP7436648B2 (zh) |
KR (1) | KR20220086635A (zh) |
CN (1) | CN112713145A (zh) |
WO (1) | WO2021078280A1 (zh) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103066072A (zh) * | 2011-10-18 | 2013-04-24 | 上海华虹Nec电子有限公司 | Pin二极管阵列结构及其制造方法 |
CN205122584U (zh) * | 2015-06-15 | 2016-03-30 | 常州银河世纪微电子有限公司 | 一种开关二极管阵列 |
CN107731818A (zh) * | 2017-10-18 | 2018-02-23 | 东莞市阿甘半导体有限公司 | 瞬态抑制二极管芯片结构 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6191969A (ja) * | 1984-10-12 | 1986-05-10 | Nec Corp | 非線形素子 |
CA2355146A1 (en) * | 1999-10-18 | 2001-04-26 | Yasunori Arima | Light-receiving element array and light-receiving element array chip |
JP2004014658A (ja) * | 2002-06-05 | 2004-01-15 | Renesas Technology Corp | 半導体装置およびその製造方法 |
KR100747657B1 (ko) * | 2006-10-26 | 2007-08-08 | 삼성전자주식회사 | 매크로 및 마이크로 주파수 튜닝이 가능한 반도체 소자 및이를 갖는 안테나와 주파수 튜닝 회로 |
US7916529B2 (en) * | 2009-02-13 | 2011-03-29 | Spansion Llc | Pin diode device and architecture |
FR2981200B1 (fr) * | 2011-10-10 | 2017-01-13 | Centre Nat De La Rech Scient (Cnrs) | Cellule monolithique de circuit integre et notamment cellule de commutation monolithique |
CN109742161B (zh) * | 2018-09-30 | 2021-05-04 | 华为技术有限公司 | 一种开关半导体器件及其制备方法、固态移相器 |
-
2019
- 2019-10-24 CN CN201911019107.XA patent/CN112713145A/zh active Pending
-
2020
- 2020-10-23 KR KR1020227016894A patent/KR20220086635A/ko unknown
- 2020-10-23 EP EP20878129.4A patent/EP4036972A4/en active Pending
- 2020-10-23 JP JP2022524009A patent/JP7436648B2/ja active Active
- 2020-10-23 WO PCT/CN2020/123374 patent/WO2021078280A1/zh unknown
-
2022
- 2022-04-22 US US17/727,258 patent/US20220247055A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103066072A (zh) * | 2011-10-18 | 2013-04-24 | 上海华虹Nec电子有限公司 | Pin二极管阵列结构及其制造方法 |
CN205122584U (zh) * | 2015-06-15 | 2016-03-30 | 常州银河世纪微电子有限公司 | 一种开关二极管阵列 |
CN107731818A (zh) * | 2017-10-18 | 2018-02-23 | 东莞市阿甘半导体有限公司 | 瞬态抑制二极管芯片结构 |
Non-Patent Citations (1)
Title |
---|
See also references of EP4036972A4 * |
Also Published As
Publication number | Publication date |
---|---|
JP2023500610A (ja) | 2023-01-10 |
CN112713145A (zh) | 2021-04-27 |
EP4036972A1 (en) | 2022-08-03 |
US20220247055A1 (en) | 2022-08-04 |
KR20220086635A (ko) | 2022-06-23 |
EP4036972A4 (en) | 2022-11-02 |
JP7436648B2 (ja) | 2024-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9202888B2 (en) | Trench high electron mobility transistor device | |
US7745848B1 (en) | Gallium nitride material devices and thermal designs thereof | |
US8026596B2 (en) | Thermal designs of packaged gallium nitride material devices and methods of packaging | |
US8823146B1 (en) | Semiconductor structure having silicon devices, column III-nitride devices, and column III-non-nitride or column II-VI devices | |
KR20190001050A (ko) | 칩 적층 구조를 갖는 led 픽셀 소자 | |
US10312360B2 (en) | Method for producing trench high electron mobility devices | |
US3990102A (en) | Semiconductor integrated circuits and method of manufacturing the same | |
US10516043B1 (en) | Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors | |
US11949024B2 (en) | Semiconductor switch device and preparation method thereof, and solid-state phase shifter | |
US20090109646A1 (en) | Packaged gallium nitride material transistors and methods associated with the same | |
WO2021078280A1 (zh) | 一种开关半导体器件及其制备方法、固态移相器 | |
JP4837939B2 (ja) | 半導体装置、及び半導体装置の製造方法 | |
KR101377165B1 (ko) | 직렬 접속식 고전자 이동도 트랜지스터 디바이스 및 그 제조 방법 | |
WO2023124249A1 (zh) | 混合单片微波集成电路及其制作方法 | |
TW202245205A (zh) | 具有均勻組件之裝置封裝及其形成方法 | |
JP7533793B2 (ja) | 窒化物半導体基板及びその製造方法 | |
TWI825175B (zh) | 發光元件之製造方法 | |
KR100518059B1 (ko) | 스위칭 다이오드 및 그 제조 방법 | |
JP2850766B2 (ja) | 半導体装置 | |
CN112420630A (zh) | 一种堆叠键合式igbt器件 | |
CN118522761A (zh) | 半导体器件及其制备方法、芯片、电子设备 | |
JPH02156546A (ja) | 半導体装置の製造方法 | |
JP2013098326A (ja) | 集積型半導体装置 | |
JPH098334A (ja) | 可変容量ダイオード装置 | |
JPH04113448U (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 20878129 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2022524009 Country of ref document: JP Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2020878129 Country of ref document: EP Effective date: 20220428 |
|
ENP | Entry into the national phase |
Ref document number: 20227016894 Country of ref document: KR Kind code of ref document: A |