WO2021027253A1 - 用于多线程处理的方法、装置及系统 - Google Patents

用于多线程处理的方法、装置及系统 Download PDF

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Publication number
WO2021027253A1
WO2021027253A1 PCT/CN2020/071423 CN2020071423W WO2021027253A1 WO 2021027253 A1 WO2021027253 A1 WO 2021027253A1 CN 2020071423 W CN2020071423 W CN 2020071423W WO 2021027253 A1 WO2021027253 A1 WO 2021027253A1
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Prior art keywords
instruction
thread
instructions
logical register
transfer
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English (en)
French (fr)
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马凌
周伟
何昌华
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Advanced New Technologies Co Ltd
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Advanced New Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30069—Instruction skipping instructions, e.g. SKIP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file

Definitions

  • the embodiments of this specification generally relate to computer application technology, and more specifically, to a method, device, and system for multi-thread processing.
  • the processing core for example, CPU
  • the processing core performs instruction access and decoding operations in a polling manner in each instruction cycle according to the thread data, and places the instructions in the corresponding hardware instruction decoding queue after completion.
  • the CPU execution unit polls every instruction cycle to obtain the decoded instructions from each hardware instruction decoding queue, and then puts them into the CPU execution unit to start running.
  • the CPU prepares an independent hardware operating environment for each thread to run the thread. For example, the CPU prepares hardware resources such as instruction prediction, instruction execution, and instruction submission for each thread. Generally, when the number of running threads increases from one to two, the hardware cost will increase by 5%. The more threads the multi-threaded processing mechanism runs, the more hardware costs need to increase.
  • the embodiments of the present specification provide a method, device, and system for multi-thread processing.
  • multiple threads can be merged into a single merged thread to run, thereby realizing multi-thread processing without increasing hardware costs.
  • a method for multi-thread processing includes: for each thread of the first number of threads to be processed, using a different first logical register set to compile to obtain Corresponding machine instruction code; and using the first instruction in the instruction set supported by the processing core to perform fusion processing on the machine instruction code of each thread to obtain the machine instruction code of a single fused thread, wherein the first instruction includes fetching Effective address instructions and transfer instructions, the effective address fetch instructions and transfer instructions are compiled using a second logical register different from the first logical register set, and the transfer instructions are set in the machine corresponding to each thread
  • the instruction code is used to implement the jump operation between the machine instruction codes of the respective threads.
  • the first number does not exceed a first predetermined threshold
  • the first predetermined threshold is determined based on the number of logical registers that can be used by the processing core.
  • the transfer instruction includes a first transfer instruction obtained by modifying all or part of the jump instruction in the machine instruction code of each thread.
  • the transfer instruction further includes a second transfer instruction added based on the transfer instruction addition rule.
  • the transfer instruction adding rule includes: making the transfer instructions not more than a second predetermined number of instructions apart from each other; and/or using an instruction compiler tuning strategy to optimize The second transfer instruction is added after the machine instruction.
  • the second predetermined number is determined based on the number of instructions that can be executed by the processing core in a single instruction cycle.
  • each thread after fusion has at least one instruction jump block divided based on the transfer instruction.
  • the effective address fetching instruction includes a single first effective address fetching instruction, and all the first A fetch effective address instruction is placed at the beginning of the machine instruction code of the fusion thread, used to transfer the address of the first instruction of the thread to the corresponding second logical register, and for the first number of Each instruction in each thread in a thread jumps to a block, and the effective address fetching instruction includes two second effective address fetching instructions, and one of the second effective address fetching instructions is used to jump the instruction to the first of the block.
  • the address of one instruction is transferred to the corresponding second logical register, and the other second effective address instruction is used to transfer the address of the first instruction after the instruction jump block to the corresponding second logical register.
  • Two second effective address fetching instructions are placed between the corresponding instruction jump block and the previous instruction jump block of the respective threads, and the transfer instructions include conditional transfer instructions and unconditional jump instructions.
  • the instruction set includes leaxxj instructions, and for each thread except the first thread of the first number of threads, the effective address instruction includes a single An effective address fetch instruction, the first effective address fetch instruction is used to transfer the address of the first instruction of the thread to the corresponding second logical register, and all the first effective address fetch instructions are placed in the fusion
  • the jump instruction includes a single leaxxj instruction, wherein the instruction format of the leaxxj instruction is leaxxj L_loop_i(rm), rn, where the logical register rm represents the second logical register used by the first effective address instruction of the thread to which the corresponding instruction jump block belongs, and the logical register rn represents the first thread that needs to be jumped to A second logic register used by the effective address instruction, the leaxxj instruction is used to instruct to put the instruction address pointed to by L_loop
  • the second logic register has a flag bit for indicating the use state of the second logic register, and the use state includes the first state and the use state for indicating normal use.
  • the second logical register rn pointed to is released The physical register makes the second logical register rn point to the second logical register used by the target jump thread, and assigns the flag bit of the second logical register rn to indicate the second state.
  • the processing core has retrieved the leaxxj instruction, the instruction block corresponding to the address stored in the logical register rn in the leaxxj instruction Prefetched into the instruction decode queue of the processing core.
  • the method further includes: obtaining the machine instructions in the fusion thread in units of instruction blocks via the processing core to run.
  • the size of the instruction block is determined by the ability of the processing core to read instructions in a single instruction cycle.
  • the instruction block is adjusted to take the transfer instruction as the end instruction .
  • an apparatus for multi-thread processing including: a thread compiling unit, for each thread of the first number of threads to be processed, using a different first logical register set to Compile to obtain the corresponding machine instruction code; and the thread fusion unit, which uses the first instruction in the instruction set supported by the processing kernel to fuse the machine instruction code of each thread to obtain the machine instruction code of a single fused thread, where
  • the first instruction includes an effective address fetching instruction and a transfer instruction, the effective address fetching instruction and the transfer instruction are compiled by using a second logical register different from the first logical register set, and the transfer instruction is set in
  • the machine instruction codes corresponding to the respective threads are used to implement jump operations between the machine instruction codes of the respective threads.
  • the device further includes: a transfer instruction obtaining unit, a first transfer instruction obtained by modifying all or part of the jump instructions in the machine instruction code of each thread .
  • the transfer instruction obtaining unit further adds a second transfer instruction based on the transfer instruction adding rule.
  • the transfer instruction adding rule includes: making the transfer instructions not more than a second predetermined number of instructions apart from each other; and/or using an instruction compiler tuning strategy to optimize The second transfer instruction is added after the machine instruction.
  • each thread after fusion has at least one instruction jump block divided based on the transfer instruction.
  • the effective address fetching instruction includes a single first effective address fetching instruction, and all the first A fetch effective address instruction is placed at the beginning of the machine instruction code of the fusion thread, used to transfer the address of the first instruction of the thread to the corresponding second logical register, and for the first number of Each instruction in each thread in a thread jumps to a block, and the effective address fetching instruction includes two second effective address fetching instructions, and one of the second effective address fetching instructions is used to jump the instruction to the first of the block.
  • the address of one instruction is transferred to the corresponding second logical register, and the other second effective address instruction is used to transfer the address of the first instruction after the instruction jump block to the corresponding second logical register.
  • Two second effective address fetching instructions are placed between the corresponding instruction jump block and the previous instruction jump block of the respective threads, and the transfer instructions include conditional transfer instructions and unconditional jump instructions.
  • the instruction set includes leaxxj instructions, and for each thread except the first thread of the first number of threads, the effective address instruction includes a single An effective address fetch instruction, the first effective address fetch instruction is used to transfer the address of the first instruction of the thread to the corresponding second logical register, and all the first effective address fetch instructions are placed in the fusion
  • the jump instruction includes a single leaxxj instruction, wherein the instruction format of the leaxxj instruction is leaxxj L_loop_i(rm), rn, where the logical register rm represents the second logical register used by the first effective address instruction of the thread to which the corresponding instruction jump block belongs, and the logical register rn represents the first thread that needs to be jumped to A second logical register used by the effective address instruction, the leaxxj instruction is used to instruct to put the instruction address pointed to by L_l
  • a system for multi-thread processing including: a compiler, including the device for multi-thread processing as described above, and compiling a first number of threads into a single fusion thread The machine instruction code of the fusion thread; the instruction set; and the processing core, the machine instruction in the fusion thread is obtained and executed in the unit of instruction block.
  • the instruction set includes leaxxj instructions, and the instruction format of the leaxxj instructions is leaxxj L_loop_i(rm), rn, where the logical register rm represents the thread to which the corresponding instruction jump block belongs The second logical register used by the first effective address instruction, and the logical register rn represents the second logical register used by the first effective address instruction of the thread that needs to jump to.
  • the leaxxj instruction is used to indicate the condition When it is satisfied, the instruction address pointed to by L_loop_i is placed in the logical register rm, and when the condition is not satisfied, the instruction address of the first instruction after the leaxxj instruction is placed in the logical register rm, and jumps to the logical register rn. The instruction corresponding to the address.
  • the second logic register has a flag bit for indicating the use state of the second logic register, and the use state includes the first state and the use state for indicating normal use.
  • the processing core recognizes that L_loop_i in the leaxxj instruction is assigned a specified value, the processing core releases the second logic register
  • the physical register pointed to by rn makes the second logical register rn point to the second logical register used by the target jump thread, and the flag bit of the second logical register rn is assigned to indicate the second state.
  • the processing core when the machine instruction is executed, if the processing core has retrieved the leaxxj instruction, the processing core will match the address stored in the logical register rn in the leaxxj instruction.
  • the corresponding instruction block is prefetched into the instruction decoding queue of the processing core.
  • a computing device including: one or more processors, and a memory coupled with the one or more processors, the memory stores instructions, and when the instructions are When the one or more processors are executed, the at least one processor is caused to execute the method for multi-thread processing as described above.
  • a machine-readable storage medium which stores executable instructions that, when executed, cause the machine to execute the method for multithreading processing as described above.
  • Figure 1 shows a schematic diagram of a multithreading process in the prior art
  • Fig. 2 shows an example schematic diagram for compiling multiple threads in the prior art
  • Fig. 3 shows an example schematic diagram of the instruction running process
  • Figure 4 shows a block diagram of a multi-threaded processing system according to an embodiment of the present specification
  • Fig. 5 shows a flowchart of a method for multi-thread processing according to an embodiment of the present specification
  • Fig. 6 shows an example schematic diagram of thread fusion processing according to an embodiment of the present specification
  • Fig. 7 shows another example schematic diagram of thread fusion processing according to an embodiment of the present specification
  • FIG. 8 shows a flowchart of a fusion thread running process according to an embodiment of the specification
  • FIG. 9 shows a schematic diagram of a thread example of thread exit processing according to an embodiment of the present specification.
  • Fig. 10 shows a block diagram of a multithreading compiling apparatus according to an embodiment of the present specification
  • FIG. 11 shows a block diagram of a computing device for multi-thread processing according to an embodiment of the present specification.
  • the term “including” and its variants means open terms, meaning “including but not limited to.”
  • the term “based on” means “based at least in part on.”
  • the terms “one embodiment” and “an embodiment” mean “at least one embodiment.”
  • the term “another embodiment” means “at least one other embodiment.”
  • the terms “first”, “second”, etc. may refer to different or the same objects. Other definitions can be included below, either explicit or implicit. Unless clearly indicated in the context, the definition of a term is consistent throughout the specification.
  • Fig. 1 shows a schematic diagram of a multithreading process 100 in the prior art.
  • the multi-thread processing process 100 may include a thread compiling process 110 and a thread running process 120.
  • the same logical register set is used for compilation to obtain the corresponding machine instruction code.
  • the logical register refers to the register used in the program code, and the logical register points to the physical register.
  • FIG. 2 shows an example schematic diagram for compiling multiple threads in the prior art.
  • three threads Thread1, Thread2 and Thread3 are shown.
  • Thread1, Thread2, and Thread3 use the same logical register set ⁇ r1, r2, r3, r4, ... ⁇ to compile.
  • thread Thread1 uses logical registers r1-r3
  • thread Thread2 uses logical registers r1 and r3
  • thread Thread3 uses logical registers r1, r2, and r4.
  • each machine instruction includes an operation code and an operand, where the operation code is used to indicate the nature and function of the operation to be completed by the instruction, such as add, mul, mov, sub, jmp, etc.
  • the operand is used to specify the operation object when the operation code is executed.
  • the form of the operand can be the data itself. It can also be the address of the memory unit or the register name where the data is stored.
  • Operands are further divided into source operands and destination operands. The source operand indicates the source of the operand participating in the operation, and the destination operand address indicates the address of the storage unit or register name that stores the operation result.
  • the processing core (for example, the central processing unit CPU) also creates an independent thread operating environment for each of the multiple threads.
  • the thread running environment includes hardware resources for executing instruction prediction, hardware resources for executing instruction execution, hardware resources for executing instruction submission, and the like.
  • a separate hardware instruction decode queue is created for each of the multiple threads.
  • the CPU performs instruction access and decoding operations in a polling manner in each instruction cycle according to the thread data, and places the instructions in the respective hardware instruction decoding queues after completion.
  • the CPU execution unit polls every instruction cycle to obtain the decoded instructions from each hardware instruction decoding queue, and then puts them into the CPU execution unit to start running.
  • Fig. 3 shows an example schematic diagram of the instruction execution process.
  • an instruction fetch (Instruction Fetch, IF) operation is performed.
  • the instruction fetch operation refers to fetch the instruction to be executed from the main memory to the instruction register.
  • the value in the program counter PC is used to indicate the location of the current instruction in the main memory. When an instruction is fetched, the value in the PC will automatically increase according to the length of the instruction word: if it is a single-word instruction, add 1 byte; if it is a double-word instruction, add 2 bytes, and so on .
  • an instruction decoding (Instruction Decode, ID) operation is performed.
  • the instruction decoder splits and interprets the retrieved instructions according to a predetermined instruction format, and distinguishes different instruction types and various methods of obtaining operands.
  • the instruction decoder In a computer controlled by combinational logic, the instruction decoder generates different control potentials for different instruction operation codes to form different micro-operation sequences.
  • the instruction decoder uses the instruction opcode to find the entry of the microprogram that executes the instruction, and start execution from this entry.
  • an instruction execution (Execution, EX) operation is performed.
  • various operations specified by the instruction are completed to realize the instruction function.
  • the different component parts of the CPU are connected to perform the required operations. For example, if an addition operation is required, the arithmetic logic unit ALU will be connected to a set of inputs and a set of outputs. The input terminal provides the value to be added, and the output terminal will contain the final operation result.
  • an operand access operation is performed as required by the instruction.
  • the address of the operand in the main memory is obtained according to the instruction address code, and the operand is read from the main memory for operation.
  • a result writeback (WB) operation is performed.
  • the operation result data of the instruction execution operation is "written back" to a certain storage unit.
  • the result data is often written to the internal registers of the CPU so that it can be quickly accessed by subsequent instructions.
  • the resulting data can also be written to a relatively slow, but cheaper, and larger capacity main memory.
  • Many instructions will also change the status of the flag bits in the program status word register. These flag bits are used to identify different operation results and can be used to affect program actions.
  • the processing core After the instruction is executed and the result data write-back operation is completed, if no unexpected event (for example, result overflow, etc.) occurs, the processing core obtains the next instruction address from the program counter PC and starts a new round of instruction execution.
  • no unexpected event for example, result overflow, etc.
  • Figure 3 shows a schematic diagram of the instruction execution process in a single thread.
  • the operating system uses a thread scheduling mechanism to switch between multiple threads. For example, the operating system allocates a time slice to each of the multiple threads that the CPU allows for parallel execution, and each thread occupies the CPU in its own time slice to execute instruction execution operations. After the time slice of the current thread is used up, it will be in the ready state and give up the CPU to other threads. In addition, if the task of the thread is blocked or ended before the end of its own time slice, the thread switch will be performed immediately without causing waste of CPU resources.
  • the hyper-threading mechanism means that when one thread executes an integer instruction set, the tasks performed by other threads are executed by an execution unit different from the execution unit that executes the tasks of the current thread, for example, the floating-point instruction set. In this case, these two threads can be executed simultaneously. Hyper-threading technology allows two threads to use the resources in the CPU at the same time without conflict.
  • the CPU needs to prepare an independent hardware operating environment for each thread to run the thread, which requires more hardware costs.
  • the number of threads for parallel processing is limited by the hardware conditions for thread processing.
  • the embodiment of this specification provides a multi-thread processing solution.
  • this multi-threaded processing solution multiple threads are compiled separately by using different register sets, and the effective address instructions and transfer instructions in the instruction set supported by the processing core are used to merge multiple threads into a single fused thread, and then Run based on the obtained fusion thread, thereby realizing multi-thread processing.
  • only the hardware cost required for the operation of a single thread needs to be provided, so that multi-thread processing can be realized without increasing the hardware cost.
  • FIG. 4 shows a block diagram of a multi-thread processing system 400 according to an embodiment of the present specification.
  • the multi-thread processing system 400 includes a multi-thread compiling device 410, an instruction set 420, and a processing core 430.
  • the multi-thread compiling device 410 is configured to use different first logical register sets to compile each thread of the first number of threads to be processed to obtain the machine instruction code of each thread, and use the instruction set supported by the processing core
  • the first instruction in 420 performs fusion processing on the machine instruction code of each thread to obtain the machine instruction code of a single fused thread.
  • the obtained machine instruction code of a single fusion thread is obtained by the processing core 430 for instruction execution.
  • the first instruction includes an effective address instruction (Lea instruction) and a transfer instruction.
  • the effective address instruction and the transfer instruction are compiled by using a second logical register different from the first logical register set.
  • the transfer instruction It is set in the machine instruction code corresponding to each thread, and is used to realize the jump operation between the machine instruction code of each thread.
  • the operation and structure of the multithreading compiling apparatus 410 will be described in detail below with reference to FIGS. 5-7 and 9 respectively.
  • both the first logical register set and the second logical register belong to the logical registers that can be used by the processing core 430.
  • the first logical register set and the second logical register can be obtained by dividing the logical registers that can be used by the processing core 430.
  • the processing core 430 is configured to obtain machine instructions in the fusion thread to run in units of instruction blocks.
  • the size of the instruction block may be determined by the ability of the processing core to read instructions in a single instruction cycle.
  • the instruction block may be adjusted to take the transfer instruction as the end instruction.
  • Fig. 5 shows a flowchart of a method for multi-thread processing according to an embodiment of the present specification.
  • a different first logical register set is used for compilation to obtain the corresponding machine instruction code.
  • the different logical register sets mean that all the logical registers included in the logical register set are different.
  • the logical register set is obtained by dividing the logical registers that can be used by the processing core. For example, assuming that the logical registers that can be used by the processing core include logical registers r1-r10, the logical register set is obtained by dividing the logical registers r1-r10.
  • the first number is set to not exceed the first predetermined threshold.
  • the first predetermined threshold is determined based on the number of logical registers that can be used by the processing core. For example, in one example, the first predetermined threshold may be determined based on the number of logical registers available to the processing core and the number of logical registers required by the thread to be processed. In addition, in another example of the embodiment of this specification, the first number can be arbitrarily set by software. In this case, if the first number set exceeds the number of logical registers that can be used by the processing core or the number of logical registers required by the first number of threads exceeds the number of logical registers that can be used by the processing core, you can use The way to push the stack to achieve thread compilation.
  • FIG. 6 shows an example schematic diagram of thread fusion processing according to an embodiment of this specification
  • FIG. 7 shows another example schematic diagram of thread fusion processing according to an embodiment of this specification. 6 and FIG. 7 show the thread fusion processing of the threads Thread1, Thread2, and Thread3 shown in FIG. 2.
  • the first logical register set composed of logical registers r1-r3 is used to compile thread Thread1
  • the first logical register set composed of logical registers r8-r9 is used to compile thread Thread2
  • the logical register r12 is used.
  • the first logical register set composed of -r14 is used to compile thread Thread3.
  • the first logical register set composed of logical registers r1-r3 is used to compile thread Thread1
  • the first logical register set composed of logical registers r8-r9 is used to compile thread Thread2
  • the logical register r11 is used.
  • the first logical register set composed of -r13 is used to compile thread Thread3.
  • the first instruction in the instruction set 420 supported by the processing core is used to fuse the machine instruction code of each thread to obtain the machine instruction code of a single fused thread .
  • the first instruction includes an effective address fetch instruction (Lea instruction) and a transfer instruction, and the effective address fetch instruction and the transfer instruction are compiled by using a second logical register different from the first logical register set.
  • the transfer instruction is set in the machine instruction code corresponding to each thread, and is used to realize the jump operation between the machine instruction code of each thread.
  • the effective address fetching instruction is also called the LEA instruction, which is an instruction of the 8086/8088 series of microcomputers.
  • the instruction format of LEA instruction is: LEA operand A, operand B.
  • the instruction function of the LEA instruction transfer the effective address of operand B to the unit where operand A is located.
  • operand A is the destination operand
  • operand B is the source operand.
  • the LEA instruction requires that the source operand B must be a storage unit, and the destination operand A must be a register.
  • the logical registers r4 and r5 are used as the second logical registers to compile the first instruction related to thread Thread1
  • logical registers r6 and r7 are used as the second Logical registers are used to compile the first instruction related to thread Thread2
  • logical registers r10 and r11 are used as the second logical register to compile the first instruction related to thread Thread3.
  • the logical register r4 is used as the second logical register to compile the first instruction related to thread Thread1
  • the logical register r6 is used as the second logical register to compile and
  • the first instruction related to thread Thread2 and for thread Thread3, the logical register r10 is used as the second logical register to compile the first instruction related to thread Thread3. How to use the first instruction to perform the fusion processing will be described below with reference to the examples in FIG. 6 and FIG. 7.
  • the transfer instruction may include a first transfer instruction obtained by modifying all or part of the jump instruction in the machine instruction code of each thread.
  • the jump instructions "1.6 ja L_loop_1" in thread Thread1 in Figure 2 are modified to obtain the transfer instructions "1.10 cmovbe r5, r4" and "1.11 jmp r6"
  • the jump instruction "1.14 jbe L_loop_2" in the thread Thread1 in Figure 2 is modified to obtain the transfer instructions "1.21 cmovbe r5, r4" and "1.22 jmp r6", but the jump instruction in the thread Thread1 in Figure 2 "1.9 ja L_sub_again" will not be modified.
  • the transfer instructions "2.9 cmovbe r7, r6" and “2.10 jmp r10” obtained by modifying all the jump instructions "2.7 ja L_loop_3" in the thread Thread2 in FIG.
  • the transfer instructions "3.8 cmovbe r11, r10” and “3.9 jmp r4" obtained by modifying all the jump instructions "3.6 ja L_loop_4" in the thread Thread3 in FIG.
  • the branch instruction includes a conditional transfer instruction cmovbe and an unconditional jump instruction jmp.
  • the conditional transfer instruction may include a cmovle instruction, a cmovnz instruction, and so on.
  • the jump instruction "3.6 ja L_loop_4" in the thread Thread3 in FIG. 2 is modified to obtain the jump instruction "3.6 leaaj L_loop_4 (r10), r4".
  • the leaaj instruction is a conditional branch instruction. The specific structure and meaning of the leaaj instruction will be described in detail below.
  • using the existing jump instructions in the machine instruction code of each thread to modify the transfer instruction for thread fusion can reduce the number of instructions in the fused thread, thereby improving the efficiency of the fused thread.
  • the transfer instruction may include a second transfer instruction added based on the transfer instruction addition rule.
  • the second transfer instruction is not modified based on the original instructions in each thread, but is an added new instruction. For example, suppose thread Thread1, thread Thread2, and/or thread Thread3 do not contain jump instructions, or the instruction interval between the jump instructions contained in thread Thread1, thread Thread2, and/or thread Thread3 is too large (for example, more than A predetermined number, for example, the number of instructions that the processing core can execute in a single instruction cycle), then the second conditional branch instruction can be added in the corresponding thread based on the branch instruction increase rule.
  • the branch instruction adding rule may include: making the branch instructions to be separated from each other by no more than a second predetermined number of instructions; and/or using an instruction compiler tuning strategy to add a second instruction after a suitable machine instruction. Transfer instructions.
  • the second predetermined number may be determined based on the number of instructions that the processing core can execute in a single instruction cycle.
  • Using the instruction compiler tuning strategy to add a second branch instruction after the appropriate machine instruction refers to the strategy of loop testing to determine the method of adding branch instructions that can optimize the efficiency of the compiler.
  • the thread after the fusion can make the thread jump at an appropriate time, thereby improving the fusion The running efficiency of the subsequent thread.
  • each thread after the fusion has at least one instruction jump block divided based on the branch instruction.
  • there are two instruction jump blocks that is, the first instruction jump from instruction “L_loop_1:1.6 add(addr1), r1" to instruction “1.11 jmp r6" Transfer block, and the second instruction jump block from instruction “L_loop_2:1.17 sub(addr1), r4" to instruction "1.22 jmp r6".
  • thread Thread2 there is one instruction jump block, that is, the third instruction jump block from instruction "L_loop_3:2.5 add(addr2), r8" to instruction "2.10 jmp r10".
  • For thread Thread3 there is one instruction jump block, that is, the fourth instruction jump block from instruction "L_loop_4:3.4 sub(addr3), r14" to instruction "3.9 jmp r4".
  • the effective address instruction includes a single first effective address instruction. Address instructions, and all first effective address fetching instructions are placed at the beginning of the machine instruction code of the fusion thread, and are used to transfer the address of the first instruction of the thread to the corresponding second logical register. For example, Fig.
  • the effective address instruction includes two second effective address instructions, one of which is the first
  • the second effective address instruction is used to transfer the address of the first instruction of the instruction jump block to the corresponding second logical register
  • the other second effective address instruction is used to transfer the first instruction located after the instruction jump block.
  • the address of the instruction is transferred to the corresponding second logic register
  • the two second effective address fetching instructions are placed between the corresponding instruction jump block and the previous instruction jump block of the respective thread
  • the transfer instruction includes Conditional transfer instructions and unconditional jump instructions.
  • the two second effective address fetching instructions are placed between the instruction "Leave_loop_1:L_sub_again” and the instruction “L_loop_2:1.17 sub(addr1), r4", that is, the first instruction jump block and the second instruction jump block between.
  • the two second effective address fetching instructions are preferably placed as the first instruction of the corresponding instruction jump block.
  • the transfer instruction includes a conditional transfer instruction cmovbe and an unconditional jump instruction jmp.
  • the transfer instruction includes a conditional transfer instruction "1.10 cmovbe r5, r4" and an unconditional jump instruction "1.11 jmp r6".
  • the transfer instructions include conditional transfer instructions "1.21 cmovbe r5, r4" and unconditional jump instructions "1.22 jmp r6".
  • the transfer instructions include conditional transfer instructions "2.9 cmovbe r7, r6" and unconditional jump instructions "2.10 jmp r10”.
  • the transfer instructions include conditional transfer instructions "3.8 cmovbe r11, r10" and unconditional jump instructions "3.9 jmp r4".
  • the machine instruction codes of multiple threads can be fused into the machine instruction codes of a single thread. Therefore, when executing the instructions, only the hardware operating environment corresponding to the single thread needs to be prepared. It can realize multi-threaded processing without increasing hardware cost.
  • the instruction set 420 includes leaxxj instructions.
  • the effective address fetching instruction includes a single first effective address fetching instruction, and the first effective address fetching instruction is used for the thread The address of the first instruction is transferred to the corresponding second logical register.
  • Figure 7 shows the first effective fetching instructions "1.1 lea r6, L_Thread2(rip)” and "1.2 lea r10, L_Thread3(rip)", in which the first fetching effective instruction "1.1 lea r6, L_Thread2(rip)" "Corresponds to thread Thread2, and the first effective fetch instruction "1.2 lea r10, L_Thread3(rip)” corresponds to thread Thread3.
  • the first effective fetch instructions "1.1 lea r6, L_Thread2(rip)” and "1.2 lea r10, L_Thread3(rip)” are placed at the beginning of the fusion thread.
  • the transfer instruction includes a single leaxxj instruction.
  • the leaxxj instruction is a newly added conditional branch instruction in the instruction set of the CPU.
  • the instruction format of the leaxxj instruction is leaxxj L_loop_i(rm), rn, where the logical register rm represents the second logical register used by the first effective address instruction of the thread to which the corresponding instruction jump block belongs, and the logical register rn represents The second logical register used by the first effective address fetching instruction of the thread to be jumped to.
  • leaxxj instructions is used to instruct to put the instruction address pointed to by L_loop_i into the logical register rm when the condition is satisfied, and when the condition is not satisfied Put the instruction address of the first instruction after the leaxxj instruction into the logical register rm, and (unconditionally) jump to the instruction corresponding to the address stored in the logical register rn.
  • leaxxj instructions can include leaaj instructions, leaaej instructions, leabj instructions, leabej instructions, leagj instructions, leagej instructions, lealej instructions, lealj instructions, leanej instructions, leaej instructions, leaj instructions, leancj instructions, leacj instructions, etc. .
  • the format of the leaaj instruction is leaaj L_Loop_i(rn), rm, which means that if the unsigned is greater than, the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address after the current leaaj instruction is stored in the logic Register rn, jump to logic register rm at the same time.
  • the above leaaj instruction represents an unsigned comparison between r2 and r1. If r2 is greater than r1, the instruction address pointed to by L_Loop_i is stored in rn, otherwise, the instruction address following the current leaaj instruction is stored in rn, and at the same time jumps to rm.
  • the format of the leaaej instruction is leaaej L_Loop_i(rn), rm, which means that if the unsigned is greater than or equal to, the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leaaej instruction is stored in the logical register rn, jump to the logic register rm at the same time.
  • the above leaaej instruction represents an unsigned comparison between r2 and r1. If r2 is greater than or equal to r1, the instruction address pointed to by L_Loop_i is stored in rn, otherwise, the instruction address following the current leaaej instruction is stored in rn, and at the same time jumps to rm.
  • the format of the leabj instruction is leabj L_Loop_i(rn), rm, which is used to indicate that if the unsigned is less than, the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leabj instruction is stored in the logical register rn, At the same time jump to the logic register rm.
  • the above leabj instruction is used to express unsigned comparison between r2 and r1. If r2 is less than r1, store the instruction address pointed to by L_Loop_i into rn, otherwise store the instruction address following the current leabj instruction into rn, and jump to rm at the same time.
  • leafej L_Loop_i(rn), rm which means that if the unsigned is less than or equal to, the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leafj instruction is stored in the logical register rn, jump to the logic register rm at the same time.
  • the above leafej instruction is used to express unsigned comparison between r2 and r1. If r2 is less than or equal to r1, store the address of the instruction pointed to by L_Loop_i in rn, otherwise store the address of the instruction following the current leafj instruction in rn, and jump to rm at the same time .
  • the format of the leagj instruction is leagj L_Loop_i(rn), rm, which is used to indicate that the sign is greater than, then the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current lagj instruction is stored in the logical register rn, and Jump to the logic register rm.
  • the above leagj instruction is used to indicate a signed comparison between r2 and r1. If r2 is greater than r1, store the instruction address pointed to by L_Loop_i in rn, otherwise store the instruction address following the current leagj instruction in rn and jump to rm at the same time.
  • the format of the leagej instruction is leagej L_Loop_i(rn), rm, which is used to indicate that the sign is greater than or equal to, then the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leagej instruction is stored in the logical register rn , And jump to the logic register rm at the same time.
  • the above leagej instruction represents a signed comparison between r2 and r1. If r2 is greater than or equal to r1, the instruction address pointed to by L_Loop_i is stored in rn; otherwise, the instruction address following the current leagej instruction is stored in rn, and at the same time jumps to rm.
  • the format of the lealej instruction is lealej L_Loop_i(rn), rm, used to indicate that the sign is less than or equal to, then the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current lealej instruction is stored in the logical register rn , And jump to the logic register rm at the same time.
  • the above lealej instruction represents a signed comparison between r2 and r1. If r2 is less than or equal to r1, store the instruction address pointed to by L_Loop_i into rn; otherwise, store the instruction address following the current lealej instruction into rn and jump to rm at the same time.
  • the format of the lealj instruction is lealj L_Loop_i(rn), rm, which is used to indicate that the sign is less than, then the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current lealj instruction is stored in the logical register rn, and at the same time Jump to the logic register rm.
  • the above lealj instruction represents a signed comparison between r2 and r1. If r2 is less than r1, the instruction address pointed to by L_Loop_i is stored in rn, otherwise, the instruction address following the current lealj instruction is stored in rn, and at the same time jumps to rm.
  • leanej L_Loop_i(rn), rm which is used to indicate not equal
  • the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leanej instruction is stored in the logical register rn, and jump Go to the logic register rm.
  • the leanej instruction above represents a signed comparison between r2 and r1. If r2 is not equal to r1, store the instruction address pointed to by L_Loop_i into rn, otherwise store the instruction address following the current leanej instruction into rn and jump to rm at the same time.
  • the format of the leaej instruction is leafj L_Loop_i(rn), rm, which is used to mean equal, then the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leafj instruction is stored in the logical register rn, and jumps at the same time To the logic register rm.
  • the leaej instruction above indicates a signed comparison between r2 and r1. If r2 is equal to r1, store the instruction address pointed to by L_Loop_i in rn, otherwise store the instruction address following the current leaej instruction in rn and jump to rm at the same time.
  • leaj L_Loop_i(rn), rm which is used to unconditionally store the instruction address pointed to by L_Loop_i into the logical register rn and jump to the logical register rm at the same time.
  • the leaj instruction above means that the instruction address pointed to by L_Loop_i is stored in rn unconditionally and jumps to rm at the same time.
  • the format of the leancj instruction is leancj L_Loop_i(rn), rm, used to indicate no carry, then the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leancj instruction is stored in the logical register rn, and jump Go to the logic register rm.
  • the leancj instruction above means to compare r2 and r1. If no carry occurs, store the address of the instruction pointed to by L_Loop_i into rn; otherwise, store the instruction address following the current leancj instruction into rn and jump to rm at the same time.
  • the format of the leacj instruction is leacj L_Loop_i(rn), rm, which is used to indicate carry, then the instruction address pointed to by L_Loop_i is stored in the logical register rn, otherwise the instruction address following the current leacj instruction is stored in the logical register rn, and at the same time jump To the logic register rm.
  • the above leacj instruction means to compare r2 and r1. If no carry occurs, store the instruction address pointed to by L_Loop_i into rn, otherwise store the instruction address following the current leacj instruction into rn, and jump to rm at the same time.
  • the architecture of the CPU needs to be modified accordingly.
  • the CPU can recognize the leaxxj instruction and complete various operation tasks of the leaxxj instruction.
  • the transfer instruction includes a single leaxxj instruction.
  • the transfer instruction includes the instruction "1.8 leaaj L_loop_1 (r4), r6".
  • the transfer instruction includes the instruction "1.16 leaaj L_loop_2(r4), r6".
  • the transfer instruction includes the instruction "2.7 leaaj L_loop_3(r6), r10".
  • the transfer instruction includes the instruction "3.6 leaaj L_loop_4(r10), r4".
  • the machine instruction codes of multiple threads can be fused into the machine instruction codes of a single thread. Therefore, when the instructions are executed, only the hardware operating environment corresponding to the single thread needs to be prepared. It can realize multi-threaded processing without increasing hardware cost.
  • a single instruction can be used to implement the transfer instruction, thereby greatly reducing the number of instructions of the merged thread, thereby improving the efficiency of the merged thread.
  • the leaaj instruction is obtained by modifying the original jump instruction.
  • 4 instructions are needed to realize the jump, namely, 2 lea instructions, 1 cmovbe instruction, and 1 jmp instruction.
  • the processing core 430 obtains the machine instructions in the fusion thread in units of instruction blocks to run.
  • each instruction fetched by the current CPU is obtained from the instruction decode queue in the unit of instruction block (for example, the maximum number of instructions contained in an instruction block may be 5 or 6, and the maximum instruction of the acquired instruction block The number can be determined by the processing capability of the CPU, for example, can be determined by the number of instructions that the CPU can execute in a single instruction cycle). If according to the specified instruction block size, the instruction block fetched by the CPU this time contains a transfer instruction, such as a cmovbe instruction or a leaxxj instruction, and the transfer instruction is not the end instruction of the fetched instruction block.
  • a transfer instruction such as a cmovbe instruction or a leaxxj instruction
  • this fetch operation can only fetch the instruction until the transfer instruction (for example, leaxxj instruction), that is, the instruction block fetched this time is adjusted to use the transfer instruction as the end instruction, thereby avoiding the foregoing Roll back the situation.
  • the transfer instruction for example, leaxxj instruction
  • the processing core 430 when the machine instruction is running, if the processing core 430 has retrieved the leaxxj instruction, the instruction block corresponding to the address stored in the logical register rn in the leaxxj instruction is prefetched from the cache or memory To the instruction decode queue of the processing core 430.
  • the instruction leaxxj L_loop_2(r4), r6 is fetched, it is already known that the next time it needs to jump to the destination address pointed to by r6, so start to prefetch the instruction block pointed to by r6 (the instruction block of Thread-2) To the instruction decode queue of the CPU core. In this way, instructions will continue to enter the instruction decoding queue during the jump, and the operation in the middle will continue to expand without disconnection.
  • Fig. 8 shows a flowchart of a fusion thread running process according to an embodiment of the present specification.
  • the processing core 430 obtains machine instructions in the fusion thread in units of instruction blocks.
  • the processing core 430 obtains the instruction block 1 in the thread Thread1 in the fusion thread shown in FIG. 7.
  • the instruction block 1 consists of the instructions "1.1 lea r6, L_Thread2(rip)", “1.2 lea r10, L_Thread3(rip)", "1.3 mov r1, r3", “L_loop_1:1.4 add(addr1), r1" and "1.5 mul r1, r2".
  • the processing core 430 sequentially executes the instructions in the retrieved instruction block.
  • the processing core 430 runs the instructions "1.1 lea r6, L_Thread2(rip)", “1.2 lea r10, L_Thread3(rip)", "1.3 mov r1, r3", and "L_loop_1:1.4 add(addr1) in the instruction block 1 in sequence , R1" and "1.5 mul r1, r2".
  • block 830 it is determined whether the currently running instruction is a branch instruction. If it is a transfer instruction, determine whether the transfer instruction instructs the thread to exit.
  • the logic register has a flag bit for indicating the use state of the logic register, and the use state includes a first state for indicating normal use and a second state for indicating that the logic register points to another logic register.
  • the flag bit can use "0" to indicate the first state and "1" to indicate the second state.
  • the processing core recognizes that L_loop_i in the leakxj instruction is a specified value (for example, 0xfffffffffffffffffffffffff)
  • the thread exit processing is executed. Specifically, the processing core releases the physical register pointed to by the corresponding logical register so that the corresponding logical register points to the logical register used by the next thread, and assigns the flag bit of the corresponding logical register to “1”.
  • the command value is set to a value that cannot be recognized by the CPU or is recognized as invalid after being read, for example, 0xfffffffffffffffffffffffffffff.
  • the thread exit mechanism will be described below with reference to FIG. 9.
  • L_loop_i in the leaxxj instruction is not a specified value, it returns to block 810, retrieves the next instruction block, and executes the next loop operation.
  • retrieve instruction block 2 which includes instructions "1.6 mov r2, addr2", “1.7 sub $1, r3" and "1.8 leaaj L_loop_1(r4), r6", and execute the next loop operation.
  • FIG. 9 shows a schematic diagram of a thread example of thread exit processing according to an embodiment of the present specification.
  • the threads for thread fusion include threads Thread1, Thread2, Thread3, Thread4, and Thread5.
  • the logical register r1 has been initialized to point to the program corresponding address of thread Thread-1
  • the logical register r2 points to the program corresponding address of thread Thread-2
  • the logical register r3 points to the program corresponding to thread Thread-3.
  • the logical register r4 points to the program corresponding address of the thread Thread-4
  • the logical register r5 points to the program corresponding address of the thread Thread-5.
  • the CPU is also provided with a transfer register, which is used to retain the destination logic register of the last normal jump.
  • a transfer register which is used to retain the destination logic register of the last normal jump.
  • Thread-1 normally executes the instruction leaxxj.L_target_1(r1), r2, it is jumping At the same time, the logic register r2 needs to be stored in the transfer register.
  • Thread-2 also executes the instructions leaxxj.L_target_1(r2), r3 normally, it needs to store the logic register r3 in the transfer register to replace the last time while jumping.
  • the default value of the transfer register is "0".
  • the registers r1, r2, r3, r4, and r5 used in the thread program are all logical registers, and the logical registers point to physical registers. Therefore, the mapping relationship between logical and physical registers can be changed. To change the content stored in the register, and combine with the transfer register to realize the end of the thread.
  • a flag bit L is added to each logic register to indicate the use status of the logic register.
  • the use state may include a first state for indicating that the logical register is normally used, and a second state for indicating that the content pointed to by the logical register is another logical register.
  • the value "0" may be used to indicate the first state
  • the value "1" may be used to indicate the second state.
  • the transfer register After a period of normal operation, when the thread Thread-1 jumps normally, the transfer register stores the logical register r2, and then jumps to the thread Thread-2 to start the thread Thread-2.
  • the thread Thread-2 will end during operation, it will be represented by the instruction leakxj 0xff ff ff ff ff ff(r2), r3. Since any offset address cannot be 0xff ff ff ff ff ff ff ff ff, when the CPU runs this instruction, if it finds that it is necessary to put 0xff ff ff ffffffffffffffffffffffffffffffffff, when the CPU runs this instruction, if it finds that it is necessary to put 0xff ffffffffffffffff into the logical register r2, it is because the transfer register The logical register r2 is stored.
  • the CPU will release the physical register pointed to by the logical register r2 (if any), and at the same time make the logical register r2 point to the physical register space into the logical register used by thread Thread-3 (that is, logical Register r3), and set the flag L of logical register r2 to 1.
  • the CPU will find the real physical register according to the logical register (r3) stored in the logical register r2 at this time.
  • thread Thread-3 After running for a period of time, if thread Thread-3 also executes the command leakxj 0xff ff ff ff ff ff(r3), r4, at this time, because thread Thread-2 has exited, it will jump from thread Thread-1 to thread Thread -3, so the transfer register is stored in the logical register r2.
  • the CPU stores the space pointed to by the logical register r2 to the physical register in the logical register r4 used by the thread Thread-4, and the flag L of the logical register r2 is set to 1. In this way, when the thread Thread-1 executes the instruction leaxxj.L_target_1(r1), r2 again, it will jump directly from the thread Thread-1 to the thread Thread-4, and so on.
  • the transfer register is stored in logical register r2, then put the logical register used by thread Thread-5 (ie, logical register r5) in the space of r2 pointing to the physical register, then Thread-1 will directly Jump into Thread-5, but when Thread-5 needs to exit, the transfer register is stored in the logical register r2 at this time, and the space where r2 points to the physical register is put into the logical register used by thread Thread-1 (ie , Logical register r1), so when Thread-1 exits, it is found that the logical register pointed to by logical register r2 is itself (ie, r1), then exit normally and complete the entire operation.
  • FIG. 10 shows a block diagram of a multithreading compiling apparatus 1000 according to an embodiment of the present specification.
  • the multi-thread compiling apparatus 1000 includes a thread compiling unit 1010 and a thread fusion unit 1020.
  • the thread compiling unit 1010 is configured to use different first logical register sets for compiling for each thread of the first number of threads to be processed to obtain the corresponding machine instruction code.
  • the operation of the thread compiling unit 1010 may refer to the operation of the block 510 described above with reference to FIG. 5.
  • the thread fusion unit 1020 is configured to use the first instruction in the instruction set supported by the processing core to perform fusion processing on the machine instruction code of each thread to obtain the machine code instruction of a single fused thread.
  • the first instruction includes an effective address fetch instruction and a transfer instruction
  • the effective address fetch instruction and the transfer instruction are compiled using a second logical register different from the first logical register set
  • the transfer instruction is set
  • the machine instruction codes corresponding to the respective threads are used to implement jump operations between the machine instruction codes of the respective threads.
  • the operation of the thread fusion unit 1020 may refer to the operation of the block 520 described above with reference to FIG. 5 and the operations described with reference to FIGS. 6 to 9.
  • the multithreading compiling apparatus 1000 may further include a transfer instruction obtaining unit (not shown).
  • the transfer instruction obtaining unit obtains the first transfer instruction by modifying all or part of the jump instructions in the machine instruction code of each thread.
  • the transfer instruction obtaining unit further adds a second transfer instruction based on the transfer instruction addition rule.
  • the branch instruction adding rule includes: making the branch instructions to be separated from each other by no more than a second predetermined number of instructions; and/or using an instruction compiler tuning strategy to add the second branch instruction after a suitable machine instruction.
  • the above multi-threaded compiling device/multi-threaded processing system can be implemented by hardware, or by software or a combination of hardware and software.
  • Fig. 11 is a structural block diagram of a computing device for multi-thread processing according to an embodiment of the present specification.
  • the computing device 1100 may include at least one processor 1110, a memory (for example, a non-volatile memory) 1120, a memory 1130, a communication interface 1140, and an internal bus 1160, and at least one processor 1110, a memory 1120, The memory 1130 and the communication interface 1140 are connected together via a bus 1160.
  • the at least one processor 1110 executes at least one computer-readable instruction (that is, the above-mentioned element implemented in the form of software) stored or encoded in a computer-readable storage medium.
  • computer-executable instructions are stored in the memory, which, when executed, cause at least one processor 1110: for each thread of the first number of threads to be processed, a different first logical register set is used to Compile to obtain the corresponding machine instruction code; and use the first instruction in the instruction set supported by the processing kernel to merge the machine instruction code of each thread to obtain the machine instruction code of a single fused thread, where the first instruction Including effective address fetching instructions and transfer instructions, the effective address fetching instructions and transfer instructions are compiled by using a second logical register different from the first logical register set, and the transfer instructions are set in the machine instruction code corresponding to each thread , Used to realize the jump operation between the machine instruction codes of each thread.
  • a program product such as a non-transitory machine-readable medium.
  • the non-transitory machine-readable medium may have instructions (ie, the above-mentioned elements implemented in the form of software), which, when executed by a machine, cause the machine to execute the various embodiments described above in conjunction with FIGS. Operation and function.
  • a system or device equipped with a readable storage medium may be provided, and the software program code for realizing the function of any one of the above embodiments is stored on the readable storage medium, and the computer or device of the system or device The processor reads out and executes the instructions stored in the readable storage medium.
  • the program code itself read from the readable medium can realize the function of any one of the above embodiments, so the machine readable code and the readable storage medium storing the machine readable code constitute the present invention a part of.
  • Examples of readable storage media include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tape, Volatile memory card and ROM.
  • the program code can be downloaded from a server computer or cloud via a communication network.
  • the device structure described in the foregoing embodiments may be a physical structure or a logical structure. That is, some units may be implemented by the same physical entity, or some units may be implemented by multiple physical entities, or may be implemented by multiple physical entities. Some components in independent devices are implemented together.
  • the hardware unit or module can be implemented mechanically or electrically.
  • a hardware unit, module or processor may include permanent dedicated circuits or logic (such as a dedicated processor, FPGA or ASIC) to complete the corresponding operation.
  • the hardware unit or processor may also include programmable logic or circuits (such as general-purpose processors or other programmable processors), which may be temporarily set by software to complete corresponding operations.
  • the specific implementation mode mechanical method, or dedicated permanent circuit, or temporarily set circuit

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Abstract

本说明书实施例提供一种用于多线程处理的方法及装置。在该方法中，针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码；以及使用处理内核所支持的指令集中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码，其中，所述第一指令包括取有效地址指令和转移指令，所述取有效地址指令和转移指令利用与第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在各个线程所对应的机器指令代码中，用于实现各个线程的机器指令代码之间的跳转操作。

Description

用于多线程处理的方法、装置及系统 技术领域
本说明书实施例通常涉及计算机应用技术，更具体地，涉及用于多线程处理的方法、装置及系统。
背景技术
在多线程处理机制中，处理内核(例如，CPU)根据线程数据在每个指令周期以轮询的方式进行指令存取和解码操作，完成之后将指令放到对应的硬件指令解码队列中，同时CPU执行单元在每个指令周期会轮询地从每个硬件指令解码队列得到解码后的指令，然后放入CPU执行单元开始运行。
在上述多线程处理机制中，CPU会为每个线程准备一个独立的硬件运行环境，以便运行该线程。例如，CPU会为每个线程准备对应的指令预测、指令执行、指令提交等硬件资源。通常，在所运行的线程从1个增加到2个时，会增加5％的硬件成本。多线程处理机制所运行的线程数目越多，需要增加的硬件成本也会越多。
发明内容
鉴于上述问题，本说明书实施例提供了一种用于多线程处理的方法、装置及系统。利用该方法、装置及系统，能够将多个线程融合为单个融合线程来运行，从而在无需增加硬件成本的情况下实现多线程处理。
根据本说明书实施例的一个方面，提供了一种用于多线程处理的方法，包括：针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码；以及使用处理内核所支持的指令集中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码，其中，所述第一指令包括取有效地址指令和转移指令，所述取有效地址指令和转移指令利用与所述第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在所述各个线程所对应的机器指令代码中，用于实现所述各个线程的机器指令代码之间的跳转操作。
可选地，在上述方面的一个示例中，所述第一数目不超过第一预定阈值，所述第 一预定阈值是基于所述处理内核可使用的逻辑寄存器的数目来确定的。
可选地，在上述方面的一个示例中，所述转移指令包括通过对所述各个线程的机器指令代码中的全部或部分跳转指令进行修改而获得的第一转移指令。
可选地，在上述方面的一个示例中，所述转移指令还包括基于转移指令增加规则增加的第二转移指令。
可选地，在上述方面的一个示例中，所述转移指令增加规则包括：使得所述转移指令彼此间隔不超过第二预定数目条指令；和/或使用指令编译器调优策略来在合适的机器指令之后增加所述第二转移指令。
可选地，在上述方面的一个示例中，所述第二预定数目是基于所述处理内核在单个指令周期所能执行的指令数目确定的。
可选地，在上述方面的一个示例中，经过融合后的每个线程具有基于转移指令分割出的至少一个指令跳转块。
可选地，在上述方面的一个示例中，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器，以及针对所述第一数目个线程中的每个线程中的每个指令跳转块，所述取有效地址指令包括两条第二取有效地址指令，其中，一条第二取有效地址指令用于将该指令跳转块的第一条指令的地址传送到对应的第二逻辑寄存器，另一第二取有效地址指令用于将位于该指令跳转块之后的第一条指令的地址传送到对应的第二逻辑寄存器，所述两条第二取有效地址指令被放置在各自线程的对应指令跳转块和上一指令跳转块之间，以及所述转移指令包括条件传送指令和无条件跳转指令。
可选地，在上述方面的一个示例中，所述指令集包括leaxxj指令，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所述第一取有效地址指令用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器，并且所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，以及针对所述第一数目个线程中的各个线程中的每个指令跳转块，所述转移指令包括单条leaxxj指令，其中，所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，逻辑寄存器rm表示对应的指令跳转块所属线程的第一取有效地址指令所使用的第二逻辑寄存器，以及逻辑寄存器rn表示需要跳转到的线程的第一取有效地址指 令所使用的第二逻辑寄存器，所述leaxxj指令用于指示在条件满足时将L_loop_i所指向的指令地址放入逻辑寄存器rm，在条件不满足时将所述leaxxj指令之后的第一条指令的指令地址放入逻辑寄存器rm，并且跳转到逻辑寄存器rn中存储的地址所对应的指令。
可选地，在上述方面的一个示例中，所述第二逻辑寄存器具有用于指示该第二逻辑寄存器的使用状态的标志位，所述使用状态包括用于表示正常使用的第一状态和用于表示该逻辑寄存器指向另一逻辑寄存器的第二状态，在进行机器指令运行时，如果所述处理内核识别出leaxxj指令中的L_loop_i被赋值为指定数值，则释放第二逻辑寄存器rn所指向的物理寄存器，使得第二逻辑寄存器rn指向目标跳转线程所使用的第二逻辑寄存器，并且将第二逻辑寄存器rn的标志位赋值为指示第二状态。
可选地，在上述方面的一个示例中，在进行机器指令运行时，如果所述处理内核已经取回leaxxj指令，则将与所述leaxxj指令中的逻辑寄存器rn所存放的地址对应的指令块预取到所述处理内核的指令解码队列中。
可选地，在上述方面的一个示例中，所述方法还包括：经由所述处理内核来以指令块为单位获取所述融合线程中的机器指令来运行。
可选地，在上述方面的一个示例中，所述指令块的大小由所述处理内核在单个指令周期读取指令的能力来确定。
可选地，在上述方面的一个示例中，在所获取的指令块中包括转移指令并且该指令块的结束指令不是所述转移指令时，将该指令块调整为以所述转移指令为结束指令。
根据本说明书实施例的另一方面，提供一种用于多线程处理的装置，包括：线程编译单元，针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码；以及线程融合单元，使用处理内核所支持的指令集中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码，其中，所述第一指令包括取有效地址指令和转移指令，所述取有效地址指令和转移指令利用与所述第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在所述各个线程所对应的机器指令代码中，用于实现所述各个线程的机器指令代码之间的跳转操作。
可选地，在上述方面的一个示例中，所述装置还包括：转移指令获得单元，通过对所述各个线程的机器指令代码中的全部或部分跳转指令进行修改而获得的第一转移指令。
可选地，在上述方面的一个示例中，所述转移指令获得单元进一步基于转移指令增加规则增加第二转移指令。
可选地，在上述方面的一个示例中，所述转移指令增加规则包括：使得所述转移指令彼此间隔不超过第二预定数目条指令；和/或使用指令编译器调优策略来在合适的机器指令之后增加所述第二转移指令。
可选地，在上述方面的一个示例中，经过融合后的每个线程具有基于转移指令分割出的至少一个指令跳转块。
可选地，在上述方面的一个示例中，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器，以及针对所述第一数目个线程中的每个线程中的每个指令跳转块，所述取有效地址指令包括两条第二取有效地址指令，其中，一条第二取有效地址指令用于将该指令跳转块的第一条指令的地址传送到对应的第二逻辑寄存器，另一第二取有效地址指令用于将位于该指令跳转块之后的第一条指令的地址传送到对应的第二逻辑寄存器，所述两条第二取有效地址指令被放置在各自线程的对应指令跳转块和上一指令跳转块之间，以及所述转移指令包括条件传送指令和无条件跳转指令。
可选地，在上述方面的一个示例中，所述指令集包括leaxxj指令，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所述第一取有效地址指令用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器，并且所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，以及针对所述第一数目个线程中的各个线程中的每个指令跳转块，所述转移指令包括单条leaxxj指令，其中，所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，逻辑寄存器rm表示对应的指令跳转块所属线程的第一取有效地址指令所使用的第二逻辑寄存器，以及逻辑寄存器rn表示需要跳转到的线程的第一取有效地址指令所使用的第二逻辑寄存器，所述leaxxj指令用于指示在条件满足时将L_loop_i指向的指令地址放入逻辑寄存器rm，在条件不满足时将所述leaxxj指令之后的第一条指令的指令地址放入逻辑寄存器rm，并且跳转到逻辑寄存器rn中存储的地址所对应的指令。
根据本说明书实施例的另一方面，提供一种用于多线程处理的系统，包括：编译器，包括如上所述的用于多线程处理的装置，将第一数目个线程编译为单个融合线程的机器指令代码；指令集；以及处理内核，以指令块为单位获取所述融合线程中的机器指 令来运行。
可选地，在上述方面的一个示例中，所述指令集包括leaxxj指令，所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，逻辑寄存器rm表示对应的指令跳转块所属线程的第一取有效地址指令所使用的第二逻辑寄存器，以及逻辑寄存器rn表示需要跳转到的线程的第一取有效地址指令所使用的第二逻辑寄存器，所述leaxxj指令用于指示在条件满足时将L_loop_i所指向的指令地址放入逻辑寄存器rm，在条件不满足时将所述leaxxj指令之后的第一条指令的指令地址放入逻辑寄存器rm，并且跳转到逻辑寄存器rn中存储的地址所对应的指令。
可选地，在上述方面的一个示例中，所述第二逻辑寄存器具有用于指示该第二逻辑寄存器的使用状态的标志位，所述使用状态包括用于表示正常使用的第一状态和用于表示该逻辑寄存器指向另一逻辑寄存器的第二状态，在进行机器指令运行时，如果所述处理内核识别出leaxxj指令中的L_loop_i被赋值为指定数值，则所述处理内核释放第二逻辑寄存器rn所指向的物理寄存器，使得第二逻辑寄存器rn指向目标跳转线程所使用的第二逻辑寄存器，并且将第二逻辑寄存器rn的标志位赋值为指示第二状态。
可选地，在上述方面的一个示例中，在进行机器指令运行时，如果所述处理内核已经取回leaxxj指令，则所述处理内核将与所述leaxxj指令中的逻辑寄存器rn所存放的地址对应的指令块预取到所述处理内核的指令解码队列中。
根据本说明书实施例的又一方面，提供一种计算设备，包括：一个或多个处理器，以及与所述一个或多个处理器耦合的存储器，所述存储器存储指令，当所述指令被所述一个或多个处理器执行时，使得所述至少一个处理器执行如上所述的用于多线程处理的方法。
根据本说明书实施例的再一方面，提供一种机器可读存储介质，其存储有可执行指令，所述指令当被执行时使得所述机器执行如上所述的用于多线程处理的方法。
附图说明
通过参照下面的附图，可以实现对于本说明书实施例的内容的本质和优点的进一步理解。在附图中，类似组件或特征可以具有相同的附图标记。
图1示出了现有技术中的多线程处理过程的示意图；
图2示出了现有技术中的用于对多个线程进行编译处理的示例示意图；
图3示出了指令运行过程的示例示意图；
图4示出了根据本说明书的实施例的多线程处理系统的方框图；
图5示出了根据本说明书的实施例的用于多线程处理的方法流程图；
图6示出了根据本说明书的实施例的线程融合处理的一个示例示意图；
图7示出了根据本说明书的实施例的线程融合处理的另一示例示意图；
图8示出了根据本说明书的实施例的融合线程运行过程的流程图；
图9示出了根据本说明书的实施例的线程退出处理的线程示例示意图；
图10示出了根据本说明书的实施例的多线程编译装置的方框图；
图11示出了根据本说明书的实施例的用于多线程处理的计算设备的方框图。
具体实施方式
现在将参考示例实施方式讨论本文描述的主题。应该理解，讨论这些实施方式只是为了使得本领域技术人员能够更好地理解从而实现本文描述的主题，并非是对权利要求书中所阐述的保护范围、适用性或者示例的限制。可以在不脱离本说明书实施例的内容的保护范围的情况下，对所讨论的元素的功能和排列进行改变。各个示例可以根据需要，省略、替代或者添加各种过程或组件。例如，所描述的方法可以按照与所描述的顺序不同的顺序来执行，以及各个步骤可以被添加、省略或者组合。另外，相对一些示例所描述的特征在其它例子中也可以进行组合。
如本文中使用的，术语“包括”及其变型表示开放的术语，含义是“包括但不限于”。术语“基于”表示“至少部分地基于”。术语“一个实施例”和“一实施例”表示“至少一个实施例”。术语“另一个实施例”表示“至少一个其他实施例”。术语“第一”、“第二”等可以指代不同的或相同的对象。下面可以包括其他的定义，无论是明确的还是隐含的。除非上下文中明确地指明，否则一个术语的定义在整个说明书中是一致的。
图1示出了现有技术中的多线程处理过程100的示意图。
如图1所示，多线程处理过程100可以包括线程编译过程110和线程运行过程120。
具体地，在线程编译过程110中，针对待处理的多个线程中的各个线程，使用相同的逻辑寄存器集合来进行编译以得到对应的机器指令代码。这里，逻辑寄存器是指在 程序代码中使用的寄存器，并且逻辑寄存器指向物理寄存器。
图2示出了现有技术中的用于对多个线程进行编译处理的示例示意图。在图2中，示出了3个线程Thread1、Thread2和Thread3。如图2所示，Thread1、Thread2和Thread3使用了相同的逻辑寄存器集合{r1，r2，r3，r4，……}来进行编译。其中，线程Thread1使用了逻辑寄存器r1-r3，线程Thread2使用了逻辑寄存器r1和r3，以及线程Thread3使用逻辑寄存器r1，r2和r4。
在本说明书的实施例中，每条机器指令包括操作码和操作数，其中，操作码用于指明指令所要完成操作的性质和功能，比如，add，mul，mov，sub，jmp等。操作数用于指明操作码执行时的操作对象。操作数的形式可以是数据本身.也可以是存放数据的内存单元地址或寄存器名称。操作数又分为源操作数和目的操作数，源操作数指明参加运算的操作数来源，目的操作数地址指明保存运算结果的存储单元地址或寄存器名称。
此外，处理内核(例如，中央处理器CPU)还为多个线程中的每个线程创建独立的线程运行环境。所述线程运行环境包括用于执行指令预测的硬件资源、用于执行指令执行的硬件资源，用于执行指令提交的硬件资源等。另外，还为多个线程中的每个线程创建各自的硬件指令解码队列。
在线程运行过程120中，CPU根据线程数据在每个指令周期以轮询的方式进行指令存取和解码操作，完成之后将指令放到各自的硬件指令解码队列中。同时，CPU执行单元在每个指令周期会轮询地从每个硬件指令解码队列得到解码后的指令，然后放入CPU执行单元开始运行。
图3示出了指令运行过程的示例示意图。
如图3所示，在块310，执行指令获取(Instruction Fetch，IF)操作。指令获取操作是指将待运行的指令从主存中取到指令寄存器中。程序计数器PC中的数值用来指示当前指令在主存中的位置。当一条指令被取出后，PC中的数值将根据指令字长度而自动递增：若为单字长指令，则增加1个字节；若为双字长指令，则增加2个字节，依此类推。
在取出待运行指令后，在块320，执行指令译码(Instruction Decode，ID)操作。在指令译码操作中，指令译码器按照预定的指令格式，对取回的指令进行拆分和解释，识别区分出不同的指令类别以及各种获取操作数的方法。在组合逻辑控制的计算机中，指令译码器对不同的指令操作码产生不同的控制电位，以形成不同的微操作序列。在微 程序控制的计算机中，指令译码器用指令操作码来找到执行该指令的微程序的入口，并从此入口开始执行。
在完成指令译码操作后，在块330，进行指令执行(Execution，EX)操作。在指令执行操作中，完成指令所规定的各种操作来实现指令功能。为此，CPU的不同组件部分被连接起来，以执行所需操作。例如，如果要求完成加法运算，则算术逻辑单元ALU将被连接到一组输入和一组输出，输入端提供需要相加的数值，输出端将含有最后的运算结果。
此外，可选地，在块340，根据指令需要，执行操作数存取操作。在操作数存取操作中，根据指令地址码得到操作数在主存中的地址，并从主存中读取该操作数以用于运算。
在完成指令运行后，在块350，执行结果写回(Writeback，WB)操作。在结果回写操作中，将指令执行操作的运行结果数据“写回”到某种存储单元中。例如，结果数据经常被写到CPU的内部寄存器中，以便被后续的指令快速地存取。在有些情况下，结果数据也可以被写入相对较慢、但较廉价且容量较大的主存。许多指令还会改变程序状态字寄存器中标志位的状态，这些标志位用于标识不同的操作结果，可被使用来影响程序动作。
在指令执行完毕并且完成结果数据写回操作后，若无意外事件(例如，结果溢出等)发生，处理内核就从程序计数器PC中取得下一条指令地址，开始新一轮的指令运行过程。
图3中示出的是单个线程中的指令运行过程的示意图。在多线程处理机制中，操作系统使用线程调度机制来在多个线程之间进行线程切换。例如，操作系统为CPU允许并行执行的多个线程中的每个线程分配一个时间片，各个线程在各自的时间片内占用CPU来执行指令运行操作。当前线程的时间片使用完毕后就会处于就绪状态，并且让出CPU给其它线程占用。此外，如果线程的任务在自己的时间片结束前被阻塞或结束，则会马上进行线程切换，而不会造成CPU资源浪费。
此外，还可以使用超线程机制来实现多线程处理。超线程机制是指在一个线程执行整数指令集时，其它线程所执行的任务是由与执行当前线程的任务的执行单元不同的执行单元执行的任务，比如，浮点指令集。在这种情况下，可以同时执行这两个线程。超线程技术允许两个线程同时不冲突地使用CPU中的资源。
在上面的多线程处理方案中，CPU需要为每个线程准备一个独立的硬件运行环境来运行该线程，从而需要更多的硬件成本。多线程处理机制所运行的线程数目越多，需要增加的硬件成本也会越多。在这种多任务处理方案中，并行处理的线程数目受限于用于线程处理的硬件条件。
为了解决上述问题，本说明书实施例提供了一种多线程处理方案。在该多线程处理方案中，通过使用不同的寄存器集合来分别编译多个线程，并且使用处理内核所支持的指令集中的取有效地址指令和转移指令来将多个线程融合为单个融合线程，然后基于所得到的融合线程来运行，由此实现多线程处理。在这种情况下，仅仅需要提供单个线程运行所需的硬件成本，从而能够在无需增加硬件成本的情况下实现多线程处理。
图4示出了根据本说明书的实施例的多线程处理系统400的方框图。如图4所示，多线程处理系统400包括多线程编译装置410、指令集420和处理内核430。
多线程编译装置410被配置为使用不同的第一逻辑寄存器集合来分别编译待处理的第一数目个线程中的各个线程，以得到各个线程的机器指令代码，并且使用处理内核所支持的指令集420中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码。所得到的单个融合线程的机器指令代码被处理内核430获取来进行指令运行。这里，所述第一指令包括取有效地址指令(Lea指令)和转移指令，所述取有效地址指令和转移指令利用与第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在各个线程所对应的机器指令代码中，用于实现各个线程的机器指令代码之间的跳转操作。多线程编译装置410的操作和结构将在下面分别参照图5-图7和图9详细描述。
这里要说明的是，第一逻辑寄存器集合和第二逻辑寄存器都属于处理内核430可使用的逻辑寄存器。在本说明书的实施例中，可以通过对处理内核430可使用的逻辑寄存器进行分割处理来得到第一逻辑寄存器集合和第二逻辑寄存器。
处理内核430被配置为以指令块为单位获取融合线程中的机器指令来运行。在本说明书实施例的一个示例中，指令块的大小可以由处理内核在单个指令周期读取指令的能力来确定。此外，在所获取的指令块中包括转移指令并且该指令块的结束指令不是转移指令时，可以将该指令块调整为以转移指令为结束指令。处理内核430的操作将在下面参照图8详细描述。
图5示出了根据本说明书的实施例的用于多线程处理的方法流程图。
如图5所示，在块510，针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码。在本说明书的实施例中，逻辑寄存器集合不同是指逻辑寄存器集合中的包括的所有逻辑寄存器都不同。此外，逻辑寄存器集合是通过对处理内核可使用的逻辑寄存器进行分割而得到的。例如，假设处理内核可使用的逻辑寄存器包括逻辑寄存器r1-r10，则逻辑寄存器集合是通过对逻辑寄存器r1-r10进行分割而得到的。在本说明书实施例的一个示例中，第一数目被设置为不超过第一预定阈值。所述第一预定阈值是基于处理内核可使用的逻辑寄存器的数目来确定的。例如，在一个示例中，可以基于处理内核可使用的逻辑寄存器的数目以及待处理的线程所需逻辑寄存器的数目确定所述第一预定阈值。此外，在本说明书实施例的另一示例中，第一数目可以通过软件来任意设定。在这种情况下，如果所设定的第一数目超过处理内核可使用的逻辑寄存器的数目或者第一数目个线程所需逻辑寄存器的数目超过处理内核可使用的逻辑寄存器的数目，则可以使用压栈的方式来实现线程编译。
图6示出了根据本说明书的实施例的线程融合处理的一个示例示意图；以及图7示出了根据本说明书的实施例的线程融合处理的另一示例示意图。图6和图7中示出的是对图2中示出的线程Thread1、Thread2和Thread3的线程融合处理。在图6中，使用逻辑寄存器r1-r3组成的第一逻辑寄存器集合来对线程Thread1进行编译，使用逻辑寄存器r8-r9组成的第一逻辑寄存器集合来对线程Thread2进行编译，以及使用逻辑寄存器r12-r14组成的第一逻辑寄存器集合来对线程Thread3进行编译。在图7中，使用逻辑寄存器r1-r3组成的第一逻辑寄存器集合来对线程Thread1进行编译，使用逻辑寄存器r8-r9组成的第一逻辑寄存器集合来对线程Thread2进行编译，以及使用逻辑寄存器r11-r13组成的第一逻辑寄存器集合来对线程Thread3进行编译。
在如上得到各个线程的机器指令代码后，在块520，使用处理内核所支持的指令集420中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码。这里，所述第一指令包括取有效地址指令(Lea指令)和转移指令，所述取有效地址指令和转移指令利用与所述第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在所述各个线程所对应的机器指令代码中，用于实现所述各个线程的机器指令代码之间的跳转操作。
取有效地址指令也称为LEA指令，是微机8086/8088系列的一条指令。LEA指令的指令格式为：LEA操作数A，操作数B。LEA指令的指令功能：将操作数B的有效地址传送到操作数A所在的单元。这里，操作数A是目的操作数，以及操作数B是源 操作数。LEA指令要求源操作数B必须是存储单元，而且目的操作数A必须是寄存器。
例如，在图6所示的方案中，针对线程Thread1，使用逻辑寄存器r4和r5作为第二逻辑寄存器来编译与线程Thread1相关的第一指令，针对线程Thread2，使用逻辑寄存器r6和r7作为第二逻辑寄存器来编译与线程Thread2相关的第一指令，以及针对线程Thread3，使用逻辑寄存器r10和r11作为第二逻辑寄存器来编译与线程Thread3相关的第一指令。在图7中示出的示例中，针对线程Thread1，使用逻辑寄存器r4作为第二逻辑寄存器来编译与线程Thread1相关的第一指令，针对线程Thread2，使用逻辑寄存器r6作为第二逻辑寄存器来编译与线程Thread2相关的第一指令，以及针对线程Thread3，使用逻辑寄存器r10作为第二逻辑寄存器来编译与线程Thread3相关的第一指令。关于如何使用第一指令来进行融合处理，将在下面参照图6和图7的示例来进行说明。
在一个示例中，所述转移指令可以包括通过对各个线程的机器指令代码中的全部或部分跳转指令进行修改而获得的第一转移指令。例如，在图6中，针对线程Thread1，对图2中的线程Thread1中的跳转指令“1.6 ja L_loop_1”进行修改而得到的转移指令“1.10 cmovbe r5，r4”和“1.11 jmp r6”，对图2中的线程Thread1中的跳转指令“1.14 jbe L_loop_2”进行修改而得到的转移指令“1.21 cmovbe r5，r4”和“1.22 jmp r6”，但是对图2中的线程Thread1中的跳转指令“1.9 ja L_sub_again”不进行修改。针对线程Thread2，对图2中的线程Thread2中的全部跳转指令“2.7 ja L_loop_3”进行修改而得到的转移指令“2.9 cmovbe r7，r6”和“2.10 jmp r10”。针对线程Thread3，通过对图2中的线程Thread3中的全部跳转指令“3.6 ja L_loop_4”进行修改而得到的转移指令“3.8 cmovbe r11，r10”和“3.9 jmp r4”。在图6中示出的示例中，转移指令包括条件传送指令cmovbe和无条件跳转指令jmp。这里要说明的是，图6中示出的cmovbe指令仅仅是示例。在本说明书实施例的其它示例中，条件传送指令可以包括cmovle指令，cmovnz指令等。
在图7中，针对线程Thread1，对图2中的线程Thread1中的跳转指令“1.6 ja L_loop_1”进行修改而得到转移指令“1.8 leaaj L_loop_1(r4)，r6”，以及对图2中的线程Thread1中的跳转指令“1.14 jbe L_loop_2”进行修改而得到转移指令“1.16 leaaj L_loop_2(r4)，r6”。同样，对图2中的线程Thread1中的跳转指令“1.9 ja L_sub_again”不进行修改。针对线程Thread2，对图2中的线程Thread2中的跳转指令“2.7 ja L_loop_3”进行修改而得到转移指令“2.7 leaaj L_loop_3(r6)，r10”。针对线程Thread3，对图2中的线程Thread3中的跳转指令“3.6 ja L_loop_4”进行修改而得到转移指令“3.6 leaaj L_loop_4 (r10)，r4”。这里，leaaj指令是条件转移指令。关于leaaj指令的具体结构和含义将在下面具体描述。
在该示例中，利用各个线程的机器指令代码中的现有跳转指令来修改得到用于线程融合的转移指令，可以减少融合后的线程中的指令数目，由此提高融合线程的效率。
此外，在另一示例中，所述转移指令可以包括基于转移指令增加规则增加的第二转移指令。这里，第二转移指令不是基于各个线程中的原有指令修改得到的，而是增加的新指令。例如，假设线程Thread1、线程Thread2和/或线程Thread3中都不包含跳转指令，或者线程Thread1、线程Thread2和/或线程Thread3中所包含的跳转指令之间的指令间隔太大(例如，超过预定数目，比如，处理内核在单个指令周期所能执行的指令数目)，则可以在对应的线程中，基于转移指令增加规则增加第二条件转移指令。
在本说明书实施例中，所述转移指令增加规则可以包括：使得转移指令彼此间隔不超过第二预定数目条指令；和/或使用指令编译器调优策略来在合适的机器指令之后增加第二转移指令。这里，所述第二预定数目可以是基于处理内核在单个指令周期所能执行的指令数目确定的。
在本说明书实施例中，“使得所述转移指令彼此间隔不超过第二预定数目条指令”是指线程中的转移指令(第一转移指令和/或第二转移指令)之间的间隔不超过第二预定数目条指令。
“使用指令编译器调优策略来在合适的机器指令之后增加第二转移指令”是指通过循环测试的策略来确定可以使得编译器效率最佳的转移指令增加方式。
在该示例中，在融合前的线程中缺少跳转指令的情况下，通过按照转移指令增加规则来增加转移指令，可以使得融合后的线程能够在合适的时机进行线程跳转，由此提高融合后的线程的运行效率。
此外，在经过上述融合处理后，经过融合后的每个线程具有基于转移指令分割出的至少一个指令跳转块。例如，在图6中的融合方案中，针对线程Thread1，具有2个指令跳转块，即，从指令“L_loop_1:1.6 add(addr1)，r1”到指令“1.11 jmp r6”的第一指令跳转块，以及从指令“L_loop_2:1.17 sub(addr1)，r4”到指令“1.22 jmp r6”的第二指令跳转块。针对线程Thread2，具有1个指令跳转块，即，从指令“L_loop_3:2.5 add(addr2)，r8”到指令“2.10 jmp r10”的第三指令跳转块。针对线程Thread3，具有1个指令跳转块，即，从指令“L_loop_4:3.4 sub(addr3)，r14”到指令“3.9 jmp r4”的第四 指令跳转块。
在本说明书实施例的融合处理方案的一个示例中，如图6中所示，针对除第一数目个线程中的第一线程之外的每个线程，取有效地址指令包括单条第一取有效地址指令，并且所有第一取有效地址指令都被放置在融合线程的机器指令代码的开始处，用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器。例如，图6中示出第一取有效指令“1.1 lea r6，L_Thread2(rip)”和“1.2 lea r10，L_Thread3(rip)”，其中，第一取有效指令“1.1 lea r6，L_Thread2(rip)”与线程Thread2对应，以及第一取有效指令“1.2 lea r10，L_Thread3(rip)”与线程Thread3对应。
此外，在图6中示出的示例中，针对第一数目个线程中的每个线程中的每个指令跳转块，取有效地址指令包括两条第二取有效地址指令，其中，一条第二取有效地址指令用于将该指令跳转块的第一条指令的地址传送到对应的第二逻辑寄存器，另一第二取有效地址指令用于将位于该指令跳转块之后的第一条指令的地址传送到对应的第二逻辑寄存器，所述两条第二取有效地址指令被放置在各自线程的对应指令跳转块和上一指令跳转块之间，以及所述转移指令包括条件传送指令和无条件跳转指令。
如图6中所示，针对线程Thread1中的第一指令跳转块，存在两条第二取有效地址指令“1.4 lea r5，Leave_loop_1(rip)”和“1.5 lea r4 L_loop_1(rip)”，即，将指令“L_loop_1：1.6 add(addr1)，r1”(即，L_loop_1所指向的指令)的地址传送(存放)到逻辑寄存器r4，以及将指令“Leave_loop_1：L_sub_again 1.12 sub r1，r3”(即，Leave_loop_1所指向的指令)的地址传送(存放)到逻辑寄存器r5。并且该两条第二取有效地址指令被放置在指令“L_loop_1:1.6 add(addr1)，r1”之前。针对线程Thread1中的第二指令跳转块，存在两条第二取有效指令“1.15 lea r5，Leave_loop_2(rip)”和“1.16 lea r4 L_loop_2(rip)”，即，将指令“L_loop_2：1.17 sub(addr1)，r4”的地址传送(存放)到逻辑寄存器r4，以及将指令“Leave_loop_2……”的地址传送(存放)到逻辑寄存器r5。并且该两条第二取有效地址指令被放置在指令“Leave_loop_1:L_sub_again”和指令“L_loop_2:1.17 sub(addr1)，r4”之间，即，第一指令跳转块和第二指令跳转块之间。通常，该两条第二取有效地址指令被优选放置为紧接对应的指令跳转块的第一条指令。
针对线程Thread2中的第三指令跳转块，存在两条第二取有效地址指令“2.1lea r7，Leave_loop_3(rip)”和“2.2 lea r6 L_loop_3(rip)”，即，将指令“L_loop_3：2.5 add(addr2)，r8”的地址传送(存放)到逻辑寄存器r6，以及将指令“Leave_loop_3:2.11 add $9，r9”的地址传送(存放)到逻辑寄存器r7。并且该两条第二取有效地址指令被放置在指令 “L_loop_3:2.5 add(addr2)，r8”之前，即，放置在线程Thread2的第三指令跳转块之前。
针对线程Thread3中的第四指令跳转块，存在两条第二取有效地址指令“3.1 lea r11，Leave_loop_4(rip)”和“3.2 lea r10 L_loop_4(rip)”，即，将指令“L_loop_4：3.4 sub(addr3)，r14”的地址传送(存放)到逻辑寄存器r10，以及将指令“Leave_loop_4:……”的地址传送(存放)到逻辑寄存器r11。并且该两条第二取有效地址指令被放置在指令“L_loop_4:3.4 sub(addr3)，r14”之前，即，放置在线程Thread3的第四指令跳转块之前。
在图6的示例中，针对第一数目个线程中的每个线程中的每个指令跳转块，转移指令包括条件传送指令cmovbe和无条件跳转指令jmp。例如，针对线程Thread1中的第一指令跳转块，转移指令包括条件传送指令“1.10 cmovbe r5，r4”和无条件跳转指令“1.11 jmp r6”。针对线程Thread1中的第二指令跳转块，转移指令包括条件传送指令“1.21 cmovbe r5，r4”和无条件跳转指令“1.22 jmp r6”。针对线程Thread2中的第三指令跳转块，转移指令包括条件传送指令“2.9 cmovbe r7，r6”和无条件跳转指令“2.10 jmp r10”。针对线程Thread3中的第四指令跳转块，转移指令包括条件传送指令“3.8 cmovbe r11，r10”和无条件跳转指令“3.9 jmp r4”。
按照图6中示出的线程融合方案，可以将多个线程的机器指令代码融合为单个线程的机器指令代码，由此在进行指令执行时，仅仅需要准备与单个线程对应的硬件运行环境，从而能够在无需增加硬件成本的情况下实现多线程处理。
要说明的是，在图6中示出的线程融合方案中，由于在跳转指令之前，处理内核还不知道跳转目的寄存器，从而需要进行寄存器预测处理。
在本说明书实施例的融合处理方案的另一示例中，如图7中所示，指令集420包括leaxxj指令。相应地，针对除第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所述第一取有效地址指令用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器。例如，图7中示出第一取有效指令“1.1 lea r6，L_Thread2(rip)”和“1.2 lea r10，L_Thread3(rip)”，其中，第一取有效指令“1.1 lea r6，L_Thread2(rip)”与线程Thread2对应，以及第一取有效指令“1.2 lea r10，L_Thread3(rip)”与线程Thread3对应。并且，第一取有效指令“1.1 lea r6，L_Thread2(rip)”和“1.2 lea r10，L_Thread3(rip)”被放置在融合线程的开始处。
此外，针对第一数目个线程中的各个线程中的每个指令跳转块，转移指令包括单条leaxxj指令。
这里，leaxxj指令是CPU的指令集中的新增条件转移指令。所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，逻辑寄存器rm表示对应的指令跳转块所属线程的第一取有效地址指令所使用的第二逻辑寄存器，以及逻辑寄存器rn表示需要跳转到的线程的第一取有效地址指令所使用的第二逻辑寄存器，所述leaxxj指令用于指示在条件满足时将L_loop_i所指向的指令地址放入逻辑寄存器rm，在条件不满足时将该leaxxj指令之后的第一条指令的指令地址放入逻辑寄存器rm，并且(无条件)跳转到逻辑寄存器rn中存储的地址所对应的指令。根据条件判断的方式不同，leaxxj指令可以包括leaaj指令，leaaej指令，leabj指令，leabej指令，leagj指令，leagej指令，lealej指令，lealj指令，leanej指令，leaej指令，leaj指令，leancj指令和leacj指令等。
具体地，leaaj指令的格式为leaaj L_Loop_i(rn)，rm，用于表示如果无符号大于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn,否则将当前leaaj指令后面的指令地址存入逻辑寄存器rn,同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leaaj L_Loop_i(rn)，rm
上述leaaj指令表示无符号比较r2和r1，如果r2大于r1，则将L_Loop_i所指向的指令地址存入rn,否则将当前leaaj指令后面的指令地址存入rn，同时跳转到rm。
leaaej指令的格式为leaaej L_Loop_i(rn)，rm，用于表示如果无符号大于或者等于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn,否则将当前leaaej指令后面的指令地址存入逻辑寄存器rn,同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leaaej L_Loop_i(rn)，rm
上述leaaej指令表示无符号比较r2和r1，如果r2大于或者等于r1，则将L_Loop_i所指向的指令地址存入rn,否则将当前leaaej指令后面的指令地址存入rn,同时跳转到rm。
leabj指令的格式为leabj L_Loop_i(rn)，rm，用于表示如果无符号小于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn,否则将当前leabj指令后面的指令地址 存入逻辑寄存器rn,同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leabj L_Loop_i(rn)，rm
上述leabj指令用于表示无符号比较r2和r1，如果r2小于r1，则将L_Loop_i所指向的指令地址存入rn，否则将当前leabj指令后面的指令地址存入rn，同时跳转到rm。
leabej指令的格式为leabej L_Loop_i(rn)，rm，用于表示如果无符号小于或者等于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前leabej指令后面的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leabej L_Loop_i(rn)，rm
上述leabej指令用于表示无符号比较r2和r1，如果r2小于或者等于r1，则将L_Loop_i所指向的指令地址存入rn,否则将当前leabej指令后面的指令地址存入rn，同时跳转到rm。
leagj指令的格式为leagj L_Loop_i(rn)，rm，用于表示有符号大于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn,否则将当前leagj指令后面的指令地址存入逻辑寄存器rn,同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leagj L_Loop_i(rn)，rm
上述leagj指令用于表示有符号比较r2和r1，如果r2大于r1，则将L_Loop_i所指向的指令地址存入rn，否则将当前leagj指令后面的指令地址存入rn，同时跳转到rm。
leagej指令的格式为leagej L_Loop_i(rn)，rm，用于表示有符号大于或者等于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前leagej指令后面的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leagej L_Loop_i(rn)，rm
上述leagej指令表示有符号比较r2和r1，如果r2大于或者等于r1，则将L_Loop_i所指向的指令地址存入rn，否则将当前leagej指令后面的指令地址存入rn，同时跳转到rm。
lealej指令的格式为lealej L_Loop_i(rn)，rm，用于表示有符号小于或者等于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前lealej指令后面的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
lealej L_Loop_i(rn)，rm
上述lealej指令表示有符号比较r2和r1，如果r2小于或者等于r1，则将L_Loop_i所指向的指令地址存入rn，否则将当前lealej指令后面的指令地址存入rn，同时跳转到rm。
lealj指令的格式为lealj L_Loop_i(rn)，rm，用于表示有符号小于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前lealj指令后面的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
lealj L_Loop_i(rn)，rm
上述lealj指令表示有符号比较r2和r1，如果r2小于r1，则将L_Loop_i所指向的指令地址存入rn，否则将当前lealj指令后面的指令地址存入rn，同时跳转到rm。
leanej指令的格式为leanej L_Loop_i(rn)，rm，用于表示不等于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前leanej指令后面的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leanej L_Loop_i(rn)，rm
上述leanej指令表示有符号比较r2和r1，如果r2不等于r1，则将L_Loop_i所指向的指令地址存入rn，否则将当前leanej指令后面的指令地址存入rn，同时跳转到rm。
leaej指令的格式为leaej L_Loop_i(rn)，rm，用于表示等于，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前leaej指令后面的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leaej L_Loop_i(rn)，rm
上述leaej指令表示有符号比较r2和r1，如果r2等于r1，则将L_Loop_i所指向的指令地址存入rn，否则将当前leaej指令后面的指令地址存入rn，同时跳转到rm。
leaj指令的格式为leaj L_Loop_i(rn)，rm，用于表示无条件将L_Loop_i所指向的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leaj L_Loop_i(rn)，rm
上述leaj指令表示无条件将L_Loop_i所指向的指令地址存入rn，同时跳转到rm。
leancj指令的格式为leancj L_Loop_i(rn)，rm，用于表示不进位，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前leancj指令后面的指令地址存入逻辑寄存器rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leancj L_Loop_i(rn)，rm
上述leancj指令表示比较r2和r1，如果不产生进位，则将L_Loop_i所指向的指令地址存入rn，否则将当前leancj指令后面的指令地址存入rn，同时跳转到rm。
leacj指令的格式为leacj L_Loop_i(rn)，rm，用于表示进位，则将L_Loop_i所指向的指令地址存入逻辑寄存器rn，否则将当前leacj指令后面的指令地址存入逻辑寄存器 rn，同时跳转到逻辑寄存器rm。
例如：
sub r1，r2
leacj L_Loop_i(rn)，rm
上述leacj指令表示比较r2和r1，如果不产生进位，则将L_Loop_i所指向的指令地址存入rn，否则将当前leacj指令后面的指令地址存入rn，同时跳转到rm。
相应地，为了保证所增加的leaxxj指令的指令功能能够顺利执行，需要对CPU的架构进行相应修改。例如，使得CPU能够识别leaxxj指令以及完成leaxxj指令的各种操作任务。
此外，针对各个线程中的各个指令块，转移指令包括单条leaxxj指令。例如，针对线程Thread1的第一指令块，转移指令包括指令“1.8 leaaj L_loop_1(r4)，r6”。针对线程Thread1的第二指令块，转移指令包括指令“1.16 leaaj L_loop_2(r4)，r6”。针对线程Thread2的第三指令块，转移指令包括指令“2.7 leaaj L_loop_3(r6)，r10”。针对线程Thread3的第四指令块，转移指令包括指令“3.6 leaaj L_loop_4(r10)，r4”。
按照图7中示出的线程融合方案，可以将多个线程的机器指令代码融合为单个线程的机器指令代码，由此在进行指令执行时，仅仅需要准备与单个线程对应的硬件运行环境，从而能够在无需增加硬件成本的情况下实现多线程处理。
此外，在图7中示出的示例中，可以利用单条指令来实现转移指令，从而大大减少融合后的线程的指令数目，由此提高融合后的线程的效率。例如，在图7的示例中，对于每个指令跳转块，仅仅需要1条leaaj指令，并且该leaaj指令是通过对原有的跳转指令修改而得到的。而在图6的示例中，对于每个指令跳转块，需要使用4条指令来实现跳转，即，2条lea指令、1条cmovbe指令和1条jmp指令。
要说明的是，在图7中示出的线程融合方案中，由于在跳转指令之前，处理内核知道跳转目的寄存器，从而无需进行寄存器预测处理。
回到图5，在如上完成多线程融合后，在块530，经由处理内核430来以指令块为单位获取所述融合线程中的机器指令来运行。
具体地，当前CPU每次取指令都是以指令块为单位来从指令解码队列中获取(例如，指令块所包含的最大指令条数可以为5或者6条，所获取的指令块的最大指令数目 可以由CPU的处理能力来确定，例如，可以由CPU在单个指令周期中能够执行的指令数目来确定)。如果按照规定的指令块大小，CPU本次取到的指令块包含转移指令，例如，cmovbe指令或leaxxj指令，并且该转移指令不是所获取的指令块的结束指令。在这种情况下，由于转移指令的后续指令是否执行仍然不明确，如果取到转移指令之后的指令，则可能会存在转移指令之后的指令没有执行，由此导致本次取值操作失败，需要回滚到本次取指操作的初始状态。针对这种情况，可以将本次取指操作仅仅取指到转移指令(例如，leaxxj指令)为止，即，将本次取值的指令块调整为将转移指令作为结束指令，由此避免出现前述回滚情形。
此外，要说明的是，在进行机器指令运行时，如果处理内核430已经取回leaxxj指令，则将与该leaxxj指令中的逻辑寄存器rn中存放的地址对应的指令块从缓存或内存中预取到处理内核430的指令解码队列中。比如在取到指令leaxxj L_loop_2(r4)，r6的时候，就已经知道下次需要跳转到r6所指向的目的地址，因此开始预取r6所指向地址的指令块(Thread-2的指令块)到该CPU内核的指令解码队列中。这样，在跳转过程中就会有指令连续进入指令解码队列，中间的运行持续展开无断开的现象。
图8示出了根据本说明书的实施例的融合线程运行过程的流程图。
如图8所示，在块810，处理内核430以指令块为单位获取融合线程中的机器指令。例如，处理内核430获取图7中示出的融合线程中的线程Thread1中的指令块1。假设指令块的大小为5条指令，则该指令块1由指令“1.1 lea r6，L_Thread2(rip)”、“1.2 lea r10，L_Thread3(rip)”“1.3 mov r1，r3”、“L_loop_1:1.4 add(addr1)，r1”和“1.5 mul r1，r2”。
然后，在块820，处理内核430依次运行所取回的指令块中的指令。例如，处理内核430依次运行指令块1中的指令“1.1 lea r6，L_Thread2(rip)”、“1.2 lea r10，L_Thread3(rip)”“1.3 mov r1，r3”、“L_loop_1:1.4 add(addr1)，r1”和“1.5 mul r1，r2”。
接着，在块830，判断当前运行的指令是否是转移指令。如果是转移指令，则判断该转移指令是否指示线程退出。
例如，在使用转移指令leaxxj来进行线程融合的情况下，如果leaxxj指令中的L_loop_i设置为指定数值(例如，0xff ff ff ff ff ff ff ff)，则表示线程准备结束。此外，逻辑寄存器具有用于指示该逻辑寄存器的使用状态的标志位，所述使用状态包括用于表 示正常使用的第一状态和用于表示该逻辑寄存器指向另一逻辑寄存器的第二状态。例如，标志位可以使用“0”来表示第一状态，以及使用“1”来表示第二状态。
在进行机器指令运行时，如果处理内核识别出leaxxj指令中的L_loop_i为指定数值(例如，0xff ff ff ff ff ff ff ff)，则在块850，执行线程退出处理。具体地，处理内核释放对应的逻辑寄存器所指向的物理寄存器，使得对应的逻辑寄存器指向下一线程所使用的逻辑寄存器，并且将该对应的逻辑寄存器的标志位赋值为“1”。通常，指令数值被设置为CPU读取后不能识别其含义或者被识别为无效的数值，比如，0xff ff ff ff ff ff ff ff。关于线程退出机制，将在下面参照图9进行说明。
如果处理内核识别出leaxxj指令中的L_loop_i不是指定数值，则返回到块810，取回下一指令块，执行下一循环操作。例如，取回指令块2，该指令块包括指令“1.6 mov r2，addr2”、“1.7 sub $1，r3”和“1.8 leaaj L_loop_1(r4)，r6”，执行下一循环操作。
图9示出了根据本说明书的实施例的线程退出处理的线程示例示意图。在图9中，进行线程融合的线程包括线程Thread1、Thread2、Thread3、Thread4和Thread5。
假设在融合线程程序的起始处，已经初始化了逻辑寄存器r1指向线程Thread-1的程序相应地址，逻辑寄存器r2指向线程Thread-2的程序相应地址，逻辑寄存器r3指向线程Thread-3的程序相应地址，逻辑寄存器r4指向线程Thread-4的程序相应地址，以及逻辑寄存器r5指向线程Thread-5的程序相应地址。
此外，在CPU中还设置有中转寄存器，该中转寄存器用来保留上一次正常跳转时的目的逻辑寄存器，例如当Thread-1正常执行指令leaxxj.L_target_1(r1)，r2，此时在跳转的同时，需要将逻辑寄存器r2存入中转寄存器，若Thread-2也正常执行指令leaxxj.L_target_1(r2)，r3，则在跳转的同时，需要将逻辑寄存器r3存入中转寄存器来替换上次存入的逻辑寄存器r2。这里，中转寄存器的默认值为“0”。
在本说明书实施例中，在线程程序中使用的寄存器r1，r2，r3，r4，r5都是逻辑寄存器，逻辑寄存器指向的是物理寄存器，由此可以通过改变逻辑-物理寄存器之间的映射关系来改变寄存器中存储的内容，同时结合中转寄存器来实现线程结束。
另外，在每个逻辑寄存器中增加一个标志位L，用来指示该逻辑寄存器的使用状态。所述使用状态可以包括用于指示该逻辑寄存器被正常使用的第一状态，以及用于指示该逻辑寄存器指向的内容为另外一个逻辑寄存器的第二状态。在本说明书实施例中，例如，可以使用值“0”来指示第一状态，以及使用值“1”来指示第二状态。
下面来结合图9详细说明根据本说明书的实施例的线程退出机制。
在正常运行一段时间之后，当线程Thread-1正常跳转后，中转寄存器存储着逻辑寄存器r2，然后跳转到线程Thread-2，开始执行线程Thread-2。
如果在运行过程中，线程Thread-2将会结束，则会使用指令leaxxj 0xff ff ff ff ff ff ff ff(r2)，r3来表示。由于任何一个偏移地址都不可能是0xff ff ff ff ff ff ff ff，因此CPU运行这条指令时，如果发现需要将0xff ff ff ff ff ff ff ff放入逻辑寄存器r2中，则由于中转寄存器存储的是逻辑寄存器r2，CPU会将逻辑寄存器r2原来指向的物理寄存器释放(如果有)，同时使逻辑寄存器r2指向物理寄存器的空间中放入线程Thread-3所使用的逻辑寄存器(即，逻辑寄存器r3)，同时将逻辑寄存器r2的标志位L设定为1。在指令重命名过程中，如果发现逻辑寄存器对应的L标志位是1，则CPU会根据逻辑寄存器r2此时存储的逻辑寄存器(r3)来找到真正的物理寄存器。由于此时逻辑寄存器r2，r3都指向同一物理寄存器，因此当线程Thread-1再次运行leaxxj指令需要跳到逻辑寄存器r2的地址时，会直接跳入线程Thread-3对应的上下文中。
在运行一段时间后，如果线程Thread-3也要执行指令leaxxj 0xff ff ff ff ff ff ff ff(r3)，r4，此时由于线程Thread-2已经退出，会从线程Thread-1跳到线程Thread-3，因此中转寄存器存入的是逻辑寄存器r2。由此，CPU将逻辑寄存器r2指向物理寄存器的空间存入线程Thread-4所使用的逻辑寄存器r4，并且逻辑寄存器r2的标志位L被设定为1。这样，当线程Thread-1再次执行指令leaxxj.L_target_1(r1)，r2时，会直接从线程Thread-1跳入到线程Thread-4，以此类推。
如果线程4退出时，中转寄存器存入的是逻辑寄存器r2，那么使r2指向物理寄存器的空间中放入线程Thread-5所使用的逻辑寄存器(即，逻辑寄存器r5),那么Thread-1会直接跳入Thread-5,但是当Thread-5需要退出的时候，此时中转寄存器存入的是逻辑寄存器r2，会将r2指向物理寄存器的空间中放入线程Thread-1所使用的逻辑寄存器(即，逻辑寄存器r1)，因此当Thread-1退出的时候发现逻辑寄存器r2指向的逻辑寄存器为自己(即，r1)，那么正常退出，完成整个操作。
图10示出了根据本说明书的实施例的多线程编译装置1000的方框图。如图10所示，多线程编译装置1000包括线程编译单元1010和线程融合单元1020。
线程编译单元1010被配置为针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码。线程编译单元1010 的操作可以参考上面参照图5描述的块510的操作。
线程融合单元1020被配置为使用处理内核所支持的指令集中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器代码指令。这里，所述第一指令包括取有效地址指令和转移指令，所述取有效地址指令和转移指令利用与所述第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在所述各个线程所对应的机器指令代码中，用于实现所述各个线程的机器指令代码之间的跳转操作。线程融合单元1020的操作可以参考上面参照图5描述的块520的操作以及参照图6到图9描述的操作。
此外，多线程编译装置1000还可以包括转移指令获得单元(未示出)。转移指令获得单元通过对所述各个线程的机器指令代码中的全部或部分跳转指令进行修改而获得第一转移指令。此外，在本说明书实施例的另一示例中，所述转移指令获得单元进一步基于转移指令增加规则增加第二转移指令。所述转移指令增加规则包括：使得转移指令彼此间隔不超过第二预定数目条指令；和/或使用指令编译器调优策略来在合适的机器指令之后增加所述第二转移指令。
如上参照图1到图10，对根据本说明书实施例的用于多线程处理的方法、装置和多线程处理系统的实施例进行了描述。上面的多线程编译装置/多线程处理系统可以采用硬件实现，也可以采用软件或者硬件和软件的组合来实现。
图11为根据本说明书的实施例的用于多线程处理的计算设备的结构框图。
如图11所示，计算设备1100可以包括至少一个处理器1110、存储器(例如，非易失性存储器)1120、内存1130、通信接口1140以及内部总线1160，并且至少一个处理器1110、存储器1120、内存1130和通信接口1140经由总线1160连接在一起。该至少一个处理器1110执行在计算机可读存储介质中存储或编码的至少一个计算机可读指令(即，上述以软件形式实现的元素)。
在一个实施例中，在存储器中存储有计算机可执行指令，其当执行时使得至少一个处理器1110：针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码；以及使用处理内核所支持的指令集中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码，其中，第一指令包括取有效地址指令和转移指令，所述取有效地址指令和转移指令利用与第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置 在各个线程所对应的机器指令代码中，用于实现各个线程的机器指令代码之间的跳转操作。
应该理解的是，在存储器中存储的计算机可执行指令当执行时使得至少一个处理器1110进行本说明书的各个实施例中以上结合图1-10描述的各种操作和功能。
根据一个实施例，提供了一种例如非暂时性机器可读介质的程序产品。非暂时性机器可读介质可以具有指令(即，上述以软件形式实现的元素)，该指令当被机器执行时，使得机器执行本说明书的各个实施例中以上结合图1-10描述的各种操作和功能。
具体地，可以提供配有可读存储介质的系统或者装置，在该可读存储介质上存储着实现上述实施例中任一实施例的功能的软件程序代码，且使该系统或者装置的计算机或处理器读出并执行存储在该可读存储介质中的指令。
在这种情况下，从可读介质读取的程序代码本身可实现上述实施例中任何一项实施例的功能，因此机器可读代码和存储机器可读代码的可读存储介质构成了本发明的一部分。
可读存储介质的实施例包括软盘、硬盘、磁光盘、光盘(如CD-ROM、CD-R、CD-RW、DVD-ROM、DVD-RAM、DVD-RW、DVD-RW)、磁带、非易失性存储卡和ROM。可选择地，可以由通信网络从服务器计算机上或云上下载程序代码。
本领域技术人员应当理解，上面公开的各个实施例可以在不偏离发明实质的情况下做出各种变形和修改。因此，本发明的保护范围应当由所附的权利要求书来限定。
需要说明的是，上述各流程和各系统结构图中不是所有的步骤和单元都是必须的，可以根据实际的需要忽略某些步骤或单元。各步骤的执行顺序不是固定的，可以根据需要进行确定。上述各实施例中描述的装置结构可以是物理结构，也可以是逻辑结构，即，有些单元可能由同一物理实体实现，或者，有些单元可能分由多个物理实体实现，或者，可以由多个独立设备中的某些部件共同实现。
以上各实施例中，硬件单元或模块可以通过机械方式或电气方式实现。例如，一个硬件单元、模块或处理器可以包括永久性专用的电路或逻辑(如专门的处理器，FPGA或ASIC)来完成相应操作。硬件单元或处理器还可以包括可编程逻辑或电路(如通用处理器或其它可编程处理器)，可以由软件进行临时的设置以完成相应操作。具体的实现方式(机械方式、或专用的永久性电路、或者临时设置的电路)可以基于成本和时间上的考虑来确定。
上面结合附图阐述的具体实施方式描述了示例性实施例，但并不表示可以实现的或者落入权利要求书的保护范围的所有实施例。在整个本说明书中使用的术语“示例性”意味着“用作示例、实例或例示”，并不意味着比其它实施例“优选”或“具有优势”。出于提供对所描述技术的理解的目的，具体实施方式包括具体细节。然而，可以在没有这些具体细节的情况下实施这些技术。在一些实例中，为了避免对所描述的实施例的概念造成难以理解，公知的结构和装置以框图形式示出。
本公开内容的上述描述被提供来使得本领域任何普通技术人员能够实现或者使用本公开内容。对于本领域普通技术人员来说，对本公开内容进行的各种修改是显而易见的，并且，也可以在不脱离本公开内容的保护范围的情况下，将本文所定义的一般性原理应用于其它变型。因此，本公开内容并不限于本文所描述的示例和设计，而是与符合本文公开的原理和新颖性特征的最广范围相一致。

Claims (27)

  1. 一种用于多线程处理的方法，包括：
    针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码；以及
    使用处理内核所支持的指令集中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码，
    其中，所述第一指令包括取有效地址指令和转移指令，所述取有效地址指令和转移指令利用与所述第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在所述各个线程所对应的机器指令代码中，用于实现所述各个线程的机器指令代码之间的跳转操作。
  2. 如权利要求1所述的方法，其中，所述第一数目不超过第一预定阈值，所述第一预定阈值是基于所述处理内核可使用的逻辑寄存器的数目来确定的。
  3. 如权利要求1所述的方法，其中，所述转移指令包括通过对所述各个线程的机器指令代码中的全部或部分跳转指令进行修改而获得的第一转移指令。
  4. 如权利要求3所述的方法，其中，所述转移指令还包括基于转移指令增加规则增加的第二转移指令。
  5. 如权利要求4所述的方法，其中，所述转移指令增加规则包括：
    使得所述转移指令彼此间隔不超过第二预定数目条指令；和/或
    使用指令编译器调优策略来在合适的机器指令之后增加所述第二转移指令。
  6. 如权利要求5所述的方法，其中，所述第二预定数目是基于所述处理内核在单个指令周期所能执行的指令数目确定的。
  7. 如权利要求1所述的方法，其中，经过融合后的每个线程具有基于转移指令分割出的至少一个指令跳转块。
  8. 如权利要求7所述的方法，其中，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器，以及
    针对所述第一数目个线程中的每个线程中的每个指令跳转块，所述取有效地址指令包括两条第二取有效地址指令，其中，一条第二取有效地址指令用于将该指令跳转块的第一条指令的地址传送到对应的第二逻辑寄存器，另一第二取有效地址指令用于将位于该指令跳转块之后的第一条指令的地址传送到对应的第二逻辑寄存器，所述两条第二取 有效地址指令被放置在各自线程的对应指令跳转块和上一指令跳转块之间，以及所述转移指令包括条件传送指令和无条件跳转指令。
  9. 如权利要求7所述的方法，其中，所述指令集包括leaxxj指令，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所述第一取有效地址指令用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器，并且所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，以及针对所述第一数目个线程中的各个线程中的每个指令跳转块，所述转移指令包括单条leaxxj指令，
    其中，所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，逻辑寄存器rm表示对应的指令跳转块所属线程的第一取有效地址指令所使用的第二逻辑寄存器，以及逻辑寄存器rn表示需要跳转到的线程的第一取有效地址指令所使用的第二逻辑寄存器，所述leaxxj指令用于指示在条件满足时将L_loop_i所指向的指令地址放入逻辑寄存器rm，在条件不满足时将所述leaxxj指令之后的第一条指令的指令地址放入逻辑寄存器rm，并且跳转到逻辑寄存器rn中存储的地址所对应的指令。
  10. 如权利要求9所述的方法，其中，所述第二逻辑寄存器具有用于指示该第二逻辑寄存器的使用状态的标志位，所述使用状态包括用于表示正常使用的第一状态和用于表示该逻辑寄存器指向另一逻辑寄存器的第二状态，
    在进行机器指令运行时，如果所述处理内核识别出leaxxj指令中的L_loop_i被赋值为指定数值，则释放第二逻辑寄存器rn所指向的物理寄存器，使得第二逻辑寄存器rn指向目标跳转线程所使用的第二逻辑寄存器，并且将第二逻辑寄存器rn的标志位赋值为指示第二状态。
  11. 如权利要求9所述的方法，其中，在进行机器指令运行时，如果所述处理内核已经取回leaxxj指令，则将与所述leaxxj指令中的逻辑寄存器rn所存放的地址对应的指令块预取到所述处理内核的指令解码队列中。
  12. 如权利要求7到11中任一所述的方法，还包括：
    经由所述处理内核来以指令块为单位获取所述融合线程中的机器指令来运行。
  13. 如权利要求12所述的方法，其中，所述指令块的大小由所述处理内核在单个指令周期读取指令的能力来确定。
  14. 如权利要求13所述的方法，其中，在所获取的指令块中包括转移指令并且该指令块的结束指令不是所述转移指令时，将该指令块调整为以所述转移指令为结束指令。
  15. 一种用于多线程处理的装置，包括：
    线程编译单元，针对待处理的第一数目个线程中的各个线程，使用不同的第一逻辑寄存器集合来进行编译以得到对应的机器指令代码；以及
    线程融合单元，使用处理内核所支持的指令集中的第一指令来对各个线程的机器指令代码进行融合处理，以得到单个融合线程的机器指令代码，
    其中，所述第一指令包括取有效地址指令和转移指令，所述取有效地址指令和转移指令利用与所述第一逻辑寄存器集合不同的第二逻辑寄存器来编译得到，所述转移指令被设置在所述各个线程所对应的机器指令代码中，用于实现所述各个线程的机器指令代码之间的跳转操作。
  16. 如权利要求15所述的装置，还包括：
    转移指令获得单元，通过对所述各个线程的机器指令代码中的全部或部分跳转指令进行修改而获得的第一转移指令。
  17. 如权利要求16所述的装置，其中，所述转移指令获得单元进一步基于转移指令增加规则增加第二转移指令。
  18. 如权利要求16所述的装置，其中，所述转移指令增加规则包括：
    使得所述转移指令彼此间隔不超过第二预定数目条指令；和/或
    使用指令编译器调优策略来在合适的机器指令之后增加所述第二转移指令。
  19. 如权利要求15所述的装置，其中，经过融合后的每个线程具有基于转移指令分割出的至少一个指令跳转块。
  20. 如权利要求19所述的装置，其中，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，用于将该线程的第一条指令的地址传送到对应的第二逻辑寄存器，以及
    针对所述第一数目个线程中的每个线程中的每个指令跳转块，所述取有效地址指令包括两条第二取有效地址指令，其中，一条第二取有效地址指令用于将该指令跳转块的第一条指令的地址传送到对应的第二逻辑寄存器，另一第二取有效地址指令用于将位于该指令跳转块之后的第一条指令的地址传送到对应的第二逻辑寄存器，所述两条第二取有效地址指令被放置在各自线程的对应指令跳转块和上一指令跳转块之间，以及所述转移指令包括条件传送指令和无条件跳转指令。
  21. 如权利要求19所述的装置，其中，所述指令集包括leaxxj指令，针对除所述第一数目个线程中的第一线程之外的每个线程，所述取有效地址指令包括单条第一取有效地址指令，所述第一取有效地址指令用于将该线程的第一条指令的地址传送到对应的 第二逻辑寄存器，并且所有第一取有效地址指令都被放置在所述融合线程的机器指令代码的开始处，以及针对所述第一数目个线程中的各个线程中的每个指令跳转块，所述转移指令包括单条leaxxj指令，
    其中，所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，逻辑寄存器rm表示对应的指令跳转块所属线程的第一取有效地址指令所使用的第二逻辑寄存器，以及逻辑寄存器rn表示需要跳转到的线程的第一取有效地址指令所使用的第二逻辑寄存器，所述leaxxj指令用于指示在条件满足时将L_loop_i所指向的指令地址放入逻辑寄存器rm，在条件不满足时将所述leaxxj指令之后的第一条指令的指令地址放入逻辑寄存器rm，并且跳转到逻辑寄存器rn中存储的地址所对应的指令。
  22. 一种用于多线程处理的系统，包括：
    编译器，包括如权利要求15到21中任一所述的装置，将第一数目个线程编译为单个融合线程的机器指令代码；
    指令集；以及
    处理内核，以指令块为单位获取所述融合线程中的机器指令来运行。
  23. 如权利要求22所述的系统，其中，所述指令集包括leaxxj指令，所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，所述leaxxj指令的指令格式为leaxxj L_loop_i(rm)，rn，其中，逻辑寄存器rm表示对应的指令跳转块所属线程的第一取有效地址指令所使用的第二逻辑寄存器，以及逻辑寄存器rn表示需要跳转到的线程的第一取有效地址指令所使用的第二逻辑寄存器，所述leaxxj指令用于指示在条件满足时将L_loop_i所指向的指令地址放入逻辑寄存器rm，在条件不满足时将所述leaxxj指令之后的第一条指令的指令地址放入逻辑寄存器rm，并且跳转到逻辑寄存器rn中存储的地址所对应的指令。
  24. 如权利要求23所述的系统，其中，所述第二逻辑寄存器具有用于指示该第二逻辑寄存器的使用状态的标志位，所述使用状态包括用于表示正常使用的第一状态和用于表示该逻辑寄存器指向另一逻辑寄存器的第二状态，
    在进行机器指令运行时，如果所述处理内核识别出leaxxj指令中的L_loop_i被赋值为指定数值，则所述处理内核释放第二逻辑寄存器rn所指向的物理寄存器，使得第二逻辑寄存器rn指向目标跳转线程所使用的第二逻辑寄存器，并且将第二逻辑寄存器rn的标志位赋值为指示第二状态。
  25. 如权利要求23所述的系统，其中，在进行机器指令运行时，如果所述处理内核已经取回leaxxj指令，则所述处理内核将与所述leaxxj指令中的逻辑寄存器rn所存放 的地址对应的指令块预取到所述处理内核的指令解码队列中。
  26. 一种计算设备，包括：
    一个或多个处理器，以及
    与所述一个或多个处理器耦合的存储器，所述存储器存储指令，当所述指令被所述一个或多个处理器执行时，使得所述一个或多个处理器执行如权利要求1到14中任一项所述的方法。
  27. 一种机器可读存储介质，其存储有可执行指令，所述指令当被执行时使得所述机器执行如权利要求1到14中任一项所述的方法。
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