WO2021004454A1 - 运算方法、装置及设备 - Google Patents

运算方法、装置及设备 Download PDF

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Publication number
WO2021004454A1
WO2021004454A1 PCT/CN2020/100658 CN2020100658W WO2021004454A1 WO 2021004454 A1 WO2021004454 A1 WO 2021004454A1 CN 2020100658 W CN2020100658 W CN 2020100658W WO 2021004454 A1 WO2021004454 A1 WO 2021004454A1
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WIPO (PCT)
Prior art keywords
processing circuit
secret information
scheduling
data
task
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PCT/CN2020/100658
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English (en)
French (fr)
Inventor
章庆隆
汤倩莹
戴望辰
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20836050.3A priority Critical patent/EP3985917A4/en
Publication of WO2021004454A1 publication Critical patent/WO2021004454A1/zh
Priority to US17/568,967 priority patent/US11868485B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3247—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials involving digital signatures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
    • H04L9/302—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3066—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy involving algebraic varieties, e.g. elliptic or hyper-elliptic curves
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2103—Challenge-response

Definitions

  • This application relates to the field of computer technology, in particular to a computing method, device and equipment.
  • a software processing circuit and a hardware processing circuit usually coordinate to perform data processing.
  • Data processing usually includes multiple types of operations, such as point multiplication, point addition, point multiplication, modular addition, and so on.
  • the software processing circuit usually generates scheduling instructions corresponding to each operation based on the secret information, and the hardware processing circuit executes the scheduling instructions to complete the corresponding operations.
  • the software processing circuit is attacked by the software, it will lead to the leakage of secret information, which in turn leads to lower operation security.
  • the application provides an operation method, device and equipment, which improve the safety of operation.
  • the embodiments of the present application provide an operation method applied to an operation system.
  • the operation system includes a software processing circuit, a hardware processing circuit, and a storage circuit.
  • the software processing circuit is used to work by executing a software program, and the storage circuit stores Secret information, the software processing circuit obtains the calculation task, and generates one or more scheduling instructions corresponding to the calculation task according to the calculation task.
  • the calculation task includes one or more calculations, and each scheduling instruction includes the calculation type and Flag bit; the software processing circuit sends one or more scheduling instructions to the hardware processing circuit.
  • the hardware processing circuit obtains secret information from the storage circuit and determines the completion of the scheduling instruction based on the secret information
  • the data address of one or more operation data required by the corresponding operation, and one or more operation data is obtained according to the data address to complete the operation corresponding to each scheduling instruction, thereby completing the operation task.
  • the software processing circuit After the software processing circuit obtains the computing task, the software processing circuit generates one or more scheduling instructions according to the computing task, and the process of generating the scheduling instructions by the software processing circuit does not depend on secret information, and the hardware processing circuit can be based on the scheduling Instructions and secret information perform corresponding operations. Since the process of generating scheduling instructions by the software processing circuit does not rely on secret information, the software processing circuit is prevented from acquiring secret information, and the leakage of secret information caused by software attacks on the software processing circuit can be avoided, thereby improving the security of operations.
  • the data address of one or more operation data required to complete the operation corresponding to the scheduling instruction can be determined according to the secret information through the following feasible implementation manners: obtain the preset first relationship, first The relationship is the operation relationship between the register used to store the one or more operation data and the secret information; the register is determined according to the first relationship and the secret information; the address of the register is determined as the data address.
  • the hardware processing circuit can perform operations based on the operation relationship and the secret information.
  • the information is determined to obtain the register, and then the data address of one or more operation data required to complete the operation corresponding to the scheduling instruction can be determined according to the address of the register.
  • the one or more operation data includes a first source operand and a target operand
  • the data address of the one or more operation data required to complete the operation corresponding to the scheduling instruction is determined according to the secret information. : The data address of the first source operand and the data address of the destination operand.
  • the calculation task is a dot product calculation task or a modular exponentiation calculation task;
  • the scheduling instruction also includes the number of cycles i, where i is the number of times the calculation is currently executed in the calculation task, and i is 0 to N-1
  • the integer between, N is the binary length of the secret information; correspondingly, the first relationship is the relationship between the identifier of the register and the value of the i-th bit in the secret information.
  • the operation included in the operation task is a cyclic operation.
  • the cycle number i in the scheduling instruction can be passed Determine the number of times the operation is currently executed.
  • the software processing circuit generates one or more scheduling instructions corresponding to the operation task according to the operation task, including: the software processing circuit determines that the data address of one or more operation data required for one operation exists in the data address When the data address is related to the secret information, the flag bit in the scheduling instruction corresponding to the operation is set to a valid value; the software processing circuit determines that the data address of one or more operation data required for one operation is not related to the secret information Set the flag bit in the dispatch instruction corresponding to the operation to an invalid value when the data address is set.
  • the hardware processing circuit when the software processing circuit generates the scheduling instruction, the flag bit is set in the scheduling instruction, and the value of the flag bit in the scheduling instruction is set to a valid value or an invalid value according to the actual operation. In this way, After the hardware processing circuit receives the scheduling instruction, the hardware processing circuit can determine whether it is necessary to determine the data address of one or more operation data required to complete the operation corresponding to the scheduling instruction based on the secret information according to the value of the flag bit in the scheduling instruction , Which in turn enables the hardware processing circuit to perform correct operations.
  • the operation type is modular multiplication or modular addition.
  • the secret information is a private key in the RSA algorithm, or the secret information is a random number in an elliptic curve encryption algorithm.
  • an embodiment of the present application provides an arithmetic device, including a software processing circuit, a hardware processing circuit, and a storage circuit.
  • the software processing circuit is configured to work by executing a software program, and the storage circuit stores secret information. among them,
  • the software processing circuit is used to obtain a calculation task, and the calculation task includes performing one or more calculations;
  • the software processing circuit is configured to generate one or more scheduling instructions corresponding to the operation task according to the operation task, and each of the scheduling instructions includes an operation type and a flag bit of an operation;
  • the hardware processing circuit is configured to, after receiving the one or more scheduling instructions, when the flag bit in the scheduling instruction is a valid value, obtain the secret information from the storage circuit, and Determine the data address of one or more operation data required to complete the operation corresponding to the scheduling instruction according to the secret information, and obtain the one or more operation data according to the data address to complete each of the scheduling The operation corresponding to the instruction to complete the operation task.
  • the hardware processing circuit is specifically configured to:
  • the first relationship is an operation relationship between a register used to store the one or more operation data and the secret information
  • the address of the register is determined as the data address.
  • the one or more operation data includes a first source operand and a target operand, and the one or more operations required to complete the operation corresponding to the scheduling instruction are determined according to the secret information.
  • the data addresses of the multiple operation data include: the data address of the first source operand and the data address of the target operand.
  • the operation task is a point multiplication operation task or a modular exponentiation operation task;
  • the scheduling instruction further includes the number of cycles i, where i is the operation currently being executed in the operation task The number of times, the i is an integer between 0 and N-1, and the N is the binary length of the secret information;
  • the first relationship is the relationship between the identifier of the register and the value of the i-th bit in the secret information.
  • the software processing circuit is specifically configured to:
  • the flag bit in the scheduling instruction corresponding to the operation is set to an invalid value.
  • the operation type is a modular multiplication operation or a modular addition operation.
  • the secret information is the private key in the RSA algorithm, or
  • the secret information is a random number in an elliptic curve encryption algorithm.
  • the present application provides a storage medium, where the storage medium is used to store a computer program, and the computer program is used to implement the operation method described in any one of the above-mentioned first aspects.
  • an embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;
  • the memory is used for storing program instructions and sometimes also used for storing intermediate data
  • the processor is configured to call the program instructions stored in the memory to implement the operation method described in any one of the first aspect above.
  • an embodiment of the present application also provides a program product, the program product includes a computer program, the computer program is stored in a storage medium, and the computer program is used to implement any one of the foregoing Operation method.
  • the embodiments of the present application provide an operation method, device, and equipment.
  • the operation system may include a software processing circuit and a hardware processing circuit.
  • the software processing circuit After obtaining the operation task, the software processing circuit generates one or more scheduling instructions according to the operation task, and the software processing The process of generating scheduling instructions by the circuit does not depend on secret information, and the hardware processing circuit can perform corresponding operations according to the scheduling instructions and secret information. Since the process of generating scheduling instructions by the software processing circuit does not rely on secret information, the software processing circuit is prevented from acquiring secret information, and the leakage of secret information caused by software attacks on the software processing circuit can be avoided, thereby improving the operational security.
  • FIG. 1 is a schematic diagram of an application scenario of an operation method provided by an embodiment of the present invention
  • FIG. 2 is an architecture diagram of a computing system provided by an embodiment of the application
  • FIG. 3 is a schematic flowchart of an operation method provided by an embodiment of the application.
  • 4A is a schematic diagram of a scheduling instruction provided by an embodiment of this application.
  • 4B is a schematic diagram of another scheduling instruction provided by an embodiment of this application.
  • Fig. 5 is a schematic diagram of a computing system provided by an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of another operation method provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a scheduling instruction generation provided by an embodiment of the application.
  • FIG. 8A is a schematic diagram of still another scheduling instruction provided by an embodiment of this application.
  • 8B is a schematic diagram of another scheduling instruction provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a computing device provided by an embodiment of the application.
  • Public key algorithm The public key algorithm is an asymmetric encryption (asymmetric cryptography) algorithm.
  • the public key algorithm can realize data encryption/decryption, data signature/verification, etc.
  • the public key algorithm usually needs to use a pair of keys (also known as a key pair), and only a pair of keys can be used to realize data Encryption/decryption, data signature/verification, etc.
  • Common public key algorithms include: RSA (Rivest-Shamir-Adleman) algorithm, elliptic curve encryption algorithm (Elliptic Curve Cryptography, ECC), SM2 elliptic curve public key encryption algorithm, ElGamal algorithm, knapsack algorithm, etc.
  • a password pair includes a private key (referred to as a private key) and a public key (referred to as a public key).
  • the private key is confidential information.
  • the private key is usually held by the key pair owner, and the private key needs to be kept secret.
  • the public key is public information, and the public key is usually published by the key pair holder to others, and the public key does not need to be kept secret.
  • Public key digital signature/verification When digitally signing a message, a private key is used to digitally sign the message. When verifying the digital signature, the digital signature is verified by the private key.
  • Public key algorithm operation refers to the operation involved in the public key algorithm.
  • the operation involved can include modular multiplication, modular addition, modular exponentiation, point addition, point multiplication, or point doubling At least one of.
  • the private key may be used during the execution of the above operations.
  • FIG. 1 is a schematic diagram of an application scenario of an operation method provided by an embodiment of the present invention. Please refer to Fig. 1, including a first device and a second device.
  • the first device and the second device may be terminal devices, network devices, and so on.
  • the first device may be a server-side device
  • the second device may be a terminal device.
  • the first device may send identity challenge information to the second device, and the identity challenge information is used to request verification of the identity of the second device.
  • the second device uses the private key of the second device to perform a public key signature operation on the identity challenge information to obtain a digital signature result, and sends the digital signature result to the first device.
  • the second device uses the public key of the second device to verify the digital signature result.
  • this application at least relates to the improvement of the above-mentioned second device using the private key of the second device to perform the public key signature operation on the identity challenge information, so as to improve the security of the private key of the second device.
  • FIG. 1 is only a possible application scenario in the form of an example, and is not a limitation on the application scenario.
  • the applicable application scenarios shown in the embodiments of this application may also be other, and the embodiments of this application do not make specifics about this. limited.
  • FIG. 2 is an architecture diagram of a computing system provided by an embodiment of the application.
  • the computing system can be deployed in any electronic device.
  • the computing system can be deployed in the second device shown in the embodiment of FIG. 1.
  • the computing system includes a processor 201, a Public Key Engine (PKE) 202, a communication component 203, a memory 204, a bus 205, and so on.
  • PKE Public Key Engine
  • the PKE 202 is mounted on the bus 205 in the form of an Intellectual Property (IP) core.
  • IP Intellectual Property
  • the PKE 202 may include hardware circuits, memory, and so on.
  • the hardware circuit may include a logic judgment circuit, a logic operation circuit, and the like.
  • the memory may include registers, RAM, etc.
  • the operand to be operated on can be stored in the register.
  • the communication part 203 may include a transmitter and/or a receiver.
  • the computing system can communicate with other devices through communication components, for example, receive information from other devices and/or send information to other devices.
  • the memory 204 may store a public key algorithm and a related driver program that drives the execution of the public key algorithm.
  • the memory 204 may be a Flash memory.
  • the processor can execute public key algorithms in memory.
  • the processor in the process of executing the public key algorithm operation, can generate scheduling instructions according to the public key algorithm stored in the memory, and the hardware circuit in the PKE can perform the scheduling instructions on the memory (such as registers) according to the scheduling instructions. Operands are operated on.
  • the computing system may include a software processing circuit and a hardware processing circuit.
  • the processing process of the software processing circuit depends on the processor 201 that supports the instruction set, for example, an x86 processor, or an ARM processor, that is, The function of the software processing circuit is realized by the processor 201.
  • the hardware processing circuit may include the components shown in PKE202 in the embodiment of FIG. 2.
  • the hardware processing circuit can be specifically implemented based on integrated circuits (such as ASIC, FPGA) or discrete components. In practice, in order to achieve better performance, it is usually implemented using integrated circuits.
  • the software processing circuit In the process of public key algorithm operation, the software processing circuit generates scheduling instructions, and the process of generating the scheduling instructions by the software processing circuit does not rely on secret information (such as private keys).
  • the hardware processing circuit performs operations in the corresponding registers according to the scheduling instructions. Number to perform operations.
  • the process of generating scheduling instructions by the software processing circuit since the process of generating scheduling instructions by the software processing circuit does not rely on secret information, it prevents the software processing circuit from acquiring secret information, and thus can avoid the leakage of secret information when the software processing circuit is attacked by software, thereby improving Operational security.
  • FIG. 3 is a schematic flowchart of an operation method provided by an embodiment of the application.
  • the method can be applied to a computing system, which includes a software processing circuit and a hardware processing circuit, and the hardware processing circuit stores secret information. See Figure 3.
  • the method can include:
  • the software processing circuit acquires a computing task, and the computing task includes performing one or more operations.
  • the calculation task may be a dot product calculation task, a modular exponentiation calculation task, and the like.
  • the operations included in the operation task may be modular multiplication operations and/or modular addition operations.
  • the software processing circuit in the computing system can obtain computing tasks when the computing system executes steps that involve computing tasks.
  • the RSA signature process usually includes the following steps:
  • Step 1 Encode the message to be signed.
  • the encoding may be Public Key Cryptography Standards (PKCS) 1_v1_5 encoding.
  • PKCS Public Key Cryptography Standards
  • Step 2 Perform a modular exponentiation operation on the encoded data M to obtain a data signature result, where the modular exponentiation operation is M d , and d is the private key.
  • T[0] r mod N; //T[0] represents the register T[0], r is a random number, and N is the binary length of the secret information
  • T[1] r-1mod N; //T[1] means register T[1]
  • T[2] M mod N; //T[1] means register T[2]
  • T[ ⁇ ki] T[ ⁇ ki]*T[2]mod N; //ki is the i-th bit in the binary secret information, the value is 0 or 1, ⁇ ki is the inverse of ki
  • the software processing circuit generates one or more scheduling instructions corresponding to the computing task according to the computing task.
  • One operation in an operation task corresponds to one or more instructions.
  • an operation is a cyclic operation
  • the operation corresponds to multiple scheduling instructions.
  • an operation is not a loop operation, the operation corresponds to a scheduling instruction.
  • each scheduling instruction includes the operation type and flag bit of an operation.
  • the operation type included in the scheduling instruction may be a modular multiplication operation or a modular addition operation.
  • the flag bit can be a valid value or an invalid value.
  • the valid value can be 1, and the invalid value can be 0.
  • the valid value can be 0 and the invalid value can be 1.
  • the effective value and the invalid value may also be other values, which are not specifically limited in the embodiment of the present application.
  • the software processing circuit determines that there is a data address related to the secret information in the data address of one or more operation data required for one operation, it sets the flag bit in the scheduling instruction corresponding to the operation to a valid value.
  • the software processing circuit determines that there is a data address related to the secret information in the data address of one or more operation data required for one operation, it sets the flag bit in the scheduling instruction corresponding to the operation to a valid value.
  • the software processing circuit determines that there is no data address related to the secret information in the data address of one or more operation data required for one operation, it sets the flag bit in the scheduling instruction corresponding to the operation to an invalid value.
  • the secret information shown in the embodiments of the present application is information that needs to be kept secret and that needs to be used when performing calculations in calculation tasks.
  • the secret information may be a private key in the RSA algorithm, or the secret information may be a random number in an elliptic curve encryption algorithm.
  • the register T[ ⁇ ki] involved in the operation needs to be related to secret information Therefore, the flag bit in the scheduling instruction corresponding to the operation generated by the software processing circuit is a valid value, and the software processing circuit can also determine that the operation type is modular multiplication according to the operation.
  • the software processing circuit generated by the operation corresponding to the scheduling instruction The flag bit is an invalid value, and the software processing circuit can also determine that the operation type is modular multiplication according to the operation.
  • the dispatch instruction usually includes three address fields, and the values in the three address fields respectively represent the address of the target register (target address), the address of the first source register (first source address), and the second source The address of the register (second source address).
  • the data in the first source register is the first source operand
  • the data in the second source register is the second source operand.
  • the operation result is determined according to the data in the first source register and the second source register, and the operation result is stored in the target register.
  • the target register is T[ ⁇ ki]
  • the first source register is T[ ⁇ ki]
  • the second source register is T[2]
  • the following operation T[ ⁇ ki]*T[2]mod N to get the result of the operation
  • write the result of the operation to the target register T[ ⁇ ki].
  • the scheduling instruction generated according to the calculation in the calculation task may also include the number of cycles i, where i is the current execution of the calculation in the calculation task The number of times, i is an integer between 0 and N-1, and N is the binary length of the secret information.
  • i is the current execution of the calculation in the calculation task
  • N is the binary length of the secret information.
  • the generated scheduling instruction corresponding to the operation also includes The number of cycles i.
  • the dispatch instruction may also include the constant operand.
  • the constant operand For example, please refer to the pseudo code in S301.
  • the generated scheduling instruction corresponding to the operation can be as shown in Figure 4A, and Figure 4A is this A schematic diagram of a scheduling instruction provided in an application embodiment.
  • the dispatch instruction includes the following fields: operation type, flag bit, number of cycles, operation constant, target address, source address 2 and source address 1.
  • the value of the operation type field is the identifier of the modular multiplication operation
  • the value of the flag bit field is 1
  • the value of the number of cycles field is i (the value of i is 0 to N-1)
  • the value of the operation constant field is N
  • the value of the destination address field is the preset filling value
  • the value of the source address 2 field is the address of the register T[2]
  • the value of the source address 1 field is the preset filling value.
  • Fig. 4B is an embodiment of the application A schematic diagram of another scheduling instruction provided. Please refer to Figure 4B.
  • the scheduling instruction includes the following fields: operation type, flag bit, number of cycles, operation constant, target address, source address 2 and source address 1.
  • the value of the operation type field is the identifier and flag bit of the modular multiplication operation
  • the value of the field is 0, the value of the number of cycles field is i (the value of i is 0 to N-1), the value of the operation constant field is N, the value of the target address field is the address of register T[2], the source address The value of field 2 is the address of register T[2], and the value of field 1 of source address is the address of register T[2].
  • the hardware processing circuit After receiving one or more scheduling instructions, the hardware processing circuit obtains secret information from the storage circuit when the flag bit in the scheduling instruction is a valid value.
  • the software processing circuit After the software processing circuit generates the scheduling instruction, the software processing circuit sends the scheduling instruction to the hardware processing circuit.
  • the software processing circuit can generate scheduling instructions in a certain order according to the actual operations in the operation tasks, and send the generated scheduling instructions to the hardware processing circuit. Accordingly, the hardware processing circuit also executes the scheduling instructions in the order of the scheduling instructions.
  • the software processing circuit sends the scheduling instructions to the hardware processing circuit in the order in which the scheduling instructions are generated, and correspondingly, the hardware processing circuit executes the scheduling instructions in the order in which the scheduling instructions are received.
  • the hardware processing circuit determines the data address of one or more operation data required to complete the operation corresponding to the scheduling instruction according to the secret information, and obtains one or more operation data according to the data address to complete the operation corresponding to each scheduling instruction , So as to complete the calculation task.
  • the hardware processing circuit may determine the data address of one or more operation data required to complete the operation corresponding to the scheduling instruction through the following feasible implementation manners: obtain a preset first relationship, where the first relationship is The operation relationship between the register storing one or more operation data and the secret information; according to the first relationship and the secret information, the register is determined, and the address of the register is determined as the data address.
  • the first relationship may be an operational relationship between the identifier of the register and the secret information.
  • the identifier of the register may be determined based on the first relationship and the secret information, and the register address corresponding to the identifier of the register may be determined Is the data address.
  • the binary private key is 01100100
  • the foregoing is only illustrative of the first relationship in the form of an example, and is not a limitation on the first relationship.
  • the first relationship can be set according to actual needs, which is not specifically limited in the embodiment of the application. .
  • the embodiment of the application provides an operation method.
  • the operation system may include a software processing circuit and a hardware processing circuit.
  • the software processing circuit After obtaining the operation task, the software processing circuit generates one or more scheduling instructions according to the operation task, and the software processing circuit generates the scheduling instructions
  • the process does not depend on secret information, and the hardware processing circuit can perform corresponding operations according to scheduling instructions and secret information. Since the process of generating scheduling instructions by the software processing circuit does not rely on secret information, the software processing circuit is prevented from acquiring secret information, and the leakage of secret information caused by software attacks on the software processing circuit can be avoided, thereby improving the security of operations.
  • Fig. 5 is a schematic diagram of a computing system provided by an embodiment of the present invention. Please refer to Figure 5, the operating system includes a software processing circuit and a hardware processing circuit.
  • the execution process of the software processing circuit depends on the central processing unit (CPU).
  • the software processing circuit includes a variety of calculation functions and instruction generation units. After obtaining the calculation task, the software processing circuit can be based on the calculation task and The arithmetic function generates scheduling instructions. When the software processing circuit generates the scheduling instruction, there is no need to rely on secret information. If the value of part of the field (address of the register) in the scheduling instruction is related to the secret information, the value of this part of the field is filled with the preset filling value, and The value of the flag bit is set to a valid value to indicate that the scheduling instruction does not have complete and true information, and it needs to be determined by the hardware processing circuit combined with the secret information.
  • the software processing circuit can also set the number of cycles and operation constants in the scheduling instructions. After the software processing circuit generates the scheduling instruction, it sends the scheduling instruction to the hardware processing circuit.
  • the hardware processing circuit includes an instruction analysis circuit, and the received scheduling instruction can be analyzed through the instruction analysis circuit.
  • the value of the flag bit is obtained by analysis as a valid value, it means that the value of some fields in the scheduling instruction is not true, and the true value of this part of the field needs to be obtained according to the secret information.
  • control circuit when the control circuit determines that the value of the flag bit obtained by the analysis of the instruction analysis circuit is a valid value, the control circuit can also obtain the operation type obtained by the analysis (such as modular multiplication operation, modular addition operation, etc.), and obtain the corresponding operation type , The method of obtaining the true value of this part of the field according to the secret information, according to the method to obtain the true value of the part of the field, to determine the complete and true information in the scheduling instruction, and scheduling the underlying calculation based on the complete and true information in the scheduling instruction Sub-module and RAM, complete the operation corresponding to the scheduling instruction.
  • the operator circuits at the bottom layer can also be implemented by hardware circuits, and RAM is used to store intermediate values.
  • FIG. 6 is a schematic flowchart of another operation method provided by an embodiment of the application. Referring to Figure 6, the method may include:
  • the software processing circuit acquires the computing task.
  • the calculation task includes one or more calculations.
  • the software processing circuit generates one or more scheduling instructions corresponding to the computing task according to the computing task.
  • each scheduling instruction may include: operation type, flag bit, destination address, first source address, and second source address of an operation.
  • the scheduling instruction also includes the number of loops i.
  • the dispatch instruction also includes the constant operand.
  • the software processing circuit sends one or more scheduling instructions to the hardware processing circuit.
  • the hardware processing circuit has the same processing procedure for the received scheduling instruction.
  • the processing procedure of any one of the received scheduling instructions by the hardware processing circuit will be described as an example.
  • the hardware processing circuit obtains the value of the flag bit in the scheduling instruction.
  • the operation is directly performed according to the scheduling instruction.
  • the hardware processing circuit acquires the preset first relationship when determining that the flag bit in the scheduling instruction is a valid value.
  • the first relationship is the operational relationship between the register and the secret information. For example, according to the secret information and the first relationship, the identifier of the register can be calculated.
  • the algorithm (software code) corresponding to the computing task can be acquired, and the first relationship can be acquired according to the algorithm corresponding to the computing task.
  • the corresponding relationship between the operation type and the first relationship can also be preset in the hardware processing circuit, and accordingly, the first relationship can be obtained according to the operation type and the corresponding relationship.
  • the first relationship is the relationship between the identifier of the register and the value of the i-th bit in the secret information.
  • the hardware processing circuit determines the identifier of the register related to the secret information according to the first relationship and the secret information, and determines the address of the register related to the secret information according to the identifier of the register.
  • the register related to the secret information refers to the register related to the data address and the secret information.
  • the identifier of the register may be the number of the register.
  • the identifier of register T[0] is 0, the identifier of register [1] is 1, and the identifier of register [2] is 2.
  • the address of the register refers to the actual physical address of the register.
  • the corresponding relationship between the identifier of the register and the address of the register can be preset, and the address of the register can be determined according to the identifier of the register and the corresponding relationship.
  • the hardware processing circuit determines the address field of the register related to the secret information in the scheduling instruction.
  • the algorithm (software code) corresponding to the operation task can be obtained, and the address field of the register can be determined according to the algorithm corresponding to the operation task.
  • the address field of the register related to the secret information is the target address field and the first source address field .
  • the hardware processing circuit updates the value of the address field of the register related to the secret information in the scheduling instruction to the address of the register related to the secret information.
  • the addresses of the registers in the updated scheduling instructions can be made real addresses.
  • the hardware processing circuit executes the first operation according to the updated scheduling instruction.
  • the software processing circuit generates scheduling instructions according to the operation tasks, and the process of generating the scheduling instructions by the software processing circuit does not depend on secret information, and the hardware processing circuit can perform corresponding operations according to the scheduling instructions and secret information. Since the process of generating scheduling instructions by the software processing circuit does not rely on secret information, the software processing circuit is prevented from acquiring secret information, and the leakage of secret information caused by software attacks on the software processing circuit can be avoided, thereby improving the security of operations.
  • Example 1 Take the RSA signature process as an example.
  • the RSA signature process may include the following steps: Step 1. Encode the message to be signed. Step 2. Perform a modular exponentiation operation on the encoded data M to obtain a data signature result, where the modular exponentiation operation is M d , and d is the private key.
  • T[0] r mod N; //T[0] represents the register T[0], r is a random number, and N is the binary length of the private key
  • T[1] r-1mod N; //T[1] means register T[1]
  • T[2] M mod N; //T[1] means register T[2]
  • T[ ⁇ ki] T[ ⁇ ki]*T[2]mod N; //ki is the i-th bit in the binary secret information, the value is 0 or 1, and ⁇ ki is the inverse of ki
  • FIG. 7 is a schematic diagram of a scheduling instruction generation provided by an embodiment of the application.
  • the i-th loop is executed, the i+1-th loop is executed, and so on, until the N loops are executed.
  • MM is the identifier of modular multiplication operation
  • the value 1 of the flag bit is used to indicate that the secret information is required
  • the value of the target address field and the source address 1 field are the preset filling values.
  • the value 0 of the flag bit is used to indicate that the addresses of some registers need to be determined according to the secret information
  • the target address field, the source address field and The value of the source address 2 field is the address of the real register.
  • the software processing circuit determines that the operation type in the operation task is a modular multiplication operation, and then sets the value of the operation type field to the identifier (MM) of the modular multiplication operation.
  • the software processing circuit determines that there is a data address related to the secret information in the data address of one or more operation data required for the operation, and then sets the value of the flag bit field to 1. Since this operation is the first operation, the value of the loop count field is set to the current loop count 0. Since the modulus is the binary length of the secret information, and the binary length of the secret information is 8, the value of the modulus field is set to 8. Since the target register T[ ⁇ ki] is related to secret information, the value of the target address field can be filled with the preset filling value.
  • the value of the target address field can be set to the address of register T[0]. Since the source register 2 (T[2]) has nothing to do with secret information, the value of the source address 2 field can be set to the address of the register T[2]. Since the source register 1 (T[ ⁇ ki]) is related to secret information, and the preset filling value is the address of the register T[0], the value of the source address 1 field can be set to the address of the register T[0].
  • FIG. 8A is a schematic diagram of still another scheduling instruction provided by an embodiment of the application. Please refer to Figure 8A.
  • the scheduling instruction includes an operation type field, a flag bit field, a cycle number field, a modulus field, a destination address field, a source address 2 field, and a source address 1 field. The value of each field is shown in Figure 8A. Show, I won’t repeat it here.
  • the software processing circuit After the software processing circuit generates the scheduling instruction, the software processing circuit sends the scheduling instruction to the hardware processing circuit.
  • FIG. 8B is a schematic diagram of another scheduling instruction provided by an embodiment of the application. Please refer to Figure 8B, the value of the destination address field is the address of register T[1], and the value of the source address 1 field is the address of register T[1].
  • the hardware processing circuit After the hardware processing circuit determines that the dispatch instruction shown in FIG. 8B is obtained, it can perform a modular multiplication operation according to the values of the target address field, the source address 1 field, and the source address 2 field in the dispatch instruction shown in FIG. 8B.
  • Example 2 Take the ellipse signature process as an example.
  • the ellipse signature process can include the following steps:
  • Step 1 Select a random number k, the value range of k is [1, n-1], where n is the order of the elliptic curve. k is secret information.
  • Step 6 Return (r, s).
  • the pseudo code corresponding to the dot product operation can be as follows:
  • T[1] -R; //-R is the inverse element point of R on the elliptic curve
  • T[ ⁇ ki] T[ ⁇ ki]+T[2]//Add operation
  • ki is the i-th bit in the binary secret information, the value is 0 or 1
  • ⁇ ki is the inverse of ki
  • the above pseudo code shows that it includes N cycles.
  • the corresponding scheduling instruction process will be described.
  • the operation corresponding to the point-and-add operation requires multiple scheduling instructions to be implemented.
  • the add operation is composed of 28 instructions. Since the first operand P of the add operation depends on secret information, when generating the scheduling instruction, if the addresses of X1, Y1, and Z1 are involved, the flag bits are all Is 1 (1 indicates that the first type of register is involved). The flag bit of the scheduling instruction corresponding to the calculation result (X3, Y3, Z3) of the dot addition is also 1.
  • the software processing circuit After the software processing circuit generates the scheduling instruction, the software processing circuit sends the scheduling instruction to the hardware processing circuit.
  • the hardware processing circuit After the hardware processing circuit receives the scheduling instruction, it executes the corresponding operation according to the scheduling instruction.
  • the process is similar to the process of performing the corresponding operation in Example 1, and will not be repeated here.
  • FIG. 9 is a schematic structural diagram of a computing device provided by an embodiment of the application.
  • the computing device 10 may include a software processing circuit 11, a hardware processing circuit 12, and a storage circuit 13.
  • the software processing circuit 11 is used to execute software programs to work, and the storage circuit 13 stores secret information. ,among them,
  • the software processing circuit 11 is used to obtain a calculation task, and the calculation task includes performing one or more calculations;
  • the software processing circuit 11 is configured to generate one or more scheduling instructions corresponding to the operation task according to the operation task, and each of the scheduling instructions includes an operation type and a flag bit of an operation;
  • the hardware processing circuit 12 is configured to obtain the secret information from the storage circuit when the flag bit in the scheduling instruction is a valid value after receiving the one or more scheduling instructions, And determine the data address of one or more operation data required to complete the operation corresponding to the scheduling instruction according to the secret information, and obtain the one or more operation data according to the data address to complete each Scheduling the operation corresponding to the instruction to complete the operation task.
  • the software program may be stored in the storage circuit 13, and the software processing circuit 11 may read the software program in the storage circuit 13.
  • the software processing circuit may execute S301-S302 in the embodiment of FIG. 3 and S601-S603 in the embodiment of FIG. 6.
  • the software processing circuit may execute S303-S304 in the embodiment of FIG. 3 and S604-S609 in the embodiment of FIG. 6.
  • the hardware processing circuit is specifically configured to:
  • the first relationship is an operation relationship between a register used to store the one or more operation data and the secret information
  • the address of the register is determined as the data address.
  • the one or more operation data includes a first source operand and a target operand, and the one or more operations required to complete the operation corresponding to the scheduling instruction are determined according to the secret information.
  • the data addresses of the multiple operation data include: the data address of the first source operand and the data address of the target operand.
  • the operation task is a point multiplication operation task or a modular exponentiation operation task;
  • the scheduling instruction further includes the number of cycles i, where i is the operation currently being executed in the operation task The number of times, the i is an integer between 0 and N-1, and the N is the binary length of the secret information;
  • the first relationship is the relationship between the identifier of the register and the value of the i-th bit in the secret information.
  • the software processing circuit is specifically configured to:
  • the flag bit in the scheduling instruction corresponding to the operation is set to an invalid value.
  • the operation type is a modular multiplication operation or a modular addition operation.
  • the secret information is the private key in the RSA algorithm, or
  • the secret information is a random number in an elliptic curve encryption algorithm.
  • the present application provides a storage medium, the storage medium is used to store a computer program, and the computer program is used to implement the operation method described in the foregoing embodiment.
  • the embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;
  • the memory is used for storing program instructions and sometimes also used for storing intermediate data
  • the processor is configured to call the program instructions stored in the memory to implement the above-mentioned operation method.
  • the memory can be independent or integrated with the processor.
  • the memory may also be located outside the chip or integrated circuit.
  • An embodiment of the present application further provides a program product, the program product includes a computer program, the computer program is stored in a storage medium, and the computer program is used to implement the foregoing calculation method.
  • All or part of the steps in the foregoing method embodiments can be implemented by a program instructing relevant hardware.
  • the aforementioned program can be stored in a readable memory.
  • the program executes the steps that include the foregoing method embodiments; and the foregoing memory (storage medium) includes: read-only memory (English: read-only memory, abbreviation: ROM), RAM, flash memory, hard disk, Solid state drives, magnetic tapes (English: magnetic tape), floppy disks (English: floppy disk), optical discs (English: optical disc) and any combination thereof.
  • These computer program instructions can be provided to the processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing equipment to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing equipment are generated for use It is a device that realizes the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing functions specified in a flow or multiple flows in the flowchart and/or a block or multiple blocks in the block diagram.
  • the term “including” and its variations may refer to non-limiting inclusion; the term “or” and its variations may refer to “and/or”.
  • the terms “first”, “second”, etc. in the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.
  • “plurality” means two or more.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone.
  • the character “/” generally indicates that the associated objects are in an "or” relationship.

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Abstract

本申请实施例提供一种运算方法、装置及设备，应用于包括软件处理电路、硬件处理电路以及存储电路的运算系统，软件处理电路用于通过执行软件程序来工作，存储电路中存储有秘密信息，该方法包括：软件处理电路获取运算任务，并根据运算任务生成运算任务对应的一条或多条调度指令，每条调度指令中包括一次运算的运算类型和标志位；硬件处理电路收到一条或多条调度指令后，当调度指令中的标志位为有效值时，从存储电路中获取秘密信息，并根据秘密信息确定完成调度指令所对应的运算所需的一个或多个运算数据的数据地址，并根据数据地址获取一个或多个运算数据来完成每个调度指令所对应的运算，从而完成运算任务。提高了运算的安全性。

Description

运算方法、装置及设备
本申请要求于2019年07月09日提交中国专利局、申请号为201910613478.4、申请名称为“运算方法、装置及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种运算方法、装置及设备。
背景技术
在信息安全技术领域，在进行很多数据处理(例如数字签名、数据加密等)过程中，需要依赖秘密信息，秘密信息为影响数据安全的信息。
在现有技术中，在数据处理过程中，为了提高运算速度，通常由软件处理电路和硬件处理电路协调进行数据处理。数据处理通常包括多种类型的运算，例如，点乘运算、点加运算、倍点运算、模加运算等。在进行数据处理时，软件处理电路通常根据秘密信息生成各运算对应的调度指令，并由硬件处理电路执行调度指令以完成相应的运算。然而，在软件处理电路受到软件攻击时，会导致秘密信息的泄露，进而导致运算的安全性较低。
发明内容
本申请提供一种运算方法、装置及设备，提高了运算的安全性。
第一方面，本申请实施例提供一种运算方法，应用于运算系统，运算系统包括软件处理电路、硬件处理电路以及存储电路，软件处理电路用于通过执行软件程序来工作，存储电路中存储有秘密信息，软件处理电路获取运算任务，以及根据运算任务生成运算任务对应的一条或多条调度指令，其中，运算任务包括进行一次或多次运算，每条调度指令中包括一次运算的运算类型和标志位；软件处理电路将一条或多条调度指令发送给硬件处理电路，当调度指令中的标志位为有效值时，硬件处理电路从存储电路中获取秘密信息，并根据秘密信息确定完成调度指令所对应的运算所需的一个或多个运算数据的数据地址，并根据数据地址获取一个或多个运算数据来完成每个调度指令所对应的运算，从而完成运算任务。
在上述过程中，在软件处理电路获取到运算任务之后，软件处理电路根据运算任务生成一条或多条调度指令，且软件处理电路生成调度指令的过程不依赖于秘密信息，硬件处理电路可以根据调度指令和秘密信息执行相应的运算。由于软件处理电路生成调度指令的过程不依赖于秘密信息，避免了软件处理电路获取秘密信息，进而可以避免软件处理电路受到软件攻击时，导致的秘密信息的泄露，进而提高了运算的安全性。
在一种可能的实施方式中，可以通过如下可行的实现方式根据秘密信息确定完成调度指令所对应的运算所需的一个或多个运算数据的数据地址：获取预设的第一关系，第一关系为用于存储所述一个或多个运算数据的寄存器与秘密信息之间的运算关系；根据第一关 系和秘密信息，确定寄存器；将寄存器的地址确定为数据地址。
在上述过程中，由于第一关系用于存储所述一个或多个运算数据的寄存器与秘密信息之间的运算关系，因此，在硬件处理电路执行运算的过程中，可以根据该运算关系和秘密信息确定得到寄存器，进而可以根据寄存器的地址确定得到完成调度指令所对应的运算所需的一个或多个运算数据的数据地址。
在一种可能的实施方式中，一个或多个运算数据包括第一源操作数以及目标操作数，根据秘密信息确定完成调度指令所对应的运算所需的一个或多个运算数据的数据地址包括：第一源操作数的数据地址和目标操作数的数据地址。
在一种可能的实施方式中，运算任务为点乘运算任务或者模幂运算任务；调度指令还包括循环次数i，i为在运算任务中运算当前被执行的次数，i为0至N-1之间的整数，N为秘密信息的二进制长度；相应的，第一关系为寄存器的标识与秘密信息中第i位的数值之间的关系。
在上述过程中，当运算任务为点乘运算任务或者模幂运算任务时，运算任务中包括的运算为循环运算，通过在调度指令中设置循环次数i，可以使得通过调度指令中的循环次数i确定运算当前被执行的次数。
在一种可能的实施方式中，软件处理电路根据运算任务生成运算任务对应的一条或多条调度指令，包括：软件处理电路在判断一次运算所需的一个或多个运算数据的数据地址中存在与秘密信息相关的数据地址时，将运算对应的调度指令中的标志位设置成有效值；软件处理电路在判断一次运算所需的一个或多个运算数据的数据地址中不存在与秘密信息相关的数据地址时，将运算对应的调度指令中的标志位设置成无效值。
在上述过程中，在软件处理电路生成调度指令的过程中，通过在调度指令中设置标志位，并根据实际运算情况将调度指令中的标志位的值设置为有效值或者无效值，这样，在硬件处理电路接收到的调度指令之后，硬件处理电路根据调度指令中标志位的值，即可确定是否需要根据秘密信息确定完成调度指令所对应的运算所需的一个或多个运算数据的数据地址，进而使得硬件处理电路可以执行正确的运算。
在一种可能的实施方式中，运算类型为模乘运算或者模加运算。
在一种可能的实施方式中，秘密信息为RSA算法中的私钥，或者秘密信息为椭圆曲线加密算法中的随机数。
第二方面，本申请实施例提供一种运算装置，包括软件处理电路、硬件处理电路以及存储电路，所述软件处理电路用于通过执行软件程序来工作，所述存储电路中存储有秘密信息，其中，
所述软件处理电路用于，获取运算任务，所述运算任务包括进行一次或多次运算；
所述软件处理电路用于，根据所述运算任务生成所述运算任务对应的一条或多条调度指令，每条所述调度指令中包括一次运算的运算类型和标志位；
所述硬件处理电路用于，在收到所述一条或多条调度指令后，当所述调度指令中的所述标志位为有效值时，从所述存储电路中获取所述秘密信息，并根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址，并根据所述数据地址获取所述一个或多个运算数据来完成每个所述调度指令所对应的运算，从而完成所述运算任务。
在一种可能的实施方式中，所述硬件处理电路具体用于：
获取预设的第一关系，所述第一关系为用于存储所述一个或多个运算数据的寄存器与所述秘密信息之间的运算关系；
根据所述第一关系和所述秘密信息，确定寄存器；
将所述寄存器的地址确定为所述数据地址。
在一种可能的实施方式中，所述一个或多个运算数据包括第一源操作数以及目标操作数，所述根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址包括：所述第一源操作数的数据地址和所述目标操作数的数据地址。
在一种可能的实施方式中，所述运算任务为点乘运算任务或者模幂运算任务；所述调度指令还包括循环次数i，所述i为在所述运算任务中所述运算当前被执行的次数，所述i为0至N-1之间的整数，所述N为所述秘密信息的二进制长度；
相应的，所述第一关系为寄存器的标识与所述秘密信息中第i位的数值之间的关系。
在一种可能的实施方式中，所述软件处理电路具体用于：
在判断一次运算所需的一个或多个运算数据的数据地址中存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成有效值；
在判断一次运算所需的一个或多个运算数据的数据地址中不存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成无效值。
在一种可能的实施方式中，所述运算类型为模乘运算或者模加运算。
在一种可能的实施方式中，所述秘密信息为RSA算法中的私钥，或者
所述秘密信息为椭圆曲线加密算法中的随机数。
第三方面，本申请提供一种存储介质，所述存储介质用于存储计算机程序，所述计算机程序用于实现上述第一方面任一项所述的运算方法。
第四方面，本申请实施例还提供一种芯片或者集成电路，包括：存储器和处理器；
所述存储器，用于存储程序指令，有时还用于存储中间数据；
所述处理器，用于调用所述存储器中存储的所述程序指令以实现如上第一方面任一项所述的运算方法。
第五方面，本申请实施例还提供一种程序产品，所述程序产品包括计算机程序，所述计算机程序存储在存储介质中，所述计算机程序用于实现上述第一方面任一项所述的运算方法。
本申请实施例提供一种运算方法、装置及设备，运算系统可以包括软件处理电路和硬件处理电路，在获取到运算任务之后，软件处理电路根据运算任务生成一条或多条调度指令，且软件处理电路生成调度指令的过程不依赖于秘密信息，硬件处理电路可以根据调度指令和秘密信息执行相应的运算。由于软件处理电路生成调度指令的过程不依赖于秘密信息，避免了软件处理电路获取秘密信息，进而可以避免软件处理电路受到软件攻击时，导致的秘密信息的泄露，进而提高了运算安全性。
附图说明
图1为本发明实施例提供的一种运算方法的应用场景示意图；
图2为本申请实施例提供的一种运算系统架构图；
图3为本申请实施例提供的一种运算方法的流程示意图；
图4A为本申请实施例提供的一种调度指令的示意图；
图4B为本申请实施例提供的另一种调度指令的示意图；
图5为本发明实施例提供的运算系统示意图；
图6为本申请实施例提供的另一种运算方法的流程示意图；
图7为本申请实施例提供的一种调度指令生成示意图；
图8A为本申请实施例提供的再一种调度指令的示意图；
图8B为本申请实施例提供的另一种调度指令的示意图；
图9为本申请实施例提供的运算装置的结构示意图。
具体实施方式
为了便于对本申请实施例的理解，首先对本申请实施例涉及到的相关名词进行解释说明。
公钥算法：公钥算法是一种非对称加密(asymmetric cryptography)算法。通过公钥算法可以实现数据的加密/解密、数据签名/验签等，公钥算法中通常需要使用一对密钥(还可以称为密钥对)，只有使用一对密钥才能实现数据的加密/解密、数据签名/验签等。常见的公钥算法包括：RSA(Rivest-Shamir-Adleman)算法、椭圆曲线加密算法(Elliptic Curve Cryptography，ECC)、SM2椭圆曲线公钥密码算法，ElGamal算法、背包算法等
密钥对：密码对包括私人密钥(简称私钥)和公开密钥(简称公钥)。私钥为机密信息，私钥通常由密钥对所有者持有，私钥需要保密。公钥为公开信息，公钥通常由密钥对持有者公布给其它人，公钥无需保密。
公钥数字签名/验签：在对消息进行数字签名时，通过私钥对消息进行数字签名。在对数字签名验签时，通过私钥对数字签名进行验证。
公钥算法运算：公钥算法运算是指公钥算法中涉及的运算，例如，涉及的运算可以包括模乘运算、模加运算、模幂运算、点加运算、点乘运算或倍点运算中的至少一种。在上述运算执行的过程中可能需要使用私钥。
图1为本发明实施例提供的一种运算方法的应用场景示意图。请参见图1，包括第一设备和第二设备，第一设备和第二设备可以终端设备、网络设备等。例如，第一设备可以为服务器端设备，第二设备可以为终端设备。
当第一设备需要对第二设备的身份进行认证时，第一设备可以向第二设备发送身份挑战信息，身份挑战信息用于请求验证第二设备的身份。第二设备接收到身份挑战信息之后，使用第二设备的私钥对身份挑战信息进行公钥签名运算，得到数字签名结果，并向第一设备发送数字签名结果。第二设备使用第二设备的公钥对数字签名结果进行验证。其中，本申请至少涉及对上述第二设备使用第二设备的私钥对身份挑战信息进行公钥签名运算的改进，以提高第二设备的私钥的安全性。
需要说明的是，图1只是以示例的形式示意一种可能的应用场景，并非对应用场景的限定，本申请实施例所示适用的应用场景还可以为其它，本申请实施例对此不作具体限定。
图2为本申请实施例提供的一种运算系统架构图。该运算系统可以部署在任意的电子设备中，例如，该运算系统可以部署在图1实施例所示的第二设备中。请参见图2，运算 系统包括处理器201、公钥算法引擎(Public Key Engine，PKE)202、通信部件203、内存204和总线205等。其中，PKE 202以知识产权(Intellectual Property，IP)核的形式挂载在总线205上。
PKE 202可以包括硬件电路、存储器等。硬件电路可以包括逻辑判断电路、逻辑运算电路等。存储器可以包括寄存器、RAM等。在寄存器中可以存储进行运算的操作数。通信部件203可以包括发送器和/或接收器。运算系统可以通过通信部件与其它设备进行通信，例如，从其它设备接收信息，和/或向其它设备发送信息。内存204中可以存储公钥算法、驱动公钥算法执行的相关驱动程序，例如，内存204可以为Flash内存。处理器可以执行内存中的公钥算法。
在实际应用过程中，在执行公钥算法运算的过程中，处理器可以根据内存中存储的公钥算法生成调度指令，并由PKE中的硬件电路根据调度指令，对存储器(例如寄存器)中的操作数进行运算。
在本申请实施例中，运算系统可以包括软件处理电路和硬件处理电路，例如，软件处理电路的处理过程依赖于支持指令集的处理器201，例如，x86处理器，或者ARM处理器，即，通过处理器201实现软件处理电路的功能。硬件处理电路可以包括图2实施例中PKE202中所示的部件。硬件处理电路具体可以基于集成电路(如ASIC、FPGA)或分立元器件来实现，实际中，为了达到更好的性能，通常使用集成电路来实现。
在进行公钥算法运算的过程中，软件处理电路生成调度指令，且软件处理电路生成调度指令的过程不依赖于秘密信息(例如私钥)，由硬件处理电路根据调度指令对相应寄存器中的操作数进行运算。在上述过程中，由于软件处理电路生成调度指令的过程不依赖于秘密信息，避免了软件处理电路获取秘密信息，进而可以避免软件处理电路受到软件攻击时，导致的秘密信息的泄露，进而提高了运算的安全性。
下面，通过具体实施例，对本申请所示的技术方案进行详细说明。需要说明的是，下面几个实施例可以独立存在，也可以相互结合，对于相同或相似的内容，在不同的实施例中不再重复说明。
图3为本申请实施例提供的一种运算方法的流程示意图。该方法可以应用于运算系统，运算系统包括软件处理电路和硬件处理电路，硬件处理电路中存储有秘密信息。请参见图3，该方法可以包括：
S301、软件处理电路获取运算任务，运算任务包括进行一次或多次运算。
可选的，运算任务可以为点乘运算任务、模幂运算任务等。运算任务中包括的运算可以为模乘运算和/或模加运算。
在运算系统进行数据处理的过程中，在运算系统执行至涉及运算任务的步骤时，运算系统中的软件处理电路可以获取得到运算任务。
下面，通过示例说明软件处理电路获取运算任务的方式。
例如，RSA签名流程通常包括如下步骤：
步骤1、对待签名消息进行编码，例如，编码可以为公钥加密标准(Public Key Cryptography Standards，PKCS)1_v1_5编码等。
步骤2、对编码后的数据M进行模幂运算，得到数据签名结果，其中，模幂运算为M d，d为私钥。
上述步骤2对应的伪代码可以如下所示：
初始化：
T[0]＝r mod N；//T[0]表示寄存器T[0]，r为随机数，N为秘密信息的二进制长度
T[1]＝r-1mod N；//T[1]表示寄存器T[1]
T[2]＝M mod N；//T[1]表示寄存器T[2]
循环：
For i＝0…N-1begin
    T[～ki]＝T[～ki]*T[2]mod N；//ki为二进制秘密信息中的第i位，取值为0或1，～ki为ki取反
    T[2]＝T[2]*T[2]mod N；
End
Return：T[0]*r-1mod N
在实际应用过程中，在运算系统执行至上述步骤2时，运算系统中的软件处理电路可以获取得到模幂运算任务。请参见上述伪代码，该模幂运算任务中包括模乘运算T[～ki]＝T[～ki]*T[2]mod N，以及模乘运算T[2]＝T[2]*T[2]mod N。其中，模乘运算T[～ki]＝T[～ki]*T[2]mod N的执行过程为：根据寄存器T[～ki]和寄存器T[2]中的值执行模乘运算，并将运算结果存储至寄存器T[～ki]中。模乘运算T[2]＝T[2]*T[2]mod N的执行过程为：根据寄存器T[2]中的值执行模乘运算，并将运算结果存储至寄存器T[2]中。
S302、软件处理电路根据运算任务生成运算任务对应的一条或多条调度指令。
运算任务中的一次运算对应一条或者多条指令。
若一次运算为循环运算，则该一次运算对应多条调度指令。例如，请参见S301中所示的伪代码，对于运算T[～ki]＝T[～ki]*T[2]mod N，该运算为循环运算，i的取值依次为0至N-1，当i的取值为0时，对应一条调度指令，当i的取值为1时，对应一条调度指令，依次类推，运算T[～ki]＝T[～ki]*T[2]mod N对应N条调度指令。
若一次运算不是循环运算，则该一次运算对应一条调度指令。
其中，每条调度指令中包括一次运算的运算类型和标志位。
可选的，调度指令中包括的运算类型可以为模乘运算或者模加运算等。
可选的，标志位可以为有效值，也可以为无效值。例如，有效值可以为1，无效值可以为0。或者，有效值可以为0，无效值可以为1。当然，有效值和无效值还可以为其它，本申请实施例对此不作具体限定。
软件处理电路在判断一次运算所需的一个或多个运算数据的数据地址中存在与秘密信息相关的数据地址时，将运算对应的调度指令中的标志位设置成有效值。可选的，在一次运算所需的一个或多个运算数据中，可能存在一个或者多个运算数据的数据地址与秘密信息相关。
软件处理电路在判断一次运算所需的一个或多个运算数据的数据地址中不存在与秘密信息相关的数据地址时，将运算对应的调度指令中的标志位设置成无效值。
本申请实施例所示的秘密信息为需要保密的、且在执行运算任务中的运算时需要使用的信息。例如，秘密信息可以为RSA算法中的私钥，或者秘密信息可以为椭圆曲线加密算法中的随机数。
例如，请参见S301中所示的伪代码，对于运算T[～ki]＝T[～ki]*T[2]mod N，由于该运算所涉及的寄存器T[～ki]需要与秘密信息相关，因此，软件处理电路生成的该运算对应的调度指令中的标志位为有效值，软件处理电路还可以根据该运算确定运算类型为模乘。对于运算T[2]＝T[2]*T[2]mod N，由于该运算所涉及的寄存器T[2]与秘密信息无关，因此，软件处理电路生成的该运算对应的调度指令中的标志位为无效值，软件处理电路还可以根据该运算确定运算类型为模乘。
可选的，调度指令中通常还包括三个地址字段，该三个地址字段中的值分别表示目标寄存器的地址(目标地址)、第一源寄存器的地址(第一源地址)和第二源寄存器的地址(第二源地址)。第一源寄存器中的数据为第一源操作数，第二源寄存器中的数据为第二源操作数。在运算中，根据第一源寄存器和第二源寄存器中的数据确定运算结果，并将该运算结果存储至目标寄存器。例如，假设运算为T[～ki]＝T[～ki]*T[2]mod N，则目标寄存器为T[～ki]，第一源寄存器为T[～ki]，第二源寄存器为T[2]，则根据第一源寄存器(T[～ki])和第二源寄存器(T[2])中的数据进行如下运算T[～ki]*T[2]mod N得到运算结果，并将运算结果写入至目标寄存器T[～ki]。
可选的，当运算任务为点乘运算任务或者模幂运算任务时，根据该运算任务中的运算生成的调度指令中可能还包括循环次数i，i为在运算任务中该运算当前被执行的次数，i为0至N-1之间的整数，N为秘密信息的二进制长度。例如，请参见S301中的伪代码，对于运算任务中的运算T[～ki]＝T[～ki]*T[2]mod N为循环运算，则生成的该运算对应的调度指令中还包括循环次数i。
可选的，当一个运算中涉及常量操作数时，则调度指令中还可以包括该常量操作数。例如，请参见S301中的伪代码，对于运算T[～ki]＝T[～ki]*T[2]mod N，该运算中包括常量操作数N，则调度指令中可以包括常量操作数N。
下面，结合图4A-图4B，介绍几种可能的调度指令。
例如，请参见S301中的伪代码，对于运算T[～ki]＝T[～ki]*T[2]mod N，生成的该运算对应的调度指令可以如图4A所示，图4A为本申请实施例提供的一种调度指令的示意图。请参见图4A，调度指令包括如下字段：运算类型、标志位、循环次数、运算常量、目标地址、源地址2和源地址1。其中，运算类型字段的值为模乘运算的标识、标志位字段的值为1、循环次数字段的值为i(i的取值为0至N-1)，运算常量字段的值为N，目标地址字段的值为预设填充值，源地址2字段的值为寄存器T[2]的地址，源地址1字段的值为预设填充值。
例如，请参见S301中的伪代码，对于运算T[2]＝T[2]*T[2]mod N，生成的该运算对应的调度指令如图4B所示，图4B为本申请实施例提供的另一种调度指令的示意图。请参见图4B，调度指令包括如下字段：运算类型、标志位、循环次数、运算常量、目标地址、源地址2和源地址1，其中，运算类型字段的值为模乘运算的标识、标志位字段的值为0、循环次数字段的值为i(i的取值为0至N-1)，运算常量字段的值为N，目标地址字段的值为寄存器T[2]的地址，源地址2字段的值为寄存器T[2]的地址，源地址1字段的值为寄存器T[2]的地址。
S303、硬件处理电路收到一条或多条调度指令后，当调度指令中的标志位为有效值时，从存储电路中获取秘密信息。
在软件处理电路生成调度指令之后，软件处理电路将调度指令发送给硬件处理电路。软件处理处理电路可以根据运算任务中的实际运算，按照一定的顺序生成调度指令，并将生成的调度指令发送给硬件处理电路，相应的，硬件处理电路也按照调度指令的顺序执行调度指令。
例如，请参见S301中的伪代码，软件处理电路可以先生成i＝0时，T[～ki]＝T[～ki]*T[2]mod N对应的调度指令，再生成i＝0时，T[2]＝T[2]*T[2]mod N对应的调度指令。然后，软件处理电路再生成i＝1时，T[～ki]＝T[～ki]*T[2]mod N对应的调度指令，再生成i＝1时，T[2]＝T[2]*T[2]mod N对应的调度指令。以此类推，直至生成i＝N-1时，T[2]＝T[2]*T[2]mod N对应的调度指令。软件处理电路按照上述调度指令的生成顺序向硬件处理电路发送调度指令，相应的，硬件处理电路按照接收到调度指令的顺序执行调度指令。
S304、硬件处理电路根据秘密信息确定完成调度指令所对应的运算所需的一个或多个运算数据的数据地址，并根据数据地址获取一个或多个运算数据来完成每个调度指令所对应的运算，从而完成运算任务。
可选的，硬件处理电路可以通过如下可行的实现方式确定完成调度指令所对应的运算所需的一个或多个运算数据的数据地址：获取预设的第一关系，所述第一关系为用于存储一个或多个运算数据的寄存器与秘密信息之间的运算关系；根据第一关系和秘密信息，确定寄存器，并将寄存器的地址确定为所述数据地址。
可选的，该第一关系可以为寄存器的标识与秘密信息之间的运算关系，相应的，可以根据该第一关系和秘密信息确定寄存器的标识，并将寄存器的标识所对应的寄存器地址确定为所述数据地址。
可选的，当调度指令中包括循环次数i时，则第一关系可以为寄存器的标识＝～ki，ki为二进制秘密信息中的第i位的数值，取值为0或1，～ki为ki取反，即，当ki为1时，～ki为0，当ki为0时，～ki为1。
例如，假设二进制私钥为01100100，第一关系为寄存器的标识＝～ki，则在i＝0时，可以确定寄存器的标识为～k0＝1，在i＝1时，可以确定寄存器的标识为～k1＝0。
需要说明的是，上述只是以示例的形式示意第一关系，并非对第一关系进行的限定，在实际应用过程中，可以根据实际需要设置该第一关系，本申请实施例对此不作具体限定。
本申请实施例提供一种运算方法，运算系统可以包括软件处理电路和硬件处理电路，在获取到运算任务之后，软件处理电路根据运算任务生成一条或多条调度指令，且软件处理电路生成调度指令的过程不依赖于秘密信息，硬件处理电路可以根据调度指令和秘密信息执行相应的运算。由于软件处理电路生成调度指令的过程不依赖于秘密信息，避免了软件处理电路获取秘密信息，进而可以避免软件处理电路受到软件攻击时，导致的秘密信息的泄露，进而提高了运算的安全性。
在上述任意一个实施例的基础上，下面，结合图5，对本申请所示的运算方法进行详细说明。
图5为本发明实施例提供的运算系统示意图。请参见图5，运算系统包括软件处理电路和硬件处理电路。
软件处理电路的执行过程依赖于中央处理器(Central Processing Unit，CPU)，软件处理电路中包括多种运算的运算函数和指令生成单元，在获取到运算任务之后，软件处理 电路可以根据运算任务和运算函数生成调度指令。软件处理电路生成调度指令的过程中，无需依赖秘密信息，若调度指令中部分字段(寄存器的地址)的取值与秘密信息相关，则该部分字段的取值采用预设填充值进行填充，并将标志位的取值设置为有效值，以指示该调度指令中不具备完整真实的信息，需要硬件处理电路结合秘密信息确定。软件处理电路还可以在调度指令中设置循环次数、运算常量等。软件处理电路生成调度指令之后，将调度指令发送给硬件处理电路。
硬件处理电路包括指令解析电路，可以通过指令解析电路对接收到的调度指令进行解析。在解析得到标志位的取值为有效值时，说明调度指令中部分字段的取值为不真实的，则需要根据秘密信息获取该部分字段的真实取值。具体的：在控制电路确定指令解析电路解析得到标志位的取值为有效值时，控制电路还可以获取解析得到的运算类型(如模乘运算、模加运算等)，并获取运算类型对应的、根据秘密信息获取该部分字段的真实取值的方法，根据该方法获取该部分字段的真实取值，以确定得到调度指令中完整真实的信息，并根据调度指令中完整真实的信息调度底层算子模块和RAM，完整调度指令对应的操作。底层各算子电路也可以通过硬件电路实现，RAM用于存放中间值。
图6为本申请实施例提供的另一种运算方法的流程示意图。请参见图6，该方法可以包括：
S601、软件处理电路获取运算任务。
其中，运算任务包括进行一次或多次运算。
需要说明的是，S601的执行过程可以参见S301的执行过程，此处不再进行赘述。
S602、软件处理电路根据运算任务生成运算任务对应的一条或多条调度指令。
可选的，每条调度指令中可以包括：一次运算的运算类型、标志位、目的地址、第一源地址和第二源地址。当运算为循环运算时，调度指令中还包括循环次数i。当运算中涉及常量操作数时，调度指令中还包括常量操作数。
需要说明的是，S602的执行过程可以参见S302的执行过程，此处不再进行赘述。
S603、软件处理电路向硬件处理电路发送一条或多条调度指令。
硬件处理电路对接收到的调度指令的处理过程相同，下面，以硬件处理电路对接收到的任意一条调度指令的处理过程为例进行说明。
S604、硬件处理电路在调度指令中获取标志位的取值。
可选的，若标志位为有效值，则继续执行如下S605-S609。
可选的，若标志位为无效值时，则直接根据调度指令进行运算。
S605、硬件处理电路在确定调度指令中的标志位为有效值时，获取预设的第一关系。
其中，第一关系为寄存器与秘密信息之间的运算关系。例如，根据秘密信息和第一关系，可以计算得到寄存器的标识。
可选的，可以获取运算任务对应的算法(软件代码)，并根据运算任务对应的算法，获取第一关系。
例如，假设一个运算为T[～ki]＝T[～ki]*T[2]mod N，则可以确定第一关系为：寄存器的标识＝～ki。
可选的，还可以在硬件处理电路中预设运算类型与第一关系之间的对应关系，相应的，可以根据运算类型和该对应关系获取第一关系。
可选的，当调度指令包括循环次数i时，第一关系为寄存器的标识与秘密信息中第i位的数值之间的关系。
需要说明的是，第一关系的相关描述可以参见S303，此处不再进行赘述。
S606、硬件处理电路根据第一关系和秘密信息，确定与秘密信息相关的寄存器的标识，并根据寄存器的标识确定与秘密信息相关的寄存器的地址。
其中，与秘密信息相关的寄存器是指，数据地址与秘密信息相关的寄存器。
可选的，寄存器的标识可以为对寄存器的编号。例如，寄存器T[0]的标识为0，寄存器[1]的标识为1，寄存器[2]的标识为2。
可选的，寄存器的地址是指寄存器的实际物理地址。
可以预先设置寄存器的标识和寄存器的地址之间的对应关系，并根据寄存器的标识和该对应关系，确定寄存器的地址。
S607、硬件处理电路在调度指令中确定与秘密信息相关的寄存器的地址字段。
可选的，可以获取运算任务对应的算法(软件代码)，并根据运算任务对应的算法，确定寄存器的地址字段。
例如，假设一个运算的伪代码为T[～ki]＝T[～ki]*T[2]mod N，则可以确定与秘密信息相关的寄存器的地址字段为目标地址字段和第一源地址字段。
S608、硬件处理电路将调度指令中与秘密信息相关的寄存器的地址字段的值更新为与秘密信息相关的寄存器的地址。
由于硬件处理电路接收到的调度指令中与秘密信息相关的寄存器的地址为预设填充值，该预设填充值并非该寄存器的真实地址，因此，对与秘密信息相关的寄存器的地址字段的值更新之后，可以使得更新后调度指令中各寄存器的地址均为真实的地址。
S609、硬件处理电路根据更新后的调度指令，执行第一运算。
在图6所示的实施例中，软件处理电路根据运算任务生成调度指令，且软件处理电路生成调度指令的过程不依赖于秘密信息，硬件处理电路可以根据调度指令和秘密信息执行相应的运算。由于软件处理电路生成调度指令的过程不依赖于秘密信息，避免了软件处理电路获取秘密信息，进而可以避免软件处理电路受到软件攻击时，导致的秘密信息的泄露，进而提高了运算的安全性。
下面，通过具体示例，对上述实施例所示的运算方法进行详细说明。
示例1，以RSA签名流程为例进行说明。
RSA签名流程可以包括如下步骤：步骤1、对待签名消息进行编码。步骤2、对编码后的数据M进行模幂运算，得到数据签名结果，其中，模幂运算为M d，d为私钥。
上述步骤2对应的伪代码可以如下所示：
初始化：
T[0]＝r mod N；//T[0]表示寄存器T[0]，r为随机数，N为私钥的二进制长度
T[1]＝r-1mod N；//T[1]表示寄存器T[1]
T[2]＝M mod N；//T[1]表示寄存器T[2]
循环：
For i＝0…N-1begin
    T[～ki]＝T[～ki]*T[2]mod N；//ki为二进制秘密信息中的第i位，取值为0或1，～ki 为ki取反
    T[2]＝T[2]*T[2]mod N；
End
Return：T[0]*r-1mod N
由上述伪代码可知，包括N次循环，在每个循环中，软件处理电路生成T[～ki]＝T[～ki]*T[2]mod N对应的调度指令和T[2]＝T[2]*T[2]mod N对应的调度指令，相应的，硬件处理电路执行T[～ki]＝T[～ki]*T[2]mod N对应的调度指令和T[2]＝T[2]*T[2]mod N对应的调度指令。即，执行上述步骤2的过程中，软件处理电路生成2N个调度指令，包括N个T[～ki]＝T[～ki]*T[2]mod N对应的调度指令和N个T[2]＝T[2]*T[2]mod N对应的调度指令，相应的，硬件处理电路执行该2N个调度指令。
下面，结合图7，对生成调度指令的过程进行说明。
图7为本申请实施例提供的一种调度指令生成示意图。请参见图7，针对任意第i次循环，软件处理电路先生成T[～ki]＝T[～ki]*T[2]mod N对应的调度指令，并由硬件处理电路执行该调度指令。硬件处理电路执行完成该调度指令之后，软件处理电路再生成T[2]＝T[2]*T[2]mod N对应的调度指令，并由硬件处理电路执行该调度指令。执行完第i次循环之后，执行第i+1次循环，依次类推，直至执行完N次循环。
请参见图7，在T[～ki]＝T[～ki]*T[2]mod N对应的调度指令中，MM为模乘运算的标识，标志位的值1用于指示需要根据秘密信息确定部分寄存器的地址，目标地址字段和源地址1字段的值(T[0]的地址)为预设填充值。在T[2]＝T[2]*T[2]mod N对应的调度指令中，标志位的值0用于指示需要根据秘密信息确定部分寄存器的地址，目标地址字段、源地址1字段和源地址2字段的值均为真实的寄存器的地址。
需要说明的是，软件处理电路每次生成T[～ki]＝T[～ki]*T[2]mod N对应的调度指令的过程类似，硬件处理电路每次执行T[～ki]＝T[～ki]*T[2]mod N对应的调度指令的过程类似。下面，对软件处理电路生成一次T[～ki]＝T[～ki]*T[2]mod N对应的调度指令的过程，以及硬件处理电路执行一次T[～ki]＝T[～ki]*T[2]mod N对应的调度指令的过程进行说明。
假设二进制的秘密信息为01001011，软件处理电路第一次生成T[～ki]＝T[～ki]*T[2]mod N对应的调度指令的过程如下：
软件处理电路确定运算任务中的运算类型为模乘运算，则将运算类型字段的值设置为模乘运算的标识(MM)。软件处理电路判断该运算所需的一个或多个运算数据的数据地址中存在与秘密信息相关的数据地址，则将标志位字段的值设置为1。由于本次运算为第一次运算，因此，将循环次数字段的值设置为当前的循环次数0。由于模数为秘密信息的二进制长度，且秘密信息的二进制长度为8，则将模数字段的值设置为8。由于目标寄存器T[～ki]与秘密信息相关，因此，可以将目标地址字段的值填充为预设填充值，假设预设填充值为寄存器T[0]的地址，则将目标地址字段的值设置为寄存器T[0]的地址。由于源寄存器2(T[2])与秘密信息无关，因此，可以将源地址2字段的值设置为寄存器T[2]的地址。由于源寄存器1(T[～ki])与秘密信息相关，由于预设填充值为寄存器T[0]的地址，因此，可以将源地址1字段的值设置为寄存器T[0]的地址。
经过上述处理，软件处理电路可以生成调度指令，该调度指令可以如图8A所示。图8A为本申请实施例提供的再一种调度指令的示意图。请参见图8A，该调度指令中包括运 算类型字段、标志位字段、循环次数字段、模数字段、目标地址字段、源地址2字段和源地址1字段，其中，各字段的值如图8A所示，此处不再进行赘述。
在软件处理电路生成调度指令之后，软件处理电路向硬件处理电路发送该调度指令。
在硬件处理电路接收到该调度指令之后，先对该调度指令进行解析。硬件处理电路判断该调度指令中标志位字段的值为1，则确定存在与秘密信息相关的寄存器。由T[～ki]＝T[～ki]*T[2]mod N可知，调度指令中第一类型的寄存器的地址字段为目标地址字段和源地址1字段。由T[～ki]＝T[～ki]*T[2]mod N可知，与秘密信息相关寄存器的标识＝～ki，ki为二进制私钥中的第i位，则硬件处理电路在调度指令中获取当前循环次数为0，并在秘密信息(01001011)中获取第0位的数值(0)，则与秘密信息相关的寄存器的标识为1，因此，可以确定调度指令中目标地址字段和源地址1字段的值分别为寄存器T[1]的地址，并对目标地址字段和源地址1字段的值进行修改，修改后的调度指令如图8B所示。
图8B为本申请实施例提供的另一种调度指令的示意图。请参见图8B，目标地址字段的值为寄存器T[1]的地址，源地址1字段的值为寄存器T[1]的地址。
在硬件处理电路确定得到图8B所示的调度指令之后，可以根据图8B所示的调度指令中目标地址字段、源地址1字段和源地址2字段的值进行模乘运算。
示例2，以椭圆签名流程为例进行说明。
椭圆签名流程可以包括如下步骤：
步骤1、选取随机数k，k的取值范围是[1，n-1]，其中，n为椭圆曲线的阶。k是秘密信息。
步骤2、计算k*P＝(x1，y1)，其中，P为椭圆曲线的基点。
步骤3、计算r＝x1mod n，判断r是否为0，若是，则执行步骤1，若否，则执行步骤4。
步骤4、计算e＝H(m)，其中，m为待签名计算的消息，H()为哈希函数。
步骤5、计算s＝k-1(e+d*r)mod n，其中，d为椭圆曲线的签名私钥。判断s是否为0，若是，则执行步骤1，若否，则执行步骤6。
步骤6、返回(r，s)。
针对椭圆签名的步骤2，在进行点乘运算k*P＝(x1，y1)的过程中，需要使用秘密信息k。点乘运算对应的伪代码可以如下所示：
初始化：
T[0]＝R；//R为椭圆曲线上的一个随机点
T[1]＝-R；//-R为R在椭圆曲线上的逆元素点
T[2]＝C；//C为椭圆曲线上的点
循环：
For i＝0…N-1begin
    T[～ki]＝T[～ki]+T[2]//点加操作，ki为二进制秘密信息中的第i位，取值为0或1，～ki为ki取反
    T[2]＝2*T[2]//倍点操作
End
Return：T[0]+(-R)
有上述伪代码可知，包括N个循环，在每个循环中，软件处理电路生成T[～ki]＝T[～ki]+T[2]对应的调度指令和T[2]＝2*T[2]对应的调度指令，相应的，硬件处理电路执行T[～ki]＝T[～ki]+T[2]对应的调度指令和T[2]＝2*T[2]对应的调度指令。即，执行上述步骤2的过程中，软件处理电路生成2N个调度指令，包括N个T[～ki]＝T[～ki]+T[2]对应的调度指令和N个T[2]＝2*T[2]对应的调度指令，相应的，硬件处理电路执行该2N个调度指令。
需要说明的是，软件处理电路每次生成T[～ki]＝T[～ki]+T[2]对应的调度指令的过程类似，硬件处理电路每次执行T[～ki]＝T[～ki]+T[2]应的调度指令的过程类似。下面，对软件处理电路生成一次T[～ki]＝T[～ki]+T[2]对应的调度指令的过程，以及硬件处理电路执行一次T[～ki]＝T[～ki]+T[2]对应的调度指令的过程进行说明。
点加操作对应的操作需要多条调度指令实现，下面，结合表1示意该多条调度指令。以Jacobian坐标系为例，假设输入的两个点为P(X1，Y1，Z1)和Q(X2，Y2，Z2)，输出点加结果P+Q＝(X3，Y3，Z3)，则点加操作需要由表1所示的多条调度指令实现。
表1
Figure PCTCN2020100658-appb-000001
由表1可知，点加操作由28条指令构成，由于点加的第一个操作数P依赖于秘密信息，因此，在生成调度指令时，如果涉及X1、Y1、Z1的地址，标志位均为1(1指示涉及第一类型的寄存器)。点加的计算结果(X3、Y3、Z3)对应的调度指令的标志位也为1。
在软件处理电路生成调度指令之后，软件处理电路向硬件处理电路发送该调度指令。
在硬件处理电路接收到该调度指令之后，根据调度指令执行相应的运算，其过程与示例1中执行相应的运算的过程类似，此处不再进行赘述。
图9为本申请实施例提供的运算装置的结构示意图。请参见图9，该运算装置10可以 包括软件处理电路11、硬件处理电路12以及存储电路13，所述软件处理电路11用于通过执行软件程序来工作，所述存储电路13中存储有秘密信息，其中，
所述软件处理电路11用于，获取运算任务，所述运算任务包括进行一次或多次运算；
所述软件处理电路11用于，根据所述运算任务生成所述运算任务对应的一条或多条调度指令，每条所述调度指令中包括一次运算的运算类型和标志位；
所述硬件处理电路12用于，在收到所述一条或多条调度指令后，当所述调度指令中的所述标志位为有效值时，从所述存储电路中获取所述秘密信息，并根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址，并根据所述数据地址获取所述一个或多个运算数据来完成每个所述调度指令所对应的运算，从而完成所述运算任务。
可选的，软件程序可以存储在存储电路13中，软件处理电路11可以在存储电路13中读取软件程序。
可选的，软件处理电路可以执行图3实施例中的S301-S302，以及图6实施例中的S601-S603。
可选的，软件处理电路可以执行图3实施例中的S303-S304，以及图6实施例中的S604-S609。
需要说明的是，本申请实施例所示的运算装置可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似，此处不再进行赘述。
在一种可能的实施方式中，所述硬件处理电路具体用于：
获取预设的第一关系，所述第一关系为用于存储所述一个或多个运算数据的寄存器与所述秘密信息之间的运算关系；
根据所述第一关系和所述秘密信息，确定寄存器；
将所述寄存器的地址确定为所述数据地址。
在一种可能的实施方式中，所述一个或多个运算数据包括第一源操作数以及目标操作数，所述根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址包括：所述第一源操作数的数据地址和所述目标操作数的数据地址。
在一种可能的实施方式中，所述运算任务为点乘运算任务或者模幂运算任务；所述调度指令还包括循环次数i，所述i为在所述运算任务中所述运算当前被执行的次数，所述i为0至N-1之间的整数，所述N为所述秘密信息的二进制长度；
相应的，所述第一关系为寄存器的标识与所述秘密信息中第i位的数值之间的关系。
在一种可能的实施方式中，所述软件处理电路具体用于：
在判断一次运算所需的一个或多个运算数据的数据地址中存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成有效值；
在判断一次运算所需的一个或多个运算数据的数据地址中不存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成无效值。
在一种可能的实施方式中，所述运算类型为模乘运算或者模加运算。
在一种可能的实施方式中，所述秘密信息为RSA算法中的私钥，或者
所述秘密信息为椭圆曲线加密算法中的随机数。
需要说明的是，本申请实施例所示的运算装置可以执行上述方法实施例所示的技术方 案，其实现原理以及有益效果类似，此处不再进行赘述。
本申请提供一种存储介质，所述存储介质用于存储计算机程序，所述计算机程序用于实现上述实施例所述的运算方法。
本申请实施例还提供一种芯片或者集成电路，包括：存储器和处理器；
所述存储器，用于存储程序指令，有时还用于存储中间数据；
所述处理器，用于调用所述存储器中存储的所述程序指令以实现如上所述的运算方法。
可选的，存储器可以是独立的，也可以跟处理器集成在一起。在有些实施方式中，存储器还可以位于所述芯片或者集成电路之外。
本申请实施例还提供一种程序产品，所述程序产品包括计算机程序，所述计算机程序存储在存储介质中，所述计算机程序用于实现上述的运算方法。
实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一可读取存储器中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储器(存储介质)包括：只读存储器(英文：read-only memory，缩写：ROM)、RAM、快闪存储器、硬盘、固态硬盘、磁带(英文：magnetic tape)、软盘(英文：floppy disk)、光盘(英文：optical disc)及其任意组合。
本申请实施例是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理单元以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理单元执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。
在本申请中，术语“包括”及其变形可以指非限制性的包括；术语“或”及其变形可以指“和/或”。本本申请中术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。本申请中，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。

Claims (15)

  1. 一种运算方法，其特征在于，应用于运算系统，所述运算系统包括软件处理电路、硬件处理电路以及存储电路，所述软件处理电路用于通过执行软件程序来工作，所述存储电路中存储有秘密信息，所述方法包括：
    所述软件处理电路获取运算任务，所述运算任务包括进行一次或多次运算；
    所述软件处理电路根据所述运算任务生成所述运算任务对应的一条或多条调度指令，每条所述调度指令中包括一次运算的运算类型和标志位；
    所述硬件处理电路收到所述一条或多条调度指令后，当所述调度指令中的所述标志位为有效值时，从所述存储电路中获取所述秘密信息，并根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址，并根据所述数据地址获取所述一个或多个运算数据来完成每个所述调度指令所对应的运算，从而完成所述运算任务。
  2. 根据权利要求1所述的方法，其特征在于，根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址，包括：
    获取预设的第一关系，所述第一关系为用于存储所述一个或多个运算数据的寄存器与所述秘密信息之间的运算关系；
    根据所述第一关系和所述秘密信息，确定寄存器；
    将所述寄存器的地址确定为所述数据地址。
  3. 根据权利要求1或2所述的方法，其特征在于，所述一个或多个运算数据包括第一源操作数以及目标操作数，所述根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址包括：所述第一源操作数的数据地址和所述目标操作数的数据地址。
  4. 根据权利要求2所述的方法，其特征在于，所述运算任务为点乘运算任务或者模幂运算任务；所述调度指令还包括循环次数i，所述i为在所述运算任务中所述运算当前被执行的次数，所述i为0至N-1之间的整数，所述N为所述秘密信息的二进制长度；
    相应的，所述第一关系为寄存器的标识与所述秘密信息中第i位的数值之间的关系。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述软件处理电路根据所述运算任务生成所述运算任务对应的一条或多条调度指令，包括：
    所述软件处理电路在判断一次运算所需的一个或多个运算数据的数据地址中存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成有效值；
    所述软件处理电路在判断一次运算所需的一个或多个运算数据的数据地址中不存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成无效值。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述运算类型为模乘运算或者模加运算。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，
    所述秘密信息为RSA算法中的私钥，或者
    所述秘密信息为椭圆曲线加密算法中的随机数。
  8. 一种运算装置，其特征在于，包括软件处理电路、硬件处理电路以及存储电路，所述软件处理电路用于通过执行软件程序来工作，所述存储电路中存储有秘密信息，其中，
    所述软件处理电路用于，获取运算任务，所述运算任务包括进行一次或多次运算；
    所述软件处理电路用于，根据所述运算任务生成所述运算任务对应的一条或多条调度指令，每条所述调度指令中包括一次运算的运算类型和标志位；
    所述硬件处理电路用于，在收到所述一条或多条调度指令后，当所述调度指令中的所述标志位为有效值时，从所述存储电路中获取所述秘密信息，并根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址，并根据所述数据地址获取所述一个或多个运算数据来完成每个所述调度指令所对应的运算，从而完成所述运算任务。
  9. 根据权利要求8所述的装置，其特征在于，所述硬件处理电路具体用于：
    获取预设的第一关系，所述第一关系为用于存储所述一个或多个运算数据的寄存器与所述秘密信息之间的运算关系；
    根据所述第一关系和所述秘密信息，确定寄存器；
    将所述寄存器的地址确定为所述数据地址。
  10. 根据权利要求8或9所述的装置，其特征在于，所述一个或多个运算数据包括第一源操作数以及目标操作数，所述根据所述秘密信息确定完成所述调度指令所对应的运算所需的一个或多个运算数据的数据地址包括：所述第一源操作数的数据地址和所述目标操作数的数据地址。
  11. 根据权利要求9所述的装置，其特征在于，所述运算任务为点乘运算任务或者模幂运算任务；所述调度指令还包括循环次数i，所述i为在所述运算任务中所述运算当前被执行的次数，所述i为0至N-1之间的整数，所述N为所述秘密信息的二进制长度；
    相应的，所述第一关系为寄存器的标识与所述秘密信息中第i位的数值之间的关系。
  12. 根据权利要求8-11任一项所述的装置，其特征在于，所述软件处理电路具体用于：
    在判断一次运算所需的一个或多个运算数据的数据地址中存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成有效值；
    在判断一次运算所需的一个或多个运算数据的数据地址中不存在与所述秘密信息相关的数据地址时，将所述运算对应的调度指令中的标志位设置成无效值。
  13. 根据权利要求8-12任一项所述的装置，其特征在于，所述运算类型为模乘运算或者模加运算。
  14. 根据权利要求8-13任一项所述的装置，其特征在于，
    所述秘密信息为RSA算法中的私钥，或者
    所述秘密信息为椭圆曲线加密算法中的随机数。
  15. 一种存储介质，其特征在于，所述存储介质用于存储计算机程序，所述计算机程序用于实现权利要求1-7任一项所述的运算方法。
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