WO2021003871A1 - Flexible array substrate and flexible display panel - Google Patents

Flexible array substrate and flexible display panel Download PDF

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Publication number
WO2021003871A1
WO2021003871A1 PCT/CN2019/111168 CN2019111168W WO2021003871A1 WO 2021003871 A1 WO2021003871 A1 WO 2021003871A1 CN 2019111168 W CN2019111168 W CN 2019111168W WO 2021003871 A1 WO2021003871 A1 WO 2021003871A1
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WO
WIPO (PCT)
Prior art keywords
source
drain
layer
array substrate
flexible
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PCT/CN2019/111168
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French (fr)
Chinese (zh)
Inventor
张福阳
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武汉华星光电半导体显示技术有限公司
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Publication of WO2021003871A1 publication Critical patent/WO2021003871A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

  • This application relates to the field of display technology, and in particular to a flexible array substrate and a flexible display panel.
  • the flexible array substrate is mainly provided with a bending area on one side of the display area, and the flexible array substrate is bent to bend it to the back of the flexible array substrate to reduce the bending radius.
  • the metal traces on the flexible array substrate will generate a large stress, which causes the metal traces to break.
  • the present application provides a flexible array substrate and a flexible display panel, which can improve the reliability of the flexible array substrate in the bending area, so as to solve the problem of the existing flexible array substrate.
  • the flexible array substrate is bent.
  • the metal traces on the flexible array substrate generate greater stress, which further causes the technical problem of the phenomenon of fracture of the metal traces.
  • the present application provides a flexible array substrate, which includes a display area and a bending area on one side of the display area, and further includes a first flexible substrate, a water and oxygen barrier layer, a second flexible substrate, a buffer layer, and an array structure layer ;
  • the portion of the array structure layer located in the display area has a first source and drain wiring
  • the portion of the array structure layer located in the bending area has a second source and drain wiring
  • the second source The relative distance between the drain trace and the buffer layer is smaller than the relative distance between the first source drain trace and the buffer layer.
  • the materials of the first source and drain wiring and the second source and drain wiring are one or more of copper, aluminum, silver, and titanium The combination.
  • the array structure layer includes an active layer, a first gate insulating layer, a first gate, a second gate insulating layer, and a second gate arranged from bottom to top. Pole, interlayer insulating layer, planarization layer and anode.
  • the second source and drain traces are located on any one of the buffer layer, the first gate insulating layer, and the second gate insulating layer on.
  • the second source and drain wirings are located on the interlayer insulating layer.
  • the second source-drain wiring further includes a third source-drain sub-wiring and a fourth source-drain sub-wiring.
  • the wiring is located on any one of the buffer layer, the first gate insulating layer and the second gate insulating layer, and the fourth source and drain sub-wiring is located on the interlayer insulating layer .
  • the third source-drain sub-wire is electrically connected to the fourth source-drain sub-wire through a first via hole.
  • the material of the third source and drain sub-wiring is aluminum
  • the fourth source and drain sub-wiring is a lower titanium film, a middle aluminum film, and an upper titanium film Structured laminated film.
  • the buffer layer is a laminated film composed of a lower layer silicon dioxide, a middle layer silicon nitride, and an upper layer silicon dioxide.
  • the application also provides a flexible display panel prepared by using the flexible array substrate.
  • the beneficial effects of the present application are: in the flexible array substrate and flexible display panel provided by the present application, the source and drain traces are arranged in the bending area and are located below the source and drain traces in the display area, thereby improving the flexible array substrate The reliability in the bending area further avoids the risk of breaking the metal traces of the flexible array substrate due to bending.
  • FIG. 1 is a schematic structural diagram of Embodiment 1 of a flexible array substrate of this application.
  • FIG. 2 is a schematic diagram of the structure of the source and drain wirings in the first embodiment of the flexible array substrate of this application.
  • FIG. 3 is a schematic diagram of the structure of the source and drain wirings in the second embodiment of the flexible array substrate of this application.
  • Embodiment 4 is a schematic diagram of the structure of the source and drain wirings in Embodiment 3 of the flexible array substrate of this application.
  • Flexible array substrates are known for their thin thickness and bendable performance.
  • the bending area is often subjected to excessive stress, which leads to signals in the bending area and the bending area.
  • Broken wiring leads to defects in the flexible array substrate; in addition, with the update of products, the bending radius of the flexible array substrate continues to decrease, making the bending area more and more stressed. It is urgent to design a structure that can be controlled , Relieve the stress in the bending area and improve the bending performance of the flexible array substrate.
  • This application is directed to the existing flexible array substrates and flexible display panels.
  • the metal traces on the flexible array substrate will be subjected to greater stress, which further leads to the appearance of metal traces.
  • This embodiment can solve the technical problem of the fracture phenomenon.
  • the flexible array substrate includes a display area 10 and a bending area 20 located on one side of the display area 10.
  • the flexible array substrate also includes a first flexible substrate 11, a water and oxygen barrier layer 12, and a second flexible liner. Bottom 13, buffer layer 14, and array structure layer;
  • the portion of the array structure layer located in the display area 10 has a first source and drain wiring 111, and the portion of the array structure layer located in the bending area 20 has a second source and drain wiring.
  • the relative distance between the source-drain traces and the buffer layer 14 is smaller than the relative distance between the first source-drain traces 111 and the buffer layer 14.
  • the array structure layer further includes an active layer 15, a first gate insulating layer 16, a first gate 17, a second gate insulating layer 18, a second gate 19, and interlayers arranged from bottom to top.
  • the specific preparation method of the flexible array substrate is as follows:
  • a glass substrate is provided, and a first flexible substrate 11 is deposited on the glass substrate.
  • the material of the first flexible substrate 11 is preferably a polyimide film, and the thickness of the first flexible substrate 11 is preferably 10 microns.
  • a water and oxygen barrier layer 12 is deposited on the flexible substrate 11, the material of the water and oxygen barrier layer 12 is silicon dioxide, and its thickness is preferably 500 nanometers.
  • a second flexible substrate 13 is deposited on the water and oxygen barrier layer 12.
  • the material of the second flexible substrate 13 is preferably a polyimide film, and the thickness of the second flexible substrate 13 is preferably 10 Micrometers.
  • a buffer layer 14 is prepared on the second flexible substrate 13, and the buffer layer 14 is a laminated film composed of a lower layer of silicon dioxide, a middle layer of silicon nitride, and an upper layer of silicon dioxide.
  • the thickness of the lower layer silicon dioxide is preferably 500 nanometers
  • the thickness of the middle layer silicon nitride is preferably 40 nanometers
  • the thickness of the upper layer silicon dioxide is preferably 200 nanometers.
  • an active layer 15 is prepared on the buffer layer 14.
  • the material of the active layer 15 is polysilicon (Poly-Si), and both ends of the active layer 15 are doped with P+ ions to form ion doping.
  • the impurity layer 151, the thickness of the active layer 15 is preferably 50 nanometers
  • a first gate insulating layer 16 is then prepared on the buffer layer 14.
  • the first gate insulating layer 16 completely covers the active layer 15, and the material of the first gate insulating layer 16 is silicon dioxide
  • the thickness of the first gate insulating layer 16 is preferably 140 nanometers.
  • a first gate 17 is deposited on the first gate insulating layer 16, the material of the first gate 17 is molybdenum, and the thickness of the first gate 17 is preferably 250 nanometers.
  • a second gate insulating layer 18 is deposited on the first gate insulating layer 16, the second gate insulating layer 18 completely covers the first gate 17, and the second gate insulating layer 18
  • the material is silicon nitride, and the thickness of the second gate insulating layer 18 is preferably 140 nanometers.
  • a second gate 19 is deposited on the second gate insulating layer 18, the material of the second gate 19 is molybdenum, and the thickness of the second gate 19 is preferably 250 nanometers.
  • an interlayer insulating layer 110 is deposited on the second gate insulating layer 18, the interlayer insulating layer 110 completely covers the second gate 19, and the material of the interlayer insulating layer 110 is silicon dioxide,
  • the thickness of the interlayer insulating layer 110 is preferably 500 nanometers.
  • a first source-drain trace 111 is prepared on the interlayer insulating layer 110, and the first source-drain trace 111 is electrically connected to the ion doped layer 151 through a via hole, and the first
  • the material of the source and drain wiring 111 is one or a combination of copper, aluminum, silver and titanium, preferably a laminated film composed of a lower titanium film, a middle aluminum film, and an upper titanium film.
  • the thickness of the lower titanium film is preferably 80 nm
  • the thickness of the middle aluminum film is preferably 600 nm
  • the thickness of the upper titanium film is preferably 50 nm.
  • a planarization layer 112 is prepared on the interlayer insulating layer 110, the material of the planarization layer 112 is a polyimide film, and the thickness of the planarization layer 112 is preferably 200 nanometers.
  • an anode 113 is prepared on the planarization layer 112, and the anode 113 is electrically connected to the first source/drain trace 111 through another via hole.
  • the anode 113 is made of ITO (Indium Tin Oxide).
  • the thickness of the lower ITO film is preferably 15 nm, the thickness of the middle silver film is preferably 100 nm, and the thickness of the upper ITO film is preferably 15 nm, Finally, the array structure layer is formed.
  • the portion of the array structure layer located in the bending region 20 further includes a second source-drain trace, and the relative distance D2 between the second source-drain trace and the buffer layer 14 is less than The relative distance D1 between the first source-drain trace 111 and the buffer layer 14.
  • the second source-drain wiring further includes a third source-drain sub-wiring 21 and a fourth source-drain sub-wiring 22, and the third source-drain sub-wiring 21 is located in the buffer layer 14.
  • the fourth source-drain sub-wiring 22 is located on the interlayer insulating layer 110;
  • the third source-drain sub-wire 21 is electrically connected to the fourth source-drain sub-wire 22 through the first via 23.
  • the relative distance D2 between the second source-drain trace and the buffer layer 14 is smaller than the relative distance D1 between the first source-drain trace 111 and the buffer layer 14. Therefore, there is a certain height difference h1 between the source and drain traces of the flexible substrate located in the bending area 20 and the source and drain traces of the flexible substrate located in the display area 10.
  • the difference h1 can couple the stress between the flexible array substrate and the source/drain traces, so that in the process of bending the flexible array substrate, the source/drain traces located in the bending area of the flexible array substrate The stress received is small, which prevents the source and drain wires from breaking during the bending process, and improves the bending performance of the flexible array substrate.
  • the material of the third source and drain sub-wiring 21 is aluminum, and the thickness of the third source and drain sub-wiring 21 is preferably 50 nanometers;
  • the fourth source and drain sub-wiring 22 is a lower layer A laminated film composed of a titanium film, a middle aluminum film and an upper titanium film, the thickness of the lower titanium film is preferably 80 nm, the thickness of the middle aluminum film is preferably 600 nm, and the thickness of the upper titanium film is preferably 50 nm .
  • FIG. 2 it is a schematic diagram of the source and drain wiring structure in the first embodiment of the flexible array substrate of this application.
  • the first source-drain wiring 111 is electrically connected to the fourth source-drain sub-wiring 22.
  • a flexible array substrate, as shown in FIG. 3, is different from the first embodiment only in that the second source-drain wiring 31 is located in the buffer layer 14, the first gate insulating layer 16, and On any one of the second gate insulating layers 18.
  • the relative distance D3 between the second source-drain trace 31 and the buffer layer 14 is smaller than the relative distance D1 between the first source-drain trace 111 and the buffer layer 14. Therefore, there is a certain height difference h2 between the source and drain traces of the flexible substrate located in the bending area 20 and the source and drain traces of the flexible substrate located in the display area 10.
  • the difference h2 can couple the stress between the flexible array substrate and the source/drain traces, so that in the process of bending the flexible array substrate, the source/drain traces located in the bending area of the flexible array substrate The stress received is small, which prevents the source and drain wires from breaking during the bending process, and improves the bending performance of the flexible array substrate.
  • a flexible array substrate, as shown in FIG. 4, is different from the first embodiment only in that the second source and drain wiring 41 is located on the interlayer insulating layer 110.
  • the relative distance D4 between the second source-drain trace 41 and the buffer layer 14 is smaller than the relative distance D1 between the first source-drain trace 111 and the buffer layer 14. Therefore, there is a certain height difference h3 between the source and drain traces of the flexible substrate located in the bending area 20 and the source and drain traces of the flexible substrate located in the display area 10.
  • the difference h3 can couple the stress between the flexible array substrate and the source/drain traces, so that in the process of bending the flexible array substrate, the source/drain traces located in the bending area of the flexible array substrate The stress received is small, which prevents the source and drain wires from breaking during the bending process, and improves the bending performance of the flexible array substrate.
  • the present application also provides a flexible display panel, which includes a flexible array substrate having any of the features described in the above embodiments.
  • the type of the flexible display panel may be an organic light emitting diode (Organic Light-Emitting Diode (OLED) panel, In-Plane Switching (IPS) panel, Twisted Nematic (TN) panel, Vertical Alignment (VA) panel, QLED (Quantum Dot Light Emitting) Any one of display panels such as Diodes (quantum dot light emitting) display panels or micro LED (micro light emitting diodes, ⁇ LED) panels, which is not specifically limited in this application.
  • OLED Organic Light-Emitting Diode
  • IPS In-Plane Switching
  • TN Twisted Nematic
  • VA Vertical Alignment
  • QLED Quadantum Dot Light Emitting
  • Any one of display panels such as Diodes (quantum dot light emitting) display panels or micro LED (micro light emitting diodes, ⁇ LED) panels, which is not specifically limited
  • the source and drain traces are arranged in the bending area and are located below the source and drain traces in the display area, which improves the reliability of the flexible array substrate in the bending area This further avoids the risk of metal traces breaking due to bending of the flexible array substrate.

Abstract

A flexible array substrate, comprising a first flexible substrate (11), a water-oxygen barrier layer (12), a second flexible substrate (13), a buffer layer (14), and an array structure layer; a portion of the array structure layer located in a display area (10) is provided with a first source/drain wiring (111), a portion of the array structure layer located in a bending area (20) is provided with a second source/drain wiring, and the relative distance between the second source/drain wiring and the buffer layer is less than the relative distance between the first source/drain wiring and the buffer layer.

Description

柔性阵列基板及柔性显示面板Flexible array substrate and flexible display panel 技术领域Technical field
本申请涉及显示技术领域，尤其涉及一种柔性阵列基板及柔性显示面板。This application relates to the field of display technology, and in particular to a flexible array substrate and a flexible display panel.
背景技术Background technique
随着手机显示技术的发展，对手机面板的要求越来越高。窄边框、高平占比、“无下巴”的手机面板已经成为绝大多是手机面板供应商与手机厂商追求的目标。而要实现手机的上述要求，离不开手机面板制造技术的提高。现有技术中，主要在柔性阵列基板中位于显示区的一侧设置有弯折区，并对柔性阵列基板进行弯折，以将其弯折至柔性阵列基板背后，以减小弯曲半径。但是目前在对柔性阵列基板进行弯折后，柔性阵列基板上的金属走线会产生较大应力，导致金属走线出现断裂的现象。With the development of mobile phone display technology, the requirements for mobile phone panels are getting higher and higher. Narrow bezels, high flat ratio, and "no chin" mobile phone panels have become the goal pursued by most mobile phone panel suppliers and mobile phone manufacturers. To achieve the above requirements of mobile phones, it is inseparable from the improvement of mobile phone panel manufacturing technology. In the prior art, the flexible array substrate is mainly provided with a bending area on one side of the display area, and the flexible array substrate is bent to bend it to the back of the flexible array substrate to reduce the bending radius. However, at present, after the flexible array substrate is bent, the metal traces on the flexible array substrate will generate a large stress, which causes the metal traces to break.
综上所述，现有的柔性阵列基板及柔性显示面板，为了实现高屏占比对柔性阵列基板进行弯折时，会使柔性阵列基板上的金属走线产生较大应力，进一步导致金属走线出现断裂的现象。To sum up, in the existing flexible array substrate and flexible display panel, when the flexible array substrate is bent in order to achieve a high screen-to-body ratio, the metal traces on the flexible array substrate will generate greater stress, which will further cause the metal to travel. The thread is broken.
技术问题technical problem
现有的柔性阵列基板及柔性显示面板，为了实现高屏占比对柔性阵列基板进行弯折时，会使柔性阵列基板上的金属走线产生较大应力，从而导致金属走线出现断裂的现象。In the existing flexible array substrates and flexible display panels, when the flexible array substrate is bent in order to achieve a high screen-to-body ratio, the metal traces on the flexible array substrate will have a large stress, which will cause the metal traces to break. .
技术解决方案Technical solutions
本申请提供一种柔性阵列基板及柔性显示面板，能够提高其位于弯折区域的可靠性，以解决现有的柔性阵列基板，为了实现高屏占比对柔性阵列基板进行弯折时，会使柔性阵列基板上的金属走线产生较大应力，进一步导致金属走线出现断裂的现象的技术问题。The present application provides a flexible array substrate and a flexible display panel, which can improve the reliability of the flexible array substrate in the bending area, so as to solve the problem of the existing flexible array substrate. In order to achieve a high screen-to-body ratio, the flexible array substrate is bent. The metal traces on the flexible array substrate generate greater stress, which further causes the technical problem of the phenomenon of fracture of the metal traces.
为解决上述问题，本申请提供的技术方案如下：To solve the above problems, the technical solutions provided by this application are as follows:
本申请提供一种柔性阵列基板，包括显示区域以及位于所述显示区域一侧的弯折区域，还包括第一柔性衬底、水氧阻隔层、第二柔性衬底、缓冲层以及阵列结构层；The present application provides a flexible array substrate, which includes a display area and a bending area on one side of the display area, and further includes a first flexible substrate, a water and oxygen barrier layer, a second flexible substrate, a buffer layer, and an array structure layer ；
其中，所述阵列结构层位于所述显示区域的部分具有第一源漏极走线，所述阵列结构层位于所述弯折区域的部分具有第二源漏极走线，所述第二源漏极走线与所述缓冲层之间的相对距离小于所述第一源漏极走线与所述缓冲层之间的相对距离。Wherein, the portion of the array structure layer located in the display area has a first source and drain wiring, the portion of the array structure layer located in the bending area has a second source and drain wiring, and the second source The relative distance between the drain trace and the buffer layer is smaller than the relative distance between the first source drain trace and the buffer layer.
在本申请实施例所提供的柔性阵列基板中，所述第一源漏极走线及所述第二源漏极走线的材料为铜、铝、银以及钛中的一种或一种以上的组合。In the flexible array substrate provided by the embodiment of the present application, the materials of the first source and drain wiring and the second source and drain wiring are one or more of copper, aluminum, silver, and titanium The combination.
在本申请实施例所提供的柔性阵列基板中，所述阵列结构层包括由下至上设置的有源层、第一栅极绝缘层、第一栅极、第二栅极绝缘层、第二栅极、层间绝缘层、平坦化层以及阳极。In the flexible array substrate provided by the embodiment of the present application, the array structure layer includes an active layer, a first gate insulating layer, a first gate, a second gate insulating layer, and a second gate arranged from bottom to top. Pole, interlayer insulating layer, planarization layer and anode.
在本申请实施例所提供的柔性阵列基板中，所述第二源漏极走线位于所述缓冲层、所述第一栅极绝缘层以及所述第二栅极绝缘层中的任意一层上。In the flexible array substrate provided by the embodiment of the present application, the second source and drain traces are located on any one of the buffer layer, the first gate insulating layer, and the second gate insulating layer on.
在本申请实施例所提供的柔性阵列基板中，所述第二源漏极走线位于所述层间绝缘层上。In the flexible array substrate provided by the embodiment of the present application, the second source and drain wirings are located on the interlayer insulating layer.
在本申请实施例所提供的柔性阵列基板中，所述第二源漏极走线还包括第三源漏极子走线以及第四源漏极子走线，所述第三源漏极子走线位于所述缓冲层、所述第一栅极绝缘层以及所述第二栅极绝缘层中的任意一层上，所述第四源漏极子走线位于所述层间绝缘层上。In the flexible array substrate provided by the embodiment of the present application, the second source-drain wiring further includes a third source-drain sub-wiring and a fourth source-drain sub-wiring. The wiring is located on any one of the buffer layer, the first gate insulating layer and the second gate insulating layer, and the fourth source and drain sub-wiring is located on the interlayer insulating layer .
在本申请实施例所提供的柔性阵列基板中，所述第三源漏极子走线通过第一过孔与所述第四源漏极子走线电性连接。In the flexible array substrate provided by the embodiment of the present application, the third source-drain sub-wire is electrically connected to the fourth source-drain sub-wire through a first via hole.
在本申请实施例所提供的柔性阵列基板中，所述第三源漏极子走线的材料为铝，所述第四源漏极子走线为下层钛膜、中层铝膜及上层钛膜构成的层叠膜。In the flexible array substrate provided by the embodiment of the present application, the material of the third source and drain sub-wiring is aluminum, and the fourth source and drain sub-wiring is a lower titanium film, a middle aluminum film, and an upper titanium film Structured laminated film.
在本申请实施例所提供的柔性阵列基板中，所述缓冲层为下层二氧化硅、中层硅氮化物及上层二氧化硅构成的层叠膜。In the flexible array substrate provided by the embodiment of the present application, the buffer layer is a laminated film composed of a lower layer silicon dioxide, a middle layer silicon nitride, and an upper layer silicon dioxide.
本申请还提供一种使用所述柔性阵列基板制备的柔性显示面板。The application also provides a flexible display panel prepared by using the flexible array substrate.
有益效果Beneficial effect
本申请的有益效果为：本申请所提供的柔性阵列基板及柔性显示面板，在弯折区域内设置源漏极走线且位于显示区域内的源漏极走线的下方，提高了柔性阵列基板位于弯折区域的可靠性，进一步避免了柔性阵列基板因为弯折造成金属走线断裂的风险。The beneficial effects of the present application are: in the flexible array substrate and flexible display panel provided by the present application, the source and drain traces are arranged in the bending area and are located below the source and drain traces in the display area, thereby improving the flexible array substrate The reliability in the bending area further avoids the risk of breaking the metal traces of the flexible array substrate due to bending.
附图说明Description of the drawings
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to explain the embodiments or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for application. For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.
图1为本申请柔性阵列基板实施例一结构示意图。FIG. 1 is a schematic structural diagram of Embodiment 1 of a flexible array substrate of this application.
图2为本申请柔性阵列基板实施例一中源漏极走线的结构示意图。2 is a schematic diagram of the structure of the source and drain wirings in the first embodiment of the flexible array substrate of this application.
图3为本申请柔性阵列基板实施例二中源漏极走线的结构示意图。3 is a schematic diagram of the structure of the source and drain wirings in the second embodiment of the flexible array substrate of this application.
图4为本申请柔性阵列基板实施例三中源漏极走线的结构示意图。4 is a schematic diagram of the structure of the source and drain wirings in Embodiment 3 of the flexible array substrate of this application.
本发明的实施方式Embodiments of the invention
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that can be implemented in this application. The directional terms mentioned in this application, such as [Up], [Down], [Front], [Back], [Left], [Right], [Inner], [Outer], [Side], etc., are for reference only The direction of the additional schema. Therefore, the directional terms used are used to illustrate and understand the application, rather than to limit the application. In the figure, units with similar structures are indicated by the same reference numerals.
柔性阵列基板以其厚度薄、可弯折性能而闻名，然而在将柔性阵列基板弯折的过程中，往往因为弯折区域所受的应力过大而导致弯折区域以及弯折区域中的信号走线断裂，导致柔性阵列基板发生不良；此外，随着产品的更新，柔性阵列基板的弯折半径不断减小，使得弯折区域所受应力越来越大，急切需要设计一种结构能够控制、缓解弯折区域的应力，提高柔性阵列基板的弯折性能。Flexible array substrates are known for their thin thickness and bendable performance. However, in the process of bending the flexible array substrate, the bending area is often subjected to excessive stress, which leads to signals in the bending area and the bending area. Broken wiring leads to defects in the flexible array substrate; in addition, with the update of products, the bending radius of the flexible array substrate continues to decrease, making the bending area more and more stressed. It is urgent to design a structure that can be controlled , Relieve the stress in the bending area and improve the bending performance of the flexible array substrate.
本申请针对现有的柔性阵列基板及柔性显示面板，为了实现高屏占比对柔性阵列基板进行弯折时，会使柔性阵列基板上的金属走线产生较大应力，进一步导致金属走线出现断裂的现象的技术问题，本实施例能够解决该缺陷。This application is directed to the existing flexible array substrates and flexible display panels. When the flexible array substrate is bent in order to achieve a high screen-to-body ratio, the metal traces on the flexible array substrate will be subjected to greater stress, which further leads to the appearance of metal traces. This embodiment can solve the technical problem of the fracture phenomenon.
实施例一：Example one:
如图1所示，为本申请柔性阵列基板实施例一的结构示意图。其中，所述柔性阵列基板包括显示区域10以及位于所述显示区域10一侧的弯折区域20，所述柔性阵列基板还包括第一柔性衬底11、水氧阻隔层12、第二柔性衬底13、缓冲层14以及阵列结构层；As shown in FIG. 1, it is a schematic structural diagram of Embodiment 1 of a flexible array substrate of this application. Wherein, the flexible array substrate includes a display area 10 and a bending area 20 located on one side of the display area 10. The flexible array substrate also includes a first flexible substrate 11, a water and oxygen barrier layer 12, and a second flexible liner. Bottom 13, buffer layer 14, and array structure layer;
所述阵列结构层位于所述显示区域10的部分具有第一源漏极走线111，所述阵列结构层位于所述弯折区域20的部分具有第二源漏极走线，所述第二源漏极走线与所述缓冲层14之间的相对距离小于所述第一源漏极走线111与所述缓冲层14之间的相对距离。The portion of the array structure layer located in the display area 10 has a first source and drain wiring 111, and the portion of the array structure layer located in the bending area 20 has a second source and drain wiring. The relative distance between the source-drain traces and the buffer layer 14 is smaller than the relative distance between the first source-drain traces 111 and the buffer layer 14.
具体地，所述阵列结构层还包括由下至上设置的有源层15、第一栅极绝缘层16、第一栅极17、第二栅极绝缘层18、第二栅极19、层间绝缘层110、平坦化层112以及阳极113。Specifically, the array structure layer further includes an active layer 15, a first gate insulating layer 16, a first gate 17, a second gate insulating layer 18, a second gate 19, and interlayers arranged from bottom to top. The insulating layer 110, the planarization layer 112, and the anode 113.
所述柔性阵列基板的具体制备方法如下：The specific preparation method of the flexible array substrate is as follows:
首先提供一玻璃基板，在所述玻璃基板上沉积第一柔性衬底11，所述第一柔性衬底11的材料优选为聚酰亚胺薄膜，所述第一柔性衬底11的厚度优选为10微米。之后，在所述柔性衬底11上沉积水氧阻隔层12，所述水氧阻隔层12的材料为二氧化硅，其厚度优选为500纳米。接着，在所述水氧阻隔层12上沉积第二柔性衬底13，所述第二柔性衬底13的材料优选为聚酰亚胺薄膜，所述第二柔性衬底13的厚度优选为10微米。First, a glass substrate is provided, and a first flexible substrate 11 is deposited on the glass substrate. The material of the first flexible substrate 11 is preferably a polyimide film, and the thickness of the first flexible substrate 11 is preferably 10 microns. After that, a water and oxygen barrier layer 12 is deposited on the flexible substrate 11, the material of the water and oxygen barrier layer 12 is silicon dioxide, and its thickness is preferably 500 nanometers. Next, a second flexible substrate 13 is deposited on the water and oxygen barrier layer 12. The material of the second flexible substrate 13 is preferably a polyimide film, and the thickness of the second flexible substrate 13 is preferably 10 Micrometers.
之后在所述第二柔性衬底13上制备缓冲层14，所述缓冲层14由下层二氧化硅、中层硅氮化物及上层二氧化硅构成的层叠膜。所述下层二氧化硅的厚度优选为500纳米，所述中层硅氮化物的厚度优选为40纳米，所述上层二氧化硅的厚度优选为200纳米。Then, a buffer layer 14 is prepared on the second flexible substrate 13, and the buffer layer 14 is a laminated film composed of a lower layer of silicon dioxide, a middle layer of silicon nitride, and an upper layer of silicon dioxide. The thickness of the lower layer silicon dioxide is preferably 500 nanometers, the thickness of the middle layer silicon nitride is preferably 40 nanometers, and the thickness of the upper layer silicon dioxide is preferably 200 nanometers.
接着在所述缓冲层14上制备有源层15，所述有源层15的材料为多晶硅（Poly-Si），对所述有源层15的边缘两端采用P+离子掺杂，形成离子掺杂层151，所述有源层15的厚度优选为50纳米Next, an active layer 15 is prepared on the buffer layer 14. The material of the active layer 15 is polysilicon (Poly-Si), and both ends of the active layer 15 are doped with P+ ions to form ion doping. The impurity layer 151, the thickness of the active layer 15 is preferably 50 nanometers
之后在所述缓冲层14上制备第一栅极绝缘层16，所述第一栅极绝缘层16完全覆盖所述有源层15，所述第一栅极绝缘层16的材料为二氧化硅，所述第一栅极绝缘层16的厚度优选为140纳米。A first gate insulating layer 16 is then prepared on the buffer layer 14. The first gate insulating layer 16 completely covers the active layer 15, and the material of the first gate insulating layer 16 is silicon dioxide The thickness of the first gate insulating layer 16 is preferably 140 nanometers.
再之后在所述第一栅极绝缘层16上沉积第一栅极17，所述第一栅极17的材料为钼，所述第一栅极17的厚度优选为250纳米。Then, a first gate 17 is deposited on the first gate insulating layer 16, the material of the first gate 17 is molybdenum, and the thickness of the first gate 17 is preferably 250 nanometers.
接着在所述第一栅极绝缘层16上沉积第二栅极绝缘层18，所述第二栅极绝缘层18完全覆盖所述第一栅极17，所述第二栅极绝缘层18的材料为硅氮化物，所述第二栅极绝缘层18的厚度优选为140纳米。Next, a second gate insulating layer 18 is deposited on the first gate insulating layer 16, the second gate insulating layer 18 completely covers the first gate 17, and the second gate insulating layer 18 The material is silicon nitride, and the thickness of the second gate insulating layer 18 is preferably 140 nanometers.
再之后在所述第二栅极绝缘层18上沉积第二栅极19，所述第二栅极19的材料为钼，所述第二栅极19的厚度优选为250纳米。Then, a second gate 19 is deposited on the second gate insulating layer 18, the material of the second gate 19 is molybdenum, and the thickness of the second gate 19 is preferably 250 nanometers.
接着在所述第二栅极绝缘层18上沉积层间绝缘层110，所述层间绝缘层110完全覆盖所述第二栅极19，所述层间绝缘层110的材料为二氧化硅，所述层间绝缘层110的厚度优选为500纳米。Next, an interlayer insulating layer 110 is deposited on the second gate insulating layer 18, the interlayer insulating layer 110 completely covers the second gate 19, and the material of the interlayer insulating layer 110 is silicon dioxide, The thickness of the interlayer insulating layer 110 is preferably 500 nanometers.
之后，在所述层间绝缘层110上制备第一源漏极走线111，所述第一源漏极走线111经由过孔与所述离子掺杂层151电性连接，所述第一源漏极走线111的材料为铜、铝、银以及钛中的一种或一种以上的组合，优选为下层钛膜、中层铝膜及上层钛膜构成的层叠膜。其中，下层钛膜的厚度优选为80纳米，中层铝膜的厚度优选为600纳米，上层钛膜的厚度优选为50纳米。After that, a first source-drain trace 111 is prepared on the interlayer insulating layer 110, and the first source-drain trace 111 is electrically connected to the ion doped layer 151 through a via hole, and the first The material of the source and drain wiring 111 is one or a combination of copper, aluminum, silver and titanium, preferably a laminated film composed of a lower titanium film, a middle aluminum film, and an upper titanium film. Among them, the thickness of the lower titanium film is preferably 80 nm, the thickness of the middle aluminum film is preferably 600 nm, and the thickness of the upper titanium film is preferably 50 nm.
接着，在所述层间绝缘层110上制备平坦化层112，所述平坦化层112的材料为聚酰亚胺薄膜，所述平坦化层112的厚度优选为200纳米。Next, a planarization layer 112 is prepared on the interlayer insulating layer 110, the material of the planarization layer 112 is a polyimide film, and the thickness of the planarization layer 112 is preferably 200 nanometers.
之后，在所述平坦化层112上制备阳极113，所述阳极113经由另一过孔与所述第一源漏极走线111电性连接，所述阳极113由下层ITO(氧化铟锡)膜、中层银膜及上层ITO膜构成的层叠膜，所述下层ITO膜的厚度优选为15纳米，所述中层银膜的厚度优选为100纳米，所述上层ITO膜的厚度优选为15纳米，最后形成所述阵列结构层。After that, an anode 113 is prepared on the planarization layer 112, and the anode 113 is electrically connected to the first source/drain trace 111 through another via hole. The anode 113 is made of ITO (Indium Tin Oxide). The thickness of the lower ITO film is preferably 15 nm, the thickness of the middle silver film is preferably 100 nm, and the thickness of the upper ITO film is preferably 15 nm, Finally, the array structure layer is formed.
具体的，所述阵列结构层位于所述弯折区域20的部分还包括第二源漏极走线，所述第二源漏极走线与所述缓冲层14之间的相对距离D2小于所述第一源漏极走线111与所述缓冲层14之间的相对距离D1。其中，所述第二源漏极走线还包括第三源漏极子走线21以及第四源漏极子走线22，所述第三源漏极子走线21位于所述缓冲层14、所述第一栅极绝缘层16以及所述第二栅极绝缘层18中的任意一层上，所述第四源漏极子走线22位于所述层间绝缘层110上；所述第三源漏极子走线21通过第一过孔23与所述第四源漏极子走线22电性连接。Specifically, the portion of the array structure layer located in the bending region 20 further includes a second source-drain trace, and the relative distance D2 between the second source-drain trace and the buffer layer 14 is less than The relative distance D1 between the first source-drain trace 111 and the buffer layer 14. Wherein, the second source-drain wiring further includes a third source-drain sub-wiring 21 and a fourth source-drain sub-wiring 22, and the third source-drain sub-wiring 21 is located in the buffer layer 14. , On any one of the first gate insulating layer 16 and the second gate insulating layer 18, the fourth source-drain sub-wiring 22 is located on the interlayer insulating layer 110; The third source-drain sub-wire 21 is electrically connected to the fourth source-drain sub-wire 22 through the first via 23.
由于所述第二源漏极走线与所述缓冲层14之间的相对距离D2小于所述第一源漏极走线111与所述缓冲层14之间的相对距离D1。因此，所述柔性衬底基板位于所述弯折区域20的源漏极走线与所述柔性衬底基板位于所述显示区域10的源漏极走线存在着一定的高度差h1，此高度差h1可以耦合所述柔性阵列基板与源漏极走线之间的应力，使得在对所述柔性阵列基板进行弯折的过程中，位于柔性阵列基板的弯折区域中的源漏极走线受到的应力较小，避免弯折过程中源漏极走线发生断裂，提高了所述柔性阵列基板的弯折性能。Because the relative distance D2 between the second source-drain trace and the buffer layer 14 is smaller than the relative distance D1 between the first source-drain trace 111 and the buffer layer 14. Therefore, there is a certain height difference h1 between the source and drain traces of the flexible substrate located in the bending area 20 and the source and drain traces of the flexible substrate located in the display area 10. The difference h1 can couple the stress between the flexible array substrate and the source/drain traces, so that in the process of bending the flexible array substrate, the source/drain traces located in the bending area of the flexible array substrate The stress received is small, which prevents the source and drain wires from breaking during the bending process, and improves the bending performance of the flexible array substrate.
具体的，所述第三源漏极子走线21的材料为铝，所述第三源漏极子走线21的厚度优选为50纳米；所述第四源漏极子走线22为下层钛膜、中层铝膜及上层钛膜构成的层叠膜，所述下层钛膜的厚度优选为80纳米，所述中层铝膜的厚度优选为600纳米，所述上层钛膜的厚度优选为50纳米。Specifically, the material of the third source and drain sub-wiring 21 is aluminum, and the thickness of the third source and drain sub-wiring 21 is preferably 50 nanometers; the fourth source and drain sub-wiring 22 is a lower layer A laminated film composed of a titanium film, a middle aluminum film and an upper titanium film, the thickness of the lower titanium film is preferably 80 nm, the thickness of the middle aluminum film is preferably 600 nm, and the thickness of the upper titanium film is preferably 50 nm .
如图2所示，为本申请柔性阵列基板实施例一中源漏极走线的结构示意图。其中，所述第一源漏极走线111与所述第四源漏极子走线22电性连接。As shown in FIG. 2, it is a schematic diagram of the source and drain wiring structure in the first embodiment of the flexible array substrate of this application. Wherein, the first source-drain wiring 111 is electrically connected to the fourth source-drain sub-wiring 22.
实施例二：Embodiment two:
一种柔性阵列基板，如图3所示，其与实施例一的不同之处仅在于所述第二源漏极走线31位于所述缓冲层14、所述第一栅极绝缘层16以及所述第二栅极绝缘层18中的任意一层上。所述第二源漏极走线31与所述缓冲层14之间的相对距离D3小于所述第一源漏极走线111与所述缓冲层14之间的相对距离D1。因此，所述柔性衬底基板位于所述弯折区域20的源漏极走线与所述柔性衬底基板位于所述显示区域10的源漏极走线存在着一定的高度差h2，此高度差h2可以耦合所述柔性阵列基板与源漏极走线之间的应力，使得在对所述柔性阵列基板进行弯折的过程中，位于柔性阵列基板的弯折区域中的源漏极走线受到的应力较小，避免弯折过程中源漏极走线发生断裂，提高了所述柔性阵列基板的弯折性能。A flexible array substrate, as shown in FIG. 3, is different from the first embodiment only in that the second source-drain wiring 31 is located in the buffer layer 14, the first gate insulating layer 16, and On any one of the second gate insulating layers 18. The relative distance D3 between the second source-drain trace 31 and the buffer layer 14 is smaller than the relative distance D1 between the first source-drain trace 111 and the buffer layer 14. Therefore, there is a certain height difference h2 between the source and drain traces of the flexible substrate located in the bending area 20 and the source and drain traces of the flexible substrate located in the display area 10. The difference h2 can couple the stress between the flexible array substrate and the source/drain traces, so that in the process of bending the flexible array substrate, the source/drain traces located in the bending area of the flexible array substrate The stress received is small, which prevents the source and drain wires from breaking during the bending process, and improves the bending performance of the flexible array substrate.
实施例三：Example three:
一种柔性阵列基板，如图4所示，其与实施例一的不同之处仅在于所述第二源漏极走线41位于所述层间绝缘层110上。所述第二源漏极走线41与所述缓冲层14之间的相对距离D4小于所述第一源漏极走线111与所述缓冲层14之间的相对距离D1。因此，所述柔性衬底基板位于所述弯折区域20的源漏极走线与所述柔性衬底基板位于所述显示区域10的源漏极走线存在着一定的高度差h3，此高度差h3可以耦合所述柔性阵列基板与源漏极走线之间的应力，使得在对所述柔性阵列基板进行弯折的过程中，位于柔性阵列基板的弯折区域中的源漏极走线受到的应力较小，避免弯折过程中源漏极走线发生断裂，提高了所述柔性阵列基板的弯折性能。A flexible array substrate, as shown in FIG. 4, is different from the first embodiment only in that the second source and drain wiring 41 is located on the interlayer insulating layer 110. The relative distance D4 between the second source-drain trace 41 and the buffer layer 14 is smaller than the relative distance D1 between the first source-drain trace 111 and the buffer layer 14. Therefore, there is a certain height difference h3 between the source and drain traces of the flexible substrate located in the bending area 20 and the source and drain traces of the flexible substrate located in the display area 10. The difference h3 can couple the stress between the flexible array substrate and the source/drain traces, so that in the process of bending the flexible array substrate, the source/drain traces located in the bending area of the flexible array substrate The stress received is small, which prevents the source and drain wires from breaking during the bending process, and improves the bending performance of the flexible array substrate.
进一步地，本申请还提供一种柔性显示面板，所述柔性显示面板包括具有上述实施例描述的任一特征的柔性阵列基板。其中，所述柔性显示面板的类型可以为有机发光二极管（Organic Light-Emitting Diode，OLED）面板、平面转换(In-Plane Switching，IPS)面板、扭曲向列型(Twisted Nematic，TN) 面板、垂直配向技术(Vertical Alignment，VA)面板、QLED(Quantum Dot Light Emitting Diodes，量子点发光)显示面板或者micro LED(微发光二极管，μLED)面板等显示面板中的任意一种，本申请对此并不具体限制。Further, the present application also provides a flexible display panel, which includes a flexible array substrate having any of the features described in the above embodiments. Wherein, the type of the flexible display panel may be an organic light emitting diode (Organic Light-Emitting Diode (OLED) panel, In-Plane Switching (IPS) panel, Twisted Nematic (TN) panel, Vertical Alignment (VA) panel, QLED (Quantum Dot Light Emitting) Any one of display panels such as Diodes (quantum dot light emitting) display panels or micro LED (micro light emitting diodes, μLED) panels, which is not specifically limited in this application.
本申请所提供的柔性阵列基板及柔性显示面板，在弯折区域内设置源漏极走线且位于显示区域内的源漏极走线的下方，提高了柔性阵列基板位于弯折区域的可靠性，进一步避免了柔性阵列基板因为弯折造成金属走线断裂的风险。In the flexible array substrate and flexible display panel provided by the present application, the source and drain traces are arranged in the bending area and are located below the source and drain traces in the display area, which improves the reliability of the flexible array substrate in the bending area This further avoids the risk of metal traces breaking due to bending of the flexible array substrate.
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。In summary, although the application has been disclosed as above in preferred embodiments, the above-mentioned preferred embodiments are not intended to limit the application, and those of ordinary skill in the art can make various decisions without departing from the spirit and scope of the application. Such changes and modifications, so the protection scope of this application is subject to the scope defined by the claims.

Claims (10)

  1. 一种柔性阵列基板，包括显示区域以及位于所述显示区域一侧的弯折区域，其中，还包括第一柔性衬底、水氧阻隔层、第二柔性衬底、缓冲层以及阵列结构层；A flexible array substrate includes a display area and a bending area located on one side of the display area, wherein it also includes a first flexible substrate, a water and oxygen barrier layer, a second flexible substrate, a buffer layer and an array structure layer;
    其中，所述阵列结构层位于所述显示区域的部分具有第一源漏极走线，所述阵列结构层位于所述弯折区域的部分具有第二源漏极走线，所述第二源漏极走线与所述缓冲层之间的相对距离小于所述第一源漏极走线与所述缓冲层之间的相对距离。Wherein, the portion of the array structure layer located in the display area has a first source and drain wiring, the portion of the array structure layer located in the bending area has a second source and drain wiring, and the second source The relative distance between the drain trace and the buffer layer is smaller than the relative distance between the first source drain trace and the buffer layer.
  2. 根据权利要求1所述的柔性阵列基板，其中，所述第一源漏极走线及所述第二源漏极走线的材料为铜、铝、银以及钛中的一种或一种以上的组合。The flexible array substrate according to claim 1, wherein the materials of the first source and drain traces and the second source and drain traces are one or more of copper, aluminum, silver, and titanium The combination.
  3. 根据权利要求1所述的柔性阵列基板，其中，所述阵列结构层还包括由下至上设置的有源层、第一栅极绝缘层、第一栅极、第二栅极绝缘层、第二栅极、层间绝缘层、平坦化层以及阳极。The flexible array substrate according to claim 1, wherein the array structure layer further comprises an active layer, a first gate insulating layer, a first gate, a second gate insulating layer, and a second gate insulating layer arranged from bottom to top. Gate, interlayer insulating layer, planarization layer and anode.
  4. 根据权利要求3所述的柔性阵列基板，其中，所述第二源漏极走线位于所述缓冲层、所述第一栅极绝缘层以及所述第二栅极绝缘层中的任意一层上。The flexible array substrate according to claim 3, wherein the second source and drain traces are located on any one of the buffer layer, the first gate insulating layer, and the second gate insulating layer on.
  5. 根据权利要求3所述的柔性阵列基板，其中，所述第二源漏极走线位于所述层间绝缘层上。4. The flexible array substrate according to claim 3, wherein the second source and drain traces are located on the interlayer insulating layer.
  6. 根据权利要求3所述的柔性阵列基板，其中，所述第二源漏极走线还包括第三源漏极子走线以及第四源漏极子走线，所述第三源漏极子走线位于所述缓冲层、所述第一栅极绝缘层以及所述第二栅极绝缘层中的任意一层上，所述第四源漏极子走线位于所述层间绝缘层上。The flexible array substrate according to claim 3, wherein the second source-drain wiring further comprises a third source-drain sub-wiring and a fourth source-drain sub-wiring, the third source-drain sub-wiring The wiring is located on any one of the buffer layer, the first gate insulating layer, and the second gate insulating layer, and the fourth source-drain sub-wiring is located on the interlayer insulating layer .
  7. 根据权利要求6所述的柔性阵列基板，其中，所述第三源漏极子走线通过第一过孔与所述第四源漏极子走线电性连接。7. The flexible array substrate according to claim 6, wherein the third source and drain sub-wires are electrically connected to the fourth source and drain sub-wires through a first via hole.
  8. 根据权利要求6所述的柔性阵列基板，其中，所述第三源漏极子走线的材料为铝，所述第四源漏极子走线为下层钛膜、中层铝膜及上层钛膜构成的层叠膜。The flexible array substrate according to claim 6, wherein the material of the third source and drain sub-wiring is aluminum, and the fourth source and drain sub-wiring is a lower titanium film, a middle aluminum film and an upper titanium film Structured laminated film.
  9. 根据权利要求1所述的柔性阵列基板，其中，所述缓冲层为下层二氧化硅、中层硅氮化物及上层二氧化硅构成的层叠膜。The flexible array substrate according to claim 1, wherein the buffer layer is a laminated film composed of a lower layer silicon dioxide, a middle layer silicon nitride, and an upper layer silicon dioxide.
  10. 一种柔性显示面板，其中，包括如权利要求1所述的柔性阵列基板。A flexible display panel, which comprises the flexible array substrate according to claim 1.
PCT/CN2019/111168 2019-07-08 2019-10-15 Flexible array substrate and flexible display panel WO2021003871A1 (en)

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