WO2020258567A1 - 区块链数字签名方法与系统 - Google Patents

区块链数字签名方法与系统 Download PDF

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WO2020258567A1
WO2020258567A1 PCT/CN2019/108917 CN2019108917W WO2020258567A1 WO 2020258567 A1 WO2020258567 A1 WO 2020258567A1 CN 2019108917 W CN2019108917 W CN 2019108917W WO 2020258567 A1 WO2020258567 A1 WO 2020258567A1
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digital signature
coprocessor
fpga
blockchain
main
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French (fr)
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李雪雷
赵雅倩
李仁刚
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/38—Payment protocols; Details thereof
    • G06Q20/382—Payment protocols; Details thereof insuring higher security of transaction
    • G06Q20/3825—Use of electronic signatures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/38—Payment protocols; Details thereof
    • G06Q20/389—Keeping log of transactions for guaranteeing non-repudiation of a transaction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q40/00—Finance; Insurance; Tax strategies; Processing of corporate or income taxes
    • G06Q40/04—Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange

Definitions

  • the invention relates to the technical field of reconfigurable computing, in particular to a blockchain digital signature method and system.
  • Digital signatures are used in blockchain applications to achieve the accuracy and non-repudiation of messages.
  • digital signatures play an extremely important security role and directly affect the response time, throughput, and scalability of blockchain applications in terms of data processing speed.
  • the embodiments of the present invention provide a blockchain digital signature method and system to increase the data processing speed of the digital signature.
  • a block chain digital signature method based on a block chain digital signature system
  • the block chain digital signature system includes a main processor and a co-processor; the main processor is at least used to run a block chain application main program;
  • the coprocessor is used as a hardware acceleration unit to run multiple digital signature subprograms; the multiple digital signature subprograms correspond to different digital signature types;
  • the method includes:
  • the main processor runs the main blockchain application program
  • the main blockchain application program determines the digital signature type to which the digital signature processing to be executed belongs; the determined digital signature type is the target digital signature type; the target digital signature type corresponds to The digital signature subroutine is a digital signature subroutine;
  • the main block chain application program calls the coprocessor to run the target digital signature subroutine to perform parallel and streamlined digital signature processing.
  • the main processor is a general-purpose CPU; the coprocessor is a field programmable gate array FPGA.
  • the main blockchain application program is further used to perform the following operations:
  • the main blockchain application program is further used to perform the following operations:
  • running the target digital signature subroutine by the coprocessor to perform parallel and streamlined digital signature processing includes:
  • auxiliary data set perform parallel and streamlined computing operations on the data in the to-be-processed data set
  • a completion signal is returned to the host.
  • the parameter information includes: buffer size, data writing and reading configuration information, execution configuration information of the target digital signature subroutine, and FPGA platform information.
  • the method further includes: using a high-level language to complete descriptions of multiple types of digital signature algorithms to obtain the multiple digital signature subroutines Complete the automatic mapping of the description of the various types of digital signature algorithms to the bit stream executed by the FPGA through the mapping tool, and generate the corresponding AOCX file; compile the main program to generate the executable on the general CPU Executable program file.
  • the main processor running the blockchain application main program includes: the general CPU running the executable program file; the coprocessor running the target digital signature subprogram includes: the FPGA Run the AOCX file corresponding to the target digital signature subprogram.
  • a blockchain digital signature system includes a main processor and a coprocessor as a hardware acceleration unit; wherein, the coprocessor is used to run multiple digital signature subprograms; the multiple digital signature subprograms correspond to different Digital signature type;
  • the main processor is used for:
  • the digital signature type to which the digital signature processing to be executed belongs determines the digital signature type to which the digital signature processing to be executed belongs; the determined digital signature type is the target digital signature type; the digital signature subroutine corresponding to the target digital signature type is the digital signature subroutine program;
  • the main processor is a CPU; the coprocessor is a field programmable gate array FPGA.
  • the main processor cooperates with the co-processor to provide blockchain application services, where the main processor is responsible for determining the required target from multiple digital signature types when digital signature processing is required.
  • Digital signature type and call the coprocessor to execute the target digital signature subroutine corresponding to the target digital signature type.
  • the parallel pipeline method of the coprocessor can increase the parallelism and data processing speed of the digital signature algorithm, thereby improving the digital signature algorithm The data processing speed during execution improves the response time, throughput and scalability of blockchain applications.
  • Figure 1 is a schematic diagram of an application scenario of a blockchain digital signature system provided by an embodiment of the present invention
  • Figure 2 is an exemplary structure diagram of a blockchain digital signature system provided by an embodiment of the present invention.
  • FIG. 3 is another exemplary structure diagram of a blockchain digital signature system provided by an embodiment of the present invention.
  • FIG. 4 is an exemplary flowchart of a blockchain digital signature method provided by an embodiment of the present invention.
  • FIG. 5 is an example diagram of file generation provided by an embodiment of the present invention.
  • Fig. 6 is another exemplary flowchart of a blockchain digital signature method provided by an embodiment of the present invention.
  • Blockchain is a new application mode of computer technology such as distributed data storage, point-to-point transmission, consensus mechanism, and encryption algorithm. Blockchain is an important concept of Bitcoin. It is essentially a decentralized database. At the same time, as the underlying technology of Bitcoin, it is a series of data blocks generated using cryptographic methods. Each data block contains A batch of Bitcoin network transaction information is used to verify the validity of the information (anti-counterfeiting) and generate the next block;
  • OpenCL Open Computing Language, open computing language
  • DDR Dual Data Rate, double-rate synchronous dynamic random access memory
  • FPGA Field-Programmable Gate Array, field programmable gate array
  • DSA Digital Signature Algorithm, standard digital signature algorithm
  • GPU Graphics Processing Unit, graphics processor
  • PCI Peripheral Component Interconnect, the interconnection standard of peripheral components
  • PCI-E PCI Express.
  • the PCI-E interface is a relatively common interface standard on the motherboard. It is currently mainly provided for devices that need to directly communicate with the CPU, usually to expand functions that are not supported on the motherboard;
  • DDRSDRAM Double Data RateSDRAM, double-rate synchronous dynamic random access memory
  • DDR3 A computer memory specification.
  • the memory products belonging to the SDRAM family provide higher operating performance and lower voltage than DDR2SDRAM. It is the successor of DDR2SDRAM (synchronous dynamic dynamic random access memory) (increased by eight times), and it is also a popular memory.
  • Product specifications ;
  • EXE File executable program, executable program.
  • An executable program is a binary executable program that can float in the operating system storage space. It can be loaded into memory, loaded and executed by the operating system;
  • OpenCL Open Computing Language, an open computing language. OpenCL is the first open, free standard for general-purpose parallel programming of heterogeneous systems. It is also a unified programming environment that facilitates software developers to write efficient and portable code for high-performance computing servers, desktop computing systems, and handheld devices. Widely applicable to other parallel processors such as multi-core processors (CPU), graphics processing units (GPU), Cell type architectures, and digital signal processors (DSP). It has broad applications in various fields such as games, entertainment, scientific research, and medical treatment. Development prospects;
  • GCC GNU Compiler Collection, GNU compiler suite, including the front end of C, C++, Objective-C, Fortran, Java, Ada and Go languages, as well as libraries of these languages (such as libstdc++, libgcj, etc.).
  • GCC was originally used as the official compiler of the GNU operating system, and has now been adopted as a standard compiler by most Unix-like operating systems (such as Linux, BSD, Mac OS X, etc.);
  • MAC MessageAuthenticationCode, message authentication code.
  • Blockchain technology can be applied to the fields of product traceability and personal credit investigation.
  • Digital signature is the basic technology and core algorithm for blockchain applications.
  • Digital signature algorithms are some algorithms that have been applied earlier and mature in technology.
  • the signer uses his own key to process the message to generate a digital signature (signature).
  • the verifier who receives the message uses the public (verifiable) public key of the system to verify the digital signature to confirm the source and accuracy of the message.
  • the digital signature processing process requires certain computing resources. Under the conditions of data explosion and limited response time, it has become a severe challenge to meet the user's response to data access as quickly as possible.
  • the embodiments of the present invention provide a blockchain digital signature method and system.
  • the above-mentioned blockchain digital signature system may specifically be a back-end server 102 (such as an application server, a platform server, a digital signature server), and an example of its application scenario is as follows: a user submits a digital signature processing request to the web server 101 ( Generate a message signature request or verification request), the web server 101 communicates with the back-end server 102, and the back-end server 102 performs digital signature processing.
  • a back-end server 102 such as an application server, a platform server, a digital signature server
  • an example of its application scenario is as follows: a user submits a digital signature processing request to the web server 101 ( Generate a message signature request or verification request), the web server 101 communicates with the back-end server 102, and the back-end server 102 performs digital signature processing.
  • the above-mentioned blockchain digital signature system may include a main processor 1 and a coprocessor 2.
  • the main processor 1 is used to run at least the main program 3 of the blockchain application; and the coprocessor 2 is used as a hardware acceleration Unit for running multiple digital signature subroutines 4.
  • the main blockchain application program will call the coprocessor 2 to run the digital signature subroutine to perform parallel and streamlined digital signature processing.
  • the parallel pipeline method of the coprocessor can increase the parallelism and data processing speed of the digital signature algorithm, thereby improving the throughput performance when the digital signature algorithm is executed.
  • the blockchain digital signature system is a heterogeneous acceleration platform: the main processor 1 is a general-purpose CPU 1', and the co-processor 2 is an FPGA 2'.
  • the PCI-E interface is used for data communication between the general-purpose CPU1' and FPGA2', and the DDR3 memory on the FPGA development board is used as a data buffer (Buffer).
  • the coprocessor may also be a GPU.
  • the digital signature algorithm is very suitable for parallel and pipelined accelerated processing, which is quite consistent with the computing characteristics of FPGA and GPU. Therefore, using FPGA or GPU as the hardware acceleration unit (or called hardware circuit) for digital signature processing, its parallel pipeline processing method can increase the parallelism and data processing speed of the digital signature algorithm, thereby improving the throughput of the digital signature algorithm execution Rate performance.
  • FPGA can easily achieve fine-grained parallelism, which is equivalent to multiple threads from the CPU.
  • the multiple threads of the CPU require expensive servers or clusters to support, but the FPGA does not need it. Therefore, the solution provided by the embodiment of the present invention can reduce the hardware cost.
  • Figures 4 and 5 show an exemplary process of the blockchain digital signature method executed by the blockchain digital signature system, including:
  • the main blockchain application program can be written in C language.
  • the main blockchain application program can perform processing operations other than or before digital signature processing, such as scheduling, preparing data to be processed, and data recovery.
  • S1 Use OpenCL high-level language to complete the description of multiple types of digital signature algorithms, and obtain multiple digital signature subroutines.
  • Exemplary types of digital signature algorithms include: standard digital signature algorithms, proxy signature algorithms, blind signature algorithms, group signature algorithms, and ring signature algorithms. Different algorithms are used in different fields to achieve their specific functions, but the signature algorithm will not change at all: to ensure the source of the message and its reliability.
  • each digital signature subprogram may be a Kernel program file oriented to the FPGA platform.
  • the digital signature processing algorithm includes two parts: signature and verification.
  • the Kernel program file corresponding to a digital signature processing algorithm may specifically include a Kernel program file for signature and a Kernel for verification. program files.
  • FPGA since FPGA currently only supports the OpenCL high-level language, this embodiment uses the OpenCL high-level language to complete the description of the digital signature algorithm. But the future does not rule out the possibility that FPGA can support other high-level languages.
  • the coprocessor is a GPU, other high-level languages can also be used to complete the description of the digital signature algorithm.
  • AOC Advanced Driver Assistance Code
  • Kernel program files that is, automatic mapping
  • the AOCX file corresponding to a digital signature algorithm includes a Kernel program file for signing and a Kernel program file for verification
  • the AOCX file correspondingly includes the AOCX file for signing and the AOCX file.
  • the AOCX file performs calculations on the hardware circuit of the digital signature core algorithm on the FPGA.
  • S3 Compile the main program of the blockchain application to generate an executable program file that can be executed on a general-purpose CPU.
  • the GCC compiler can be used to compile the host-side program to generate an EXE File.
  • S4 The main processor runs the main program of the blockchain application.
  • the above executable program file is run on a general-purpose CPU.
  • a general-purpose CPU can load executable program files into memory to run.
  • Each digital signature type can correspond to a unique identifier, and the digital signature type can be determined by the type identifier.
  • the type identification can be carried in the application request.
  • the application request is a request that triggers the main program of the blockchain application to perform digital signature processing.
  • the determined digital signature type can be called the target digital signature type, and the digital signature subprogram corresponding to the target digital signature type is called the digital signature subprogram.
  • S6 The main program of the blockchain application calls the coprocessor to run the target digital signature subroutine to perform parallel and streamlined digital signature processing.
  • the main processor cooperates with the co-processor to provide blockchain application services, where the main processor is responsible for determining the required target from multiple digital signature types when digital signature processing is required.
  • Digital signature type and call the coprocessor to execute the target digital signature subroutine corresponding to the target digital signature type.
  • the parallel pipeline method of the coprocessor can increase the parallelism and data processing speed of the digital signature algorithm, thereby improving the digital signature algorithm The data processing speed during execution improves the response time, throughput and scalability of blockchain applications.
  • FPGA as a coprocessor can effectively improve the execution performance of the core digital signature algorithm.
  • the above-mentioned automatic mapping method can effectively shorten the time for deploying the digital signature algorithm to the FPGA-based heterogeneous acceleration platform and improve the product development cycle.
  • the specific operations performed by the general-purpose CPU running the executable program file may include:
  • digital signature processing includes signature and verification.
  • the data set to be processed may include data to be signed; and for the verification process, the data set to be processed may include data to be verified (signed data).
  • S602 Create a buffer for data communication between the host side and the FPGA side.
  • the buffer is located on the DDR memory on the FPGA development board.
  • the auxiliary data set participates in the operation of digital signature processing.
  • the auxiliary data set may include: block information of the data to be signed (indicating how large the data to be signed is divided into blocks), the user's private key, and the function (such as a hash function) used in the signing process When calling and other information.
  • the auxiliary data set includes the signature system parameters (modulus, number field, etc.) and the public key.
  • S604 Transmit the prepared data set to be processed to the foregoing cache.
  • auxiliary data set must be transmitted before the data set to be processed.
  • the parameter information may include: cache size, data writing and reading configuration information (such as when to write, when to read, the amount of data written at one time, the amount of data read at one time, etc.), the kernel file Implementation configuration information (for example, when to call) and FPGA platform information (for example, FPGA board model).
  • S606 Determine the digital signature type to which the digital signature processing to be executed belongs, and call the FPGA side to run the target digital signature subroutine.
  • a start signal can be sent to the FPGA first, and then the FPGA-side running target digital signature subroutine can be called.
  • the specific operations performed by the FPGA to run the AOCX file can include:
  • the DDR of the FPGA can be used as a buffer.
  • the auxiliary data set and the data set to be processed can be read in batches from the DDR of the FPGA to the on-chip buffer of the FPGA.
  • S608 According to the auxiliary data set, perform parallel and streamlined computing operations on the data in the data set to be processed.
  • the completion signal can be returned to the host.
  • the data in the cache is read by the host.
  • S612 Complete the digital signature process and output the corresponding signature information or verification result.
  • the steps of the method or model described in combination with the embodiments disclosed in this document can be directly implemented by hardware, a software module executed by a processor, or a combination of the two.
  • the software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, WD-ROM, or all areas in the technical field. Any other known storage medium.

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Abstract

一种区块链数字签名方法与系统，该区块链数字签名系统包括主处理器（1）和协处理器（2）；主处理器（1）至少用于运行区块链应用主程序（3）；协处理器（2）作为硬件加速单元，用于运行多个数字签名子程序（4）；多个数字签名子程序（4）对应不同的数字签名类型；上述方法包括：在需要进行数字签名处理时，区块链应用主程序（3）确定所需执行的数字签名处理所属的数字签名类型；确定出的数字签名类型为目标数字签名类型；目标数字签名类型对应的数字签名子程序为数字签名子程序（4）；区块链应用主程序（3）调用协处理器（2）运行目标数字签名子程序，以进行并行和流水化的数字签名处理。

Description

区块链数字签名方法与系统
本申请要求于2019年6月28日提交中国专利局、申请号为201910575768.4、发明名称为“区块链数字签名方法与系统”的国内申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及可重构计算技术领域，特别涉及区块链数字签名方法与系统。
背景技术
由于信息时代数据量的暴增，信息和数据的隐私安全成为各商业领域内最有价值的资产，尤其在区块链应用中更加注重数据的隐私和安全。
区块链应用中利用数字签名(包含但不限于：群签名、环签名、标准数字签名算法、盲签名等)实现消息的准确性和不可否认性。数字签名作为区块链应用的基础技术和核心算法，发挥着极其重要的安全作用，在数据处理速度上直接影响区块链应用的响应时间、吞吐量和可扩展性。
发明内容
有鉴于此，本发明实施例提供区块链数字签名方法与系统，以提高数字签名的数据处理速度。
为实现上述目的，本发明实施例提供如下技术方案：
一种区块链数字签名方法，基于区块链数字签名系统，所述区块链数字签名系统包括主处理器和协处理器；所述主处理器至少用于运行区块链应用主程序；所述协处理器作为硬件加速单元，用于运行多个数字签名子程序；所述多个数字签名子程序对应不同的数字签名类型；
所述方法包括：
所述主处理器运行所述区块链应用主程序；
在需要进行数字签名处理时，所述区块链应用主程序确定所需执行的数字签名处理所属的数字签名类型；确定出的数字签名类型为目标数字签名类型；所述目标数字签名类型对应的数字签名子程序为数字签名子程序；
所述区块链应用主程序调用所述协处理器运行所述目标数字签名子程序，以进行并行和流水化的数字签名处理。
可选的，所述主处理器为通用CPU；所述协处理器为现场可编程门阵列FPGA。
可选的，在所述调用协处理器运行所述目标数字签名子程序之前，所述区块链应用主程序还用于执行如下操作：
准备待处理数据集；
创建主机端与FPGA端进行数据通信的缓存；
将辅助数据集传输到所述缓存；
将准备好的待处理数据集传输到所述缓存；
设置FPGA端运行所需的参数信息；
在所述调用协处理器运行所述目标数字签名子程序之后，所述区块链应用主程序还用于执行如下操作：
在所述FPGA端返回完成信号之后，读取FPGA端的执行结果。
可选的，所述协处理器运行所述目标数字签名子程序，以进行并行和流水化的数字签名处理包括：
从所述缓存处读取所述辅助数据集和所述待处理数据集；
依据所述辅助数据集，对所述待处理数据集中的数据进行并行和流水化的计算操作；
将计算操作所得数据写入所述缓存；
在对所述待处理数据集中的数据的计算结束后，向主机端返回完成信号。
可选的，所述参数信息包括：缓存大小、数据的写入和读出配置信息、所述目标数字签名子程序的执行配置信息以及FPGA平台信息。
可选的，在所述主处理器运行所述区块链应用主程序之前，所述方法还包括：采用高级语言完成多种类型的数字签名算法的描述，得到所述多个数字签名子程序；通过映射工具完成所述多种类型的数字签名算法的描述到FPGA所执行比特流的自动化映射，生成相应的AOCX文件；对所述主程序进行编译，生成可在所述通用CPU上执行的可执行程序文件。
可选的，所述主处理器运行所述区块链应用主程序包括：所述通用CPU运行所述可执行程序文件；所述协处理器运行所述目标数字签名子程序包括：所述FPGA运行所述目标数字签名子程序对应的AOCX文件。
一种区块链数字签名系统，包括主处理器和作为硬件加速单元的协处理器；其中，所述协处理器用于运行多个数字签名子程序；所述多个数字签名 子程序对应不同的数字签名类型；
所述主处理器用于：
运行区块链应用主程序；
在需要进行数字签名处理时，确定所需执行的数字签名处理所属的数字签名类型；确定出的数字签名类型为目标数字签名类型；所述目标数字签名类型对应的数字签名子程序为数字签名子程序；
调用所述协处理器运行所述目标数字签名子程序，以进行并行和流水化的数字签名处理。
可选的，所述主处理器为CPU；所述协处理器为现场可编程门阵列FPGA。
可见，在本发明实施例中，主处理器与协作处理器合作提供区块链应用服务，其中主处理器负责在需要进行数字签名处理时，从多种数字签名类型中确定出所需的目标数字签名类型，并调用协作处理器执行运行目标数字签名类型所对应的目标数字签名子程序，协作处理器的并行流水化方式可提高数字签名算法的并行度和数据处理速度，进而改善数字签名算法执行时的数据处理速度，提高区块链应用的响应时间、吞吐量和可扩展性。
附图说明
图1为本发明实施例提供的区块链数字签名系统应用场景示意图；
图2为本发明实施例提供的区块链数字签名系统示例性结构图；
图3为本发明实施例提供的区块链数字签名系统另一示例性结构图；
图4为本发明实施例提供的区块链数字签名方法示例性流程图；
图5为本发明实施例提供的文件生成示例图；
图6为本发明实施例提供的区块链数字签名方法的另一示例性流程图。
具体实施方式
为了引用和清楚起见，下文中使用的技术名词、简写或缩写总结如下：
区块链：Blockchain。区块链是分布式数据存储、点对点传输、共识机制、加密算法等计算机技术的新型应用模式。区块链是比特币的一个重要概念，它本质上是一个去中心化的数据库，同时作为比特币的底层技术，是一串使用密码学方法相关联产生的数据块，每一个数据块中包含了一批次比特币网络交易的信息，用于验证其信息的有效性(防伪)和生成下一个区块；
OpenCL:Open Computing Language，开放式计算语言；
DDR：Dual Data Rate，双倍速率同步动态随机存储器；
FPGA：Field-Programmable Gate Array，现场可编程门阵列；
DSA：Digital Signature Algorithm，标准数字签名算法；
GPU：Graphics Processing Unit，图形处理器；
PCI：Peripheral Component Interconnect，外设部件互连标准；
PCI-E：PCI Express，PCI-E接口是主板上比较通用的一种接口标准，目前主要提供给需要直接与CPU进行通讯的设备使用，通常是为了扩展主板上没有支持的功能；
DDRSDRAM：Double Data RateSDRAM，双倍速率同步动态随机存储器；
DDR3：一种计算机内存规格。属于SDRAM家族的内存产品，提供了相较于DDR2SDRAM更高的运行效能与更低的电压，是DDR2SDRAM(同步动态动态随机存取内存)的后继者(增加至八倍)，也是现时流行的内存产品规格；
EXE File：executable program，可执行程序。可执行程序是可在操作系统存储空间中浮动定位的二进制可执行程序。它可以加载到内存中，由操作系统加载并执行；
OpenCL：Open Computing Language，开放运算语言。OpenCL是第一个面向异构系统通用目的并行编程的开放式、免费标准，也是一个统一的编程环境，便于软件开发人员为高性能计算服务器、桌面计算系统、手持设备编写高效轻便的代码，而且广泛适用于多核心处理器(CPU)、图形处理器(GPU)、Cell类型架构以及数字信号处理器(DSP)等其他并行处理器，在游戏、娱乐、科研、医疗等各种领域都有广阔的发展前景；
GCC：GNU Compiler Collection，GNU编译器套件，包括C、C++、Objective-C、Fortran、Java、Ada和Go语言的前端，也包括了这些语言的库(如libstdc++、libgcj等等)。GCC原本作为GNU操作系统的官方编译器，现已被大多数类Unix操作系统(如Linux、BSD、Mac OS X等)采纳为标准的编译器；
MAC：MessageAuthenticationCode，消息认证码。
区块链技术可应用于商品溯源、个人征信等领域，数字签名是区块链应 用的基础技术和核心算法。
数字签名算法是应用较早、技术成熟的一些算法。在数字签名算法中，签名者利用自己的密钥对消息进行处理，生成数字签名(签章)。收到消息的为验证者，利用系统公开(可验证)的公钥对数字签名进行验证，用来确认消息来源及其准确性。
数字签名处理过程需要一定的计算资源。在数据暴增、响应时间有限的条件下，能够以最快的速度满足用户对数据的存取响应成为一项严峻的挑战。
为解决上述问题，本发明实施例提供了区块链数字签名方法与系统。
请参见图1，上述区块链数字签名系统具体可为后端服务器102(例如应用服务器、平台服务器、数字签名服务器)，其应用场景示例性如下：用户向web服务器101提交数字签名处理请求(生成消息签名请求或验证请求)，web服务器101与后端服务器102通讯，由后端服务器102进行数字签名处理。
请参见图2，上述区块链数字签名系统可包括主处理器1和协处理器2；其中，主处理器1至少用于运行区块链应用主程序3；而协处理器2作为硬件加速单元，用于运行多个数字签名子程序4。
在需要进行数字签名处理时，区块链应用主程序会调用协处理器2运行数字签名子程序，以进行并行和流水化的数字签名处理。协作处理器的并行流水化方式可提高数字签名算法的并行度和数据处理速度，进而改善数字签名算法执行时的吞吐率性能。
在一个示例中，请参见图3，区块链数字签名系统为异构加速平台：主处理器1为通用CPU1’，而协处理器2为FPGA 2’。通用CPU1’与FPGA2’之间采用PCI-E接口进行数据通信，并采用FPGA开发板上的DDR3内存作为数据缓存(Buffer)。
在另一示例中，协处理器也可为GPU。
数字签名算法非常适合于并行、流水化的加速处理，与FPGA、GPU的计算特点相当吻合。因此，采用FPGA或GPU作为数字签名处理的硬件加速单元(或称为硬件电路)，其并行流水化处理方式可提高数字签名算法的并行度和数据处理速度，进而改善数字签名算法执行时的吞吐率性能。
此外，FPGA可以很容易实现细粒化并行，相当于CPU起多个线程。但CPU起多个线程需要价格昂贵的服务器或集群进行支持，而FPGA则不需要， 因此，采用本发明实施例所提供的方案可以降低硬件成本。
下面将以主处理器为通用CPU、协处理器为FPGA的区块链数字签名系统为例，对本发明所提供的技术方案进行具体的介绍。
图4和图5示出了由区块链数字签名系统所执行的区块链数字签名方法的一种示例性流程，包括：
S0：生成区块链应用主程序；
在一个示例中，区块链应用主程序可采用C语言编写。区块链应用主程序可执行除数字签名处理之外或之前的处理操作，例如，调度、准备待处理数据、数据回收等。
S1：采用OpenCL高级语言完成多种类型的数字签名算法的描述，得到多个数字签名子程序。
数字签名算法种类示例性得可包括：标准数字签名算法、代理签名算法、盲签名算法、群签名算法和环签名算法等。不同算法应用在不同领域以实现其特定的功能，但是签名算法的根本不会发生改变：确保消息的来源及其可靠性。
具体的，对于linux操作系统而言，每一数字签名子程序可为面向FPGA平台的Kernel程序文件。
需要说明的是，数字签名处理算法包括签名和验证两部分，则在一个示例中，与一数字签名处理算法对应的Kernel程序文件具体可包含用于签名的Kernel程序文件，以及用于验证的Kernel程序文件。
需要说明的是，由于FPGA目前仅支持OpenCL高级语言，因此，本实施例采用OpenCL高级语言完成数字签名算法的描述。但未来并不排除FPGA可支持其他高级语言的可能。此外，若协处理器为GPU，则也可使用其他高级语言完成数字签名算法的描述。
S2：通过映射工具完成多种类型的数字签名算法的描述到FPGA所执行比特流的自动化映射，生成相应的、可在FPGA上运行的AOCX文件(比特流)。
具体的，可采用AOC(Altera SDK for OpenCL)高层次综合工具对Kernel程序文件进行编译综合(即自动化映射)，生成AOCX文件。
在一个示例中，若与一数字签名算法对应的Kernel程序文件包含用于签 名的Kernel程序文件，以及用于验证的Kernel程序文件，则AOCX文件相应包括用于签名的AOCX文件，以及用于验证的AOCX文件。
具体的，AOCX文件在FPGA上的数字签名核心算法硬件电路上执行计算。
S3：对区块链应用主程序进行编译，生成可在通用CPU上执行的可执行程序文件。
具体的，可采用GCC编译器对主机端程序进行编译，生成EXE File。
S4：主处理器运行区块链应用主程序。
具体的，是在通用CPU上运行上述可执行程序文件。
通用CPU可将可执行程序文件加载至内存运行。
S5：在需要进行数字签名处理时，区块链应用主程序确定所需执行的数字签名处理所属的数字签名类型。
当然，实际上是通用CPU运行可执行程序文件来确定所需执行的数字签名处理所属的数字签名类型。
每一数字签名类型可对应唯一标识，可通过类型标识来确定数字签名类型。类型标识可在应用请求中携带。
需要说明的是，应用请求是触发区块链应用主程序进行数字签名处理的请求。
为后续称呼方便，可将确定出的数字签名类型称为目标数字签名类型，而将目标数字签名类型对应的数字签名子程序称为数字签名子程序。
S6：区块链应用主程序调用协处理器运行目标数字签名子程序，以进行并行和流水化的数字签名处理。
当然，FPGA底层真正执行的是AOCX文件。
可见，在本发明实施例中，主处理器与协作处理器合作提供区块链应用服务，其中主处理器负责在需要进行数字签名处理时，从多种数字签名类型中确定出所需的目标数字签名类型，并调用协作处理器执行运行目标数字签名类型所对应的目标数字签名子程序，协作处理器的并行流水化方式可提高数字签名算法的并行度和数据处理速度，进而改善数字签名算法执行时的数据处理速度，提高区块链应用的响应时间、吞吐量和可扩展性。
使用FPGA作为协处理器，能够有效的提升数字签名核心算法的执行性能，上述自动化映射方式能够有效缩短将数字签名算法部署到基于FPGA的异构加速平台时的时间，提高产品研发周期。
下面介绍通用CPU运行可执行程序文件所执行的具体操作，以及FPGA运行AOCX文件所执行的具体操作。
请参见图6，通用CPU运行可执行程序文件所执行的具体操作可包括：
S601：准备待处理数据集。
前述提及了，数字签名处理包括签名和验证，对于签名过程，待处理数据集可包括待签名数据；而对于验证过程，待处理数据集可包括待验证数据(已签名数据)。
S602：创建主机端与FPGA端进行数据通信的缓存。
该缓存位于在FPGA开发板的DDR内存上。
S603：将辅助数据集传输到上述缓存。
辅助数据集参与数字签名处理的运算。以签名过程为例，辅助数据集可包括：将待签名数据的分块信息(指示将待签名数据以多大分块)、用户私钥以及签名过程中所使用的函数(例如哈希函数)何时调用等信息。
在验证时，辅助数据集包括签名系统参数(模数、数域等)和公钥。
S604：将准备好的待处理数据集传输到上述缓存。
需要说明的是，辅助数据集要先于待处理数据集传输。
S605：设置FPGA端运行所需的参数信息。
其中，参数信息可包括：缓存大小、数据的写入和读出配置信息(例如何时写入，何时读出、一次写入的数据量、一次读取的数据量等)、kernel文件的执行配置信息(例如，何时调用)以及FPGA平台信息(例如FPGA板卡型号)。
S606：确定所需执行的数字签名处理所属的数字签名类型，调用FPGA端运行目标数字签名子程序。
具体的，可先向FPGA发送启动信号，再调用FPGA端运行目标数字签名子程序。
FPGA运行AOCX文件所执行的具体操作则可包括：
S607：读取上述辅助数据集和待处理数据集。
前述提及，可使用FPGA的DDR作为缓存，则在本步骤中，可从FPGA的DDR批量读取辅助数据集和待处理数据集至FPGA的片上缓存。
S608：依据辅助数据集，对待处理数据集中的数据进行并行和流水化的计算操作。
S609：将计算操作所得数据写入上述缓存；
S610：对待处理数据集中的数据的计算结束后，向主机端返回完成信号。
在签名或验证步骤执行完毕后，可向主机端返回完成信号。由主机端读取缓存中的数据。
则通用CPU运行可执行程序文件所执行的具体操作还包括：
S611：在接收到FPGA端返回完成信号后，从缓存中读取数字签名处理得到的数据；
S612：完成数字签名过程并输出相应的签名信息或者验证结果。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及模型步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
结合本文中所公开的实施例描述的方法或模型的步骤可以直接用硬件、处理器执行的软件模块，或者二者的结合来实施。软件模块可以置于随机存储器(RAM)、内存、只读存储器(ROM)、电可编程ROM、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、WD-ROM、或技术领域内所公知的任意其它形式的存储介质中。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (9)

  1. 一种区块链数字签名方法，其特征在于，基于区块链数字签名系统，所述区块链数字签名系统包括主处理器和协处理器；所述主处理器至少用于运行区块链应用主程序；所述协处理器作为硬件加速单元，用于运行多个数字签名子程序；所述多个数字签名子程序对应不同的数字签名类型；
    所述方法包括：
    所述主处理器运行所述区块链应用主程序；
    在需要进行数字签名处理时，所述区块链应用主程序确定所需执行的数字签名处理所属的数字签名类型；确定出的数字签名类型为目标数字签名类型；所述目标数字签名类型对应的数字签名子程序为数字签名子程序；
    所述区块链应用主程序调用所述协处理器运行所述目标数字签名子程序，以进行并行和流水化的数字签名处理。
  2. 如权利要求1所述的方法，其特征在于，所述主处理器为通用CPU；所述协处理器为现场可编程门阵列FPGA。
  3. 如权利要求2所述的方法，其特征在于，在所述调用协处理器运行所述目标数字签名子程序之前，所述区块链应用主程序还用于执行如下操作：
    准备待处理数据集；
    创建主机端与FPGA端进行数据通信的缓存；
    将辅助数据集传输到所述缓存；
    将准备好的待处理数据集传输到所述缓存；
    设置FPGA端运行所需的参数信息；
    在所述调用协处理器运行所述目标数字签名子程序之后，所述区块链应用主程序还用于执行如下操作：
    在所述FPGA端返回完成信号之后，读取FPGA端的执行结果。
  4. 如权利要求3所述的方法，其特征在于，所述协处理器运行所述目标数字签名子程序，以进行并行和流水化的数字签名处理包括：
    从所述缓存处读取所述辅助数据集和所述待处理数据集；
    依据所述辅助数据集，对所述待处理数据集中的数据进行并行和流水化的计算操作；
    将计算操作所得数据写入所述缓存；
    在对所述待处理数据集中的数据的计算结束后，向主机端返回完成信号。
  5. 如权利要求3所述的方法，其特征在于，所述参数信息包括：
    缓存大小、数据的写入和读出配置信息、所述目标数字签名子程序的执行配置信息以及FPGA平台信息。
  6. 如权利要求2-5任一项所述的方法，其特征在于，
    在所述主处理器运行所述区块链应用主程序之前，所述方法还包括：
    采用高级语言完成多种类型的数字签名算法的描述，得到所述多个数字签名子程序；
    通过映射工具完成所述多种类型的数字签名算法的描述到FPGA所执行比特流的自动化映射，生成相应的AOCX文件；
    对所述主程序进行编译，生成可在所述通用CPU上执行的可执行程序文件。
  7. 如权利要求6所述的方法，其特征在于，
    所述主处理器运行所述区块链应用主程序包括：所述通用CPU运行所述可执行程序文件；
    所述协处理器运行所述目标数字签名子程序包括：所述FPGA运行所述目标数字签名子程序对应的AOCX文件。
  8. 一种区块链数字签名系统，其特征在于，包括主处理器和作为硬件加速单元的协处理器；其中，所述协处理器用于运行多个数字签名子程序；所述多个数字签名子程序对应不同的数字签名类型；
    所述主处理器用于：
    运行区块链应用主程序；
    在需要进行数字签名处理时，确定所需执行的数字签名处理所属的数字签名类型；确定出的数字签名类型为目标数字签名类型；所述目标数字签名类型对应的数字签名子程序为数字签名子程序；
    调用所述协处理器运行所述目标数字签名子程序，以进行并行和流水化的数字签名处理。
  9. 如权利要求8所述的系统，其特征在于，所述主处理器为CPU；所述协处理器为现场可编程门阵列FPGA。
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