WO2020258033A1 - 发光二极管及其制作方法、显示装置 - Google Patents

发光二极管及其制作方法、显示装置 Download PDF

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WO2020258033A1
WO2020258033A1 PCT/CN2019/092803 CN2019092803W WO2020258033A1 WO 2020258033 A1 WO2020258033 A1 WO 2020258033A1 CN 2019092803 W CN2019092803 W CN 2019092803W WO 2020258033 A1 WO2020258033 A1 WO 2020258033A1
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semiconductor layer
layer
light emitting
barrier
light
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PCT/CN2019/092803
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English (en)
French (fr)
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孟虎
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to PCT/CN2019/092803 priority Critical patent/WO2020258033A1/zh
Priority to CN201980000904.5A priority patent/CN110521010B/zh
Priority to US16/957,058 priority patent/US11870011B2/en
Publication of WO2020258033A1 publication Critical patent/WO2020258033A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a light emitting diode, a manufacturing method of the light emitting diode, and a display device with the light emitting diode.
  • micro LEDs have received widespread attention.
  • the size of the light emitting diode is small (for example, less than 10 ⁇ m)
  • the external quantum efficiency of the light emitting diode will be significantly attenuated, and the smaller the size, the lower the external quantum efficiency.
  • a light emitting diode which includes: a first semiconductor layer; a second semiconductor layer; a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and a barrier layer disposed between the first semiconductor layer and the second semiconductor layer.
  • the blocking layer is configured to form a charge depletion region between the blocking layer and at least a part of the side surface.
  • the first semiconductor layer is a P-type semiconductor layer
  • the second semiconductor layer is an N-type semiconductor layer
  • the barrier layer includes a first barrier layer covering at least a portion of the side surface of the P-type semiconductor layer, and The work function of the barrier layer is smaller than the work function of the P-type semiconductor layer.
  • the first barrier layer includes: a first body portion covering a side surface of the P-type semiconductor layer; a first extension portion connected to a side of the first body portion close to the light-emitting layer, the first extension portion covering On a partial area close to the P-type semiconductor layer in the side surface of the light-emitting layer; in a direction perpendicular to one main surface of the light-emitting layer, there is a gap between the first extension and the N-type semiconductor layer.
  • the first barrier layer further includes: a second extension portion connected to the side of the first body portion away from the light emitting layer, the second extension portion covering the edge area of the main surface of the P-type semiconductor layer away from the light emitting layer on.
  • the orthographic projection of the first barrier layer on one main surface of the light-emitting layer is in the shape of a closed frame.
  • the work function of the first barrier layer ranges from 4.0 eV to 5.5 eV.
  • the absolute value of the difference between the work function of the first barrier layer and the work function of the P-type semiconductor layer is greater than or equal to 0.3 eV.
  • the material of the first barrier layer includes at least one of metal, conductive metal oxide, graphene, and metallic carbon nanotubes.
  • the first semiconductor layer is a P-type semiconductor layer
  • the second semiconductor layer is an N-type semiconductor layer
  • the barrier layer includes a second barrier layer covering at least a portion of the side surface of the N-type semiconductor layer, and The work function of the barrier layer is greater than the work function of the N-type semiconductor layer.
  • the orthographic projection of the second barrier layer on the plane defined by the light-emitting layer is in the shape of a closed frame.
  • the work function of the second barrier layer ranges from 4.5 eV to 5.1 eV.
  • the absolute value of the difference between the work function of the second barrier layer and the work function of the N-type semiconductor layer is greater than or equal to 0.3 eV.
  • the material of the second barrier layer includes at least one of metal, conductive metal oxide, graphene, and metallic carbon nanotubes.
  • the first semiconductor layer is a P-type semiconductor layer
  • the second semiconductor layer is an N-type semiconductor layer
  • the barrier layer includes a first barrier layer covering at least a part of the side surface of the P-type semiconductor layer, and, A second barrier layer covering at least a part of the side surface of the N-type semiconductor layer; in a direction perpendicular to one main surface of the light emitting layer, there is a gap between the first barrier layer and the second barrier layer.
  • the second semiconductor layer has a body region and a second electrode arrangement region, the part of the second semiconductor layer in the body region overlaps the light emitting layer and the first semiconductor layer, and the second semiconductor layer is in the second electrode arrangement region.
  • the part of the region does not overlap the light-emitting layer and the first semiconductor layer.
  • the light emitting diode further includes: a substrate arranged on the side of the second semiconductor layer away from the light emitting layer; a first electrode arranged on the main surface of the first semiconductor layer away from the light emitting layer; and a second electrode arranged on the side of the second semiconductor layer In the second electrode setting area.
  • a method for manufacturing a light emitting diode includes: providing a substrate; sequentially forming a second semiconductor layer, a light emitting layer, and a first semiconductor layer on the substrate; patterning the first semiconductor layer, and removing the first semiconductor layer.
  • the part of the layer at the edge of the light-emitting area of the light-emitting diode; the first barrier film is formed on the side of the substrate where the patterned first semiconductor layer is formed; the first barrier film is patterned so that the first barrier film covers the The part of the side surface of the patterned first semiconductor layer is retained to form a first barrier layer; wherein the first barrier layer is configured to form a charge depletion region between the first barrier layer and the first semiconductor layer.
  • the method further includes: using a mask used for patterning the first semiconductor layer to etch a portion of the light-emitting layer at the edge of the light-emitting region, The etching depth is smaller than the thickness of the light-emitting layer.
  • the portion of the first barrier film covering the edge region of the main surface of the patterned first semiconductor layer in the light-emitting region is retained.
  • the method before forming the light-emitting layer, further includes: patterning the second semiconductor layer, removing a portion of the second semiconductor layer at the edge of the light-emitting region; and forming a patterned second semiconductor layer on the substrate A second barrier film is formed on one side; the second barrier film is patterned so that the part of the first barrier film covering the side surface of the patterned second semiconductor layer is retained to form a second barrier layer; wherein the second barrier layer is It is configured to form a charge depletion region between the second barrier layer and the second semiconductor layer.
  • a display device including: a driving substrate; a plurality of light-emitting diodes mounted on one side of the driving substrate, each light-emitting diode is a light-emitting diode as in any of the above-mentioned embodiments, and each light-emitting diode is connected to the driving The substrate is electrically connected.
  • FIG. 1 is a top view of a light emitting diode according to some embodiments of the present disclosure
  • Fig. 2 is a cross-sectional view taken along the line A-A of the light emitting diode in Fig. 1;
  • FIG. 3 is a schematic cross-sectional structure diagram of another light emitting diode according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of yet another light emitting diode according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic flowchart of a method for manufacturing a light emitting diode according to some embodiments of the present disclosure
  • 6 to 14 are schematic diagrams of various steps of a method for manufacturing a light emitting diode according to some embodiments of the present disclosure
  • 15 to 18 are schematic diagrams of various steps of making a second barrier layer according to some embodiments of the present disclosure.
  • FIG. 19 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 20 is a schematic structural diagram of another display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • connection should be construed broadly, for example, they may be fixed connections or Removable connection, or integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • installation should be construed broadly, for example, they may be fixed connections or Removable connection, or integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • connection should be construed broadly, for example, they may be fixed connections or Removable connection, or integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • the leakage current of the sidewall of the light-emitting diode rises in proportion to the total current, and most of the carriers undergo transition through the non-radiative recombination mechanism on the sidewall surface. Therefore, when the size of the light-emitting diode is small For example, when it is less than 10 ⁇ m, the external quantum efficiency of the light-emitting diode will be significantly attenuated, and the smaller the size, the lower the external quantum efficiency.
  • a mild dry etching process is used to prepare micro light emitting diodes, or a passivation film is prepared on the sidewalls of the micro light emitting diodes, in order to reduce the side defects of the micro light emitting diodes and the density of recombination centers.
  • the mild dry etching process will cause the process uniformity and line width of the film layer of the micro-light-emitting diode to be deteriorated.
  • the preparation of the passivation film usually requires a high-temperature annealing process. The reduction effect of the defects and the density of the recombination center is poor, resulting in a large leakage current on the sidewall surface, and the external quantum efficiency of the miniature light-emitting diode cannot be significantly improved.
  • some embodiments of the present disclosure provide a light emitting diode 100 including a first semiconductor layer 10, a light emitting layer 20, a second semiconductor layer 30 and a barrier layer 40.
  • the light-emitting layer 20 is disposed between the first semiconductor layer 10 and the second semiconductor layer 30.
  • one of the first semiconductor layer 10 and the second semiconductor layer 30 is a P-type semiconductor layer, and the other is an N-type semiconductor layer.
  • the electrons in the N-type semiconductor layer will migrate to the light-emitting layer 20 and enter the light-emitting layer 20; the holes in the P-type semiconductor layer will also migrate to the light-emitting layer 20 and enter the light-emitting layer 20.
  • the electrons and holes entering the light-emitting layer 20 recombine, thereby generating spontaneous emission light.
  • the light emitting layer 20 is a multiple quantum well layer (MQW, Multiple Quantum Well).
  • the barrier layer 40 is provided on at least a partial area of the side surface of at least one of the first semiconductor layer 10 and the second semiconductor layer 30 (for example, the side surface 10A of the first semiconductor layer shown in FIG. 2), and the barrier layer 40 is It is configured to form a charge depletion region 70 between the barrier layer 40 and at least a portion of the side surface. In this way, due to the presence of the charge depletion region 70, the carriers (holes and/or electrons) moving in the first semiconductor layer 10 and/or the second semiconductor layer 30 will be far away from at least part of the side area, thereby achieving light emission
  • the lateral current limitation of the diode makes at least part of the side surface less prone to leakage current and improves the external quantum efficiency of the light emitting diode.
  • the charge depletion region 70 is a high resistance region. Due to the existence of the charge depletion region 70, when the carriers (holes and/or electrons) in the first semiconductor layer 10 and/or the second semiconductor layer 30 move to at least a part of the side surface, it is necessary to overcome the Schottky Barrier. As a result, these moving carriers are mainly concentrated in at least part of the area away from the side surface, so that the lateral suppression of the injected current can be realized, and the formation of defects and recombination centers on at least part of the side area of the carriers can be reduced. Non-radiative recombination helps to improve the luminous efficiency of the light-emitting diode 100.
  • barrier layer 40 there are many structures and arrangements of the barrier layer 40, including but not limited to the structures and arrangements of the barrier layer 40 shown in the following embodiments.
  • the first semiconductor layer 10 is a P-type semiconductor layer 101 and the second semiconductor layer 30 is an N-type semiconductor layer 301.
  • the barrier layer 40 includes a first barrier layer 40A covering at least a portion of the side surface 10A of the P-type semiconductor layer 101, and the work function of the first barrier layer 40A is smaller than that of the P-type semiconductor layer 101.
  • the electrons in the first barrier layer 40A will move into the P-type semiconductor layer 101, thereby forming a built-in electric field and semiconductor energy band bending. And when the first barrier layer 40A and the P-type semiconductor layer 101 reach thermal equilibrium, the Fermi levels of the two remain the same. Between the first barrier layer 40A and the P-type semiconductor layer 101, the electrons in the first barrier layer 40A and Holes in the P-type semiconductor layer 101 combine to form a charge depletion region 70, that is, a high resistance region.
  • the hole current distribution in the P-type semiconductor layer 101 will change, that is, the hole current is mainly concentrated in the body area of the P-type semiconductor layer 101, so the lateral suppression of the injected hole current can be achieved.
  • the first barrier layer 40A includes a first body portion 401 and a first extension portion 402.
  • the first body portion 401 covers the side surface 10A of the P-type semiconductor layer 101.
  • a charge depletion region 70 can be formed between the first body portion 401 and the entire side surface 10A of the P-type semiconductor layer 101, so that the lateral suppression of injection current can be better achieved, and the leakage of the side surface 10A of the P-type semiconductor layer 101 can be improved.
  • the phenomenon of electric current is not limited to
  • the first extension portion 402 is connected to a side of the first body portion 401 close to the light emitting layer 20, and the first extension portion 402 covers a part of the side surface of the light emitting layer 20 close to the P-type semiconductor layer 101.
  • Such a design makes the end of the side surface 10A close to the light-emitting layer 20 less prone to leakage current phenomenon, and helps reduce the difficulty of processing the first barrier layer 40A.
  • the first barrier layer 40A further includes a second extension portion 403 connected to the side of the first main body portion 401 away from the light emitting layer 20, and the second extension portion 403 covers
  • the P-type semiconductor layer 101 is on the edge region of the main surface 10B away from the light emitting layer 20. This design makes the end of the side surface 10A close to the main surface 10B less likely to have leakage current, and is beneficial to reduce the difficulty of processing the first barrier layer 40A.
  • the orthographic projection of the first barrier layer 40A on one main surface 20A of the light-emitting layer 20 is in a closed frame shape.
  • the charge depletion region 70 can be formed between the first barrier layer 40A and the entire side surface 10A of the P-type semiconductor layer 101, so that the lateral suppression of the injected current can be better realized, and the leakage of the side surface 10A of the P-type semiconductor layer 101 can be improved.
  • the phenomenon of current increases the luminous efficiency of the light-emitting diode 100.
  • the orthographic projection of the first barrier layer 40A on one main surface 20A of the light-emitting layer 20 is not limited to a closed frame shape.
  • the first barrier layer 40A includes at least two parts, and the at least two parts are sequentially spaced and arranged one week around the side surface of the P-type semiconductor layer 101.
  • the material of the first barrier layer 40A includes at least one of metal, conductive metal oxide, graphene, metallic carbon nanotube, and the like.
  • the first barrier layer 40A is a 200-300 nm thick metal layer or a conductive metal oxide layer; for another example, the first barrier layer 40A is one or two layers of graphene.
  • the work function of the first barrier layer 40A ranges from 4.0 eV to 5.5 eV.
  • Materials in this range include, but are not limited to, titanium, aluminum, silver, indium, molybdenum, copper, chromium, gold, and the like.
  • the work function range of the first barrier layer 40A is 4.0eV ⁇ 5.5eV, so that the work function of the first barrier layer 40A can be smaller than the work function of the P-type semiconductor layer 101 (the work function range of the P-type semiconductor layer 101 is usually 6eV ⁇ 7eV), therefore, a charge depletion region 70 can be formed between the first barrier layer 40A and the side surface 10A of the P-type semiconductor layer 101, so as to improve the leakage current phenomenon of the side surface 10A of the P-type semiconductor layer 101.
  • the absolute value of the difference between the work function of the first barrier layer 40A and the work function of the P-type semiconductor layer 101 is greater than or equal to 0.3 eV.
  • the charge depletion region 70 formed between the first barrier layer 40A and the P-type semiconductor layer 101 has a higher Schottky barrier, which can effectively prevent the hole current in the P-type semiconductor layer 101 from flowing therefrom.
  • the side 10A leaks out, which has high stability and reliability.
  • the barrier layer 40 includes a second barrier layer 40B covering at least a part of the side surface 30A of the N-type semiconductor layer 301, and the work function of the second barrier layer 40B is greater than that of the N-type semiconductor layer. Work function of the semiconductor layer 301.
  • the electrons in the N-type semiconductor layer 301 will move into the second barrier layer 40B, thereby forming a built-in electric field and semiconductor band bending. And when the second barrier layer 40B and the N-type semiconductor layer 301 reach thermal equilibrium, the Fermi levels of the two remain the same. Between the second barrier layer 40B and the N-type semiconductor layer 301, the electrons in the N-type semiconductor layer 301 and The holes in the second barrier layer 40B combine to form a charge depletion region 70, that is, a high resistance region.
  • the electron current distribution in the N-type semiconductor layer 301 will change, that is, the electron current is mainly concentrated in the body area of the N-type semiconductor layer 301, so that the lateral suppression of the injected electron current can be achieved and the electron current can be prevented.
  • Non-radiative recombination is formed on the side surface 30A of the N-type semiconductor layer 301 due to defects and recombination centers, which reduces leakage current in at least part of the side surface 30A, thereby improving the external quantum efficiency of the light emitting diode, that is, improving the light emitting diode The luminous efficiency.
  • the second barrier layer 40B covers the entire side surface 30A of the N-type semiconductor layer 301.
  • a charge depletion region 70 can be formed between the second barrier layer 40B and the entire side surface 30A of the N-type semiconductor layer 301, which can better realize the lateral suppression of injection current and improve the leakage current of the side 30A of the N-type semiconductor layer 301 The phenomenon.
  • the second barrier layer 40B covers a part of the side surface of the light emitting layer 20 close to the N-type semiconductor layer 301.
  • Such a design makes the end of the side surface 30A close to the light-emitting layer 20 less prone to leakage current phenomenon, and helps reduce the difficulty of processing the second barrier layer 40B.
  • the orthographic projection of the second barrier layer 40B on one main surface 20A of the light emitting layer 20 is in a closed frame shape.
  • a charge depletion region 70 can be formed between the second barrier layer 40B and the entire side surface 30A of the N-type semiconductor layer 301, so that the lateral suppression of the injected current can be better realized, and the leakage of the side surface 30A of the N-type semiconductor layer 301 can be improved.
  • the phenomenon of current increases the luminous efficiency of the light-emitting diode 100.
  • the orthographic projection of the second barrier layer 40B on the one main surface 20A of the light-emitting layer 20 is not limited to being a closed frame shape.
  • the first barrier layer 40A includes at least two parts, and the at least two parts are sequentially spaced and arranged one week around the side surface 30A of the N-type semiconductor layer 301.
  • the material of the second barrier layer 40B includes at least one of metal, conductive metal oxide, graphene, and metallic carbon nanotubes.
  • the second barrier layer 40B is a 200-300 nm thick metal layer or a conductive metal oxide layer; for another example, the second barrier layer 40B is one or two layers of graphene.
  • the work function of the second barrier layer 40B ranges from 4.5 eV to 5.1 eV.
  • Materials in this range include, but are not limited to, molybdenum, copper, chromium, gold, nickel, etc.
  • the work function of the second barrier layer 40B ranges from 4.5 eV to 5.1 eV, so that the work function of the second barrier layer 40B can be greater than the work function of the N-type semiconductor layer 301 (the work function range of the N-type semiconductor layer 301 is usually 4.0 eV ⁇ 4.2 eV), therefore, a charge depletion region 70 can be formed between the second barrier layer 40B and the side surface 30A of the N-type semiconductor layer 301, so as to improve the leakage current phenomenon of the side surface 30A of the N-type semiconductor layer 301.
  • the absolute value of the difference between the work function of the second barrier layer 40B and the work function of the N-type semiconductor layer 301 is greater than or equal to 0.3 eV.
  • the charge depletion region 70 formed between the second barrier layer 40B and the N-type semiconductor layer 301 has a higher Schottky barrier, which can effectively prevent the electron current in the N-type semiconductor layer 301 from flowing from its side. 30A leaks out, with high stability and reliability.
  • the barrier layer 40 includes a first barrier layer 40A covering at least a portion of the side surface 10A of the P-type semiconductor layer 101, and covering the side surface of the N-type semiconductor layer 301 The second barrier layer 40B on at least a partial area of 30A. In this way, it is possible to reduce leakage currents in at least part of the side surface 10A and at least part of the side surface 30A at the same time, thereby improving the external quantum efficiency of the light emitting diode and improving the luminous efficiency of the light emitting diode.
  • the first barrier layer 40A and the second barrier layer 40B may be separated by the light emitting layer 20.
  • the second barrier layer 40B does not cover a part of the side surface of the light emitting layer 20 close to the N-type semiconductor layer 301.
  • This design can prevent the first barrier layer 40A and the second barrier layer 40B from affecting each other, so that the first barrier layer 40A and the P-type semiconductor layer 101, and the second barrier layer 40B and the N-type semiconductor layer 301 are equal A stable and reliable charge depletion region can be generated.
  • the second semiconductor layer 30 has a body region M 1 and a second electrode arrangement region M 2 , the part of the second semiconductor layer 30 in the body region M 1 and the light emitting layer 20 and The first semiconductor layer 10 overlaps, and the portion of the second semiconductor layer 30 in the second electrode arrangement region M 2 does not overlap the light emitting layer 20 and the first semiconductor layer 10.
  • the light emitting diode 100 further includes a substrate 80, a first electrode 50 and a second electrode 60.
  • the substrate 80 is disposed on the side of the second semiconductor layer 30 away from the light-emitting layer 20.
  • the substrate 80 it is convenient to form the second semiconductor layer 30, the light emitting layer 20, and the first semiconductor layer 10 that are sequentially stacked.
  • the substrate includes a sapphire substrate 801 and a buffer layer 802 located between the sapphire substrate 801 and the second semiconductor layer 30.
  • the first electrode 50 is arranged on the main surface 10B of the first semiconductor layer 10 away from the light-emitting layer 20, and the second electrode 60 is arranged in the second electrode arrangement area M 2 of the second semiconductor layer 30. In this way, carriers (one of holes and electrons) can be injected into the first semiconductor layer 10 through the first electrode 50, and carriers (holes) can be injected into the second semiconductor layer 30 through the second electrode 60. And the other in electronics).
  • the first semiconductor layer 10 is a P-type semiconductor layer 101 and the second semiconductor layer 30 is an N-type semiconductor layer 301
  • the first electrode 50 is an anode and the second semiconductor layer
  • the electrode 60 is a cathode.
  • the first semiconductor layer 10 is one of the P-type semiconductor layer 101 and the N-type semiconductor layer 301
  • the second semiconductor layer 30 is the other of the P-type semiconductor layer 101 and the N-type semiconductor layer 301.
  • the first semiconductor layer 10 is an N-type semiconductor layer 301
  • the second semiconductor layer 30 is a P-type semiconductor layer 101
  • the second barrier layer 40B covering the side surface 30A of the N-type semiconductor layer 301, It includes a structure similar to that of the second extension 403 of the first barrier layer 40A.
  • some embodiments of the present disclosure provide a method for manufacturing a light emitting diode.
  • the manufacturing method includes steps 901 to 905.
  • Step 901 as shown in FIG. 6, a substrate 80 is provided.
  • the substrate 80 plays a supporting role, enabling the subsequent formation of various layers (for example, the first semiconductor layer, the second semiconductor layer, and the light-emitting layer) to have higher stability and reliability.
  • the substrate 80 includes a sapphire substrate 801 and a buffer layer 802 located on one side of the sapphire substrate 801.
  • step 902 as shown in FIG. 7, the second semiconductor layer 30, the light emitting layer 20, and the first semiconductor layer 10 are sequentially formed on the substrate 80.
  • the first semiconductor layer 10 is one of the P-type semiconductor layer 101 and the N-type semiconductor layer 301
  • the second semiconductor layer 30 is the other of the P-type semiconductor layer 101 and the N-type semiconductor layer 301.
  • FIG. 7 shows that the first semiconductor layer 10 is a P-type semiconductor layer 101 and the second semiconductor layer 30 is an N-type semiconductor layer 301.
  • step 902 includes, but is not limited to, using an epitaxial growth process to sequentially grow an N-type semiconductor layer 301, a light-emitting layer 20, and a P-type semiconductor layer 101 on one side of the substrate 80.
  • first semiconductor layer 10 is patterned, removing portions of the first semiconductor layer 100 in the light emitting region P of the light emitting diode 10 of the edge 1.
  • the first semiconductor layer 10 is patterned by a patterning process. For example, first a photoresist layer is formed on the side of the first semiconductor layer 10 away from the light-emitting layer 20; then the photoresist layer is exposed and developed to obtain a patterned photoresist layer. the exposed surface layer portion of the light emitting region P 1 at the edge of the first semiconductor layer 10; and finally, using the patterned photoresist layer on the first semiconductor layer 10 is etched, removing the first semiconductor layer in the light emitting diode 10 an edge portion P of the light emitting area 100 1.
  • the patterned first semiconductor layer 10 may be removed only the portion of the first semiconductor layer 100 in the light emitting region of the light emitting diode 1 P edge 10 (FIG. 8); may be removed in the first semiconductor layer while the edge portion of the light emitting region in the P light emitting diode 100 1 10, the first semiconductor layer 10 in the non-emission area portion P 2 of the light emitting diode 100 is removed together (Fig. 9).
  • the non-light emitting area P 2 here refers to the area on the light emitting diode 100 excluding the light emitting area P 1 .
  • the light emitting region is partially removed only in the light emitting diode of the first semiconductor layer 10 edge P 1, a first semiconductor layer 10 is formed on the groove 10C 8.
  • the orthographic projection of the groove 10C on one main surface 20A of the light-emitting layer 20 is in a closed frame shape; or, the number of grooves 10C is multiple, and the plurality of grooves 10C are sequentially spaced around the first semiconductor layer 10 Arrange for a week.
  • Step 904 as shown in FIG. 10, a first barrier film 404 is formed on the side of the substrate 80 where the patterned first semiconductor layer 10 is formed.
  • any one of a physical vapor deposition process, a sputtering process, an evaporation process, and a transfer process can be used.
  • the material of the first barrier film 404 is a conductive metal oxide or metal (such as molybdenum, aluminum, copper, etc.)
  • a physical vapor deposition process, a sputtering process, or an evaporation process may be used to prepare the first barrier film 404 .
  • a transfer process can be used to transfer the single-layer or few-layer graphene (for example, 1 to 2 layers) grown by chemical vapor deposition on copper to the patterned substrate 80.
  • Step 905 referring to FIG. 11, pattern the first barrier film 404 so that the portion of the first barrier film 404 covering the side surface 10A of the patterned first semiconductor layer 10 is retained to form the first barrier layer 40A.
  • the first barrier film 404 is patterned by a patterning process, and the parts of the first barrier film 404 that do not need to be retained can be removed, for example, the part of the first barrier film 404 that is in the non-light emitting region P 2 and the part in the first semiconductor layer is located on the main surface portion 10B 1 of the light emitting region P, in order to achieve the first barrier film 404 covering portion 10A is retained in the side surface of the first semiconductor layer 10 is patterned, forming the first barrier layer 40A.
  • the first barrier layer 40A is configured to form a charge depletion region 70 between the first barrier layer 40A and the first semiconductor layer 10. In this way, due to the existence of the charge depletion region 70, the moving carriers (holes or electrons) in the first semiconductor layer 10 will be far away from the side surface 10A, thereby realizing the lateral current limitation of the light emitting diode, making the side surface 10A less prone to leakage current. , The external quantum efficiency of the light emitting diode 100 is improved, and the luminous efficiency of the light emitting diode 100 is further improved.
  • the manufacturing method further includes:
  • the etching depth is less than the thickness of the light emitting layer.
  • the first barrier film 404 when the first barrier film 404 is subsequently fabricated, the first barrier film can cover a part of the side surface of the light-emitting layer 20 close to the first semiconductor layer 101. This is beneficial to reduce the processing difficulty of the first barrier layer 40A; and, as shown in FIG. 13, the first barrier layer 40A effectively covers the entire side surface 10A of the first semiconductor layer 101, and the side surface 10A of the first semiconductor layer 101 is close to the light emitting One end of the layer 20 is not prone to leakage current.
  • the step of patterning the first barrier film 404 the first major surface of the barrier is in the region of the first semiconductor layer of the light emitting film 404 covering the patterned 10 P 1 is Part of the 10B edge area is reserved. In this way, with this design, the end of the side surface 10A close to the main surface 10B is not prone to leakage current, and it is beneficial to reduce the processing difficulty of the formed first barrier layer 40A.
  • the manufacturing method further includes the following steps:
  • the light-emitting layer 20 is patterned, and the portion of the light-emitting layer 20 in the non-emitting region P 2 is removed, so that the surface of the portion of the second semiconductor layer 30 in the non-emitting region P 2 is exposed. Then, a second electrode 60 is formed on the exposed surface of the first semiconductor layer 30, and a first electrode 50 is formed on the surface of the patterned first semiconductor layer 10 away from the light-emitting layer 20.
  • the manufacturing method before forming the light-emitting layer, the manufacturing method further includes step one to step three.
  • the second semiconductor layer 30 is patterned, removing portions of the edge P in the light emitting region 1 of the second semiconductor layer 30.
  • step of patterning the second semiconductor layer 30 is the same as the step of patterning the first semiconductor layer 10 described above, and will not be repeated here.
  • the patterned first semiconductor layer 30, may be removed only the portion of the second semiconductor layer 100 in the light emitting region of the light emitting diode 1 P edge 30 (FIG. 15); or in the second semiconductor layer is removed while the edge portion of the light emitting region in the P light emitting diode 100 1 30, the second semiconductor layer 30 in the non-emission area portion P 2 of the light emitting diode 100 is removed together (as shown in Figure 16).
  • the non-light emitting area P 2 here refers to the area on the light emitting diode 100 excluding the light emitting area P 1 .
  • the groove 30B on the second semiconductor layer 30 is formed.
  • the orthographic projection of the groove 30B on the substrate 80 is in a closed frame shape; or, the number of grooves 30B is multiple, and the plurality of grooves 30B are arranged one week in sequence around the second semiconductor layer 30.
  • Step 2 As shown in FIG. 17, a second barrier film 405 is formed on the side of the substrate where the patterned second semiconductor layer 30 is formed.
  • any one of a physical vapor deposition process, a sputtering process, an evaporation process, and a transfer process can be used.
  • the material of the second barrier film 405 is a conductive metal oxide or metal (such as molybdenum, aluminum, copper, etc.)
  • a physical vapor deposition process, a sputtering process, or an evaporation process may be used to prepare the second barrier film 405 .
  • a transfer process can be used to transfer the single-layer or few-layer graphene (for example, 1 to 2 layers) grown by chemical vapor deposition on copper to the patterned substrate 80.
  • Step 3 the second barrier film 405 is patterned so that the part of the first barrier film covering the side surface of the patterned second semiconductor layer is retained to form a second barrier layer; wherein the second barrier film The layer is configured to form a charge depletion region between the second barrier layer and the second semiconductor layer.
  • the second barrier film 405 is patterned by a patterning process, and the parts of the second barrier film 405 that do not need to be retained can be removed, for example, the part of the second barrier film 405 in the non-light emitting region P 2 and the second semiconductor film can be removed.
  • layer is located on the main surface portions 30C 1 P of the light emitting region, in order to achieve the second barrier film 405 covering portion 30A is retained in the side surface of the second semiconductor layer 30 is patterned, a second barrier layer 40B is formed.
  • the second barrier layer 40B is configured to form a charge depletion region 70 between the second barrier layer 40B and the second semiconductor layer 30.
  • the moving carriers (holes or electrons) in the second semiconductor layer 30 will be far away from the side 30A, thereby realizing the lateral current limitation of the light-emitting diode, making the side 30A less prone to leakage current.
  • the external quantum efficiency of the light emitting diode 100 is improved, and the luminous efficiency of the light emitting diode 100 is further improved.
  • the second barrier layer 40B After the second barrier layer 40B is formed, one or more of the above steps can be used to form the light-emitting layer 20 and the first semiconductor layer 10, and then the first barrier layer, the first electrode and the second electrode are formed to produce the figure 4 The light emitting diode 100 is shown.
  • the display device 200 includes a driving substrate 300 and a plurality of light emitting diodes 100 mounted on one side of the driving substrate 300, and each light emitting diode 100 is any one of the above In the embodiment of the light emitting diode 200, each light emitting diode 100 is electrically connected to the driving substrate 300.
  • the driving substrate 300 is an active driving substrate or a passive driving substrate.
  • the light emitting diode 100 mounted on the driving substrate 300 does not include a substrate. That is, the light emitting diode 100 manufactured by the above-mentioned manufacturing method needs to remove the substrate before being mounted on the driving substrate 300.
  • the driving substrate 300 is disposed on the side of the second semiconductor layer 30 away from the light emitting layer 20. At this time, the first electrode 50 and the second electrode 60 of each light-emitting diode 100 can be connected to the driving substrate 300 by making the connecting wire 400.
  • the driving substrate 300 is disposed on the side of the first semiconductor layer 10 away from the light emitting layer 20. At this time, the first electrode 50 and the second electrode 60 of each light emitting diode 100 can be connected to the driving substrate 300 through the solder joint 500.
  • one of the first semiconductor layer 10 and the second semiconductor layer 30 is the P-type semiconductor layer 101 and the other is the N-type semiconductor layer 301.
  • FIG. 19 shows an example in which the first semiconductor layer 10 is a P-type semiconductor layer 101 and the second semiconductor layer 30 is an N-type semiconductor layer 301.
  • the light emitting diode 200 in the display device 200 is provided with a barrier layer 40 on at least a part of the side surface of at least one of the first semiconductor layer 10 and the second semiconductor layer 30 (such as It is shown that a first barrier layer 40A is provided on the side surface 10A of the first semiconductor layer 10), and the barrier layer 40 is configured to form a charge depletion region between the barrier layer 40 and at least a part of the side surface.
  • the carriers (holes and/or electrons) moving in the first semiconductor layer 10 and/or the second semiconductor layer 30 will be far away from at least part of the side area, thereby realizing a light emitting diode
  • the lateral current limitation of the side surface prevents leakage current in at least part of the side area, and improves the external quantum efficiency of the light-emitting diode, that is, the light-emitting efficiency of the light-emitting diode is improved.

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Abstract

一种发光二极管及其制作方法、显示装置，其中，发光二极管包括：第一半导体层；第二半导体层；发光层，设置于第一半导体层和第二半导体层之间；阻挡层，设置于第一半导体层和第二半导体层中的至少一者的侧面的至少部分区域上，阻挡层被配置为在阻挡层与所述侧面的至少部分区域之间形成电荷耗尽区。

Description

发光二极管及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种发光二极管、发光二极管的制作方法和具有发光二极管的显示装置。
背景技术
近年来，微型发光二极管(Micro LED)作为一种新型的自发光显示技术，受到广泛关注。然而，当发光二极管的尺寸较小(例如小于10μm)时，发光二极管的外量子效率将出现明显的衰减现象，且尺寸越小，外量子效率越低。
发明内容
一方面，提供了一种发光二极管，包括：第一半导体层；第二半导体层；发光层，设置于第一半导体层和第二半导体层之间；阻挡层，设置于第一半导体层和第二半导体层中的至少一者的侧面的至少部分区域上，阻挡层被配置为在阻挡层与所述侧面的至少部分区域之间形成电荷耗尽区。
在一些实施例中，第一半导体层为P型半导体层，第二半导体层为N型半导体层；阻挡层包括覆盖在P型半导体层的侧面的至少部分区域上的第一阻挡层，第一阻挡层的功函数小于P型半导体层的功函数。
在一些实施例中，第一阻挡层包括：第一主体部，覆盖在P型半导体层的侧面上；与第一主体部靠近发光层的一侧连接的第一延伸部，第一延伸部覆盖在发光层的侧面中靠近P型半导体层的部分区域上；在垂直于发光层的一个主表面的方向上，第一延伸部与N型半导体层之间具有间隙。
在一些实施例中，第一阻挡层还包括：与第一主体部远离发光层的一侧连接的第二延伸部，第二延伸部覆盖在P型半导体层远离发光层的主表面的边缘区域上。
在一些实施例中，第一阻挡层在发光层的一个主表面上的正投影呈封闭的框形。
在一些实施例中，第一阻挡层的功函数范围为4.0eV～5.5eV。
在一些实施例中，第一阻挡层的功函数与P型半导体层的功函数之间的差值的绝对值大于或等于0.3eV。
在一些实施例中，第一阻挡层的材料包括金属、导电的金属氧化物、石墨烯和金属性碳纳米管中的至少一种。
在一些实施例中，第一半导体层为P型半导体层，第二半导体层为N型半导体层；阻挡层包括覆盖在N型半导体层的侧面的至少部分区域上的第二阻挡层，第二阻挡层的功函数大于N型半导体层的功函数。
在一些实施例中，第二阻挡层在发光层所确定的平面上的正投影呈封闭的框形。
在一些实施例中，第二阻挡层的功函数范围为4.5eV～5.1eV。
在一些实施例中，第二阻挡层的功函数与N型半导体层的功函数之间的差值的绝对值大于或等于0.3eV。
在一些实施例中，第二阻挡层的材料包括金属、导电的金属氧化物、石墨烯和金属性碳纳米管中的至少一种。
在一些实施例中，第一半导体层为P型半导体层，第二半导体层为N型半导体层；阻挡层包括覆盖在P型半导体层的侧面的至少部分区域上的第一阻挡层，以及，覆盖在N型半导体层的侧面的至少部分区域上的第二阻挡层；在垂直于发光层的一个主表面的方向上，第一阻挡层与第二阻挡层之间具有间隙。
在一些实施例中，第二半导体层具有主体区域和第二电极设置区域，第二半导体层的处于主体区域的部分与发光层及第一半导体层重叠，第二半导体层的处于第二电极设置区域的部分不与发光层及第一半导体层重叠。发光二极管还包括：衬底，设置于第二半导体层远离发光层的一侧；第一电极，设置于第一半导体层远离发光层的主表面上；第二电极，设置于第二半导体层的第二电极设置区域内。
另一方面，提供了一种发光二极管的制作方法，包括：提供衬底；在衬底上依次形成第二半导体层、发光层及第一半导体层；图案化第一半导体层，去除第一半导体层的处于发光二极管的发光区域的边缘的部分；在衬底的形成有图案化的第一半导体层的一侧形成第一阻挡膜；图案化第一阻挡膜，使第一阻挡膜中覆盖在图案化的第一半导体层的侧面的部分被保留，形成第一阻挡层；其中，第一阻挡层被配置为在第一阻挡层与第一半导体层之间形成电荷耗尽区。
在一些实施例中，在图案化第一半导体层的步骤之后，还包括：使用对第一半导体层进行图案化所使用的掩膜，对发光层的处于发光区域的边 缘的部分进行刻蚀，刻蚀深度小于发光层的厚度。
在一些实施例中，图案化第一阻挡膜的步骤中，第一阻挡膜中覆盖在图案化的第一半导体层处于发光区域的主表面边缘区域的部分被保留。
在一些实施例中，在形成发光层之前，还包括：图案化第二半导体层，去除第二半导体层的处于发光区域的边缘的部分；在衬底的形成有图案化的第二半导体层的一侧形成第二阻挡膜；图案化第二阻挡膜，使第一阻挡膜中覆盖在图案化的第二半导体层的侧面的部分被保留，形成第二阻挡层；其中，第二阻挡层被配置为在第二阻挡层与第二半导体层之间形成电荷耗尽区。
再一方面，提供一种显示装置，包括：驱动基板；安装于驱动基板一侧的多个发光二极管，每个发光二极管为如上述任一实施例中的发光二极管，且每个发光二极管与驱动基板电连接。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为根据本公开的一些实施例提供一种发光二极管的俯视图；
图2为图1中发光二极管的A-A向剖视图；
图3为根据本公开的一些实施例提供另一种发光二极管的剖视结构示意图；
图4为根据本公开的一些实施例提供又一种发光二极管的剖视结构示意图；
图5为根据本公开的一些实施例提供一种发光二极管的制作方法的流程示意图；
图6～图14为根据本公开一些实施例提供的发光二极管的制作方法的各步骤示意图；
图15～图18为根据本公开一些实施例提供的制作第二阻挡层的各步骤示意图；
图19为根据本公开的一些实施例提供一种显示装置的结构示意图；
图20为根据本公开的一些实施例提供另一种显示装置的结构示意图。
具体实施方式
下面将结合附图，对本公开的一些实施例进行描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本公开实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
当发光二极管的尺寸缩小后，发光二极管的侧壁的漏电流占总电流的比例上升，绝大多数的载流子通过侧壁表面的非辐射复合机制进行跃迁，因此当发光二极管的尺寸较小时，例如小于10μm时，发光二极管的外量子效率将出现明显的衰减现象，且尺寸越小，外量子效率越低。
在相关技术中，采用缓和的干法刻蚀工艺制备微型发光二极管，或者在微型发光二极管的侧壁上制备钝化薄膜，以期降低微型发光二极管侧面的缺陷和复合中心的密度。然而，缓和的干法刻蚀工艺会造成对微型发光二极管的膜层进行图案化的工艺均匀性以及线宽变差，制备钝化薄膜通常需要进行高温退火工艺，这均导致对微型发光二极管侧面的缺陷和复合中心密度的降低效果较差，造成侧壁表面漏电流仍然较大，微型发光二极管的外量子效率不能得到明显提升。
参见图1和图2，本公开的一些实施例提供了一种发光二极管100，包括第一半导体层10、发光层20、第二半导体层30和阻挡层40。
其中，发光层20设置于第一半导体层10和第二半导体层30之间。示例性的，第一半导体层10和第二半导体层30中的一者为P型半导体层，另一者为N型半导体层。当给发光二极管100加上电压后，N型半导体层中的电子将向发光层20迁移，并进入到发光层20；P型半导体层的空穴也向发光层20迁移，并进入到发光层20。进入发光层20内的电子与空穴 发生复合，从而产生自发辐射光。此处，示例性的，发光层20为多量子阱层(MQW，Multiple Quantum Well)。
阻挡层40设置于第一半导体层10和第二半导体层30中的至少一者的侧面(例如图2中所示的第一半导体层的侧面10A)的至少部分区域上，而且阻挡层40被配置为在阻挡层40与该侧面的至少部分区域之间形成电荷耗尽区70。这样，由于存在电荷耗尽区70，第一半导体层10和/或第二半导体层30中运动的载流子(空穴和/或电子)将远离该侧面的至少部分区域，从而实现了发光二极管的横向电流限制，使该侧面的至少部分区域不易出现漏电流，提高了发光二极管的外量子效率。
需要说明的是，电荷耗尽区70是一个高电阻区。由于存在电荷耗尽区70，使得第一半导体层10和/或第二半导体层30中的载流子(空穴和/或电子)向该侧面的至少部分区域运动时，需要克服肖特基势垒。从而使这些运动的载流子主要集中在远离该侧面的至少部分区域的位置，因此可以实现对注入电流的横向抑制，减少载流子在该侧面的至少部分区域因缺陷和复合中心而形成的非辐射复合，有助于提高发光二极管100的发光效率。
阻挡层40的结构及设置方式有多种，包括但不限于以下多个实施例示出的阻挡层40的结构及设置方式。
在一些实施例中，如图2所示，第一半导体层10为P型半导体层101，第二半导体层30为N型半导体层301。阻挡层40包括覆盖在P型半导体层101的侧面10A的至少部分区域上的第一阻挡层40A，第一阻挡层40A的功函数小于P型半导体层101的功函数。
这样设计，在第一阻挡层40A与P型半导体层101达到热平衡的过程中，第一阻挡层40A内的电子将向P型半导体层101中移动，从而形成内建电场及半导体能带弯曲。而且当第一阻挡层40A与P型半导体层101达到热平衡后，二者费米能级保持一致，在第一阻挡层40A与P型半导体层101之间，第一阻挡层40A内的电子与P型半导体层101内的空穴结合形成电荷耗尽区70，即形成高电阻区。
由于存在电荷耗尽区70，P型半导体层101内的空穴电流分布将发生改变，即空穴电流主要集中在P型半导体层101的体内区域，因此可以实现注入空穴电流的横向抑制，防止空穴电流在P型半导体层101的侧面10A因缺陷和复合中心而形成非辐射复合，减少了该侧面10A的至少部分区域产生漏电流的现象，从而提高了发光二极管的外量子效率，即提高了发光 二极管的发光效率。
示例性的，如图2所示，第一阻挡层40A包括第一主体部401和第一延伸部402。
其中，第一主体部401覆盖在P型半导体层101的侧面10A上。这样，能够在第一主体部401与P型半导体层101的整个侧面10A之间形成电荷耗尽区70，从而能够更好的实现注入电流的横向抑制，改善P型半导体层101的侧面10A漏电流的现象。
第一延伸部402与第一主体部401靠近发光层20的一侧相连接，第一延伸部402覆盖在发光层20的侧面中靠近P型半导体层101的部分区域上。这样设计，使侧面10A靠近发光层20的一端不易出现漏电流现象，并且有利于降低第一阻挡层40A的加工难度。
在垂直于发光层20的一个主表面的方向(图2所示的X方向)上，第一延伸部402与N型半导体层301之间具有间隙d 1。这样能够防止第一阻挡层40A与N型半导体层301相互影响，使第一阻挡层40A与P型半导体层101之间可以产生稳定可靠的电荷耗尽区。
在此基础上，示例性的，如图2所示，第一阻挡层40A还包括与第一主体部401远离发光层20的一侧连接的第二延伸部403，第二延伸部403覆盖在P型半导体层101远离发光层20的主表面10B的边缘区域上。这样设计，使侧面10A靠近主表面10B的一端不易出现漏电流现象，并且有利于降低第一阻挡层40A的加工难度。
示例性的，如图1和图2所示，第一阻挡层40A在发光层20的一个主表面20A上的正投影呈封闭的框形。这样，能够在第一阻挡层40A与P型半导体层101的整个侧面10A之间形成电荷耗尽区70，从而能够更好的实现注入电流的横向抑制，改善P型半导体层101的侧面10A漏电流的现象，提高发光二极管100的发光效率。
此处，需要说明的是，第一阻挡层40A在发光层20的一个主表面20A上的正投影并不局限于呈封闭的框形。例如，第一阻挡层40A包括至少两部分，该至少两部分围绕P型半导体层101的侧面依次间隔设置且排列一周。
示例性的，第一阻挡层40A的材料包括金属、导电的金属氧化物、石墨烯和金属性碳纳米管等中的至少一种。例如，第一阻挡层40A为200nm～300nm厚的金属层或导电的金属氧化物层；又例如，第一阻挡层 40A为一层或两层石墨烯。
在一些可能的设计中，第一阻挡层40A的功函数范围为4.0eV～5.5eV。该范围内的材料包括但不限于钛、铝、银、铟、钼、铜、铬、金等。通过第一阻挡层40A的功函数范围为4.0eV～5.5eV，使第一阻挡层40A的功函数可以小于P型半导体层101的功函数(P型半导体层101的功函数范围通常为6eV～7eV)，因此能够在第一阻挡层40A与P型半导体层101的侧面10A之间形成电荷耗尽区70，实现改善P型半导体层101的侧面10A的漏电流现象。
在此基础上，示例性的，第一阻挡层40A的功函数与P型半导体层101的功函数之间的差值的绝对值大于或等于0.3eV。这样，使第一阻挡层40A与P型半导体层101之间形成的电荷耗尽区70具有较高的肖特基势垒，从而能够有效的防止P型半导体层101内的空穴电流从其侧面10A泄露出去，具有较高的稳定性和可靠性。
在另一些实施例中，如图3所示，阻挡层40包括覆盖在N型半导体层301的侧面30A的至少部分区域上的第二阻挡层40B，第二阻挡层40B的功函数大于N型半导体层301的功函数。
这样设计，在第二阻挡层40B与N型半导体层301达到热平衡的过程中，N型半导体层301内的电子将向第二阻挡层40B中移动，从而形成内建电场及半导体能带弯曲。而且当第二阻挡层40B与N型半导体层301达到热平衡后，二者费米能级保持一致，在第二阻挡层40B与N型半导体层301之间，N型半导体层301内的电子与第二阻挡层40B内的空穴结合形成电荷耗尽区70，即形成高电阻区。
由于存在电荷耗尽区70，N型半导体层301内的电子电流分布将发生改变，即电子电流主要集中在N型半导体层301的体内区域，因此可以实现注入电子电流的横向抑制，防止电子电流在N型半导体层301的侧面30A因缺陷和复合中心而形成非辐射复合，减少了该侧面30A的至少部分区域产生漏电流的现象，从而提高了发光二极管的外量子效率，即提高了发光二极管的发光效率。
示例性的，如图3所示，第二阻挡层40B覆盖在N型半导体层301的整个侧面30A上。这样能够在第二阻挡层40B与N型半导体层301的整个侧面30A之间形成电荷耗尽区70，从而能够更好的实现注入电流的横向抑制，改善N型半导体层301的侧面30A漏电流的现象。
在此基础上，示例性的，如图3所示，第二阻挡层40B覆盖发光层20的侧面中靠近N型半导体层301的部分区域上。这样设计，使侧面30A靠近发光层20的一端不易出现漏电流现象，并且有利于降低第二阻挡层40B的加工难度。
在垂直于发光层20的一个主表面的方向(图3所示的X方向)上，第二阻挡层40B与P型半导体层101之间具有间隙d 2。这样能够防止第二阻挡层40B与P型半导体层101相互影响，使第二阻挡层40B与N型半导体层301之间可以产生稳定可靠的电荷耗尽区。
示例性的，如图3所示，第二阻挡层40B在发光层20的一个主表面20A上的正投影呈封闭的框形。这样，能够在第二阻挡层40B与N型半导体层301的整个侧面30A之间形成电荷耗尽区70，从而能够更好的实现注入电流的横向抑制，改善N型半导体层301的侧面30A漏电流的现象，提高发光二极管100的发光效率。
此处，需要说明的是，第二阻挡层40B在发光层20的一个主表面20A上的正投影并不局限于呈封闭的框形。例如，第一阻挡层40A包括至少两部分，该至少两部分围绕N型半导体层301的侧面30A依次间隔设置且排列一周。
示例性的，第二阻挡层40B的材料包括金属、导电的金属氧化物、石墨烯和金属性碳纳米管中的至少一种。例如，第二阻挡层40B为200nm～300nm厚的金属层或导电的金属氧化物层；又例如，第二阻挡层40B为一层或两层石墨烯。
示例性的，第二阻挡层40B的功函数范围为4.5eV～5.1eV。该范围内的材料包括但不限于钼、铜、铬、金、镍等。通过第二阻挡层40B的功函数范围为4.5eV～5.1eV，使第二阻挡层40B的功函数可以大于N型半导体层301的功函数(N型半导体层301的功函数范围通常为4.0eV～4.2eV)，因此能够在第二阻挡层40B与N型半导体层301的侧面30A之间形成电荷耗尽区70，实现改善N型半导体层301的侧面30A的漏电流现象。
在此基础上，示例性的，第二阻挡层40B的功函数与N型半导体层301的功函数之间的差值的绝对值大于或等于0.3eV。这样，使第二阻挡层40B与N型半导体层301之间形成的电荷耗尽区70具有较高的肖特基势垒，从而能够有效的防止N型半导体层301内的电子电流从其侧面30A泄露出去，具有较高的稳定性和可靠性。
在另一些实施例中，如图4所示，阻挡层40包括覆盖在P型半导体层101的侧面10A的至少部分区域上的第一阻挡层40A，以及，覆盖在N型半导体层301的侧面30A的至少部分区域上的第二阻挡层40B。这样，可以同时实现减少所述侧面10A的至少部分区域和所述侧面30A的至少部分区域产生漏电流的现象，从而提高发光二极管的外量子效率，以提高发光二极管的发光效率。
示例性的，如图4所示，在垂直于发光层20的一个主表面的方向(图4中示出的X方向)上，第一阻挡层40A与第二阻挡层40B之间具有间隙d 3。例如，可以通过发光层20将第一阻挡层40A与第二阻挡层40B分隔开。这时，第二阻挡层40B不覆盖发光层20的侧面中靠近N型半导体层301的部分区域。这样设计，能够防止第一阻挡层40A与第二阻挡层40B相互影响，使第一阻挡层40A与P型半导体层101之间，以及，第二阻挡层40B与N型半导体层301之间均可以产生稳定可靠的电荷耗尽区。
参见图1～图4，在一些实施例中，第二半导体层30具有主体区域M 1和第二电极设置区域M 2，第二半导体层30的处于主体区域M 1的部分与发光层20及第一半导体层10重叠，第二半导体层30的处于第二电极设置区域M 2的部分不与发光层20及第一半导体层10重叠。
如图1～图4所示，发光二极管100还包括衬底80、第一电极50及第二电极60。
其中，衬底80设置于第二半导体层30远离发光层20的一侧。通过设置衬底80，便于形成依次叠加的第二半导体层30、发光层20及第一半导体层10。示例性的，如图2～图4所示，衬底包括蓝宝石衬底801和位于蓝宝石衬底801与第二半导体层30之间的缓冲层802。
第一电极50设置于第一半导体层10远离发光层20的主表面10B上，第二电极60设置于第二半导体层30的第二电极设置区域M 2内。这样，可以通过第一电极50向第一半导体层10内注入载流子(空穴和电子中的一者)，及通过第二电极60向第二半导体层30内注入载流子(空穴和电子中的另一者)。
其中，示例性的，如图2～图4所示，当第一半导体层10为P型半导体层101，第二半导体层30为N型半导体层301时，第一电极50为阳极，第二电极60为阴极。
需要说明的是，此处，第一半导体层10为P型半导体层101和N型 半导体层301中的一者，第二半导体层30为P型半导体层101和N型半导体层301中的另一者。当第一半导体层10为N型半导体层301，第二半导体层30为P型半导体层101时，参见图2～图4，覆盖在N型半导体层301的侧面30A的第二阻挡层40B，包括与第一阻挡层40A的第二延伸部403相类似的结构。
参见图5，本公开一些实施例提供一种发光二极管的制作方法，该制作方法包括步骤901～步骤905。
步骤901，如图6所示，提供衬底80。
其中，衬底80起支撑作用，能够使后续形成的各个层(例如第一半导体层、第二半导体层及发光层等)具有较高的稳定性和可靠性。示例性的，衬底80包括蓝宝石衬底801和位于蓝宝石衬底801一侧的缓冲层802。
步骤902，如图7所示，在衬底80上依次形成第二半导体层30、发光层20及第一半导体层10。
其中，第一半导体层10为P型半导体层101和N型半导体层301中的一者，第二半导体层30为P型半导体层101和N型半导体层301中的另一者。例如，图7中示出了第一半导体层10为P型半导体层101，第二半导体层30为N型半导体层301。示例性的，步骤902包括但不限于采用外延生长工艺在衬底80的一侧依次生长出N型半导体层301、发光层20及P型半导体层101。
步骤903，如图8和图9所示，图案化第一半导体层10，去除第一半导体层10的处于发光二极管100的发光区域P 1的边缘的部分。
其中，采用构图工艺图案化第一半导体层10。例如，首先在第一半导体层10远离发光层20的一侧形成光刻胶层；然后对该光刻胶层进行曝光和显影，得到图案化的光刻胶层，该图案化的光刻胶层暴露第一半导体层10的处于发光区域P 1边缘的部分的表面；最后，使用该图案化的光刻胶层对第一半导体层10进行刻蚀，去除第一半导体层10的处于发光二极管100的发光区域P 1的边缘的部分。
示例性的，图案化第一半导体层10，可以仅去除第一半导体层10的处于发光二极管100的发光区域P 1的边缘的部分(如图8所示)；也可以在去除第一半导体层10的处于发光二极管100的发光区域P 1的边缘的部分的同时，将第一半导体层10的处于发光二极管100的非发光区域P 2的 部分一并去除(如图9所示)。这里的非发光区域P 2指的是发光二极管100上除发光区域P 1以外的区域。
如图8所示，在仅去除第一半导体层10的处于发光二极管的发光区域P 1的边缘的部分，第一半导体层10上将形成凹槽10C。示例性的，凹槽10C在发光层20的一个主表面20A上的正投影呈封闭的框形；或者，凹槽10C的数量为多个，多个凹槽10C围绕第一半导体层10依次间隔排列一周。
步骤904，如图10所示，在衬底80的形成有图案化的第一半导体层10的一侧形成第一阻挡膜404。
其中，形成第一阻挡膜404时，可以采用物理气相沉积工艺、溅射工艺、蒸发工艺和转移工艺中的任意一种。例如，当第一阻挡膜404的材料为导电的金属氧化物或金属(例如钼、铝、铜等)时，可以采用物理气相沉积工艺或溅射工艺或蒸发工艺，制备出第一阻挡膜404。当第一阻挡膜404的材料为石墨烯时，可以采用转移工艺将铜上化学气相沉积生长的单层或少层石墨烯(例如1层～2层)转移至衬底80的形成有图案化的第一半导体层10的一侧，以形成第一阻挡膜404。
步骤905，参见图11，图案化第一阻挡膜404，使第一阻挡膜404中覆盖在图案化的第一半导体层10的侧面10A的部分被保留，形成第一阻挡层40A。
其中，采用构图工艺图案化第一阻挡膜404，可以去除第一阻挡膜404中不需要保留的部分，例如，去除第一阻挡膜404中处于非发光区域P 2的部分，及处于第一半导体层位于发光区域P 1的主表面10B上的部分，以实现使第一阻挡膜404中覆盖在图案化的第一半导体层10的侧面10A的部分被保留，形成第一阻挡层40A。
第一阻挡层40A被配置为在第一阻挡层40A与第一半导体层10之间形成电荷耗尽区70。这样，由于存在电荷耗尽区70，第一半导体层10中运动的载流子(空穴或电子)将远离侧面10A，从而实现了发光二极管的横向电流限制，使侧面10A不易出现漏电流现象，提高发光二极管100的外量子效率，进而提高发光二极管100的发光效率。
在一些实施例中，在步骤903之后，该制作方法还包括：
如图12所示，使用对第一半导体层10进行图案化所使用的掩膜，对发光层20的处于发光区域P 1的边缘的部分进行刻蚀，刻蚀深度小于发光 层的厚度。这样，在后续制作第一阻挡膜404时，可以使第一阻挡膜覆盖发光层20的侧面中靠近第一半导体层101的部分区域。从而有利于降低第一阻挡层40A的加工难度；并且，如图13所示，使第一阻挡层40A有效的覆盖第一半导体层101的整个侧面10A，第一半导体层101的侧面10A靠近发光层20的一端不易出现漏电流现象。
在一些实施例中，如图11和图13所示，图案化第一阻挡膜404的步骤中，第一阻挡膜404中覆盖在图案化的第一半导体层10处于发光区域P 1的主表面10B边缘区域的部分被保留。这样，这样设计，使侧面10A靠近主表面10B的一端不易出现漏电流现象，并且有利于降低形成的第一阻挡层40A的加工难度。
在一些实施例中，如图14所示，该制作方法还包括如下步骤：
图案化发光层20，去除发光层20的处于非发光区域P 2的部分，使第二半导体层30的处于非发光区域P 2的部分的表面被暴露。然后，在暴露出的第一半导体层30的表面上形成第二电极60，在图案化的第一半导体层10远离发光层20的表面上形成第一电极50。
在一些实施例中，在形成发光层之前，该制作方法还包括步骤一～步骤三。
步骤一、如图15和图16所示，图案化第二半导体层30，去除第二半导体层30的处于发光区域P 1的边缘的部分。
其中，采用图案化第二半导体层30的步骤与上述图案化第一半导体层10的步骤相同，此处不再赘述。
示例性的，图案化第一半导体层30，可以仅去除第二半导体层30的处于发光二极管100的发光区域P 1的边缘的部分(如图15所示)；也可以在去除第二半导体层30的处于发光二极管100的发光区域P 1的边缘的部分的同时，将第二半导体层30的处于发光二极管100的非发光区域P 2的部分一并去除(如图16所示)。这里的非发光区域P 2指的是发光二极管100上除发光区域P 1以外的区域。
如图15所示，在仅去除第二半导体层30的处于发光二极管100的发光区域P 1的边缘的部分，第二半导体层30上将形成凹槽30B。示例性的，凹槽30B在衬底80上的正投影呈封闭的框形；或者，凹槽30B的数量为多个，多个凹槽30B围绕第二半导体层30依次间隔排列一周。
步骤二、如图17所示，在衬底的形成有图案化的第二半导体层30的 一侧形成第二阻挡膜405。
其中，形成第二阻挡膜405时，可以采用物理气相沉积工艺、溅射工艺、蒸发工艺和转移工艺中的任意一种。例如，当第二阻挡膜405的材料为导电的金属氧化物或金属(例如钼、铝、铜等)时，可以采用物理气相沉积工艺或溅射工艺或蒸发工艺，制备出第二阻挡膜405。当第二阻挡膜405的材料为石墨烯时，可以采用转移工艺将铜上化学气相沉积生长的单层或少层石墨烯(例如1层～2层)转移至衬底80的形成有图案化的第二半导体层30的一侧，以形成第一阻挡膜405。
步骤三、如图18所示，图案化第二阻挡膜405，使第一阻挡膜中覆盖在图案化的第二半导体层的侧面的部分被保留，形成第二阻挡层；其中，第二阻挡层被配置为在第二阻挡层与第二半导体层之间形成电荷耗尽区。
其中，采用构图工艺图案化第二阻挡膜405，可以去除第二阻挡膜405中不需要保留的部分，例如，去除第二阻挡膜405中处于非发光区域P 2的部分，及处于第二半导体层位于发光区域P 1的主表面30C上的部分，以实现使第二阻挡膜405中覆盖在图案化的第二半导体层30的侧面30A的部分被保留，形成第二阻挡层40B。
第二阻挡层40B被配置为在第二阻挡层40B与第二半导体层30之间形成电荷耗尽区70。这样，由于存在电荷耗尽区70，第二半导体层30中运动的载流子(空穴或电子)将远离侧面30A，从而实现了发光二极管的横向电流限制，使侧面30A不易出现漏电流现象，提高发光二极管100的外量子效率，进而提高发光二极管100的发光效率。
在形成第二阻挡层40B后，可以采用上述一个或多个步骤以形成发光层20及第一半导体层10，接着形成第一阻挡层、第一电极及第二电极，以制作出如图4所示出的发光二极管100。
参见图19和图20，本公开一些实施例提供一种显示装置200，显示装置200包括驱动基板300和安装于驱动基板300一侧的多个发光二极管100，每个发光二极管100为上述任一实施例中的发光二极管200，且每个发光二极管100与驱动基板300电连接。其中，驱动基板300为有源驱动基板或者无源驱动基板。安装在驱动基板300上的发光二极管100，不包括衬底。即，通过上述制作方法制作完成的发光二极管100，在安装至驱动基板300之前，需要先去除衬底。
示例性的，如图19所示，驱动基板300设置在第二半导体层30远离 发光层20的一侧。这时，可以通过制作连接线400，使每个发光二极管100的第一电极50和第二电极60均连接至驱动基板300上。
示例性的，如图20所示，驱动基板300设置在第一半导体层10远离发光层20的一侧。这时，可以通过焊点500，使每个发光二极管100的第一电极50和第二电极60均连接至驱动基板300上。
此处，需要说明的是，第一半导体层10和第二半导体层30中的一者为P型半导体层101，另一者为N型半导体层301。例如，图19中示出了第一半导体层10为P型半导体层101，第二半导体层30为N型半导体层301的示例。
参见图19和图20，显示装置200中的发光二极管200，由于在第一半导体层10和第二半导体层30中的至少一者的侧面的至少部分区域上设置有阻挡层40(例如图19中示出了在第一半导体层10的侧面10A设置有第一阻挡层40A)，而且阻挡层40被配置为在阻挡层40与该侧面的至少部分区域之间形成电荷耗尽区。这样，由于存在电荷耗尽区，第一半导体层10和/或第二半导体层30中运动的载流子(空穴和/或电子)将远离该侧面的至少部分区域，从而实现了发光二极管的横向电流限制，使该侧面的至少部分区域不易出现漏电流现象，提高了发光二极管的外量子效率，即提高了发光二极管的发光效率。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种发光二极管，包括：
    第一半导体层；
    第二半导体层；
    发光层，设置于所述第一半导体层和所述第二半导体层之间；
    阻挡层，设置于所述第一半导体层和所述第二半导体层中的至少一者的侧面的至少部分区域上，所述阻挡层被配置为在所述阻挡层与所述侧面的至少部分区域之间形成电荷耗尽区。
  2. 根据权利要求1所述的发光二极管，其中，所述第一半导体层为P型半导体层，所述第二半导体层为N型半导体层；
    所述阻挡层包括覆盖在所述P型半导体层的侧面的至少部分区域上的第一阻挡层，所述第一阻挡层的功函数小于所述P型半导体层的功函数。
  3. 根据权利要求2所述的发光二极管，其中，所述第一阻挡层包括：
    第一主体部，覆盖在所述P型半导体层的侧面上；
    与所述第一主体部靠近所述发光层的一侧连接的第一延伸部，所述第一延伸部覆盖在所述发光层的侧面中靠近所述P型半导体层的部分区域上；在垂直于所述发光层的一个主表面的方向上，所述第一延伸部与所述N型半导体层之间具有间隙。
  4. 根据权利要求3所述的发光二极管，其中，所述第一阻挡层还包括：
    与所述第一主体部远离所述发光层的一侧连接的第二延伸部，所述第二延伸部覆盖在所述P型半导体层远离所述发光层的主表面的边缘区域上。
  5. 根据权利要求2所述的发光二极管，其中，所述第一阻挡层在所述发光层的一个主表面上的正投影呈封闭的框形。
  6. 根据权利要求2所述的发光二极管，其中，所述第一阻挡层的功函数范围为4.0eV～5.5eV。
  7. 根据权利要求2所述的发光二极管，其中，所述第一阻挡层的功函数与所述P型半导体层的功函数之间的差值的绝对值大于或等于0.3eV。
  8. 根据权利要求2所述的发光二极管，其中，所述第一阻挡层的材料包括金属、导电的金属氧化物、石墨烯和金属性碳纳米管中的至少一种。
  9. 根据权利要求1或2所述的发光二极管，其中，所述第一半导体层为P型半导体层，所述第二半导体层为N型半导体层；
    所述阻挡层包括覆盖在所述N型半导体层的侧面的至少部分区域上的 第二阻挡层，所述第二阻挡层的功函数大于所述N型半导体层的功函数。
  10. 根据权利要求9所述的发光二极管，其中，所述第二阻挡层在所述发光层所确定的平面上的正投影呈封闭的框形。
  11. 根据权利要求9所述的发光二极管，其中，所述第二阻挡层的功函数范围为4.5eV～5.1eV。
  12. 根据权利要求9所述的发光二极管，其中，所述第二阻挡层的功函数与所述N型半导体层的功函数之间的差值的绝对值大于或等于0.3eV。
  13. 根据权利要求9所述的发光二极管，其中，所述第二阻挡层的材料包括金属、导电的金属氧化物、石墨烯和金属性碳纳米管中的至少一种。
  14. 根据权利要求1所述的发光二极管，其中，所述第一半导体层为P型半导体层，所述第二半导体层为N型半导体层；
    所述阻挡层包括覆盖在所述P型半导体层的侧面的至少部分区域上的第一阻挡层，以及，覆盖在所述N型半导体层的侧面的至少部分区域上的第二阻挡层；
    在垂直于所述发光层的一个主表面的方向上，所述第一阻挡层与所述第二阻挡层之间具有间隙。
  15. 根据权利要求1所述的发光二极管，其中，所述第二半导体层具有主体区域和第二电极设置区域，所述第二半导体层的处于所述主体区域的部分与所述发光层及所述第一半导体层重叠，所述第二半导体层的处于所述第二电极设置区域的部分不与所述发光层及所述第一半导体层重叠；
    所述发光二极管还包括：
    衬底，设置于所述第二半导体层远离所述发光层的一侧；
    第一电极，设置于所述第一半导体层远离所述发光层的主表面上；
    第二电极，设置于所述第二半导体层的第二电极设置区域内。
  16. 一种发光二极管的制作方法，包括：
    提供衬底；
    在所述衬底上依次形成第二半导体层、发光层及第一半导体层；
    图案化所述第一半导体层，去除所述第一半导体层的处于所述发光二极管的发光区域的边缘的部分；
    在所述衬底的形成有图案化的第一半导体层的一侧形成第一阻挡膜；
    图案化所述第一阻挡膜，使所述第一阻挡膜中覆盖在所述图案化的第一半导体层的侧面的部分被保留，形成第一阻挡层；其中，第一阻挡层被 配置为在所述第一阻挡层与所述第一半导体层之间形成电荷耗尽区。
  17. 根据权利要求16所述的制作方法，其中，在所述图案化所述第一半导体层的步骤之后，还包括：
    使用对所述第一半导体层进行图案化所使用的掩膜，对所述发光层的处于所述发光区域的边缘的部分进行刻蚀，刻蚀深度小于所述发光层的厚度。
  18. 根据权利要求17所述的制作方法，其中，所述图案化所述第一阻挡膜的步骤中，所述第一阻挡膜中覆盖在所述图案化的第一半导体层处于所述发光区域的主表面边缘区域的部分被保留。
  19. 根据权利要求16所述的制作方法，其中，在形成所述发光层之前，还包括：
    图案化所述第二半导体层，去除所述第二半导体层的处于所述发光区域的边缘的部分；
    在所述衬底的形成有图案化的第二半导体层的一侧形成第二阻挡膜；
    图案化所述第二阻挡膜，使所述第一阻挡膜中覆盖在图案化的第二半导体层的侧面的部分被保留，形成第二阻挡层；其中，所述第二阻挡层被配置为在所述第二阻挡层与所述第二半导体层之间形成电荷耗尽区。
  20. 一种显示装置，包括：
    驱动基板；
    安装于所述驱动基板一侧的多个发光二极管，每个所述发光二极管为如权利要求1～15中任一项所述的发光二极管，且每个所述发光二极管与所述驱动基板电连接。
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