WO2020238307A1 - Mos管桥式电路的驱动电路及驱动方法及储能设备 - Google Patents

Mos管桥式电路的驱动电路及驱动方法及储能设备 Download PDF

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Publication number
WO2020238307A1
WO2020238307A1 PCT/CN2020/077270 CN2020077270W WO2020238307A1 WO 2020238307 A1 WO2020238307 A1 WO 2020238307A1 CN 2020077270 W CN2020077270 W CN 2020077270W WO 2020238307 A1 WO2020238307 A1 WO 2020238307A1
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Prior art keywords
circuit
bridge
drive
gate
driving
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PCT/CN2020/077270
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English (en)
French (fr)
Inventor
刘巍
李统成
周明亮
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深圳可立克科技股份有限公司
惠州市可立克电子有限公司
惠州市可立克科技有限公司
信丰可立克科技有限公司
安远县美景电子有限公司
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Publication of WO2020238307A1 publication Critical patent/WO2020238307A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches

Definitions

  • This application relates to the technical field of MOS tube bridge circuits, and in particular to a driving circuit and driving method of a MOS tube bridge circuit, and an energy storage device.
  • New energy energy storage products are equipped with MOS tube bridge circuits.
  • the MOS tube bridge circuit includes an H bridge, and the H bridge includes four MOS tubes. New energy storage products need to drive the H-bridge during their work.
  • an ordinary MCU Microcontroller Unit
  • an ordinary MCU Microcontroller Unit
  • the inverted signal is amplified by the driving chip, thereby generating two PWM (Pulse Width Modulation, pulse width modulation) that enable the upper and lower MOS transistors to turn on and off complementary Width modulation) waveform.
  • PWM Pulse Width Modulation, pulse width modulation
  • the current amplification capabilities of the two transistors in the reverse control circuit are different and the turn-on and turn-off times are inconsistent. It is easy to cause the output of the drive chip to turn on and turn off the complementary drive signals of the upper and lower MOS transistors at the same time, causing the upper and lower MOS transistors of the H bridge to pass through , Causing damage to the product.
  • the present application proposes a driving circuit and a driving method of a MOS transistor bridge circuit and an energy storage device, which can effectively control the operation of the H bridge and reduce the risk of direct conduction of the upper and lower MOS transistors of the H bridge.
  • the present application provides a driving circuit for a MOS transistor bridge circuit
  • the MOS transistor bridge circuit includes at least one half bridge, and the half bridge includes two MOS transistors;
  • the drive circuit includes a single-chip microcomputer, a half-bridge drive circuit, a gate circuit, a bleeder circuit, and a discharge circuit; the half-bridge drive circuit includes a drive chip with dead time control;
  • the single-chip microcomputer can generate at least one set of complementary sinusoidal pulse width modulation driving signals, and the single-chip microcomputer can set the dead time of the sinusoidal pulse width modulation driving signals;
  • the half-bridge drive circuit can amplify and convert the set of complementary sinusoidal pulse width modulation drive signals
  • the gate circuit can transmit the signal sent by the half-bridge driving circuit to the MOS tube to drive the MOS tube;
  • the bleeder circuit is connected to the gate and the source of the MOS tube for discharging the voltage between the gate and the source when the MOS tube is turned off;
  • the discharge circuit is connected to the gate and the source of the MOS tube, and is used for discharging the capacitance between the gate and the source when the MOS tube is turned off.
  • the gate circuit includes a drive resistor and a diode, one end of the drive resistor is connected to an output pin of the drive chip, and one end of the diode is connected to the other end of the drive resistor. Connected, the other end of the diode is connected to the gate of the MOS tube; the bleeder circuit includes a bleeder resistor and a triode, the base of the triode is connected between the driving resistor and the diode, the triode The emitter is connected to one end of the bleeder resistor, the collector of the triode is connected to the source of the MOS tube, and the other end of the bleeder resistor is connected to the gate of the MOS tube; the discharge The circuit includes a discharge resistor connected between the gate and the source of the MOS tube.
  • the two MOS transistors are respectively a high-end MOS transistor and a low-end MOS transistor;
  • the half-bridge drive circuit also includes a fast recovery diode and a bootstrap capacitor; one end of the fast recovery diode Connected to the start-up voltage pin of the driver chip, the other end of the fast recovery diode is used to connect voltage to provide a high-side driving voltage; one end of the bootstrap capacitor is connected to the start-up voltage pin of the driver chip Pin, the other end of the bootstrap capacitor is connected to the source of the high-side MOS transistor, thereby raising the power supply voltage to drive the high-side MOS transistor.
  • the single-chip microcomputer includes a micro-control unit, a DC bus current detection circuit, a clock signal generating circuit, and a peripheral capacitor;
  • the DC bus current detection circuit is connected to the micro control unit, and is used to trigger the micro control unit to stop outputting the sinusoidal pulse width modulation drive signal when the output load exceeds a limit value;
  • the clock signal generating circuit is connected to the micro control unit to input a clock signal for calculation to the micro control unit;
  • the peripheral capacitor is used for powering the micro control unit and for filtering out interference noise.
  • the MOS transistor bridge circuit includes two half-bridges, and the two half-bridges form an H-bridge; the voltage access pin and the ground pin of the drive chip are connected to Input capacitor for energy storage and filtering.
  • the present application provides a driving method of a MOS transistor bridge circuit, the MOS transistor bridge circuit includes at least one half bridge, and the half bridge includes two MOS transistors;
  • the driving method includes:
  • the voltage between the gate and the source of the MOS transistor is triggered by the sinusoidal pulse width modulation drive signal. Discharge.
  • the output of the sinusoidal pulse width modulation drive signal is stopped if it is detected that the output load exceeds a limit value.
  • the present application provides an energy storage device, including the above-mentioned driving circuit and at least one half bridge.
  • the present application also provides an energy storage device, including a processor, a memory, and one or more programs.
  • the one or more programs are stored in the memory and configured to be processed by the The program includes instructions for executing the above-mentioned driving method.
  • the single-chip microcomputer adopts the complementary upper and lower tube drive mode, which can set the dead time of multiple output drive signals, and the half-bridge drive circuit has dead time control.
  • the discharge circuit discharges the voltage Vgs between the gate and the source of the MOS transistor, and the discharge circuit discharges the capacitance Cgs between the gate and the source of the MOS transistor.
  • the MOS transistors can quickly respond to complementary drive signals, realize the complementary turn-on and turn-off of the upper and lower transistors, and reduce the risk of direct conduction of the upper and lower MOS transistors of the half bridge under abnormal conditions.
  • FIG. 1 schematically shows a part of the circuit structure of the MOS transistor bridge circuit of the first embodiment of the present application
  • Fig. 2 schematically shows the circuit structure of the single-chip microcomputer in the first embodiment of the present application
  • Fig. 3 schematically shows the circuit structure of the half-bridge drive circuit, the gate circuit, the bleeder circuit, the discharge circuit, and the H-bridge of the first embodiment of the present application;
  • FIG. 4 is a schematic flowchart of the driving method of the MOS transistor bridge circuit according to the first embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present application, “a plurality of” means two or more than two, unless otherwise specifically defined.
  • the MOS transistor bridge circuit 100 of this embodiment includes two half bridges and a driving circuit 200, and the two half bridges form an H bridge.
  • the driving circuit 200 is used to drive the H bridge so that the H bridge controls the load.
  • the line where the H bridge is located is the H bridge power line.
  • the MOS transistor bridge circuit includes a half bridge.
  • Each half-bridge includes two MOS transistors, which are an upper MOS transistor and a lower MOS transistor.
  • the H bridge it includes the upper left arm MOS transistor Q12, the lower left arm MOS transistor Q14, the upper right arm MOS transistor Q13, and the lower right arm MOS transistor Q15.
  • the line where the upper left bridge arm MOS transistor Q12 is located and the line where the lower left bridge arm MOS transistor Q14 is located are both high-frequency MOS transistor lines
  • the line where the upper right bridge arm MOS transistor Q13 is located and the line where the lower right bridge arm MOS transistor Q15 is located are both It is a low-frequency MOS tube circuit.
  • the driving circuit 200 of this embodiment includes a single-chip microcomputer 1, two half-bridge driving circuits 2, four gate circuits 3, four bleeder circuits 4, and four discharge circuits 5.
  • One half-bridge driving circuit 2 drives the upper left arm MOS transistor Q12 and the lower left arm MOS transistor Q14, and the other half-bridge driving circuit 2 drives the upper right arm MOS transistor Q13 and the lower right arm MOS transistor Q15.
  • the left upper bridge arm MOS transistor Q12, the left lower bridge arm MOS transistor Q14, the right upper bridge arm MOS transistor Q13 and the right lower bridge arm MOS transistor Q15 all correspond to a bleeder circuit 4 and a discharge circuit 5.
  • the single-chip microcomputer 1 can generate two complementary sinusoidal pulse width modulation (Sinusoidal Pulse Width Modulation, SPWM) driving signals.
  • MCU 1 can output four driving signals.
  • a group of complementary sinusoidal pulse width modulation drive signals are used to make the left upper bridge arm MOS transistor Q12 and the left lower bridge arm MOS transistor Q14 turn on and off complementary, that is, one turns on and the other turns off.
  • Another set of complementary sinusoidal pulse width modulation drive signals is used to turn on and off the right upper MOS transistor Q13 and the right lower MOS transistor Q15, that is, one is turned on and the other is turned off.
  • the single chip microcomputer 1 can set the dead time of each sine pulse width modulation driving signal.
  • a group of complementary sinusoidal pulse width modulation driving signals generated by the single-chip microcomputer 1 is transmitted to one half-bridge driving circuit 2, and the other group is transmitted to another half-bridge driving circuit 2.
  • Each half-bridge driving circuit 2 includes a driving chip.
  • the first half-bridge driving circuit 2 includes a driver chip U7
  • the second half-bridge driving circuit 2 includes a driver chip U17.
  • the driving chip is controlled by the dead time, and the dead time generated by the driving chip can be superimposed on the driving signal with the dead time generated by the single-chip microcomputer.
  • the half-bridge driving circuit 2 can amplify and convert a group of complementary sinusoidal pulse width modulation driving signals; among them, conversion mainly refers to reverse processing of two driving signals and inverting the two driving signals.
  • the amplified and converted two sinusoidal pulse width modulation drive signals are respectively delivered to the two gate circuits 3.
  • the driving chip is an integrated half-bridge driving amplifier circuit
  • the dead time of the driving chip is 450 nS.
  • Each gate circuit 3 can transmit the signal from the half-bridge driving circuit 2 to the MOS tube to drive the MOS tube.
  • one end of the first gate circuit 3 is connected to the high-side output pin DRV_Hi of the first half-bridge driving circuit 2, and the other end is connected to the gate of the left upper bridge MOS transistor Q12;
  • One end of the gate circuit 3 is connected to the low-end output pin DRV_Lo of the first half-bridge drive circuit 2, and the other end is connected to the gate of the left lower bridge arm MOS transistor Q14;
  • one end of the third gate circuit 3 It is connected to the high-end output pin DRV_Hi of the second half-bridge drive circuit 2, and the other end is connected to the gate of the upper right-side MOS transistor Q13;
  • one end of the fourth gate circuit 3 is connected to the second half-bridge drive circuit
  • the low-end output pin DRV_Lo of 2 is connected, and the other end is connected to the gate of the lower right-side MOS transistor Q15.
  • a bleeder circuit 4 is connected between the gate and the source of each MOS tube.
  • the bleeder circuit 4 is used to discharge the voltage Vgs between the gate and the source when the MOS tube is turned off.
  • a discharge circuit 5 is also connected between the gate and the source of each MOS tube.
  • the discharge circuit 5 is used for discharging the capacitance Cgs between the gate and the source when the MOS tube is turned off.
  • the driving method of this embodiment includes steps S1 to S5.
  • Step S1 Generate two complementary sinusoidal pulse width modulation drive signals, and set the dead time of the sinusoidal pulse width modulation drive signal.
  • the single-chip microcomputer 1 completes step S1 and sends the sinusoidal pulse width modulation driving signal to the two half-bridge driving circuits 2.
  • Step S2 Amplify and convert a group of complementary sinusoidal pulse width modulation drive signals.
  • each half-bridge drive circuit 2 receives a set of complementary sinusoidal pulse width modulation drive signals, it amplifies and converts the signals, and then sends the two signals to the two gate circuits 3 respectively.
  • Step S3 transmitting the amplified and converted signal to the MOS tube to drive the MOS tube.
  • step S3 is completed by the gate circuit 3.
  • Step S4 Discharging the voltage between the gate and the source when the MOS tube is turned off.
  • step S4 is completed by the bleeder circuit 4.
  • Step S5 Discharge the capacitance between the gate and the source when the MOS tube is turned off.
  • step S5 is completed by the discharge circuit 5.
  • the single-chip microcomputer 1 adopts a complementary upper and lower tube driving mode, which can set the dead time of four output driving signals, and the half-bridge driving circuit 2 has dead time control.
  • the bleeder circuit 4 discharges the voltage Vgs between the gate and the source of the MOS tube
  • the discharge circuit 5 discharges the capacitance Cgs between the gate and the source of the MOS tube.
  • the MOS transistors can quickly respond to complementary drive signals, realize the complementary turn-on and turn-off of the upper and lower transistors, and reduce the risk of direct conduction of the upper and lower MOS transistors of the H bridge under abnormal conditions.
  • the first gate circuit 3 includes a driving resistor R112 and a diode D18.
  • One end of the driving resistor R112 is connected to the high-end output pin DRV_Hi of the driving chip U7.
  • One end of the diode D18 is connected to the other end of the driving resistor R112, and the other end of the diode D18 is connected to the gate of the MOS transistor Q12.
  • the first bleeder circuit 4 includes a bleeder resistor R49 and a transistor Q17.
  • the transistor Q17 is a PNP type transistor.
  • the base of the transistor Q17 is connected between the driving resistor R112 and the diode D18, the emitter of the transistor Q17 is connected to one end of the bleeder resistor R49, the collector of the transistor Q17 is connected to the source of the MOS transistor Q12, and the other of the bleeder resistor R49 One end is connected to the gate of the MOS transistor Q12.
  • the first discharge circuit 5 includes a discharge resistor R114 connected between the gate and the source of the MOS transistor Q12.
  • the driving signal is output from the half-bridge driving circuit 2, and enters the gate of the MOS transistor Q12 through the driving resistor R112 and the diode D18. Since the base of the transistor Q17 is connected between the driving resistor R112 and the diode D18, the driving signal will also enter the base of the transistor Q17.
  • the drive signal is converted from a high level to a low level, the gate of the MOS transistor Q12 is low, and the base of the transistor Q17 is also low.
  • the MOS transistor Q12 when the MOS transistor Q12 is turned off, the voltage Vgs between the gate and the source of the MOS transistor Q12 will be discharged through the emitter and collector of the bleeder resistors R49 and Q17, and between the gate and the source of the MOS transistor Q12 The capacitor Cgs will be discharged through the discharge resistor R114.
  • One signal can trigger the MOS transistor Q12 to turn off, the discharge circuit 4 to discharge, and the discharge circuit 5 to discharge at almost the same time, so that the MOS transistor Q12 can be turned off quickly and reliably, and the driving circuit can be simplified.
  • the second gate circuit 3, the second bleeder circuit 4 and the second discharge circuit 5 are similar, and a brief description is given here.
  • the second gate circuit 3 includes a driving resistor R53 and a diode D21. One end of the driving resistor R53 is connected to the low-end output pin DRV_Lo of the driving chip U7.
  • the second bleeder circuit 4 includes a bleeder resistor R117 and a transistor Q19.
  • the second discharge circuit 5 includes a discharge resistor R119.
  • the third gate circuit 3, the third bleeder circuit 4, and the third discharge circuit 5 are similar, and a brief description will be made here.
  • the third gate circuit 3 includes a driving resistor R50 and a diode D19. One end of the driving resistor R50 is connected to the high-end output pin DRV_Hi of the driving chip U17.
  • the third bleeder circuit 4 includes a bleeder resistor R113 and a transistor Q18.
  • the third discharge circuit 5 includes a discharge resistor R115.
  • the fourth gate circuit 3, the fourth bleeder circuit 4, and the fourth discharge circuit 5 are similar, and a brief description is given here.
  • the fourth gate circuit 3 includes a driving resistor R54 and a diode D22. One end of the driving resistor R54 is connected to the low-end output pin DRV_Lo of the driving chip U17.
  • the fourth bleeder circuit 4 includes a bleeder resistor R120 and a transistor Q20.
  • the fourth discharge circuit 5 includes a discharge resistor R122.
  • Each half-bridge driving circuit 2 also includes a fast recovery diode and a bootstrap capacitor.
  • the first half-bridge driving circuit 2 includes a fast recovery diode D17 and a bootstrap capacitor C33.
  • One end of the fast recovery diode D17 is connected to the startup voltage pin Vboot of the driving chip 21, and the other end of the fast recovery diode D17 is used to connect the voltage +12VPRI to provide the high-side driving voltage.
  • One end of the bootstrap capacitor C33 is connected to the startup voltage pin Vboot of the driver chip 21, and the other end of the bootstrap capacitor C33 is connected to the source of the high-side MOS transistor Q12.
  • the bootstrap capacitor C33 uses the characteristic that the voltage across the capacitor cannot change suddenly.
  • the negative terminal voltage of the capacitor is increased, and the positive terminal voltage remains at the original voltage difference of the negative terminal, which is equal to the voltage at the positive terminal by the negative terminal.
  • the source potential of the upper left-side MOS transistor Q12 is raised to meet the withstand voltage between the gate and the source of the upper-side MOS transistor and the normal drive.
  • the bootstrap capacitor C33 is actually a positive feedback capacitor, which is used to increase the supply voltage to drive the high-side MOS transistor Q12.
  • the second half-bridge driving circuit 2 is similar, including fast recovery diode D20 and bootstrap capacitor C38.
  • An input capacitor C35 for energy storage and filtering is connected between the voltage access pin VCC of the first driving chip U7 and the ground pin GND. Between the voltage access pin VCC of the second drive chip U17 and the ground pin GND is connected an input capacitor C39 for energy storage and filtering.
  • the input capacitor C35 and the input capacitor C39 are mainly used for energy storage and filtering.
  • the single-chip microcomputer 1 includes a micro-control unit U801, a DC bus current detection circuit, a clock signal generating circuit and a peripheral capacitor.
  • the micro control unit U801 is a 32-bit control chip.
  • the micro-control unit U801 and its surrounding circuits form a complementary drive signal generating circuit, and its main function is to send two sets of complementary sinusoidal pulse width modulation drive signals.
  • the drive signals output by the terminals Gate1L_Inv and Gate1H_Inv of the micro-control unit U801 drive the lower and upper MOS transistors of a half-bridge respectively, and the drive signals output by the terminals Gate2L_Inv and the terminal Gate2H_Inv drive the other half respectively.
  • the lower-arm MOS tube and upper-arm MOS tube of the bridge are examples of the bridge.
  • the micro-control unit U801 can use a 20PIN MCU, which can reduce some peripheral circuits and reduce the area of the PCB.
  • the DC bus current detection circuit includes a comparator U819, a resistor R807, a resistor R809, a capacitor C805, a resistor R805, a capacitor C872, and a capacitor C875.
  • the DC bus current detection circuit is connected to the micro control unit U801, and is used to trigger the micro control unit U801 to stop outputting the sinusoidal pulse width modulation driving signal when the output load exceeds the limit value, so that the SPWM driving is turned off. That is, if it is detected that the output load exceeds the limit value, the output of the sinusoidal pulse width modulation drive signal is stopped.
  • the clock signal generating circuit is connected with the micro control unit U801 to input a clock signal for calculation to the micro control unit U801.
  • the clock signal generating circuit is a circuit for generating the external clock signal of the micro-control unit U801, which includes crystal oscillator Y801, capacitor C819, capacitor C820, and resistor R815.
  • the peripheral capacitors specifically include a capacitor C811, a capacitor C813, and a capacitor C812, which are used to supply power to the micro-control unit U801 and to filter out interference noise, which can ensure the stability of the micro-control unit U801.
  • Resistor R810, capacitor C838 and resistor R816 are peripheral circuits that the micro control unit U801 needs to configure for normal operation.
  • the terminal Vbus_Meas is used to connect the feedback weak current signal of the DC bus voltage.
  • the resistor R811 and the capacitor C842 form an RC low-pass filter circuit.
  • the terminal Uac_FB_Inv is used to connect the AC output voltage feedback signal.
  • Resistor R812 and capacitor C848 form an RC low-pass filter circuit.
  • the working voltage +12VPRI required by the driver chip U7 and the driver chip U17 and the working voltage required by the micro control unit U801 +3V3PRI will be generated through the step-down circuit.
  • the internal clock calculated by the micro control unit U801 will be obtained through the external crystal oscillator Y801.
  • the micro control unit U801 confirms that the SPWM drive signal is generated according to the detected weak feedback signal of the DC bus voltage and the voltage feedback signal of the AC output connected to the terminal Uac_FB_Inv.
  • a set of complementary sinusoidal pulse width modulation drive signals output by the terminal Gate1L_Inv and the terminal Gate1H_Inv are input to the low-end input pin IN_Lo and the high-end input pin IN_Hi of the driver chip U7.
  • the driver chip U7 outputs signals for driving the lower left-side MOS transistor Q14 and the upper left-side MOS transistor Q12 through the low-side output pin DRV_Lo and the high-side output pin DRV_Hi.
  • a set of complementary sinusoidal pulse width modulation drive signals output by the terminal Gate2L_Inv and the terminal Gate2H_Inv are input to the low-end input pin IN_Lo and the high-end input pin IN_Hi of the driver chip U17.
  • the driver chip U17 outputs signals for driving the lower right-side MOS transistor Q15 and the upper right-side MOS transistor Q13 through the low-side output pin DRV_Lo and the high-side output pin DRV_Hi.
  • pins on the micro control unit U801 including pin VSS, pin BOOT0, pin PB7, pin PB6, pin PB5, pin PB4, pin PB3, pin PA15, pin Pin PA14, Pin PA13, Pin PA12, Pin PA11, Pin PA10, Pin PA9, Pin PA8, Pin VDD, Pin PB1, Pin PB0, Pin PA7, Pin PA6, Pin PA5 , Pin PA4, Pin PA3, Pin PA1, Pin PA0, Pin VDDA, Pin NRST, Pin OSC_OUT and Pin OSC_IN. Each pin is connected to the corresponding circuit.
  • the pin OSC_OUT and the pin OSC_IN are connected, the pin PA6 is connected to the terminal Gate1H_Inv, the pin PB6 is connected to the terminal Gate1L_Inv, the pin PA8 is connected to the terminal Gate2H_Inv, and the pin PA7 is connected to the terminal Gate2L_Inv.
  • Pin PA10 is connected to one end of resistor R808.
  • the pin PA9 is connected to one end of the resistor R820.
  • the driver chip is also provided with pin IN_Lo, pin IN_Hi and pin Bridge.
  • the pins IN_Lo and IN_Hi of the driver chip U7 are respectively connected to the terminal Gate1L_Inv and the terminal Gate1H_Inv.
  • the pins IN_Lo and IN_Hi of the driver chip U17 are respectively connected to the terminal Gate2L_Inv and the terminal Gate2H_Inv.
  • This embodiment provides an energy storage device, including the above-mentioned driving circuit 200 and at least one half bridge.
  • the energy storage device of this embodiment is specifically a 500W portable energy storage new energy product, and the product specifications are:
  • the charging can meet the 12VDC charging of the car cigarette lighter, the 15VDC voltage charging of the adapter and the outdoor or indoor 10V to 25VDC solar panel charging;
  • the inverter output is pure sine wave output, which can meet the output of 100V to 230VAC, 50/60Hz.
  • This embodiment provides an energy storage device, including a processor, a memory, and one or more programs, where the one or more programs are stored in the memory and are configured to be executed by the processor, and the one or more programs include Instructions for executing the above driving method.

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Abstract

本申请公开了一种MOS管桥式电路的驱动电路及驱动方法及储能设备。所述驱动电路包括单片机、半桥驱动线路、栅极电路、泄放电路和放电电路；所述半桥驱动线路包括带有死区时间控制的驱动芯片。所述驱动方法包括产生至少一组互补的正弦脉宽调制驱动信号，以及设定所述正弦脉宽调制驱动信号的死区时间；对所述一组互补的正弦脉宽调制驱动信号进行放大和转换；将放大和转换后的信号传输给所述MOS管以驱动所述MOS管；对所述MOS管关断时的栅极与源极之间的电压放电；对所述MOS管关断时的栅极与源极之间的电容放电。所述储能设备包括用于执行所述驱动方法的一个或多个程序。本申请可有效地控制半桥的工作，可降低异常情况下半桥的上下MOS管直接导通的风险。

Description

MOS管桥式电路的驱动电路及驱动方法及储能设备 技术领域
本申请涉及MOS管桥式电路技术领域，特别涉及一种MOS管桥式电路的驱动电路及驱动方法及储能设备。
背景技术
新能源储能产品设有MOS管桥式电路，MOS管桥式电路包括H桥，H桥包括四个MOS管。新能源储能产品在工作的过程中需要驱动H桥。一般通过具有一对互补驱动输出端口的普通MCU(Microcontroller Unit，微控制单元)执行软件的查表算法，来输出互补驱动信号。由包括两个三极管的反向控制线路将互补驱动信号进行反转后，通过驱动芯片对反转信号进行放大，从而产生两个使上下MOS管互补开通和关断的PWM(Pulse Width Modulation，脉冲宽度调制)波形。反向控制线路中的两个三极管的电流放大能力不同且开通和关断时间不一致，容易造成驱动芯片输出会同时开通和关断上下MOS管的互补驱动信号，从而造成H桥的上下MOS管直通，使得产品损坏。
以上背景技术内容的公开仅用于辅助理解本申请的发明构思及技术方案，其并不必然属于本申请的现有技术，在没有明确的证据表明上述内容在本申请的申请日已经公开的情况下，上述背景技术不应当用于评价本申请的新颖性和创造性。
发明内容
本申请提出一种MOS管桥式电路的驱动电路及驱动方法及储能设备，可有效地控制H桥的工作，可降低H桥的上下MOS管直接导通的风险。
在第一方面，本申请提供一种MOS管桥式电路的驱动电路，所述MOS管桥式电路包括至少一个半桥，所述半桥包括两个MOS管；
所述驱动电路包括单片机、半桥驱动线路、栅极电路、泄放电路和放电电路；所述半桥驱动线路包括带有死区时间控制的驱动芯片；
所述单片机可产生至少一组互补的正弦脉宽调制驱动信号，所述单片机可设定所述正弦脉宽调制驱动信号的死区时间；
所述半桥驱动线路可对所述一组互补的正弦脉宽调制驱动信号进行放大和转换；
所述栅极电路可将所述半桥驱动线路发出的信号传输给所述MOS管以驱动所述MOS管；
所述泄放电路连接所述MOS管的栅极与源极，用于所述MOS管关断时的栅极与源极之间的电压放电；
所述放电电路连接所述MOS管的栅极与源极，用于所述MOS管关断时的栅极与源极之间的电容放电。
在一些优选的实施方式中，所述栅极电路包括驱动电阻和二极管，所述驱动电阻的一端与所述驱动芯片的一个输出引脚连接，所述二极管的一端与所述驱动电阻的另一端连接，所述二极管的另一端与所述MOS管的栅极连接；所述泄放电路包括泄放电阻和三极管，所述三极管的基极连接至所述驱动电阻和二极管之间，所述三极管的发射极与所述泄放电阻的一端连接，所述三极管的集电极与所述MOS管的源极连接，所述泄放电阻的另一端与所述MOS管的栅极连接；所述放电电路包括连接在所述MOS管的栅极与源极之间的放电电阻。
在一些优选的实施方式中，所述两个MOS管分别为一个高端MOS管和一个低端MOS管；所述半桥驱动线路还包括快回复二极管和自举电容；所述快回复二极管的一端连接至所述驱动芯片的启动电压引脚，所述快回复二极管的另一端用于接入电压，以提供高端驱动的电压；所述自举电容的一端连接至所述驱动芯片的启动电压引脚，所述自举电容的另一端连接至所述高端MOS管的源极，从而抬高供电电压以驱动所述高端MOS管。
在一些优选的实施方式中，所述单片机包括微控制单元、直流母线电流检测线路、时钟信号产生电路和外围电容；
所述直流母线电流检测线路与所述微控制单元连接，用于在输出负载超过限定值时触发所述微控制单元停止输出所述正弦脉宽调制驱动信号；
所述时钟信号产生电路与所述微控制单元连接，以向所述微控制单元输入用于计算的时钟信号；
所述外围电容用于为所述微控制单元供电以及用于滤除干扰杂讯。
在一些优选的实施方式中，所述MOS管桥式电路包括两个半桥，所述两个半桥形成H桥；所述驱动芯片的电压接入引脚和接地引脚之间连接有用于储能和滤波的输入电容。
在第二方面，本申请提供一种MOS管桥式电路的驱动方法，所述MOS管桥式电路包括至少一个半桥，所述半桥包括两个MOS管；
所述驱动方法包括：
产生至少一组互补的正弦脉宽调制驱动信号，以及设定所述正弦脉宽调制驱动信号的死区时间；
对所述一组互补的正弦脉宽调制驱动信号进行放大和转换；
将放大和转换后的信号传输给所述MOS管以驱动所述MOS管；
对所述MOS管关断时的栅极与源极之间的电压放电；
对所述MOS管关断时的栅极与源极之间的电容放电。
在一些优选的实施方式中，通过所述正弦脉宽调制驱动信号关断所述MOS管的同时，通过所述正弦脉宽调制驱动信号触发所述MOS管的栅极与源极之间的电压放电。
在一些优选的实施方式中，若检测到输出负载超过限定值，则停止输出所述正弦脉宽调制驱动信号。
在第三方面，本申请提供一种储能设备，包括上述驱动电路和至少一个半桥。
在第四方面，本申请还提供一种储能设备，包括处理器、存储器和一个或多个程序，所述一个或多个程序被存储在所述存储器中，并且被配置成由所述处理器执行，所述程序包括用于执行上述驱动方法的指令。
与现有技术相比，本申请的有益效果有：
单片机采用互补的上下管驱动方式，可以进行多路输出驱动信号的死区时间设定，半桥驱动线路带有死区时间控制。在MOS管关断时，泄放电路对MOS管栅极与源极之间的电压Vgs进行放电，放电电路则对对MOS管栅极与源极之间的电容Cgs进行放电。如此，可使得MOS管快速响应互补的驱动信号，实现上下管的互补开通和关断，可降低异常情况下半桥的上下MOS管直接导通的风险。
附图说明
图1示意性地示出本申请第一实施例的MOS管桥式电路的一部分电路结构；
图2示意性地示出本申请第一实施例的单片机的电路结构；
图3示意性地示出本申请第一实施例的半桥驱动线路、栅极电路、泄放电路、放电电路和H桥的电路结构；
图4为本申请第一实施例的MOS管桥式电路的驱动方法的流程示意图。
具体实施方式
为了使本申请实施例所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合图1至图4及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需要理解的是，术语“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多该特征。在本申请实施例的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
第一实施例
参考图1，本实施例的MOS管桥式电路100包括两个半桥和驱动电路200，两个半桥形成H桥。驱动电路200用于驱动H桥，以便H桥控制负载。H桥所在的线路为H桥功率线路。在其它实施例中，MOS管桥式电路包括一个半桥。
每个半桥包括两个MOS管，分别为上桥臂MOS管和下桥臂MOS管。对于H桥，则是包括左上桥臂MOS管Q12、左下桥臂MOS管Q14、右上桥臂MOS管Q13和右下桥臂MOS管Q15。其中，左上桥臂MOS管Q12所在的线路和左下桥臂MOS管Q14所在的线路均为高频MOS管线路，右上桥臂MOS管Q13所在的线路和右下桥臂MOS管Q15所在的线路均为低频MOS管线路。
本实施例的驱动电路200包括单片机1、两个半桥驱动线路2、四个栅极电路3、四个泄放电路4和四个放电电路5。一个半桥驱动线路2驱动左上桥臂MOS管Q12和左下桥臂MOS管Q14，另一个半桥驱动线路2驱动右上桥臂MOS管Q13和右下桥臂MOS管Q15。左上桥臂MOS管Q12、左下桥臂MOS管Q14、右上桥臂MOS管Q13和右下桥臂MOS管Q15均对应一个泄放电路4和一个放电电路5。
单片机1可产生两组互补的正弦脉宽调制(Sinusoidal Pulse Width Modulation，简称SPWM)驱动信号。也就是说单片机1可以输出四个驱动 信号。一组互补的正弦脉宽调制驱动信号用于使左上桥臂MOS管Q12和左下桥臂MOS管Q14互补开通和关断，也即一个开通，另一个关断。另一组互补的正弦脉宽调制驱动信号用于使右上桥臂MOS管Q13和右下桥臂MOS管Q15互补开通和关断，也即一个开通，另一个关断。单片机1可设定每个正弦脉宽调制驱动信号的死区时间。单片机1产生的一组互补的正弦脉宽调制驱动信号传输至一个半桥驱动线路2，另一组则传输至另一个半桥驱动线路2。
每个半桥驱动线路2包括一个驱动芯片。在本实施例中，参考图3，第一个半桥驱动线路2包括驱动芯片U7，第二个半桥驱动线路2包括驱动芯片U17。其中，驱动芯片是带有死区时间控制的，驱动芯片产生的死区时间可与单片机产生的死区时间在驱动信号中叠加。半桥驱动线路2可对一组互补的正弦脉宽调制驱动信号进行放大和转换；其中，转换主要是指对两个驱动信号进行反向处理，将两个驱动信号反转。经过放大和转换的两个正弦脉宽调制驱动信号分别输送至两个栅极电路3。在本实施例中，驱动芯片是集成半桥驱动放大电路，驱动芯片的死区时间为450nS。
每个栅极电路3可将半桥驱动线路2发出的信号传输给MOS管以驱动MOS管。具体的，参考图1，第一个栅极电路3的一端与第一个半桥驱动线路2的高端输出引脚DRV_Hi连接，另一端则与左上桥臂MOS管Q12的栅极连接；第二个栅极电路3的一端则与第一个半桥驱动线路2的低端输出引脚DRV_Lo连接，另一端则与左下桥臂MOS管Q14的栅极连接；第三个栅极电路3的一端与第二个半桥驱动线路2的高端输出引脚DRV_Hi连接，另一端则与右上桥臂MOS管Q13的栅极连接；第四个栅极电路3的一端则与第二个半桥驱动线路2的低端输出引脚DRV_Lo连接，另一端则与右下桥臂MOS管Q15的栅极连接。
在每个MOS管的栅极与源极之间连接有泄放电路4。泄放电路4用于MOS管关断时对栅极与源极之间的电压Vgs进行放电。
在每个MOS管的栅极与源极之间还连接有放电电路5。放电电路5用于MOS管关断时对栅极与源极之间的电容Cgs进行放电。
结合本实施例的MOS管桥式电路的驱动方法对本实施例进行说明。参考图4，本实施例的驱动方法包括步骤S1至步骤S5。
步骤S1、产生两组互补的正弦脉宽调制驱动信号，以及设定正弦脉宽调制驱动信号的死区时间。在本实施例中，通过单片机1完成步骤S1并将 正弦脉宽调制驱动信号发送至两个半桥驱动线路2。
步骤S2、对一组互补的正弦脉宽调制驱动信号进行放大和转换。在本实施例中，每个半桥驱动线路2接收到一组互补的正弦脉宽调制驱动信号后，对该信号进行放大和转换，然后将两个信号分别发送给两个栅极电路3。
步骤S3、将放大和转换后的信号传输给MOS管以驱动MOS管。在本实施例中，通过栅极电路3完成步骤S3。
步骤S4、对MOS管关断时的栅极与源极之间的电压放电。在本实施例中，通过泄放电路4完成步骤S4。
步骤S5、对MOS管关断时的栅极与源极之间的电容放电。在本实施例中，通过放电电路5完成步骤S5。
根据上述可知，单片机1采用互补的上下管驱动方式，可以进行四路输出驱动信号的死区时间设定，半桥驱动线路2带有死区时间控制。在MOS管关断时，泄放电路4对MOS管栅极与源极之间的电压Vgs进行放电，放电电路5则对对MOS管栅极与源极之间的电容Cgs进行放电。如此，可使得MOS管快速响应互补的驱动信号，实现上下管的互补开通和关断，可降低异常情况下H桥的上下MOS管直接导通的风险。
参考图3，第一个栅极电路3包括驱动电阻R112和二极管D18。驱动电阻R112的一端与驱动芯片U7的高端输出引脚DRV_Hi连接。二极管D18的一端与驱动电阻R112的另一端连接，二极管D18的另一端与MOS管Q12的栅极连接。
第一个泄放电路4包括泄放电阻R49和三极管Q17。在本实施例中，三极管Q17为PNP型的晶体三极管。三极管Q17的基极连接至驱动电阻R112和二极管D18之间，三极管Q17的发射极与泄放电阻R49的一端连接，三极管Q17的集电极与MOS管Q12的源极连接，泄放电阻R49的另一端与MOS管Q12的栅极连接。
第一个放电电路5包括连接在MOS管Q12的栅极与源极之间的放电电阻R114。
参考图3，驱动信号从半桥驱动线路2输出，经过驱动电阻R112和二极管D18进入MOS管Q12的栅极。由于三极管Q17的基极连接至驱动电阻R112和二极管D18之间，因此该驱动信号也会进入三极管Q17的基极。为了使MOS管Q12从导通状态转换到截止状态，驱动信号从高电平转换成低 电平，MOS管Q12的栅极是低电平，三极管Q17的基极也是低电平。如此，在MOS管Q12关断时，MOS管Q12的栅极与源极之间的电压Vgs会通过泄放电阻R49和Q17发射极与集电极放电，MOS管Q12的栅极与源极之间的电容Cgs会通过放电电阻R114放电。通过一个信号即可几乎同时触发MOS管Q12关断、泄放电路4放电和放电电路5放电，从而可快速、可靠地关断MOS管Q12，也可简化驱动电路。
对于第二个栅极电路3、第二个泄放电路4和第二个放电电路5也是类似，在此进行简单的描述。第二个栅极电路3包括驱动电阻R53和二极管D21。驱动电阻R53的一端与驱动芯片U7的低端输出引脚DRV_Lo连接。第二个泄放电路4包括泄放电阻R117和三极管Q19。第二个放电电路5包括放电电阻R119。
对于第三个栅极电路3、第三个泄放电路4和第三个放电电路5也是类似，在此进行简单的描述。第三个栅极电路3包括驱动电阻R50和二极管D19。驱动电阻R50的一端与驱动芯片U17的高端输出引脚DRV_Hi连接。第三个泄放电路4包括泄放电阻R113和三极管Q18。第三个放电电路5包括放电电阻R115。
对于第四个栅极电路3、第四个泄放电路4和第四个放电电路5也是类似，在此进行简单的描述。第四个栅极电路3包括驱动电阻R54和二极管D22。驱动电阻R54的一端与驱动芯片U17的低端输出引脚DRV_Lo连接。第四个泄放电路4包括泄放电阻R120和三极管Q20。第四个放电电路5包括放电电阻R122。
左上桥臂MOS管Q12和右上桥臂MOS管Q13为高端MOS管。左下桥臂MOS管Q14和右下桥臂MOS管Q15为低端MOS管。每个半桥驱动线路2还包括快回复二极管和自举电容。
第一个半桥驱动线路2包括快回复二极管D17和自举电容C33。快回复二极管D17的一端连接至驱动芯片21的启动电压引脚Vboot，快回复二极管D17的另一端用于接入电压+12VPRI，以提供高端驱动的电压。自举电容C33的一端连接至驱动芯片21的启动电压引脚Vboot，自举电容C33的另一端连接至高端MOS管Q12的源极。自举电容C33是利用电容两端电压不能突变的特性，当电容两端保持有一定电压时，提高电容负端电压，正端电压仍保持于负端的原始压差，等于正端的电压被负端举起来了，将左上桥臂MOS管Q12的源极电位提升，以满足上桥臂MOS管栅极与源极之间 的耐压和正常的驱动。自举电容C33实际就是正反馈电容，用于抬高供电电压以驱动高端MOS管Q12。
对于第二个半桥驱动线路2也是类似，包括快回复二极管D20和自举电容C38。
第一个驱动芯片U7的电压接入引脚VCC和接地引脚GND之间连接有用于储能和滤波的输入电容C35。第二个驱动芯片U17的电压接入引脚VCC和接地引脚GND之间则连接有用于储能和滤波的输入电容C39。输入电容C35和输入电容C39主要用于储能和滤波。
单片机1包括微控制单元U801、直流母线电流检测线路、时钟信号产生电路和外围电容。
在本实施例中，微控制单元U801是32位的控制芯片。微控制单元U801与其周围的线路形成互补驱动信号产生线路，主要作用是发送两组互补的正弦脉宽调制驱动信号。微控制单元U801的接线端Gate1L_Inv和接线端Gate1H_Inv输出的驱动信号分别驱动一个半桥的下桥臂MOS管和上桥臂MOS管，接线端Gate2L_Inv和接线端Gate2H_Inv输出的驱动信号分别驱动另外一个半桥的下桥臂MOS管和上桥臂MOS管。
微控制单元U801可采用使用20PIN的MCU，如此可减少部分外围线路和减少了PCB的面积。
参考图2，直流母线电流检测线路包括比较器U819、电阻R807、电阻R809、电容C805、电阻R805、电容C872和电容C875。直流母线电流检测线路与微控制单元U801连接，用于在输出负载超过限定值时触发微控制单元U801停止输出正弦脉宽调制驱动信号，使SPWM驱动关掉。也就是，若检测到输出负载超过限定值，则停止输出正弦脉宽调制驱动信号。
时钟信号产生电路与微控制单元U801连接，以向微控制单元U801输入用于计算的时钟信号。参考图2，时钟信号产生电路是微控制单元U801外部时钟信号的产生线路，包括晶振Y801、电容C819、电容C820和电阻R815。
参考图2，外围电容具体包括电容C811、电容C813和电容C812，用于为微控制单元U801供电以及用于滤除干扰杂讯，可保证微控制单元U801工作稳定。
电阻R810、电容C838和电阻R816是微控制单元U801正常工作所需要配置的外围线路。
接线端Vbus_Meas用于接入直流母线电压的反馈弱电信号。电阻R811和电容C842形成RC低通滤波线路。
接线端Uac_FB_Inv用于接入AC输出的电压反馈信号。电阻R812和电容C848形成RC低通滤波线路。
参考图3，当直流高压母线+360VPRI正常工作，将会通过降压线路产生驱动芯片U7和驱动芯片U17所需的工作电压+12VPRI以及微控制单元U801所需的工作电压+3V3PRI。微控制单元U801内部计算的时钟将会通过外部晶振Y801得到。微控制单元U801根据检测到的直流母线电压的反馈弱电信号以及接线端Uac_FB_Inv接入的AC输出的电压反馈信号，确认生成SPWM驱动信号。
接线端Gate1L_Inv和接线端Gate1H_Inv输出的一组互补的正弦脉宽调制驱动信号，输入到驱动芯片U7的低端输入脚IN_Lo和高端输入脚IN_Hi。驱动芯片U7通过低端输出引脚DRV_Lo和高端输出引脚DRV_Hi输出驱动左下桥臂MOS管Q14和左上桥臂MOS管Q12的信号。
接线端Gate2L_Inv和接线端Gate2H_Inv输出的一组互补的正弦脉宽调制驱动信号，输入到驱动芯片U17的低端输入脚IN_Lo和高端输入脚IN_Hi。驱动芯片U17通过低端输出引脚DRV_Lo和高端输出引脚DRV_Hi输出驱动右下桥臂MOS管Q15和右上桥臂MOS管Q13的信号。
参考图2，微控制单元U801上设有多个引脚，包括引脚VSS、引脚BOOT0、引脚PB7、引脚PB6、引脚PB5、引脚PB4、引脚PB3、引脚PA15、引脚PA14、引脚PA13、引脚PA12、引脚PA11、引脚PA10、引脚PA9、引脚PA8、引脚VDD、引脚PB1、引脚PB0、引脚PA7、引脚PA6、引脚PA5、引脚PA4、引脚PA3、引脚PA1、引脚PA0、引脚VDDA、引脚NRST、引脚OSC_OUT和引脚OSC_IN。各个引脚与相应的电路连接。其中，引脚OSC_OUT和引脚OSC_IN与连接，引脚PA6与接线端Gate1H_Inv连接，引脚PB6与接线端Gate1L_Inv连接，引脚PA8与接线端Gate2H_Inv连接，引脚PA7与接线端Gate2L_Inv连接。引脚PA10与电阻R808的一端连接。引脚PA9与电阻R820的一端连接。
参考图3，驱动芯片还设有引脚IN_Lo、引脚IN_Hi和引脚Bridge。驱动芯片U7的引脚IN_Lo和引脚IN_Hi分别与接线端Gate1L_Inv和接线端Gate1H_Inv连接。驱动芯片U17的引脚IN_Lo和引脚IN_Hi分别与接线端Gate2L_Inv和接线端Gate2H_Inv连接。
第二实施例
本实施例提供一种储能设备，包括上述驱动电路200和至少一个半桥。
本实施例的储能设备具体为500W便携式储能新能源产品，产品规格为：
500WH 4串17并共68节铁锂18650 1C(36AH)放电锂电储能设备，电池电压12.4V至16.8VDC，逆变输出电压230V/50Hz/500W；
充电可以满足汽车车载点烟器12VDC充电，可通过适配器的15VDC电压充电以及户外或户内的10V至25VDC太阳能板充电；
逆变输出是纯正弦波输出，可以满足100V至230VAC、50/60Hz的输出。
第三实施例
本实施例提供一种储能设备，包括处理器、存储器和一个或多个程序，其中，一个或多个程序被存储在存储器中，并且被配置成由处理器执行，一个或多个程序包括用于执行上述驱动方法的指令。
以上内容是结合具体/优选的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，其还可以对这些已描述的实施方式做出若干替代或变型，而这些替代或变型方式都应当视为属于本申请的保护范围。

Claims (10)

  1. 一种MOS管桥式电路的驱动电路，其特征在于：所述MOS管桥式电路包括至少一个半桥，所述半桥包括两个MOS管；
    所述驱动电路包括单片机、半桥驱动线路、栅极电路、泄放电路和放电电路；所述半桥驱动线路包括带有死区时间控制的驱动芯片；
    所述单片机可产生至少一组互补的正弦脉宽调制驱动信号，所述单片机可设定所述正弦脉宽调制驱动信号的死区时间；
    所述半桥驱动线路可对所述一组互补的正弦脉宽调制驱动信号进行放大和转换；
    所述栅极电路可将所述半桥驱动线路发出的信号传输给所述MOS管以驱动所述MOS管；
    所述泄放电路连接所述MOS管的栅极与源极，用于所述MOS管关断时的栅极与源极之间的电压放电；
    所述放电电路连接所述MOS管的栅极与源极，用于所述MOS管关断时的栅极与源极之间的电容放电。
  2. 根据权利要求1所述的驱动电路，其特征在于：
    所述栅极电路包括驱动电阻和二极管，所述驱动电阻的一端与所述驱动芯片的一个输出引脚连接，所述二极管的一端与所述驱动电阻的另一端连接，所述二极管的另一端与所述MOS管的栅极连接；
    所述泄放电路包括泄放电阻和三极管，所述三极管的基极连接至所述驱动电阻和二极管之间，所述三极管的发射极与所述泄放电阻的一端连接，所述三极管的集电极与所述MOS管的源极连接，所述泄放电阻的另一端与所述MOS管的栅极连接；
    所述放电电路包括连接在所述MOS管的栅极与源极之间的放电电阻。
  3. 根据权利要求2所述的驱动电路，其特征在于：
    所述两个MOS管分别为一个高端MOS管和一个低端MOS管；
    所述半桥驱动线路还包括快回复二极管和自举电容；
    所述快回复二极管的一端连接至所述驱动芯片的启动电压引脚，所述快回复二极管的另一端用于接入电压，以提供高端驱动的电压；
    所述自举电容的一端连接至所述驱动芯片的启动电压引脚，所述自举电容的另一端连接至所述高端MOS管的源极，从而抬高供电电压以驱动所 述高端MOS管。
  4. 根据权利要求1所述的驱动电路，其特征在于：所述单片机包括微控制单元、直流母线电流检测线路、时钟信号产生电路和外围电容；
    所述直流母线电流检测线路与所述微控制单元连接，用于在输出负载超过限定值时触发所述微控制单元停止输出所述正弦脉宽调制驱动信号；
    所述时钟信号产生电路与所述微控制单元连接，以向所述微控制单元输入用于计算的时钟信号；
    所述外围电容用于为所述微控制单元供电以及用于滤除干扰杂讯。
  5. 根据权利要求1至4任一项所述的驱动电路，其特征在于：所述MOS管桥式电路包括两个半桥，所述两个半桥形成H桥；所述驱动芯片的电压接入引脚和接地引脚之间连接有用于储能和滤波的输入电容。
  6. 一种MOS管桥式电路的驱动方法，其特征在于：所述MOS管桥式电路包括至少一个半桥，所述半桥包括两个MOS管；
    所述驱动方法包括：
    产生至少一组互补的正弦脉宽调制驱动信号，以及设定所述正弦脉宽调制驱动信号的死区时间；
    对所述一组互补的正弦脉宽调制驱动信号进行放大和转换；
    将放大和转换后的信号传输给所述MOS管以驱动所述MOS管；
    对所述MOS管关断时的栅极与源极之间的电压放电；
    对所述MOS管关断时的栅极与源极之间的电容放电。
  7. 根据权利要求6所述的驱动方法，其特征在于：通过所述正弦脉宽调制驱动信号关断所述MOS管的同时，通过所述正弦脉宽调制驱动信号触发所述MOS管的栅极与源极之间的电压放电。
  8. 根据权利要求6所述的驱动方法，其特征在于：若检测到输出负载超过限定值，则停止输出所述正弦脉宽调制驱动信号。
  9. 一种储能设备，其特征在于：包括根据权利要求1至5任一项所述驱动电路和至少一个半桥。
  10. 一种储能设备，其特征在于：包括处理器、存储器和一个或多个程序，所述一个或多个程序被存储在所述存储器中，并且被配置成由所述处理器执行，所述程序包括用于执行根据权利要求6至8任一项所述驱动方法的指令。
PCT/CN2020/077270 2019-05-30 2020-02-28 Mos管桥式电路的驱动电路及驱动方法及储能设备 WO2020238307A1 (zh)

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