WO2020229914A1 - 半導体装置、および半導体装置の作製方法 - Google Patents

半導体装置、および半導体装置の作製方法 Download PDF

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Publication number
WO2020229914A1
WO2020229914A1 PCT/IB2020/053912 IB2020053912W WO2020229914A1 WO 2020229914 A1 WO2020229914 A1 WO 2020229914A1 IB 2020053912 W IB2020053912 W IB 2020053912W WO 2020229914 A1 WO2020229914 A1 WO 2020229914A1
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Prior art keywords
oxide
insulator
conductor
film
transistor
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
方堂涼太
掛端哲弥
笹川慎也
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to US17/606,830 priority Critical patent/US12218247B2/en
Priority to JP2021519021A priority patent/JP7516361B2/ja
Publication of WO2020229914A1 publication Critical patent/WO2020229914A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/70—Chemical treatments

Definitions

  • One aspect of the present invention relates to transistors, semiconductor devices, and electronic devices. Further, one aspect of the present invention relates to a method for manufacturing a semiconductor device. Further, one aspect of the present invention relates to a semiconductor wafer and a module.
  • the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic unit, and a storage device are one aspect of a semiconductor device.
  • a display device liquid crystal display device, light emission display device, etc.
  • projection device lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, image pickup device, electronic device, etc. may be said to have a semiconductor device.
  • One aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Also, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).
  • transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • Non-Patent Document 1 In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystal nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).
  • Non-Patent Document 1 and Non-Patent Document 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
  • One aspect of the present invention is to provide a semiconductor device having little variation in transistor characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device having good reliability. Alternatively, one aspect of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, one aspect of the present invention is to provide a semiconductor device having a large on-current. Alternatively, one aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration. Alternatively, one aspect of the present invention is to provide a semiconductor device having low power consumption.
  • One aspect of the present invention is a first insulator, a first oxide on a first insulator, a second oxide on a first oxide, and a second on a second oxide.
  • the oxide of 3 the fourth oxide, the first conductor on the third oxide, the second conductor on the fourth oxide, and the second on the first conductor.
  • the sixth oxide on the fifth oxide, the fourth insulator on the sixth oxide, the third conductor on the fourth insulator, and the first insulator to It has a fifth insulator on a third insulator
  • the fifth oxide has a region in contact with the second to fourth oxides and the first insulator.
  • the sixth oxide has a region in contact with the fifth oxide, the first conductor, and the second conductor
  • the fourth insulator is the sixth oxide, the third conductor.
  • the first oxide to the sixth oxide have In, the element M (M is Al, Ga, Y, or Sn), and Zn, respectively, and the first oxide,
  • the third oxide, the fourth oxide, and the sixth oxide have a region in which the concentration of the element M is higher than that of the second oxide, and the first oxide, the third oxide, and the like.
  • the fourth oxide and the sixth oxide preferably have a region in which the concentration of the element M is higher than that of the fifth oxide.
  • the second insulator, the third insulator, and the fifth insulator each contain either aluminum or hafnium.
  • a first insulator is formed, and a first oxide film, a second oxide film, and a third oxide film are formed on the first insulator in this order.
  • the first heat treatment is performed, and the first conductive film, the first insulating film, and the second conductive film are formed on the third oxide film in this order, and the first oxide film and the second oxide film are formed.
  • a third oxide film, a first conductive film, a first insulating film, and a second conductive film are processed into an island shape to form a first oxide, a second oxide, and a first oxidation.
  • a material layer, a first conductive layer, a first insulating layer, and a second conductive layer are formed, the second conductive layer is removed, and the first insulator, the first oxide, and the second oxide are formed.
  • a fifth insulator is formed on the first oxide layer, the first conductive layer, and the first insulating layer, and a sixth insulator is formed on the fifth insulator.
  • An opening reaching the second oxide is formed in the first oxide layer, the first conductive layer, the first insulating layer, the fifth insulator, and the sixth insulator, and by forming the opening.
  • a third oxide and a fourth oxide are formed from the first oxide layer, a first conductor and a second conductor are formed from the first conductive layer, and the first A seventh insulator and an eighth insulator are formed from the insulating layer, a second heat treatment is performed, and a fourth oxide film is formed on the sixth insulator and in the opening to form a fourth oxide film.
  • a fifth oxide film is formed on the oxide film of 4, and a fourth oxide film is formed on the side surface of the fifth insulator to the eighth insulator in the opening by a dry etching method. And the fifth oxide film is removed, the fourth and fifth oxide films on the sixth insulator are removed, leaving the fourth and fifth oxide films at the bottom of the opening.
  • a fifth oxide and a sixth oxide are formed, a second insulating film is formed on the sixth oxide and the sixth insulator, and the second insulating film is formed on the second insulating film.
  • a third conductive film is formed on the surface, and the third conductive film and the second insulating film are polished until they reach the sixth insulator by using the CMP method. This is a method for manufacturing a semiconductor device that forms an insulator and a third conductor.
  • the dry etching method is preferably performed at a pressure of 66.5 Pa or more.
  • one aspect of the present invention it is possible to provide a semiconductor device having little variation in transistor characteristics.
  • one aspect of the present invention can provide a semiconductor device with good reliability.
  • one aspect of the present invention can provide a semiconductor device having good electrical characteristics.
  • one aspect of the present invention can provide a semiconductor device having a large on-current.
  • one aspect of the present invention can provide a semiconductor device capable of miniaturization or high integration.
  • one aspect of the present invention can provide a low power consumption semiconductor device.
  • FIG. 1A is a top view of a semiconductor device according to an aspect of the present invention.
  • 1B to 1D are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • FIG. 2A is a diagram illustrating classification of the crystal structure of IGZO.
  • FIG. 2B is a diagram illustrating an XRD spectrum of a CAAC-IGZO film.
  • FIG. 2C is a diagram illustrating a microelectron diffraction pattern of a CAAC-IGZO film.
  • FIG. 3A is a top view of a semiconductor device according to an aspect of the present invention.
  • 3B to 3D are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • FIG. 4A is a top view of a semiconductor device according to an aspect of the present invention.
  • 4B to 4D are cross-sectional views of a semiconductor device according to an aspect of the present invention.
  • FIG. 5A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 5B to 5D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 6A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 6B to 6D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 7A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 7B to 7D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 8A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 8B to 8D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 9A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 9B to 9D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 10A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 10B to 10D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 11A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 11B to 11D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 12A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 12B to 12D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 13A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 13B to 13D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 14A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 14B to 14D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 15A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 15B to 15D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 16A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 16B to 16D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 17A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 17B to 17D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 18A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 18B to 18D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 19A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 19B to 19D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 20A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 20B to 20D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 21A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 21B to 21D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • 22A and 22B are cross-sectional views of the semiconductor device according to one aspect of the present invention.
  • FIG. 20A is a top view showing a method for manufacturing a semiconductor device according to an aspect of the present invention.
  • 20B to 20D are cross-sectional views showing a method of manufacturing a semiconductor device according to an aspect of the present invention.
  • FIG. 21A is a top
  • FIG. 23 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
  • FIG. 24 is a cross-sectional view showing the configuration of the storage device according to one aspect of the present invention.
  • FIG. 25 is a cross-sectional view of the semiconductor device according to one aspect of the present invention.
  • 26A and 26B are cross-sectional views of the semiconductor device according to one aspect of the present invention.
  • FIG. 27 is a cross-sectional view of the semiconductor device according to one aspect of the present invention.
  • FIG. 28 is a cross-sectional view of the semiconductor device according to one aspect of the present invention.
  • FIG. 29 is a top view illustrating an apparatus for manufacturing a semiconductor device according to one aspect of the present invention.
  • 30A and 30B are block diagrams showing a configuration example of a storage device according to an aspect of the present invention.
  • 31A to 31H are circuit diagrams showing a configuration example of a storage device according to one aspect of the present invention.
  • FIG. 32 is a diagram showing various storage devices for each layer.
  • 33A and 33B are schematic views of a semiconductor device according to one aspect of the present invention.
  • 34A and 34B are diagrams illustrating an example of an electronic component.
  • 35A to 35E are schematic views of a storage device according to an aspect of the present invention.
  • 36A to 36H are views showing an electronic device according to an aspect of the present invention.
  • the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may not be reflected in the figure for the sake of easy understanding. Further, in the drawings, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular sign may be added.
  • a top view also referred to as a "plan view”
  • a perspective view the description of some components may be omitted.
  • some hidden lines may be omitted.
  • the ordinal numbers attached as the first, second, etc. are used for convenience, and do not indicate the process order or the stacking order. Therefore, for example, the "first” can be appropriately replaced with the “second” or “third” for explanation.
  • the ordinal numbers described in the present specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is disclosed in the figure or text.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. It also has a region (hereinafter, also referred to as a channel forming region) in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode). A current can flow between the source and the drain through the channel formation region.
  • the channel formation region means a region in which a current mainly flows.
  • source and drain functions may be interchanged when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in the present specification and the like, the terms source and drain may be used interchangeably.
  • the channel length is, for example, the source in the top view of the transistor, the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the channel formation region.
  • the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width is, for example, the channel length direction in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other in the top view of the transistor, or the channel formation region. Refers to the length of the channel formation region in the vertical direction with reference to. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the channel formation region.
  • the channel width in the region where the channel is actually formed (hereinafter, also referred to as “effective channel width”) and the channel width shown in the top view of the transistor. (Hereinafter, also referred to as “apparent channel width”) and may be different.
  • the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible.
  • the proportion of the channel forming region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.
  • channel width may refer to the apparent channel width.
  • channel width may refer to an effective channel width.
  • the channel length, channel width, effective channel width, apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • the semiconductor impurities are, for example, other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example, the defect level density of the semiconductor may increase or the crystallinity may decrease.
  • the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors.
  • transition metals other than the main component such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water may also function as an impurity.
  • the oxide semiconductor to an oxygen vacancy V O: also referred to as oxygen vacancy
  • silicon oxide nitriding has a higher oxygen content than nitrogen as its composition. Further, silicon nitride has a higher nitrogen content than oxygen in its composition.
  • the term “insulator” can be paraphrased as an insulating film or an insulating layer.
  • the term “conductor” can be rephrased as a conductive film or a conductive layer.
  • semiconductor can be paraphrased as a semiconductor film or a semiconductor layer.
  • parallel means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included.
  • approximately parallel means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • approximately vertical means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when it is described as an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • normally off means that when a potential is not applied to the gate or a ground potential is applied to the gate, the drain current per 1 ⁇ m of the channel width flowing through the transistor is 1 ⁇ 10 ⁇ at room temperature. It means that it is 20 A or less, 1 ⁇ 10 -18 A or less at 85 ° C, or 1 ⁇ 10 -16 A or less at 125 ° C.
  • FIG. 1A to 1D are a top view and a cross-sectional view of a semiconductor device having a transistor 200.
  • FIG. 1A is a top view of the semiconductor device.
  • 1B to 1D are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • FIG. 1C is a cross-sectional view of the portion shown by the alternate long and short dash line of A3-A4 in FIG.
  • FIG. 1A is also a cross-sectional view of the transistor 200 in the channel width direction.
  • FIG. 1D is a cross-sectional view of the portion shown by the alternate long and short dash line in FIG. 1A.
  • FIG. 1A In the top view of FIG. 1A, some elements are omitted for the purpose of clarifying the figure.
  • the semiconductor device of one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, and an insulator 280 on the transistor 200. It has an insulator 282 on an insulator 280 and an insulator 283 on an insulator 282.
  • the insulator 212, the insulator 214, the insulator 280, the insulator 282, and the insulator 283 function as an interlayer film.
  • conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the conductor 242 (conductor 242a and conductor 242b) of the transistor 200 and functions as a plug.
  • An insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug.
  • a conductor 246 (conductor 246a and a conductor 246b) that is electrically connected to the conductor 240 and functions as wiring is provided.
  • an insulator 286 is provided on the conductor 246 and the insulator 283.
  • the insulator 241a is provided in contact with the inner wall of the opening of the insulator 280, the insulator 282, and the insulator 283, and the first conductor of the conductor 240a is provided in contact with the side surface of the insulator 241a, and further inside.
  • a second conductor of the conductor 240a is provided.
  • the insulator 241b is provided in contact with the inner wall of the opening of the insulator 280, the insulator 282, and the insulator 283, and the first conductor of the conductor 240b is provided in contact with the side surface of the insulator 241b.
  • a second conductor of the conductor 240b is provided inside.
  • the opening also includes, for example, a groove and a slit.
  • the region where the opening is formed may be referred to as an opening.
  • the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 283 in the region overlapping the conductor 246 can be made about the same.
  • the transistor 200 shows a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are laminated, but the present invention is not limited to this.
  • the conductor 240 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
  • the transistor 200 is an insulator 216 on the insulator 214 and a conductor 205 arranged so as to be embedded in the insulator 214 or a part of the insulator 214 and the insulator 216.
  • Conductor 260 (conductor 260a and conductor 260b) that overlaps a part of oxide 230c, a part of insulator 224, side surface of oxide 230a, side surface of oxide 230b, side surface of oxide 243a, conductor It has a side surface of 242a, a side surface of an insulator 271a, an upper surface of an insulator 271a, a side surface of an insulator 271b, and an insulator 272 in contact with a side surface of a conductor 242b.
  • the oxide 230c is in contact with the side surface of the oxide 243a, the side surface of the oxide 243b, a part of the upper surface of the oxide 230b, a part of the insulator 280, and a part of the upper surface of the insulator 224, respectively.
  • the oxide 230d is in contact with the side surface of the conductor 242a, the side surface of the conductor 242b, and the upper surface of the oxide 230c, respectively.
  • the upper surface of the conductor 260 is arranged so as to substantially coincide with the upper surface of the insulator 250.
  • the insulator 282 is in contact with the upper surfaces of the conductor 260, the insulator 250, and the insulator 280, respectively.
  • the insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.
  • the insulator 280, the insulator 272, and the insulator 271 are provided with an opening reaching the oxide 230b.
  • Oxide 230c, oxide 230d, insulator 250, and conductor 260 are arranged in the opening.
  • the insulator 250 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.
  • the oxide 230c has a region in contact with the oxide 230b and a region overlapping the bottom surface of the conductor 260 via the oxide 230d and the insulator 250.
  • the oxide 230 is arranged on the oxide 230a arranged on the insulator 224, the oxide 230b arranged on the oxide 230a, and the oxide 230b, and at least a part of the oxide 230 is formed on the oxide 230b. It is preferable to have an oxide 230c in contact with the oxide 230c and an oxide 230d arranged on the oxide 230c.
  • the oxide 230a under the oxide 230b it is possible to suppress the diffusion of impurities into the oxide 230b from the structure formed below the oxide 230a.
  • the oxide 230d on the oxide 230c it is possible to suppress the diffusion of impurities into the oxide 230c from the structure formed above the oxide 230d.
  • the transistor 200 shows a configuration in which the oxide 230 is laminated with four layers of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d, but the present invention is not limited to this. ..
  • a laminated structure of five or more layers may be provided, or each of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d may have a laminated structure.
  • the conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode.
  • the insulator 250 functions as a first gate insulator, and the insulator 224 functions as a second gate insulator.
  • the conductor 242a functions as one of the source and the drain, and the conductor 242b functions as the other of the source and the drain. Further, at least a part of the region of the oxide 230 overlapping with the conductor 260 functions as a channel forming region.
  • a metal oxide that functions as a semiconductor is added to an oxide 230 (oxide 230a, oxide 230b, oxide 230c, and oxide 230d) containing a channel forming region. It is preferable to use it.
  • the metal oxide that functions as a semiconductor it is preferable to use a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • an In-M-Zn oxide having indium, element M and zinc (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium). , Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used. Further, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 230b or the oxide 230c is higher than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a or the oxide 230d. Larger is preferred.
  • the oxide 230a under the oxide 230b or the oxide 230c in this way, impurities and oxygen with respect to the oxide 230b or the oxide 230c from the structure formed below the oxide 230a. Diffusion can be suppressed.
  • the oxide 230d on the oxide 230b or the oxide 230c impurities can be diffused into the oxide 230b or the oxide 230c from the structure formed above the oxide 230d. It can be suppressed. Further, by arranging the oxide 230d on the oxide 230b or the oxide 230c, the upward diffusion of oxygen from the oxide 230b or the oxide 230c can be suppressed.
  • the oxides 230a to 230d have a common element (main component) other than oxygen, defects at the respective interfaces of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d The level density can be reduced.
  • the main path of the carrier is the interface between the oxide 230b, the oxide 230c or its vicinity, for example, the oxide 230b and the oxide 230c. Since the defect level density at the interface between the oxide 230b and the oxide 230c can be lowered, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.
  • the oxide 230b and the oxide 230c each have crystallinity.
  • CAAC-OS c-axis aligned crystalline semiconductor semiconductor
  • the oxide 230d may be configured to have crystallinity.
  • CAAC-OS has a c-axis orientation and has a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction.
  • the strain refers to a region in which a plurality of nanocrystals are connected, in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another lattice arrangement is aligned.
  • Nanocrystals are basically hexagons, but they are not limited to regular hexagons and may be non-regular hexagons. In addition, in distortion, it may have a lattice arrangement such as a pentagon and a heptagon. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as grain boundary) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Because.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is a layered crystal in which a layer having indium and oxygen (hereinafter, In layer) and a layer having elements M, zinc, and oxygen (hereinafter, (M, Zn) layer) are laminated. It tends to have a structure (also called a layered structure). Indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced with indium, it can be expressed as the (In, M, Zn) layer. Further, when the indium of the In layer is replaced with the element M, it can be expressed as the (In, M) layer.
  • CAAC-OS is a metal oxide having a highly crystalline and dense structure and having few impurities and defects (oxygen-deficient Vo, etc.).
  • the CAAC-OS is subjected to heat treatment at a temperature at which the metal oxide does not polycrystallize (for example, 400 ° C. or higher and 600 ° C. or lower), whereby CAAC-OS has a more crystalline and dense structure. Can be.
  • a temperature at which the metal oxide does not polycrystallize for example, 400 ° C. or higher and 600 ° C. or lower
  • the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide having CAAC-OS is resistant to heat and has high reliability.
  • the oxide 230c is arranged so as to cover the inner wall (side surface and bottom surface) of the groove portion. Further, the film thickness of the oxide 230c is preferably about the same as the depth of the groove.
  • the side surface of the opening in which the conductor 260 and the like are embedded is substantially perpendicular to the surface to be formed of the oxide 230b, including the groove portion of the oxide 230b. It is not limited to this.
  • the bottom of the opening may have a gently curved surface and may have a U-shape.
  • the side surface of the opening may be inclined with respect to the surface to be formed of the oxide 230b.
  • a curved surface may be provided between the side surface of the oxide 230b and the upper surface of the oxide 230b in a cross-sectional view of the transistor 200 in the channel width direction. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter, also referred to as a round shape).
  • the radius of curvature on the curved surface is preferably larger than 0 nm, smaller than the film thickness of the oxide 230b in the region overlapping the conductor 242, or smaller than half the length of the region having no curved surface.
  • the radius of curvature on the curved surface is larger than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less.
  • the oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions.
  • the atomic number ratio of the element M to the main component metal element is the ratio of the element M to the main component metal element in the metal oxide used in the oxide 230b. It is preferably larger than the atomic number ratio.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 230a.
  • the ratio of the number of indium atoms to the main component metal element in the oxide 230c is the number of indium atoms to the main component metal element in the oxide 230b. It is preferably larger than the ratio.
  • the atomic number ratio of indium to the metal element as the main component is made larger than the atomic number ratio of indium to the metal element as the main component in the oxide 230b to carry the oxide 230c. Can be the main route of.
  • the lower end of the conduction band of the oxide 230c is separated from the vacuum level from the lower end of the conduction band of the oxide 230a and the oxide 230b.
  • the electron affinity of the oxide 230c is preferably larger than the electron affinity of the oxides 230a and 230b.
  • the main path of the carrier is the oxide 230c.
  • M: Zn 4: 2: 3 [atomic number ratio] or a composition in the vicinity thereof
  • M: Zn 5: 1: 3 [atomic number ratio] or its vicinity.
  • Vsh shift voltage measured in a + GBT (Gate Bias Temperature) stress test of the transistor.
  • ⁇ Vsh may shift in the negative direction with the passage of time. Further, ⁇ Vsh may show a behavior that fluctuates in both the negative direction and the positive direction instead of fluctuating in the negative direction. In addition, in this specification and the like, the said behavior may be referred to as a jagged behavior of ⁇ Vsh in the + GBT stress test.
  • ⁇ Vsh By using a metal oxide containing no element M as a main component or a metal oxide having a small ratio of element M as the oxide 230c, for example, ⁇ Vsh can be reduced, the jagged behavior of ⁇ Vsh can be suppressed, and the reliability of the transistor can be suppressed. It is possible to improve the sex.
  • the oxide 230b and the oxide 230c are preferably oxides having crystallinity such as CAAC-OS.
  • Crystalline oxides such as CAAC-OS have a dense structure with high crystallinity with few impurities and defects (oxygen deficiency, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. As a result, oxygen can be reduced from being extracted from the oxide 230b even if heat treatment is performed, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.
  • CAAC-OS As the oxide 230c, and it is preferable that the c-axis of the crystal of the oxide 230c is oriented substantially perpendicular to the surface to be formed or the upper surface of the oxide 230c.
  • CAAC-OS has the property of easily moving oxygen in the direction perpendicular to the c-axis. Therefore, the oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.
  • the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all the metal elements.
  • the oxide 230c In-M-Zn oxide, In-Zn oxide, or indium oxide is used as the oxide 230c, and In-M-Zn oxide, M-Zn oxide, or element M is used as the oxide 230d. It is advisable to use the oxide of. As a result, the defect level density at the interface between the oxide 230c and the oxide 230d can be lowered.
  • the lower end of the conduction band of the oxide 230d is closer to the vacuum level than the lower end of the conduction band of the oxide 230c.
  • the electron affinity of the oxide 230d is preferably smaller than the electron affinity of the oxide 230c.
  • the oxide 230d it is preferable to use a metal oxide that can be used for the oxide 230a or the oxide 230b.
  • the main path of the carrier is the oxide 230c.
  • the metal oxide having the composition of the above or the oxide of the element M may be used.
  • the oxide 230d is more preferably a metal oxide that suppresses the diffusion or permeation of oxygen than the oxide 230c.
  • the atomic number ratio of In to the metal element as the main component is smaller than the atomic number ratio of In to the metal element as the main component in the metal oxide used for the oxide 230c.
  • the insulator 250 functions as a gate insulator, if In is mixed in the insulator 250 or the like, the characteristics of the transistor become poor. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.
  • the lower end of the conduction band changes gently.
  • the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d is continuously changed or continuously bonded.
  • the defect quasi of the mixed layer formed at the interface between the oxide 230a and the oxide 230b, the interface between the oxide 230b and the oxide 230c, and the interface between the oxide 230c and the oxide 230d It is advisable to lower the position density.
  • the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c, and the oxide 230c and the oxide 230d have a common element other than oxygen as a main component, so that the defect level density is low.
  • a mixed layer can be formed.
  • the oxide 230b is an In-M-Zn oxide
  • the oxides 230a, 230c, and 230d are In-M-Zn oxide, M-Zn oxide, and element M oxide. In—Zn oxide, indium oxide and the like may be used.
  • a metal oxide having a composition in the vicinity thereof may be used.
  • a metal oxide having a composition may be used.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic number ratio.
  • gallium it is preferable to use gallium as the element M.
  • the above atomic number ratio is not limited to the atomic number ratio of the formed metal oxide, but is the atomic number ratio of the sputtering target used for forming the metal oxide. It may be.
  • the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d As described above, the interface between the oxide 230a and the oxide 230b, the interface between the oxide 230b and the oxide 230c, and the oxide The defect level density at the interface between the 230c and the oxide 230d can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.
  • Insulator 212, insulator 214, insulator 271, insulator 272, insulator 282, insulator 283, and insulator 286 have impurities such as water and hydrogen from the substrate side or from above the transistor 200. It preferably functions as a barrier insulating film that suppresses diffusion to 200. Therefore, the insulator 212, the insulator 214, the insulator 271, the insulator 272, the insulator 282, the insulator 283, and the insulator 286 are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules.
  • an insulating material N 2 O, NO, NO 2, etc.
  • an insulating material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property is defined as a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability).
  • the corresponding substance has a function of capturing and fixing (also called gettering).
  • the insulator 212 it is preferable to use silicon nitride or the like as the insulator 212, the insulator 283, and the insulator 286, and to use aluminum oxide or the like as the insulator 214, the insulator 271, the insulator 272, and the insulator 282.
  • impurities such as water and hydrogen from diffusing from the substrate side to the transistor 200 side via the insulator 212 and the insulator 214.
  • the transistor 200 is made of an insulator 212, an insulator 214, an insulator 271, an insulator 272, an insulator 282, and an insulator 283 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen. It is preferable to have a structure that surrounds it.
  • the resistivity of the insulator 212, the insulator 283, and the insulator 286 may be preferable to reduce the resistivity of the insulator 212, the insulator 283, and the insulator 286.
  • the insulator 212, the insulator 283, and the insulator 286 are used in the process of manufacturing the semiconductor device using plasma or the like.
  • the insulator 286 can mitigate the charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246.
  • the resistivity of the insulator 212, the insulator 283, and the insulator 286 is preferably 1 ⁇ 10 10 ⁇ cm or more and 1 ⁇ 10 15 ⁇ cm or less.
  • the insulator 216 and the insulator 280 have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • silicon oxide, silicon oxide nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, and the like are used. It may be used as appropriate.
  • the insulator 212, the insulator 214, and the insulator 216 are formed by a sputtering method.
  • the insulator 212, the insulator 214, and the insulator 216 formed by the sputtering method are preferable because the hydrogen concentration in the film is low. Further, it is preferable that the insulator 212, the insulator 214, and the insulator 216 are continuously formed without being exposed to the atmospheric environment.
  • the film By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulator 212, the insulator 214, and the insulator 216, and the insulator 212 and the insulator 214 It is preferable because the interface and the vicinity of the interface of the above, and the interface and the vicinity of the interface between the insulator 214 and the insulator 216 can be kept clean. A description of an apparatus capable of continuously forming a film will be described later.
  • the oxide 230c and the oxide 230d are arranged only near the bottom of the insulator 280, the insulator 272, and the opening provided in the insulator 271. It has a structure.
  • the above configuration suppresses the occurrence of a current leak path between the transistor 200 and the transistor 200 adjacent to the transistor 200. be able to. Details will be described below.
  • the conductor 205 By applying a negative potential to the conductor 205 that functions as the second gate electrode, it may be possible to suppress the generation of parasitic channels in the oxide 230c and the oxide 230d.
  • the distance between the conductor 205 and the oxide 230c and the oxide 230d becomes relatively short.
  • the potential of the conductor 205 sufficiently reaches the entire oxide 230c and the oxide 230d. Therefore, the generation of parasitic channels can be suppressed in the oxide 230c and the oxide 230d as a whole. As a result, it is possible to suppress the occurrence of a current leak path between the transistor 200 and the transistor 200 adjacent to the transistor 200.
  • the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current.
  • the conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. Further, it is preferable that the conductor 205 is embedded in the insulator 214 or a part of the insulator 214 and the insulator 216.
  • the conductor 205 may be provided larger than the size of the region of the oxide 230a and the oxide 230b that does not overlap with the conductor 242a and the conductor 242b.
  • the conductor 205 is also stretched in a region outside the end portion of the oxide 230a and the oxide 230b intersecting the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 are superposed on each other via an insulator on the outside of the side surface of the oxide 230a and the oxide 230b in the channel width direction.
  • the channel forming region of the oxide 230 is electrically surrounded by the electric field of the conductor 260 that functions as the first gate electrode and the electric field of the conductor 205 that functions as the second gate electrode. Can be done.
  • the structure of the transistor that electrically surrounds the channel forming region by the electric fields of the first gate and the second gate is referred to as a Surrounded channel (S-channel) structure.
  • the transistor having the S-channel structure represents the structure of the transistor that electrically surrounds the channel formation region by the electric fields of one and the other of the pair of gate electrodes.
  • the S-channel structure disclosed in the present specification and the like is different from the Fin type structure and the planar type structure.
  • the conductor 205 is stretched to function as wiring.
  • the present invention is not limited to this, and a conductor that functions as wiring may be provided under the conductor 205. Further, it is not always necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.
  • the conductor 205 shows a configuration in which the conductor 205a and the conductor 205b are laminated, but the present invention is not limited to this.
  • the conductor 205 may be provided as a single layer or a laminated structure having three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
  • the conductor 205a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a conductive material having. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.).
  • the conductor 205a By using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used. Therefore, as the conductor 205a, the conductive material may be a single layer or a laminated material.
  • the conductor 205a may be a laminate of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.
  • the conductor 205a may be formed by using the ionization sputtering method described later.
  • the conductor 205b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 205b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the insulator 222 and the insulator 224 function as a gate insulator.
  • the insulator 222 has a function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.). Further, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.
  • the insulator 222 it is preferable to use an insulator containing oxides of one or both of aluminum and hafnium.
  • the insulator it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 222 releases oxygen from the oxide 230 to the substrate side and diffuses impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Functions as a layer that suppresses.
  • the insulator 222 it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress the generation of oxygen deficiency in the oxide 230. Further, it is possible to suppress the conductor 205 from reacting with the oxygen contained in the insulator 224 and the oxide 230.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to the insulator.
  • these insulators may be nitrided.
  • the insulator 222 may be used by laminating silicon oxide, silicon oxide or silicon nitride on these insulators.
  • the insulator 222 includes, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTIO 3 ), (Ba, Sr) TiO 3 (BST) and the like. Insulators containing so-called high-k materials may be used in single layers or in layers. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for an insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • the insulator 224 in contact with the oxide 230 desorbs oxygen by heating.
  • the insulator 224 silicon oxide, silicon oxide nitride, or the like may be appropriately used.
  • an oxide material in which a part of oxygen is desorbed by heating in other words, an insulator material having an excess oxygen region.
  • Oxides that desorb oxygen by heating are those in which the amount of desorbed oxygen molecules is 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1.0 ⁇ 10 19 molecules, as determined by TDS (Thermal Desortion Spectropy) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 230 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment.
  • heat treatment microwave treatment, or RF treatment.
  • water or hydrogen in the oxide 230 can be removed.
  • a reaction bond defects that contains hydrogen to an oxygen vacancy (V O H) is cut occurs, a reaction occurs that when other words "V O H ⁇ V O + H", dehydrogenation Can be transformed into.
  • V O H oxygen vacancy
  • the hydrogen generated as oxygen combines with H 2 O, it may be removed from the oxide 230 or oxide 230 near the insulator.
  • a part of hydrogen may be diffused or captured (also referred to as gettering) in the conductor 242.
  • the microwave processing for example, it is preferable to use an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side.
  • an apparatus having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is recommended to use less than%.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 600 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 230 to reduce oxygen deficiency ( VO ).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.
  • the insulator 222 and the insulator 224 may have a laminated structure of two or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • Oxide 243 (oxide 243a and oxide 243b) may be provided on the oxide 230b.
  • Oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation.
  • the oxide 243 having a function of suppressing the permeation of oxygen between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, electricity between the conductor 242 and the oxide 230b can be obtained. This is preferable because the resistance is reduced. With such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. If the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.
  • a metal oxide having an element M may be used.
  • the element M aluminum, gallium, yttrium, or tin may be used.
  • Oxide 243 preferably has a higher concentration of element M than oxide 230b.
  • gallium oxide may be used as the oxide 243.
  • a metal oxide such as In—M—Zn oxide may be used.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 230b.
  • the film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and further preferably 1 nm or more and 2 nm or less. Further, the oxide 243 is preferably crystalline. When the oxide 243 has crystallinity, the release of oxygen in the oxide 230 can be suitably suppressed. For example, as the oxide 243, if it has a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 230 may be suppressed.
  • the oxide film to be the oxide 230a, the oxide film to be the oxide 230b, and the oxide film to be the oxide 243 are continuously formed without being exposed to the atmospheric environment.
  • the film without opening it to the atmosphere it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film that becomes oxide 230a, the oxide film that becomes oxide 230b, and the oxide film that becomes oxide 243.
  • the conductor 242a is provided on the oxide 243a, and the conductor 242b is provided on the oxide 243b.
  • the conductor 242a and the conductor 242b function as a source electrode or a drain electrode of the transistor 200, respectively.
  • Examples of the conductors 242 include nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, and nitrides containing tantalum and aluminum. It is preferable to use a nitride containing titanium and aluminum. In one aspect of the invention, tantalum-containing nitrides are particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lantern and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxygen is absorbed.
  • the conductor 242 comes into contact with the oxide 230b or the oxide 230c, so that oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242, and the conductor 242 becomes the conductor 242. May oxidize. It is highly probable that the conductivity of the conductor 242 will decrease due to the oxidation of the conductor 242.
  • the diffusion of oxygen in the oxide 230b or the oxide 230c to the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230b or the oxide 230c.
  • oxygen in the oxide 230b or the oxide 230c diffuses into the conductor 242a and the conductor 242b, so that between the conductor 242a and the oxide 230b and between the conductor 242b and the oxide 230b, Alternatively, a layer may be formed between the conductor 242a and the oxide 230c, and between the conductor 242b and the oxide 230c. Since the layer contains more oxygen than the conductor 242a or the conductor 242b, it is presumed that the layer has insulating properties.
  • the three-layer structure of the conductor 242a or the conductor 242b, the layer, and the oxide 230b or the oxide 230c can be regarded as a three-layer structure composed of a metal, an insulator, and a semiconductor
  • MIS Metal
  • It can be regarded as a -Insulator-Semiconductor) structure or a diode junction structure mainly composed of a MIS structure.
  • hydrogen contained in the oxide 230b, the oxide 230c, etc. may diffuse into the conductor 242a or the conductor 242b.
  • the hydrogen contained in the oxide 230b, the oxide 230c, etc. is easily diffused into the conductor 242a or the conductor 242b, and the diffused hydrogen. May combine with the nitrogen contained in the conductor 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b, the oxide 230c, and the like may be absorbed by the conductor 242a or the conductor 242b.
  • a curved surface between the side surface of the conductor 242 and the upper surface of the conductor 242. That is, the side edge and the top edge may be curved.
  • the curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at the end of the conductor 242.
  • the insulator 272 is provided so as to cover the side surfaces of the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271, and preferably functions as a barrier insulating film against oxygen at least. Therefore, it is preferable that the insulator 272 has a function of suppressing the diffusion of oxygen. For example, the insulator 272 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator 272, for example, it is preferable to form an insulator containing oxides of one or both of aluminum and hafnium.
  • the insulator 272 is preferably formed by forming aluminum oxide or hafnium oxide in an atmosphere containing oxygen by a bias sputtering method.
  • the bias sputtering method is a method of sputtering while applying RF power to a substrate.
  • a bias potential a negative potential
  • + ions in the plasma are accelerated by this bias potential and injected into the substrate.
  • the bias potential can be controlled by the magnitude of the RF power applied to the substrate.
  • oxygen can be injected into the insulator 224 by forming aluminum oxide or hafnium oxide in an atmosphere containing oxygen by the bias sputtering method. Further, since the amount of oxygen injected into the insulator 224 can be controlled by adjusting the RF power applied to the substrate, the amount of oxygen injected into the insulator 224 can be optimized.
  • the insulator 271 is provided in contact with the upper surface of the conductor 242, and like the insulator 272, it preferably functions as a barrier insulating film against at least oxygen. Therefore, it is preferable that the insulator 271 also has a function of suppressing the diffusion of oxygen. For example, the insulator 271 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280.
  • the insulator 271 for example, an insulator containing oxides of one or both of aluminum and hafnium may be formed. Further, as the insulator 271, for example, an insulator containing silicon nitride may be used.
  • the oxide 230a, the oxide 230b, the oxide 243, and the conductor 242 can be separated from the insulator 280. Therefore, it is possible to suppress the direct diffusion of oxygen from the insulator 280 into the oxide 230a, the oxide 230b, the oxide 243, and the conductor 242. This can prevent excess oxygen from being supplied to the source and drain regions of the oxide 230 and reducing the carrier density in the source and drain regions. In addition, it is possible to prevent the conductor 242 from being excessively oxidized to increase the resistivity and reduce the on-current.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably arranged in contact with the upper surface of the oxide 230d.
  • the insulator 250 includes silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and the like. Can be used. In particular, silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
  • the insulator 250 is preferably formed by using an insulator that releases oxygen by heating.
  • an insulator that releases oxygen by heating As an insulator 250 in contact with the upper surface of the oxide 230d, oxygen is effectively applied to the channel forming region of the oxide 230b via the oxide 230d and the oxide 230c. Can be supplied to reduce oxygen deficiency in the channel-forming region of oxide 230b. Therefore, it is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.
  • the concentration of impurities such as water and hydrogen in the insulator 250 is reduced.
  • the film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.
  • the insulator 250 is shown as a single layer in FIGS. 1B and 1C, it may have a laminated structure of two or more layers.
  • the lower layer of the insulator 250 forms an insulator in which oxygen is released by heating
  • the upper layer of the insulator 250 is an insulator having a function of suppressing the diffusion of oxygen. It is preferable to form a body. With such a configuration, oxygen contained in the lower layer of the insulator 250 can be suppressed from diffusing into the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
  • the lower layer of the insulator 250 can be provided by using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be provided by using the same material as the insulator 222.
  • an insulating material which is a high-k material having a high relative permittivity may be used for the upper layer of the insulator 250.
  • the gate insulator By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator.
  • the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator can be thinned.
  • a thing or a metal oxide that can be used as the oxide 230 can be used.
  • the lower layer of the insulator 250 may form an insulator having a function of suppressing the diffusion of oxygen.
  • oxygen contained in the insulator 280 can be suppressed from diffusing into the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
  • the lower layer of the insulator 250 forms an insulator having a function of suppressing the permeation of impurities such as water and hydrogen. With such a configuration, impurities such as water and hydrogen contained in the insulator 280 can be suppressed from diffusing into the oxide 230.
  • the lower layer of the insulator 250 can be provided using the same material as the insulator 222.
  • an insulating material which is a high-k material having a high relative permittivity may be used for the lower layer of the insulator 250.
  • the gate insulator By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator.
  • the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator can be thinned.
  • a thing or a metal oxide that can be used as the oxide 230 can be used.
  • a metal oxide may be provided between the insulator 250 and the conductor 260.
  • the metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260.
  • the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230.
  • the oxidation of the conductor 260 by oxygen of the insulator 250 can be suppressed.
  • the metal oxide has a function as a part of the first gate electrode.
  • a metal oxide that can be used as the oxide 230 can be used as the metal oxide.
  • the conductor 260a by forming the conductor 260a into a film by a sputtering method, the electric resistance value of the metal oxide can be lowered to form a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the metal oxide By having the metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Further, by keeping the distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, the leakage current between the conductor 260 and the oxide 230 is maintained. Can be suppressed. Further, by providing the laminated structure of the insulator 250 and the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be determined. It can be easily adjusted as appropriate.
  • the conductor 260 functions as the first gate electrode of the transistor 200.
  • the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a.
  • the conductor 260a is preferably arranged so as to wrap the bottom surface and the side surface of the conductor 260b.
  • the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250.
  • the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIGS. 1B and 1C, it may be a single-layer structure or a laminated structure of three or more layers.
  • the conductor 260a it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • impurities such as hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule and copper atom.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductor 260 also functions as wiring, it is preferable to use a conductor having high conductivity.
  • a conductor having high conductivity for example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
  • the conductor 260 is self-consistently formed so as to fill the opening formed in the insulator 280 or the like.
  • the conductor 260 can be reliably arranged in the region between the conductor 242a and the conductor 242b without aligning the conductor 260.
  • the height is preferably lower than the height of the bottom surface of the oxide 230b.
  • the conductor 260 which functions as a gate electrode, covers the side surface and the upper surface of the channel forming region of the oxide 230b via an insulator 250 or the like, so that the electric field of the conductor 260 is covered with the channel forming region of the oxide 230b. It becomes easier to act on the whole. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.
  • the difference is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.
  • the insulator 280 is provided on the insulator 224, the oxide 230, the conductor 242, the insulator 271, and the insulator 272. Further, the upper surface of the insulator 280 may be flattened.
  • the insulator 280 that functions as an interlayer film preferably has a low dielectric constant.
  • a material having a low dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance generated between the wirings.
  • the insulator 280 is provided by using the same material as the insulator 216, for example.
  • silicon oxide and silicon oxide nitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxide nitride, and silicon oxide having pores are preferable because a region containing oxygen desorbed by heating can be easily formed.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
  • the insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or an excess oxygen, and may be provided by using the same material as the insulator 216, for example.
  • the insulator 280 may have a structure in which the above materials are laminated.
  • the insulator is formed by a silicon oxide film formed by a sputtering method and a chemical vapor deposition (CVD) method laminated on the silicon oxide. It may be a laminated structure of filmed silicon oxide. Further, silicon nitride may be further laminated on top of it.
  • the insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the insulator 280 from above. Further, the insulator 282 or the insulator 283 preferably functions as a barrier insulating film that suppresses the permeation of oxygen.
  • an insulator such as aluminum oxide, silicon nitride, or silicon nitride may be used as the insulator 282, and silicon nitride having a high blocking property against hydrogen may be used as the insulator 283.
  • the conductor 240a and the conductor 240b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 240a and the conductor 240b may have a laminated structure.
  • the conductor 240a and the conductor 240b have a circular shape when viewed from above, but the present invention is not limited to this.
  • the conductor 240a and the conductor 240b may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.
  • the conductor in contact with the insulator 283, the insulator 282, the insulator 280, and the insulator 271 has a function of suppressing the permeation of impurities such as water and hydrogen.
  • a sex material For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated state. Further, it is possible to prevent impurities such as water and hydrogen contained in the layer above the insulator 283 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.
  • the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen as the lower layer.
  • a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen is preferably used.
  • impurities such as water or hydrogen diffused from the insulator 280 and the like can be further reduced from being mixed into the oxide 230 through the conductor 240.
  • the upper layer it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 280, impurities such as water and hydrogen contained in the insulator 280 and the like are prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. It can be suppressed.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.
  • the conductor 246 (conductor 246a and conductor 246b) which is in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b and functions as wiring may be arranged.
  • the conductor 246 it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • the insulator 286 is provided on the conductor 246 and on the insulator 283.
  • the conductor 246 and the side surface of the conductor 246 are in contact with the insulator 286, and the lower surface of the conductor 246 is in contact with the insulator 283. That is, the conductor 246 can be configured to be wrapped with the insulator 283 and the insulator 286. With such a configuration, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 246. Further, it is preferable because impurities such as water and hydrogen can be prevented from diffusing from the conductor 246 to the outside.
  • an insulator substrate for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), a resin substrate, and the like.
  • the semiconductor substrate include a semiconductor substrate made of silicon and germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • the conductor substrate includes a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate having a metal nitride a substrate having a metal oxide, and the like.
  • a substrate in which a conductor or a semiconductor is provided in an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • those substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistance elements, switch elements, light emitting elements, storage elements, and the like.
  • Insulator examples include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties.
  • the material may be selected according to the function of the insulator.
  • Examples of the insulator having a high specific dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, nitrides having aluminum and hafnium, oxides having silicon and hafnium, silicon and hafnium. There are nitrides having oxides, or nitrides having silicon and hafnium.
  • Examples of the insulator having a low relative permittivity include silicon oxide, silicon oxide nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or silicon oxide having pores. There is resin etc.
  • the electric characteristics of the transistor can be stabilized by surrounding the transistor using the metal oxide with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen.
  • the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators containing, lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen
  • Metal oxides such as tantalum oxide and metal nitrides such as aluminum nitride, silicon nitride and silicon nitride can be used.
  • the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating.
  • the oxygen deficiency of the oxide 230 can be compensated.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above-mentioned metal element as a component, an alloy in which the above-mentioned metal element is combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a plurality of conductive layers formed of the above materials may be laminated and used.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be formed in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • the conductor functioning as the gate electrode shall have a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Is preferable.
  • a conductive material containing oxygen may be provided on the channel forming region side.
  • a conductor that functions as a gate electrode it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed.
  • the above-mentioned conductive material containing a metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal Oxide As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor.
  • a metal oxide oxide semiconductor
  • the metal oxide applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like. ..
  • FIG. 2A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
  • IGZO metal oxides containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous (amorphous)”, “Crystalline (crystallinity)", and “Crystal (crystal)”.
  • Amorphous includes “completable amorphous”.
  • the "Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned crystal) (extracting single crystal crystal).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 2A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Evaluation) spectrum.
  • XRD X-ray diffraction
  • FIG. 2B the XRD spectrum obtained by GIXD (Glazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" is shown in FIG. 2B.
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 2B will be simply referred to as an XRD spectrum.
  • the thickness of the CAAC-IGZO film shown in FIG. 2B is 500 nm.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 2C.
  • FIG. 2C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron beam diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 2A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, the plurality of crystal regions having the c-axis oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned.
  • CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. In addition, Zn may be contained in the In layer.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a heptagon.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal atoms. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may decrease due to the mixing of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures in the manufacturing process (so-called thermal budget). Therefore, if CAAC-OS is used as the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method.
  • a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan.
  • electron beam diffraction also referred to as limited field electron diffraction
  • a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.
  • a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a structure in which a material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in a film (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are referred to as [In], "Ga”, and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film, and the second region is.
  • [Ga] is a region larger than [Ga] in the composition of the CAC-OS membrane, or, for example, in the first region, [In] is larger than [In] in the second region.
  • [Ga] is a region smaller than [Ga] in the second region. In the second region, [Ga] is larger than [Ga] in the first region, and [Ga] is [.
  • In] is a region smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS for the transistor, high on-current (Ion), high field effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on-current
  • ⁇ high field effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor according to one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, and more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more than 1 ⁇ 10 -9 cm -3 .
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel forming region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor are set to 2. ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxide.
  • a semiconductor material having a bandgap (a semiconductor material that is not a zero-gap semiconductor) may be used.
  • a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, a layered substance (also referred to as an atomic layer substance, a two-dimensional material, or the like) that functions as a semiconductor as a semiconductor material.
  • a layered substance also referred to as an atomic layer substance, a two-dimensional material, or the like
  • the layered substance is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • the layered material has high electrical conductivity in the unit layer, that is, high two-dimensional electrical conductivity.
  • a chalcogenide is a compound containing a chalcogen.
  • chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.
  • oxide 230 for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor.
  • Specific transition metal chalcogenides applicable as oxide 230 include molybdenum sulfide (typically MoS 2 ), molybdenum selenate (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ).
  • Tungsten sulfide typically WS 2
  • Tungsten disulfide typically WSe 2
  • Tungsten tellurium typically WTe 2
  • Hafnium sulfide typically HfS 2
  • Hafnium serene typically typically
  • Typical examples include HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenium (typically ZrSe 2 ).
  • FIG. 3A shows a top view of the semiconductor device.
  • FIG. 3B is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in FIG. 3A.
  • FIG. 3C is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in A3-A4 in FIG. 3A.
  • FIG. 3D is a cross-sectional view corresponding to the portion shown by the alternate long and short dash line in FIG. 3A.
  • some elements are omitted for the sake of clarity.
  • the same reference numerals are added to the structures having the same functions as the structures constituting the semiconductor devices shown in ⁇ Semiconductor device configuration example>.
  • the constituent material of the semiconductor device the material described in detail in ⁇ Semiconductor device configuration example> can be used.
  • the semiconductor device shown in FIGS. 3A to 3D is a modification of the semiconductor device shown in FIGS. 1A to 1D.
  • the semiconductor device shown in FIGS. 3A to 3D has a different shape of the insulator 283 from the semiconductor device shown in FIGS. 1A to 1D. It is also different from having an insulator 274.
  • the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 280, and the insulator 282 are patterned.
  • the insulator 283 has a structure that covers the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 280, and the insulator 282. That is, the insulator 283 is in contact with the upper surface and the side surface of the insulator 282 and the upper surface of the insulator 212.
  • the insulator 214, the insulator 216, the insulator 222, the insulator 224, the insulator 272, the insulator 280, and the insulator 282, which include the oxide 230 and the like, are formed by the insulator 283 and the insulator 212. , Isolated from the outside. In other words, the transistor 200 is arranged in a region sealed by the insulator 283 and the insulator 212.
  • the insulator 214 and the insulator 282 are formed by using a material having a function of capturing hydrogen and fixing hydrogen, and the insulator 212 and the insulator 283 have a function of suppressing diffusion to hydrogen and oxygen. It is preferably formed using a material.
  • aluminum oxide can be used as the insulator 214 and the insulator 282.
  • silicon nitride can be used as the insulator 212 and the insulator 283.
  • the insulator 212 and the insulator 283 are provided as a single layer is shown, but the present invention is not limited to this.
  • the insulator 212 and the insulator 283 may each be provided as a laminated structure having two or more layers.
  • the insulator 274 functions as an interlayer film.
  • the insulator 274 preferably has a lower dielectric constant than the insulator 214.
  • the insulator 274 can be provided, for example, by using the same material as the insulator 280.
  • an insulator with reduced hydrogen As the insulator 274, for example, an insulator may be formed by a sputtering method. The hydrogen concentration of the insulator formed by the sputtering method is preferable because it is lower than the hydrogen concentration of the insulator formed by the CVD method.
  • a in each figure shows the top view.
  • B in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line of A1-A2 shown in A in each figure, and is also a cross-sectional view in the channel length direction of the transistor 200.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the alternate long and short dash line in A3 to A4 in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200.
  • D in each figure is a cross-sectional view of a portion indicated by a alternate long and short dash line in A5-A6 in each figure. In A of each figure, some elements are omitted for the purpose of clarifying the figure.
  • a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate.
  • the film of the insulator 212 is formed by a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulse laser deposition (PLD: Pulsed Laser Deposition) method, an atomic layer deposition (ALD: atomic layer deposition), or the like. Can be done using.
  • the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. .. Further, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal organic CVD) method depending on the raw material gas used.
  • PECVD Plasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal organic CVD
  • the plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) and the like included in a semiconductor device may be charged up by receiving electric charges from plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased. Further, in the thermal CVD method, plasma damage does not occur during film formation, so that a film having few defects can be obtained.
  • a thermal ALD (Thermal ALD) method in which the reaction of the precursor and the reactor is performed only by thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactor, or the like can be used.
  • the ALD method utilizes the self-regulating properties of atoms and allows atoms to be deposited layer by layer, so ultra-thin film formation is possible, and film formation into structures with a high aspect ratio is possible. It has the effects of being able to form a film with few defects such as holes, being able to form a film with excellent coverage, and being able to form a film at a low temperature.
  • PEALD Pulsma Enhanced ALD
  • Some precursors used in the ALD method contain impurities such as carbon.
  • the film provided by the ALD method may contain a large amount of impurities such as carbon as compared with the film provided by other film forming methods.
  • the quantification of impurities can be performed by using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage.
  • the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas.
  • a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film.
  • silicon nitride is formed as the insulator 212 by a sputtering method.
  • the insulator 214 is formed on the insulator 212.
  • the film formation of the insulator 214 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is formed as the insulator 214 by a sputtering method.
  • the hydrogen concentration of the insulator 214 is preferably lower than the hydrogen concentration of the insulator 212.
  • silicon nitride as the insulator 212 by a sputtering method, silicon nitride having a low hydrogen concentration can be formed. Further, by using aluminum oxide for the insulator 214, the hydrogen concentration can be made lower than that of the insulator 212.
  • the transistor 200 is formed on the insulator 214 in the subsequent step.
  • the film close to the transistor 200 preferably has a relatively low hydrogen concentration, and the film having a relatively high hydrogen concentration is remote from the transistor 200. It is preferable to arrange them.
  • the insulator 216 is formed on the insulator 214.
  • the film formation of the insulator 216 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide or silicon oxide nitride is formed as the insulator 216 by a sputtering method.
  • the insulator 212, the insulator 214, and the insulator 216 are continuously formed under reduced pressure without being exposed to the atmospheric environment.
  • the film By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulator 212, the insulator 214, and the insulator 216, and the insulator 212 and the insulator 214 It is preferable because the interface and the vicinity of the interface of the above, and the interface and the vicinity of the interface between the insulator 214 and the insulator 216 can be kept clean.
  • a multi-chamber type film forming apparatus may be used for continuous film formation. Continuous film formation is preferable because the manufacturing process time of the semiconductor device can be shortened.
  • an opening reaching the insulator 214 is formed in the insulator 216.
  • Wet etching may be used to form the openings, but dry etching is preferable for microfabrication.
  • the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove.
  • silicon oxide or silicon oxide nitride is used for the insulator 216 forming the groove
  • silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.
  • a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching apparatus having parallel plate type electrodes can be used.
  • the capacitively coupled plasma etching apparatus having the parallel plate type electrodes may be configured to apply a high frequency voltage to one of the parallel plate type electrodes.
  • a plurality of different high frequency voltages may be applied to one of the parallel plate type electrodes.
  • a high frequency voltage having the same frequency may be applied to each of the parallel plate type electrodes.
  • a high frequency voltage having a different frequency may be applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching apparatus or the like can be used.
  • a conductive film to be the conductor 205a is formed. It is desirable that the conductive film contains a conductor having a function of suppressing the permeation of oxygen.
  • a conductor having a function of suppressing the permeation of oxygen For example, tantalum nitride, tungsten nitride, titanium nitride and the like can be used. Alternatively, it can be a laminated film of a conductor having a function of suppressing oxygen permeation and a tantalum, tungsten, titanium, molybdenum, aluminum, copper or molybdenum tungsten alloy.
  • the film formation of the conductive film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205a has a multilayer structure.
  • tantalum nitride is formed into a film by a sputtering method, and titanium nitride is laminated on the tantalum nitride.
  • a metal nitride in the lower layer of the conductor 205b, even if a easily diffusible metal such as copper is used as the conductive film to be the conductor 205b described later, the metal diffuses out from the conductor 205a. Can be prevented.
  • a conductive film to be the conductor 205b is formed.
  • the film formation of the conductive film can be performed by using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low resistance conductive material such as copper is formed as a conductive film to be the conductor 205b.
  • a part of the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b is removed, and the insulator 216 is exposed.
  • the conductor 205a and the conductor 205b remain only in the opening.
  • the conductor 205 having a flat upper surface can be formed (see FIGS. 5A to 5D).
  • a part of the insulator 216 may be removed by the CMP treatment.
  • the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but the present embodiment is not limited to this.
  • a conductor 205 is formed on the insulator 214, an insulator 216 is formed on the insulator 205, and the insulator 216 is subjected to CMP treatment to remove a part of the insulator 216 and to remove the conductor.
  • the surface of 205 may be exposed.
  • the insulator 222 is formed on the insulator 216 and the conductor 205.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed.
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water.
  • the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. , The formation of oxygen deficiency in the oxide 230 can be suppressed.
  • the film formation of the insulator 222 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the heat treatment may be carried out at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, and more preferably 320 ° C. or higher and 450 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the oxygen gas may be set to about 20%.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
  • the gas used in the above heat treatment is highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the flow rate ratio of nitrogen gas and oxygen gas is set to 4 slm: 1 slm, and the treatment is performed at a temperature of 400 ° C. for 1 hour.
  • impurities such as water and hydrogen contained in the insulator 222 can be removed.
  • the heat treatment can be performed at a timing such as after the film formation of the insulator 224 is performed.
  • the insulator 224 is formed on the insulator 222.
  • the film formation of the insulator 224 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide or silicon oxide nitride film is formed as the insulator 224 by the ALD method.
  • the insulator 224 is preferably formed by a film forming method using a gas in which hydrogen atoms have been reduced or removed. Thereby, the hydrogen concentration of the insulator 224 can be reduced. Since the insulator 224 becomes an insulator 224 that comes into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • plasma treatment containing oxygen may be performed in a reduced pressure state.
  • the plasma treatment containing oxygen for example, it is preferable to use an apparatus having a power source for generating high-density plasma using microwaves.
  • the substrate side may have a power supply for applying RF (Radio Frequency).
  • RF Radio Frequency
  • high-density plasma high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can.
  • plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, the heat treatment does not have to be performed.
  • CMP treatment may be performed until the insulator 224 is reached.
  • the surface of the insulator 224 can be flattened and smoothed.
  • a part of the insulator 224 may be polished by the CMP treatment to reduce the film thickness of the insulator 224, but the film thickness may be adjusted when the insulator 224 is formed.
  • oxygen can be added to the insulator 224 by forming aluminum oxide on the insulator 224 by a sputtering method.
  • the oxide film 230A and the oxide film 230B are formed in this order on the insulator 224 (see FIGS. 5A to 5D).
  • the oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230A and the oxide film 230B are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas.
  • excess oxygen in the oxide film formed can be increased.
  • the above-mentioned oxide film is formed by a sputtering method
  • the above-mentioned In—M—Zn oxide target or the like can be used.
  • the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230B is formed by a sputtering method, if the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, the oxygen excess type oxidation A physical semiconductor is formed. Transistors using oxygen-rich oxide semiconductors in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this.
  • the oxide film 230B is formed by a sputtering method and the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. To. A transistor using an oxygen-deficient oxide semiconductor in the channel formation region can obtain a relatively high field-effect mobility. Further, the crystallinity of the oxide film can be improved by forming a film while heating the substrate.
  • an oxide film 243A is formed on the oxide film 230B (see FIGS. 5A to 5D).
  • the oxide film 243A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the atomic number ratio of Ga to In is preferably larger than the atomic number ratio of Ga to In in the oxide film 230B.
  • the oxide film 230A, the oxide film 230B, and the oxide film 243A are continuously formed under reduced pressure without being exposed to the atmospheric environment.
  • the film without opening it to the atmosphere it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A, the oxide film 230B, and the oxide film 243A, and the oxide film 230A and the oxide film 230B can be formed.
  • the interface and the vicinity of the interface of the above, and the interface and the vicinity of the interface between the oxide film 230B and the oxide film 243A can be kept clean.
  • a multi-chamber type film forming apparatus may be used. Continuous film formation is preferable because the manufacturing process time of the semiconductor device can be shortened.
  • the heat treatment may be performed in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not crystallize, and may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 400 ° C. or higher and 600 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the oxygen gas may be set to about 20%.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen. You may.
  • the gas used in the above heat treatment is highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the treatment after performing the treatment at a temperature of 550 ° C. for 1 hour in a nitrogen atmosphere, the treatment is continuously performed at a temperature of 550 ° C. for 1 hour in an oxygen atmosphere.
  • impurities such as water and hydrogen in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be removed.
  • the heat treatment can improve the crystallinity of the oxide film 230B to obtain a denser and more dense structure. Thereby, the diffusion of oxygen or impurities in the oxide film 230B can be reduced.
  • a conductive film 242A is formed on the oxide film 243A (see FIGS. 5A to 5D).
  • the film formation of the conductive film 242A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the heat treatment may be performed before the film formation of the conductive film 242A.
  • the heat treatment may be carried out under reduced pressure to continuously form a conductive film 242A without exposing it to the atmosphere. By performing such a treatment, water and hydrogen adsorbed on the surface of the oxide film 243A and the like are removed, and the water concentration and the hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A are further reduced. be able to.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In the present embodiment, the temperature of the heat treatment is set to 200 ° C.
  • an insulating film 271A is formed on the conductive film 242A (see FIGS. 5A to 5D).
  • the insulating film 271A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • As the insulating film 271A it is preferable to use an insulating film having a function of suppressing the permeation of oxygen.
  • aluminum oxide, hafnium oxide, silicon nitride or the like may be formed by a sputtering method or an ALD method.
  • a conductive film 248A is formed on the insulating film 271A (see FIGS. 5A to 5D).
  • the film formation of the conductive film 248A can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 248A for example, the same conductive film as the conductive film 242A may be used.
  • the conductive film 242A forms tantalum nitride
  • the insulating film 271A forms aluminum oxide
  • the conductive film 248A forms tantalum nitride by a sputtering method.
  • the conductive film 242A, the insulating film 271A, and the conductive film 248A are continuously formed under reduced pressure without being exposed to the atmospheric environment.
  • the film By forming the film without opening it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the conductive film 242A, the insulating film 271A, and the conductive film 248A, and the conductive film 242A and the insulating film 271A It is preferable because the interface and the vicinity of the interface, and the interface and the vicinity of the interface between the insulating film 271A and the conductive film 248A can be kept clean.
  • a multi-chamber type film forming apparatus may be used. Continuous film formation is preferable because the manufacturing process time of the semiconductor device can be shortened.
  • the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the conductive film 248A are processed into an island shape, and the oxide 230a, the oxide 230b, and the oxide are oxidized.
  • the material layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 are formed (see FIGS. 6A to 6D).
  • a dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for microfabrication.
  • the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the conductive film 248A may be processed under different conditions. In this step, the film thickness of the region that does not overlap with the oxide 230a of the insulator 224 may be reduced.
  • the resist is first exposed through a mask. Next, the exposed region is removed or left with a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used.
  • the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.
  • a hard mask made of an insulator or a conductor may be used under the resist mask.
  • a hard mask an insulating film or a conductive film to be a hard mask material is formed on the conductive film 242A, a resist mask is formed on the insulating film or a conductive film, and the hard mask material is etched to form a hard mask having a desired shape. can do.
  • Etching of the conductive film 242A or the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching after etching the conductive film 242A or the like.
  • the insulating layer 271B and the conductive layer 248 are used as hard masks.
  • the conductive layer 242B does not have a curved surface between the side surface and the upper surface as shown in FIGS. 6B to 6D.
  • the conductor 242a and the conductor 242b shown in FIGS. 3B and 3D have a square end where the side surface and the upper surface intersect. Since the end portion where the side surface and the upper surface of the conductor 242 intersect is angular, the cross-sectional area of the conductor 242 becomes larger than that in the case where the end portion has a curved surface. As a result, the resistance of the conductor 242 is reduced, so that the on-current of the transistor 200 can be increased.
  • the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 are formed so that at least a part thereof overlaps with the conductor 205. Further, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 are substantially perpendicular to the upper surface of the insulator 222.
  • a plurality of transistors 200 are provided so that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 are substantially perpendicular to the upper surface of the insulator 222. At the same time, it is possible to reduce the area and increase the density. Alternatively, the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 and the upper surface of the insulator 222 may be low. ..
  • the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the conductive layer 248 and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. .. With such a shape, the covering property of the insulator 272 or the like can be improved and defects such as voids can be reduced in the subsequent steps.
  • the conductive layer 248 is removed.
  • a dry etching method is used to remove the conductive layer 248 (see FIGS. 7A to 7D).
  • the insulator 272 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 8A to 8D).
  • the film formation of the insulator 272 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • aluminum oxide is formed as the insulator 272 by a sputtering method.
  • the insulator 272 is preferably formed by a bias sputtering method.
  • the amount of oxygen injected into the insulator 224 can be controlled by the magnitude of the RF power applied to the substrate.
  • the RF power 0.31 W / cm 2 or more, preferably 0.62 W / cm 2 or more, more preferably may be applied to 1.86W / cm 2 or more bias to the substrate. That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by the RF power at the time of forming the insulator 272.
  • an amount of oxygen suitable for improving the reliability of the transistor can be injected.
  • the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate.
  • the insulator 272 has a function of injecting oxygen into the underlying film, but the insulator 272 itself has a function of suppressing the permeation of oxygen. Therefore, when the insulator 280 is formed on the insulator 272 in a later step and oxygen is diffused from the insulator 280, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductivity are transmitted from the insulator 280. It is possible to prevent oxygen from diffusing directly into layer 242B.
  • an insulating film to be the insulator 280 is formed on the insulator 224 and the insulator 272.
  • the film formation of the insulating film can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxide film may be formed by using a sputtering method, and a silicon oxide film may be formed on the silicon oxide film by using a PEALD method or a thermal ALD method.
  • the insulating film is formed by a film forming method using a gas in which hydrogen atoms are reduced or removed. Thereby, the hydrogen concentration of the insulator 280 can be reduced.
  • heat treatment may be performed before the film formation of the insulating film.
  • the heat treatment may be carried out under reduced pressure to continuously form the insulating film without exposing it to the atmosphere.
  • water and hydrogen adsorbed on the surface of the insulator 224 and the insulator 272 are removed, and further, in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224. Water concentration and hydrogen concentration can be reduced.
  • the above-mentioned heat treatment conditions can be used for the heat treatment.
  • the insulating film is subjected to CMP treatment to form an insulator 280 having a flat upper surface (see FIGS. 9A to 9D).
  • CMP treatment Similar to the insulator 224, aluminum oxide may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.
  • microwave processing may be performed.
  • the microwave treatment is preferably performed in an atmosphere containing oxygen and under reduced pressure.
  • the electric field insulator 280 by microwave, oxides 230b, given such an oxide 230a, oxides 230b, and an oxygen deficient V O H in the oxide 230a and (V O) It can be divided into hydrogen (H).
  • a part of the hydrogen divided at this time may be combined with oxygen contained in the insulator 280 and removed as water molecules. Further, a part of hydrogen may be gettered to the conductive layer 242B via the insulator 272 and the insulating layer 271B.
  • the heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment.
  • hydrogen in the insulator 280, the oxide 230b, and the oxide 230a can be efficiently removed.
  • the heat treatment temperature is preferably 300 ° C. or higher and 500 ° C. or lower.
  • the film quality of the insulator 280 by modifying the film quality of the insulator 280 by performing microwave treatment, it is possible to suppress the diffusion of hydrogen, water, impurities and the like. Therefore, it is possible to prevent hydrogen, water, impurities, etc. from diffusing into the oxide 230 through the insulator 280 by a post-process after forming the insulator 280, heat treatment, or the like.
  • a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b are processed. It forms an opening that reaches the oxide 230b.
  • the opening is preferably formed so as to overlap the conductor 205.
  • an insulator 271a, an insulator 271b, a conductor 242a, a conductor 242b, an oxide 243a, and an oxide 243b are formed (see FIGS. 10A to 10D).
  • the upper part of the oxide 230b is removed.
  • a groove is formed in the oxide 230b.
  • the groove may be formed in the opening forming step, or may be formed in a step different from the opening forming step.
  • the processing of a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, a part of the oxide layer 243B, and a part of the oxide 230b is dry.
  • An etching method or a wet etching method can be used. Processing by the dry etching method is suitable for microfabrication. Further, the processing may be performed under different conditions.
  • a part of the insulator 280 is processed by a dry etching method
  • a part of the insulator 272 and a part of the insulating layer 271B are processed by a wet etching method
  • a part of the oxide layer 243B and one of the conductive layers 242B are processed by a dry etching method
  • a part and a part of the oxide 230b may be processed by a dry etching method.
  • the processing of a part of the oxide layer 243B and a part of the conductive layer 242B and the processing of a part of the oxide 230b may be performed under different conditions.
  • the power density of the bias power may be to 0.02 W / cm 2 or more, it is preferable to 0.03 W / cm 2 or more, more preferably between 0.06 W / cm 2 or more.
  • the dry etching processing time may be appropriately set according to the depth of the groove portion.
  • the impurities include the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a component contained in the conductive layer 242B, and a member used in the apparatus used for forming the opening. Examples thereof include those caused by components, components contained in gas or liquid used for etching, and the like. Examples of the impurities include aluminum, silicon, tantalum, fluorine, chlorine and the like.
  • impurities such as aluminum or silicon inhibit the conversion of oxide 230b or oxide 230c formed in a later step into CAAC-OS. Therefore, it is preferable that impurity elements such as aluminum and silicon that inhibit CAAC-OS conversion are reduced or removed.
  • the concentration of aluminum atoms at the interface between the oxides 230b and 230c and in the vicinity thereof may be 5.0 atomic% or less, preferably 2.0 atomic% or less, and 1.5 atomic% or less. More preferably, 1.0 atomic% or less is further preferable, and less than 0.3 atomic% is further preferable.
  • the region of the metal oxide that has become a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor) due to the inhibition of CAAC-OS by impurities such as aluminum or silicon is defined as the non-CAAC region. May be called.
  • the non CAAC region since the compactness of the crystal structure is reduced, V O H has a large amount of formation, the transistor tends to be normally on reduction. Therefore, it is preferable that the oxide 230b and the non-CAAC region of the oxide 230c are reduced or removed.
  • the oxide 230b and the oxide 230c preferably have a CAAC structure.
  • the oxide 230b and the oxide 230c have a CAAC structure up to the lower end of the drain.
  • the conductor 242a or the conductor 242b and its vicinity function as a drain. That is, it is preferable that either or both of the oxide 230b and the oxide 230c near the lower end of the conductor 242a (conductor 242b) has a CAAC structure.
  • the damaged region of the oxide 230b is removed, and by having the CAAC structure, the fluctuation of the electrical characteristics of the transistor 200 can be further suppressed. Moreover, the reliability of the transistor 200 can be improved.
  • the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleanings may be appropriately combined.
  • the cleaning treatment may deepen the groove.
  • the cleaning treatment may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid or the like with carbonated water or pure water, pure water, carbonated water or the like.
  • ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water.
  • these washings may be appropriately combined.
  • an aqueous solution diluted by adding pure water to hydrofluoric acid may be referred to as diluted hydrofluoric acid
  • an aqueous solution diluted by adding pure water to ammonia water may be referred to as diluted ammonia water.
  • concentration, temperature, etc. of the aqueous solution may be appropriately adjusted depending on the impurities to be removed, the configuration of the semiconductor device to be washed, and the like.
  • the ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less.
  • the hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.
  • a frequency of 200 kHz or higher preferably 900 kHz or higher. By using this frequency, damage to the oxide 230b and the like can be reduced.
  • the above cleaning treatment may be performed a plurality of times, and the cleaning liquid may be changed for each cleaning treatment.
  • a treatment using diluted hydrofluoric acid or diluted aqueous ammonia may be performed as the first cleaning treatment
  • a treatment using pure water or carbonated water may be performed as the second cleaning treatment.
  • wet cleaning is performed using diluted hydrofluoric acid, and then wet cleaning is performed using pure water or carbonated water.
  • impurities adhering to or diffused inside the surface such as oxide 230a and oxide 230b can be removed. Further, the crystallinity of the oxide 230c formed on the oxide 230b can be enhanced.
  • the heat treatment may be performed after the etching or the cleaning.
  • the heat treatment may be performed at 100 ° C. or higher and 450 ° C. or lower, preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 230a and oxides 230b, it is possible to reduce the oxygen vacancies V O.
  • the crystallinity of the oxide 230b can be improved, and the crystallinity of the oxide 230c formed in the groove portion of the oxide 230b can also be improved.
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere.
  • the heat treatment may be performed before the oxide film 230C is formed, and it is preferable that the heat treatment is performed under reduced pressure to continuously form the oxide film 230C without exposing to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, it is possible to remove the water and hydrogen adsorbed on the surface of the oxide 230b and the like, and further reduce the water concentration and the hydrogen concentration in the oxide 230a and the oxide 230b.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower. In the present embodiment, the temperature of the heat treatment is set to 200 ° C.
  • the film formation of the oxide film 230C can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230C may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C.
  • a part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b.
  • a part of oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%. Further, by forming the oxide film 230C in such an atmosphere containing a large amount of oxygen, the oxide film 230C can be easily converted into CAAC-OS.
  • the oxide film 230C is formed while heating the substrate. At this time, by setting the substrate temperature to 200 ° C. or higher, oxygen deficiency in the oxide film 230C and the oxide 230b can be reduced. The crystallinity of the oxide film 230C and the oxide 230b can be improved by forming a film while heating the substrate.
  • an oxide film 230D is formed (see FIGS. 11A to 11D).
  • the film formation of the oxide film 230D is preferably carried out continuously from the film formation of the oxide film 230C without being exposed to the atmosphere.
  • the film formation of the oxide film 230D can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230D may be formed by using the same film forming method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230D.
  • the proportion of oxygen contained in the sputtering gas of the oxide film 230D may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230C and the oxide film 230D on the side surface of the insulator 280, the side surface of the insulator 272, and the side surface of the insulator 271 in the opening are removed by using a dry etching method.
  • the oxide film 230C and the oxide film 230D on the insulator 280 are also removed.
  • the oxide 230c and the oxide 230d are formed by leaving the oxide film 230C and the oxide film 230D at the bottom of the opening (see FIGS. 12A to 12D).
  • the above processing can be performed by appropriately setting the dry etching conditions.
  • the pressure during dry etching may be set higher.
  • the pressure during dry etching is preferably 66.5 Pa or more, more preferably 133 Pa or more.
  • the traveling direction of the reactive ions becomes random, and it may be difficult for the reactive ions to reach the bottom of the opening. Therefore, the removal of the oxide film 230C and the oxide film 230D at the bottom of the opening can be suppressed, so that the oxide film 230C can remain.
  • the oxide film 230C and the oxide film 230D are each formed by an ionization sputtering method.
  • the ionization sputtering method is a method of forming a film by ionizing the sputtering particles by applying high frequency power or the like to the sputtering particles.
  • the film is mainly formed on the bottom of the opening and the insulator 280, so that the film thickness of the bottom of the opening can be made thicker than the film thickness of the side surface of the opening.
  • the oxide 230c and the oxide 230d may be formed by leaving the oxide film 230C and the oxide film 230D at the bottom of the opening using the above-mentioned dry etching method.
  • the semiconductor device having the transistor 200 produced in this manner is shown in FIGS. 4A to 4D.
  • an insulating film 250A is formed (see FIGS. 13A to 13D).
  • the heat treatment may be performed before the film formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure to continuously form the insulating film 250A without exposure to the atmosphere. Further, the heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, water and hydrogen adsorbed on the surface of the oxide 230d and the like are removed, and further, the water concentration and hydrogen in the oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d are removed. The concentration can be reduced.
  • the temperature of the heat treatment is preferably 100 ° C. or higher and 400 ° C. or lower.
  • the insulating film 250A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the insulating film 250A is preferably formed by a film forming method using a gas in which hydrogen atoms have been reduced or removed. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A becomes an insulator 250 in contact with the oxide 230d in a later step, it is preferable that the hydrogen concentration is reduced in this way.
  • the lower layer of the insulator 250 forms an insulator in which oxygen is released by heating
  • the upper layer of the insulator 250 is an insulator having a function of suppressing the diffusion of oxygen. It is preferably formed using the body. With such a configuration, it is possible to prevent oxygen contained in the lower layer of the insulator 250 from diffusing into the conductor 260 formed in a later step. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Further, it is possible to suppress the oxidation of the conductor 260 by oxygen contained in the lower layer of the insulator 250.
  • the lower layer of the insulator 250 can be provided by using a material that can be used for the insulator 250 described above
  • the upper layer of the insulator 250 can be provided by using the same material as the insulator 222.
  • an insulating material which is a high-k material having a high relative permittivity may be used for the upper layer of the insulator 250.
  • the gate insulator By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, it is possible to obtain a laminated structure that is stable against heat and has a high relative permittivity. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator.
  • the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator can be thinned.
  • the insulator that is the lower layer of the insulator 250 may form an insulator having a function of suppressing the diffusion of oxygen, and the upper layer of the insulator 250 may form an insulator that releases oxygen by heating. ..
  • the lower layer of the insulator 250 is preferably formed by using an insulator having a function of suppressing the permeation of impurities such as water and hydrogen. With such a configuration, impurities such as water and hydrogen contained in the insulator 280 can be suppressed from diffusing into the oxide 230.
  • an insulator having a barrier property against oxygen, hydrogen, and water it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium.
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like.
  • the above-mentioned insulator is formed by a thermal ALD method using an inorganic precursor. By using this method, an insulator with reduced hydrogen can be formed.
  • microwave treatment may be performed in an atmosphere containing oxygen and under reduced pressure.
  • an electric field due to microwaves is applied to the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, the oxide 230a, etc., and the oxide film 230D, the oxide film 230C, and the oxide 230b are provided.
  • V O H in the oxide 230a may be divided into the V O and hydrogen.
  • a part of hydrogen may be gettered on the conductor 242 (conductor 242a and conductor 242b).
  • the microwave treatment By performing the microwave treatment in this way, the hydrogen concentration in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be reduced.
  • the oxide 230a, in the oxide 230b, the oxide film 230C, and by oxygen in V O which may be present the V O H after cutting into a V O and hydrogen in the oxide film 230D is supplied V O can be repaired or supplemented.
  • the heat treatment may be performed while maintaining the reduced pressure state after the microwave treatment.
  • hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be efficiently removed.
  • a part of hydrogen may be gettered on the conductor 242 (conductor 242a and conductor 242b).
  • the step of performing the heat treatment may be repeated a plurality of times while maintaining the reduced pressure state after the microwave treatment. By repeating the heat treatment, hydrogen in the insulating film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, and the oxide 230a can be removed more efficiently.
  • the heat treatment temperature is preferably 300 ° C. or higher and 500 ° C. or lower.
  • the film quality of the insulating film 250A by modifying the film quality of the insulating film 250A by performing microwave treatment, it is possible to suppress the diffusion of hydrogen, water, impurities and the like. Therefore, hydrogen, water, impurities, etc. are diffused to the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as a film formation of a conductive film to be a conductor 260 or a post-treatment such as a heat treatment. Can be suppressed.
  • a post-process such as a film formation of a conductive film to be a conductor 260 or a post-treatment such as a heat treatment.
  • the conductive film 260A and the conductive film 260B are formed in this order (see FIGS. 14A to 14D).
  • the film formation of the conductive film 260A and the conductive film 260B can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 260A is formed by using the ALD method, and the conductive film 260B is continuously formed by the CVD method under reduced pressure without releasing to the atmosphere.
  • the oxide film 230C, the oxide film 230D, the edge film 250A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed, so that the oxide 230c, the oxide 230d, and the insulator are exposed.
  • 250 and conductor 260 are formed (see FIGS. 15A to 15D).
  • the oxide 230c is arranged so as to cover the opening reaching the oxide 230b and the inner wall (side surface and bottom surface) of the groove portion of the oxide 230b.
  • the oxide 230d is arranged so as to cover the opening and the inner wall of the groove via the oxide 230c.
  • the insulator 250 is arranged so as to cover the opening and the inner wall of the groove through the oxide 230d. Further, the conductor 260 is arranged so as to embed the opening and the groove through the oxide 230c, the oxide 230d, and the insulator 250.
  • the heat treatment may be performed under the same conditions as the above heat treatment.
  • the treatment is carried out in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour.
  • the heat treatment the water concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.
  • the insulator 282 may be continuously formed without being exposed to the atmosphere.
  • the insulator 282 is formed on the oxide 230d, the oxide 230c, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 16A to 16D).
  • the film formation of the insulator 282 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • oxygen can be added to the insulator 280 while forming the film.
  • the insulator 280 can contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate. Further, by forming the insulator 282 in contact with the upper surface of the conductor 260, it is possible to suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 in the subsequent heat treatment, which is preferable. ..
  • a portion is processed to form an opening that reaches the insulator 212 (see FIGS. 17A-17D).
  • the opening may be formed so as to surround the transistor 200.
  • the opening may be formed so as to surround a plurality of transistors 200.
  • a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for microfabrication. Further, the processing may be performed under different conditions.
  • the insulator 282, the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 are covered to form the insulator 283 (see FIGS. 18A to 18D).
  • the film formation of the insulator 283 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon nitride is formed by using a sputtering method.
  • the insulator 283 is in contact with the insulator 212 at the bottom surface of the opening.
  • the upper surface and the side surface of the transistor 200 are wrapped in the insulator 283, and the lower surface is wrapped in the insulator 212.
  • the transistor 200 By wrapping the transistor 200 with the insulator 283 and the insulator 212 having high barrier properties in this way, it is possible to prevent water and hydrogen from entering from the outside.
  • an insulating film to be the insulator 274 is formed on the insulator 283.
  • the film formation of the insulating film to be the insulator 274 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is advisable to deposit silicon oxide by using a CVD method.
  • the insulating film to be the insulator 274 is preferably formed by the above-mentioned film forming method using a gas in which hydrogen atoms are reduced or removed. As a result, the hydrogen concentration of the insulating film that becomes the insulator 274 can be reduced.
  • the insulating film to be the insulator 274 is subjected to CMP treatment to form the insulator 274 having a flat upper surface (see FIGS. 19A to 19D).
  • an opening reaching the conductor 242 is formed in the insulator 271, the insulator 272, the insulator 280, the insulator 282, and the insulator 283 (see FIGS. 20A to 20D).
  • the opening may be formed by using a lithography method.
  • the shape of the opening is circular in the top view, but the shape is not limited to this.
  • the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a polygonal shape such as a quadrangle with rounded corners in a top view.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241.
  • the film formation of the insulating film to be the insulator 241 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film to be the insulator 241 it is preferable to use an insulating film having a function of suppressing the permeation of oxygen.
  • the anisotropic etching of the insulating film to be the insulator 241 for example, a dry etching method or the like may be used.
  • a dry etching method or the like By providing the insulator 241 on the side surface of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. Further, it is possible to prevent impurities such as water and hydrogen from diffusing from the conductor 240a and the conductor 240b to the outside.
  • a conductive film to be the conductor 240 is formed. It is desirable that the conductive film to be the conductor 240 has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen.
  • the conductive film to be the conductor 240 has a laminated structure, for example, tantalum nitride, titanium nitride, or the like can be used as the underlying film.
  • the upper film for example, tungsten, molybdenum, copper or the like can be used.
  • the film formation of the conductive film to be the conductor 240 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the ionization sputtering method for forming the lower layer of the conductive film it is preferable to use the ionization sputtering method for forming the lower layer of the conductive film to be the conductor 240.
  • the film can be uniformly formed on the bottom and side surfaces of the opening.
  • the lower layer of the conductive film to be the conductor 240 functions well as a seed layer of the upper layer of the conductive film to be the conductor 240, which is preferable.
  • a part of the conductive film to be the conductor 240a and the conductor 240b is removed, and the upper surfaces of the insulator 283 and the insulator 274 are exposed.
  • the conductor 240a and the conductor 240b having a flat upper surface can be formed by leaving the conductive film only in the opening (see FIGS. 20A to 20D).
  • a part of the upper surface of the insulator 283 and a part of the upper surface of the insulator 274 may be removed by the CMP treatment.
  • a conductive film to be a conductor 246 is formed.
  • the film formation of the conductive film to be the conductor 246 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 246 is processed by a lithography method to form the conductor 246a in contact with the upper surface of the conductor 240a and the conductor 246b in contact with the upper surface of the conductor 240b (see FIGS. 21A to 21D). ).
  • a part of the insulator 283 in the region where the conductor 246a and the conductor 246b and the insulator 283 do not overlap may be removed.
  • the insulator 286 is formed on the conductor 246 and the insulator 283 (see FIGS. 3A to 3D).
  • the film formation of the insulator 286 can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 286 may have multiple layers.
  • silicon nitride may be formed into a film by using a sputtering method, and silicon nitride may be formed on the silicon nitride by a CVD method.
  • the semiconductor device having the transistor 200 shown in FIGS. 3A to 3D can be manufactured.
  • the transistor 200 can be manufactured by using the method for manufacturing the semiconductor device shown in the present embodiment.
  • the semiconductor device may be manufactured without performing the steps shown in FIGS. 17A to 19D.
  • the transistor 200 according to one aspect of the present invention is provided, which is different from the ones shown in the above ⁇ Semiconductor device configuration example> and the above ⁇ Semiconductor device modification>.
  • An example of a semiconductor device will be described.
  • the same reference numerals are given to the structures having the same functions as the structures constituting the semiconductor devices (see FIGS. 3A to 3D) shown in ⁇ Modified examples of semiconductor devices>. I will add it.
  • the constituent material of the transistor 200 the materials described in detail in ⁇ Semiconductor device configuration example> and ⁇ Semiconductor device modification> can be used.
  • FIGS. 22A and 22B show a configuration in which a plurality of transistors 200_1 to 200_n are comprehensively sealed with an insulator 283 and an insulator 212.
  • the transistors 200_1 to 200_n appear to be arranged in the channel length direction, but the transistor 200_1 to the transistor 200_n are not limited to this.
  • the transistors 200_1 to 200_n may be arranged in the channel width direction or may be arranged in a matrix. Further, depending on the design, they may be arranged without regularity.
  • a portion where the insulator 283 and the insulator 212 are in contact with each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n.
  • the sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With such a structure, a plurality of transistors 200_1 to 200_n can be wrapped with the insulator 283 and the insulator 212. Therefore, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.
  • a dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) may be provided on the sealing portion 265. Since the substrate is divided at the dicing line, the transistor group surrounded by the sealing portion 265 is taken out as one chip.
  • FIG. 22A an example in which a plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265 is shown, but the present invention is not limited to this.
  • a plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions.
  • a plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a, and further surrounded by an outer sealing portion 265b.
  • the portion where the insulator 283 and the insulator 212 are in contact with each other increases, so that the adhesion between the insulator 283 and the insulator 212 can be improved. It can be improved further. Thereby, a plurality of transistors 200_1 to 200_n can be more reliably sealed.
  • a dicing line may be provided on the sealing portion 265a or the sealing portion 265b, or a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.
  • one aspect of the present invention it is possible to provide a semiconductor device having little variation in transistor characteristics.
  • one aspect of the present invention can provide a semiconductor device with good reliability.
  • one aspect of the present invention can provide a semiconductor device having good electrical characteristics.
  • one aspect of the present invention can provide a semiconductor device having a large on-current.
  • one aspect of the present invention can provide a semiconductor device capable of miniaturization or high integration.
  • one aspect of the present invention can provide a low power consumption semiconductor device.
  • the configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.
  • FIG. 23 shows an example of a semiconductor device (storage device) according to one aspect of the present invention.
  • the semiconductor device of one aspect of the present invention includes a transistor 200, a transistor 300, and a capacitive element 100.
  • the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200.
  • the transistor 200 the transistor 200 described in the previous embodiment can be used.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor 200 as a storage device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitive element 100. ..
  • the storage devices shown in FIG. 23 can form a memory cell array by arranging them in a matrix.
  • the transistor 300 is provided on the substrate 311 and functions as a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311 and a low that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the semiconductor region 313 (a part of the substrate 311) on which the channel is formed has a convex shape. Further, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315.
  • the conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. It should be noted that an insulator that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate may be processed to form a semiconductor film having a convex shape.
  • transistor 300 shown in FIG. 23 is an example, and the transistor 300 is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.
  • the capacitive element 100 is provided above the transistor 200.
  • the capacitive element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.
  • the insulator 130 it is preferable to use an insulator that can be used as the insulator 286 shown in the above embodiment.
  • the conductor 112 provided on the conductor 240 and the conductor 110 can be formed at the same time.
  • the conductor 112 has a function as a plug or wiring that electrically connects to the capacitance element 100, the transistor 200, or the transistor 300.
  • the conductor 112 and the conductor 110 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • the insulator 130 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, hafnium nitride. Etc. may be used, and it can be provided in a laminated or single layer.
  • the capacitance element 100 can secure a sufficient capacitance by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacitance is improved.
  • the electrostatic breakdown of the element 100 can be suppressed.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • silicon oxide silicon oxide nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and vacancies
  • silicon oxide or resin having.
  • a wiring layer provided with an interlayer film, wiring, a plug, etc. may be provided between the structures. Further, a plurality of wiring layers can be provided according to the design.
  • the conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals. Further, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order on the transistor 300 as an interlayer film. Further, the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitance element 100, a conductor 328 electrically connected to the transistor 200, a conductor 330, and the like. The conductor 328 and the conductor 330 function as plugs or wirings.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below the insulator.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.
  • the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like.
  • the conductor 218 has a function as a plug or wiring for electrically connecting to the capacitance element 100 or the transistor 300.
  • an insulator 150 is provided on the conductor 120 and the insulator 130.
  • the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug.
  • the insulator 217 is provided in contact with the inner wall of the opening formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. That is, the insulator 217 is provided between the conductor 218, the insulator 210 insulator 212, the insulator 214, and the insulator 216. Since the conductor 205 can be formed in parallel with the conductor 218, the insulator 217 may be formed in contact with the side surface of the conductor 205.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride may be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, the insulator 216, and the insulator 222, impurities such as water or hydrogen are conductive from the insulator 210 or the insulator 216 or the like. It can be suppressed from being mixed with the oxide 230 through the body 218.
  • silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.
  • the insulator 217 can be formed in the same manner as the insulator 241.
  • the PEALD method may be used to form a film of silicon nitride, and anisotropic etching may be used to form an opening reaching the conductor 356.
  • Examples of the insulator that can be used as the interlayer film include oxides, nitrides, oxide nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides having insulating properties.
  • the material may be selected according to the function of the insulator.
  • the insulator 150, the insulator 280, the insulator 210, the insulator 352, the insulator 354, and the like have an insulator having a low relative permittivity.
  • the insulator preferably has silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having pores, or a resin.
  • the insulator may be silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having pores. And preferably have a laminated structure with a resin.
  • silicon oxide and silicon oxide nitride are thermally stable, they can be combined with a resin to form a laminated structure that is thermally stable and has a low relative permittivity.
  • the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.
  • a transistor using an oxide semiconductor can stabilize the electrical characteristics of the transistor by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.
  • Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators containing, lanthanum, neodymium, hafnium or tantalum may be used in single layers or in layers.
  • an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride and the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor having high electric conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and silicide such as nickel silicide may be used.
  • the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 240, the conductor 112, and the like include a metal material, an alloy material, a metal nitride material, or a metal formed of the above materials.
  • Conductive materials such as oxide materials can be used in a single layer or in layers. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • an insulator 241 between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240 it is preferable to provide an insulator 241 between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240.
  • the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 are configured to be sealed by an insulator having a barrier property. Can be done.
  • the insulator 241 it is possible to suppress the excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Further, by having the insulator 241, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 via the conductor 240.
  • an insulating material having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide or hafnium oxide.
  • silicon nitride is preferable because it has a high blocking property against hydrogen.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide can be used.
  • the transistor 200 is sealed with the insulator 212, the insulator 214, the insulator 282, and the insulator 283. With such a configuration, it is possible to reduce the mixing of hydrogen contained in the insulator 274, the insulator 150 and the like into the insulator 280 and the like.
  • the conductor 240 penetrates through the insulator 283 and the insulator 282, and the conductor 218 penetrates through the insulator 214, the insulator 212, and the insulator 210.
  • the insulator 241 penetrates. It is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. Thereby, hydrogen mixed in the insulator 212, the insulator 214, the insulator 282, and the insulator 283 can be reduced through the conductor 240 and the conductor 218.
  • the transistor 200 is more reliably sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 241 and the insulator 217, and hydrogen and the like contained in the insulator 274 and the like are contained. It is possible to reduce the mixing of impurities from the outside.
  • the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 are formed by a film forming method using a gas in which hydrogen atoms are reduced or removed, as shown in the previous embodiment. It is preferably formed. Thereby, the hydrogen concentration of the insulator 216, the insulator 224, the insulator 280, the insulator 250, and the insulator 274 can be reduced.
  • the hydrogen concentration of the silicon-based insulating film in the vicinity of the transistor 200 can be reduced, and the hydrogen concentration of the oxide 230 can be reduced.
  • a dicing line (sometimes referred to as a scribing line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in a chip shape by dividing a large-area substrate into semiconductor elements will be described. ..
  • a dividing method for example, there is a case where a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, then the dicing line is cut, and the semiconductor device is divided (divided) into a plurality of semiconductor devices.
  • the region where the insulator 283 and the insulator 212 are in contact overlap with the dicing line That is, in the vicinity of the region serving as the dicing line provided on the outer edge of the memory cell having the plurality of transistors 200, the insulator 282, the insulator 280, the insulator 272, the insulator 224, the insulator 222, the insulator 216, and the insulator.
  • An opening is provided in 214.
  • the insulator 212 and the insulator 283 come into contact with each other at the openings provided in the insulator 282, the insulator 280, the insulator 272, the insulator 224, the insulator 222, the insulator 216, and the insulator 214.
  • the adhesion can be improved. For example, it is preferable to use silicon nitride.
  • the transistor 200 can be wrapped by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. Since at least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing the diffusion of oxygen, hydrogen, and water, the semiconductor element shown in the present embodiment is formed. By dividing the substrate for each circuit region, even if it is processed into a plurality of chips, impurities such as hydrogen or water are prevented from being mixed in from the side surface direction of the divided substrate and diffused to the transistor 200. Can be done.
  • the structure can prevent the excess oxygen of the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen of the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which the channel is formed in the transistor 200.
  • the oxygen can reduce the oxygen deficiency of the oxide in which the channel is formed in the transistor 200.
  • the oxide in which the channel is formed in the transistor 200 can be made into an oxide semiconductor having a low defect level density and stable characteristics. That is, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability.
  • the shape of the capacitance element 100 is a planar type, but the storage device shown in the present embodiment is not limited to this.
  • the shape of the capacitance element 100 may be a cylinder type.
  • the storage device shown in FIG. 24 has the same configuration as the semiconductor device shown in FIG. 23 in the configuration below the insulator 150.
  • the capacitive element 100 shown in FIG. 24 is an insulator 150 on the insulator 130, an insulator 142 on the insulator 150, and a conductor 115 arranged in an opening formed in the insulator 150 and the insulator 142.
  • at least a part of the conductor 115, the insulator 145, and the conductor 125 is arranged in the openings formed in the insulator 150 and the insulator 142.
  • the conductor 115 functions as a lower electrode of the capacitance element 100
  • the conductor 125 functions as an upper electrode of the capacitance element 100
  • the insulator 145 functions as a dielectric of the capacitance element 100.
  • the capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched not only on the bottom surface but also on the side surface at the openings of the insulator 150 and the insulator 142, and the capacitance per unit area.
  • the capacity can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitive element 100 can be.
  • an insulator that can be used for the insulator 280 may be used.
  • the insulator 142 preferably functions as an etching stopper when forming an opening of the insulator 150, and an insulator that can be used for the insulator 214 may be used.
  • the shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a quadrangle, a polygonal shape other than the quadrangle, or a polygonal shape with curved corners. , It may be a circular shape including an ellipse.
  • it is preferable that the area where the opening and the transistor 200 overlap is large. With such a configuration, the occupied area of the semiconductor device having the capacitance element 100 and the transistor 200 can be reduced.
  • the conductor 115 is arranged in contact with the insulator 142 and the opening formed in the insulator 150. It is preferable that the upper surface of the conductor 115 substantially coincides with the upper surface of the insulator 142. Further, the lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130.
  • the conductor 115 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the insulator 145 is arranged so as to cover the conductor 115 and the insulator 142.
  • the insulator 145 includes, for example, silicon oxide, silicon nitride, silicon nitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium oxide, and nitride.
  • Hafnium or the like may be used, and it can be provided in a laminated or single layer.
  • an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • a material having a large dielectric strength such as silicon oxide or a material having a high dielectric constant (high-k) for the insulator 145.
  • a laminated structure of a material having a large dielectric strength and a high dielectric constant (high-k) material may be used.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • silicon oxide, silicon oxide, silicon nitride, silicon nitride, silicon nitride added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and pores are used as materials having high dielectric strength.
  • silicon oxide, resin, etc. laminated in the order of silicon nitride was deposited using ALD (SiN x), silicon oxide was deposited using PEALD method (SiO x), silicon nitride was deposited using ALD (SiN x)
  • An insulating film that has been formed can be used. By using such an insulator having a large dielectric strength, the dielectric strength can be improved and electrostatic breakdown of the capacitive element 100 can be suppressed.
  • the conductor 125 is arranged so as to fill the openings formed in the insulator 142 and the insulator 150. Further, the conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153.
  • the conductor 125 is preferably formed by using an ALD method, a CVD method, or the like, and for example, a conductor that can be used for the conductor 205 may be used.
  • the conductor 153 is provided on the insulator 154 and is covered with the insulator 156.
  • a conductor that can be used for the conductor 112 may be used, and as the insulator 156, an insulator that can be used for the insulator 152 may be used.
  • the conductor 153 is in contact with the upper surface of the conductor 140, and functions as a terminal of the capacitive element 100, the transistor 200, or the transistor 300.
  • FIG. 25 shows an example of a semiconductor device (storage device) according to one aspect of the present invention.
  • FIG. 25 is a cross-sectional view of a semiconductor device 290 having a memory device.
  • the semiconductor device 290 shown in FIG. 25 includes a capacitive device 292 in addition to the transistors 200 shown in FIGS. 1A to 1D.
  • FIG. 25 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.
  • the capacitive device 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, and an insulator 272 provided in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b. And a conductor 294 provided so as to cover the insulator 272. That is, the capacitance device 292 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • One of the pair of electrodes of the capacitive device 292, that is, the conductor 242b can also serve as the source electrode of the transistor.
  • the dielectric layer included in the capacitive device 292 can also serve as a protective layer provided on the transistor, that is, an insulator 271 and an insulator 272. Therefore, in the manufacturing process of the capacitive device 292, a part of the manufacturing process of the transistor can also be used, so that the semiconductor device can be highly productive. Further, since one of the pair of electrodes of the capacitive device 292, that is, the conductor 242b also serves as the source electrode of the transistor, it is possible to reduce the area where the transistor and the capacitive device are arranged.
  • the conductor 294 for example, a material that can be used for the conductor 242 may be used.
  • FIGS. 26A, 26B, 27, and 28 the transistor 200 and the capacitance device 292 according to one aspect of the present invention, which are different from those shown in the above ⁇ configuration example of the memory device>.
  • An example of a semiconductor device having the above will be described.
  • the same reference numerals are added to the structures having.
  • the constituent materials of the transistor 200 and the capacitive device 292 the materials described in detail in the previous embodiment and ⁇ configuration example of the memory device> can be used.
  • FIG. 26A is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b in the channel length direction.
  • the capacitive device 292a is provided in contact with the conductor 242a, the insulator 271a provided on the conductor 242a, the upper surface of the insulator 271a, the side surface of the insulator 271a, and the side surface of the conductor 242a. It has an insulator 272 and a conductor 294a provided so as to cover the insulator 272. Further, the capacitance device 292b is provided in contact with the conductor 242b, the insulator 271b provided on the conductor 242b, the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b. It has a body 272 and a conductor 294b provided so as to cover the insulator 272.
  • the semiconductor device 600 has a line-symmetrical configuration with the alternate long and short dash line of A3-A4 as the axis of symmetry.
  • One of the source electrode or the drain electrode of the transistor 200a and one of the source electrode or the drain electrode of the transistor 200b are configured by the conductor 242c.
  • An insulator 271c is provided on the conductor 242c.
  • the conductor 246 that functions as wiring and the conductor 240 that also functions as a plug for connecting the transistor 200a and the transistor 200b are configured.
  • the configuration examples of the semiconductor devices shown in FIGS. 1A to 1D and 25 can be referred to.
  • ⁇ Modification example 2 of memory device >>
  • the transistor 200a, the transistor 200b, the capacitive device 292a, and the capacitive device 292b have been mentioned as configuration examples of the semiconductor device, but the semiconductor device shown in the present embodiment is not limited to this.
  • the semiconductor device 600 and the semiconductor device having the same configuration as the semiconductor device 600 may be connected via a capacitance portion.
  • a semiconductor device having a transistor 200a, a transistor 200b, a capacitive device 292a, and a capacitive device 292b is referred to as a cell.
  • the above-mentioned description relating to the transistor 200a, the transistor 200b, the capacitive device 292a, and the capacitive device 292b can be referred to.
  • FIG. 26B is a cross-sectional view in which a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b and a cell having the same configuration as the semiconductor device 600 are connected via a capacitance section.
  • the conductor 294b that functions as one electrode of the capacitance device 292b of the semiconductor device 600 also serves as one electrode of the capacitance device of the semiconductor device 601 having the same configuration as the semiconductor device 600. It has become.
  • the conductor 294a, which functions as one electrode of the capacitance device 292a of the semiconductor device 600 is on the left side of the semiconductor device 600, that is, in FIG. 26B, one of the capacitance devices of the semiconductor device adjacent to the semiconductor device 600 in the A1 direction. Also serves as an electrode.
  • the cell on the right side of the semiconductor device 601, that is, in FIG. 26B has the same configuration for the cell in the A2 direction.
  • a cell array (also referred to as a memory device layer) can be formed.
  • the distance between adjacent cells can be reduced, so that the projected area of the cell array can be reduced, and high integration is possible.
  • a matrix-like cell array can be configured.
  • the cell area is reduced, and the semiconductor device having the cell array is miniaturized or increased. It can be integrated.
  • FIG. 27 shows a cross-sectional view of a configuration in which n layers of cell array 610 are laminated. As shown in FIG. 27, by stacking a plurality of cell cells (series cell array 610_1 to cell array 610_n), cells can be integrated and arranged without increasing the occupied area of the cell array. That is, a 3D cell array can be constructed.
  • FIG. 28 shows an example in which the memory unit 470 has a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layer 415_1 to memory device layer 415_4).
  • the memory device layer 415_1 to the memory device layer 415_1 each have a plurality of memory devices 420.
  • the memory device 420 is electrically connected to the memory device 420 of the different memory device layers 415 and the transistor 200T of the transistor layer 413 via the conductor 424 and the conductor 205.
  • the memory unit 470 is sealed by the insulator 212, the insulator 214, the insulator 282, and the insulator 283 (for convenience, hereinafter referred to as a sealing structure).
  • An insulator 274 is provided around the insulator 283. Further, the insulator 274, the insulator 283, and the insulator 212 are provided with a conductor 440, which is electrically connected to the element layer 411.
  • an insulator 280 is provided inside the sealing structure.
  • the insulator 280 has a function of releasing oxygen by heating.
  • the insulator 280 has an excess oxygen region.
  • the insulator 212 and the insulator 283 are materials having a high blocking property against hydrogen. Further, the insulator 214 and the insulator 282 are preferably materials having a function of capturing hydrogen or fixing hydrogen.
  • the material having a high blocking property against hydrogen includes silicon nitride, silicon nitride, and the like.
  • Examples of the material having a function of capturing hydrogen or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • the crystal structure of the materials used for the insulator 212, the insulator 214, the insulator 282, and the insulator 283 is not particularly limited, but may be an amorphous or crystalline structure.
  • Amorphous aluminum oxide may capture and adhere more hydrogen than highly crystalline aluminum oxide.
  • the excess oxygen in the insulator 280 can be considered as the following model for the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.
  • Hydrogen present in the oxide semiconductor diffuses into other structures via the insulator 280 in contact with the oxide semiconductor.
  • excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, and diffuses in the insulator 280.
  • a hydrogen atom having an OH bond reaches a material having a function of capturing hydrogen or fixing hydrogen (typically, an insulator 282)
  • the hydrogen atom becomes an atom in the insulator 282 (for example, an insulator 282). It reacts with oxygen atoms bonded to metal atoms, etc.) and is captured or fixed in the insulator 282.
  • an insulator 280 having excess oxygen is formed on an oxide semiconductor, and then an insulator 282 is formed. After that, it is preferable to perform heat treatment. Specifically, the heat treatment is carried out in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350 ° C. or higher, preferably 400 ° C. or higher.
  • the heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.
  • hydrogen in the oxide semiconductor can be diffused to the outside through the insulator 280 and the insulator 282. That is, the absolute amount of the oxide semiconductor and hydrogen existing in the vicinity of the oxide semiconductor can be reduced.
  • an insulator 283 is formed. Since the insulator 283 is a material having a function of having a high blocking property against hydrogen, hydrogen diffused to the outside or hydrogen existing on the outside is transferred to the inside, specifically, an oxide semiconductor or the insulator 280. It can be suppressed from entering the side.
  • the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layer 415_1 to the memory device layer 415_3 are formed. Further, when hydrogen is diffused outward by the above heat treatment, hydrogen is diffused above or in the lateral direction of the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layer 415_1 to the memory device layer 415_3 are formed, hydrogen is diffused upward or laterally.
  • the above-mentioned sealing structure is formed by adhering the insulator 212 and the insulator 283.
  • a so-called multi-chamber device having a plurality of processing chambers capable of continuously forming different film types.
  • film formation processing such as sputtering, CVD, and ALD can be performed.
  • a gas supply device, a gas purification device connected to the gas supply device, a vacuum pump, a target, and the like can be connected to the sputtering chamber.
  • the sputtering chamber may be configured so that the ionization sputtering method can be used. Further, the bias sputtering method may be used.
  • substrate cleaning treatment plasma treatment, reverse sputtering treatment, etching treatment, ashing treatment, heat treatment and the like may be performed.
  • the insulator, the conductor, and the semiconductor film can be formed without opening to the atmosphere.
  • a typical example of the semiconductor film used in one aspect of the present invention is an oxide semiconductor film.
  • an oxide semiconductor film having a low impurity concentration and a low defect level density can produce a transistor having excellent electrical characteristics.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has few carrier sources, the carrier density can be lowered. Therefore, the transistor in which the channel formation region is formed in the oxide semiconductor film is unlikely to have an electrical characteristic (also referred to as normal on) in which the threshold voltage is negative. Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low.
  • the off current is extremely small, even with an element with a channel width channel length L of 10 ⁇ m at 1 ⁇ 10 6 [mu] m, and a source electrode
  • the voltage between the drain electrodes is in the range of 1 V to 10 V, it is possible to obtain the characteristic that the off current is below the measurement limit of the semiconductor parameter analyzer, that is, 1 ⁇ 10 -13 A or less.
  • Typical examples of impurities in the oxide semiconductor film include water and hydrogen. Further, in the present specification and the like, reducing or removing water and hydrogen from the oxide semiconductor film may be referred to as dehydrogenation or dehydrogenation. Further, the addition of oxygen to the oxide semiconductor film may be referred to as oxygenation, and the state of being oxygenated and having excess oxygen than the stoichiometric composition may be referred to as an excess oxygen state. ..
  • the oxide semiconductor, the insulator or conductor located in the lower layer of the oxide semiconductor, and the insulator or conductor located in the upper layer of the oxide semiconductor are made of different films without opening to the atmosphere.
  • By continuously forming the seeds it is possible to form an oxide semiconductor film having a substantially high purity and intrinsicity in which the concentration of impurities (particularly hydrogen and water) is reduced.
  • FIG. 29 the details of the configuration example of the device that can be used when manufacturing the semiconductor device of one aspect of the present invention will be described with reference to FIG. 29.
  • a semiconductor film, an insulator or a conductor located in the lower layer of the semiconductor film, and an insulator or a conductor located in the upper layer of the semiconductor film can be continuously formed. it can. Therefore, impurities (particularly hydrogen and water) that can enter the semiconductor film can be suppressed.
  • FIG. 29 schematically shows a top view of the single-wafer type multi-chamber device 4000.
  • the device 4000 carries in the substrate from the atmospheric side substrate supply chamber 4010 and the atmospheric side substrate supply chamber 4010 to the atmospheric side substrate transfer chamber 4012, and reduces the pressure in the room from atmospheric pressure or reduces the pressure in the room.
  • the load lock chamber 4020a for switching from to atmospheric pressure and the unload lock chamber 4020b for carrying out the substrate and switching the pressure in the room from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, and transporting the substrate in vacuum.
  • each of the plurality of processing rooms can perform different processing in parallel. Therefore, a laminated structure of different film types can be easily produced. It should be noted that parallel processing can be performed up to the number of processing rooms.
  • the device 4000 shown in FIG. 29 is a device having seven processing chambers. Therefore, using one device (also referred to as in-situ in the present specification), seven film forming processes can be continuously performed without releasing to the atmosphere.
  • the number of laminated structures that can be produced without opening to the atmosphere is not necessarily the same as the number of processing chambers.
  • the layers can be provided in one processing chamber, so that a laminated structure having a larger number of laminated structures than the number of installed processing chambers should be produced. Can be done.
  • the atmosphere side substrate supply chamber 4010 includes a cassette port 4014 for accommodating the substrate and an alignment port 4016 for aligning the substrate.
  • the cassette ports 4014 may have a plurality of (for example, three in FIG. 29).
  • the atmospheric board transport chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber 4020b.
  • the transfer chamber 4029 is connected to the load lock chamber 4020a, the unload lock chamber 4020b, the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4024a, and the processing chamber 4024b.
  • the transfer chamber 4030a and the transfer chamber 4030b are connected to the transfer chamber 4029 and the transfer chamber 4039.
  • the transfer chamber 4039 is connected to the transfer chamber 4030a, the transfer chamber 4030b, the processing chamber 4034a, the processing chamber 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e.
  • a gate valve 4028 or a gate valve 4038 is provided at the connection portion of each chamber, and each chamber is independently held in a vacuum state except for the atmospheric side substrate supply chamber 4010 and the atmospheric side substrate transport chamber 4012. can do.
  • the atmospheric board transfer chamber 4012 has a transfer robot 4018.
  • the transport chamber 4029 has a transport robot 4026, and the transport chamber 4039 has a transport robot 4036.
  • the transfer robot 4018, the transfer robot 4026, and the transfer robot 4036 have a plurality of movable parts and an arm for holding the substrate, and can convey the substrate to each chamber.
  • the number of transport chambers, processing chambers, load lock chambers, unload lock chambers and transfer chambers is not limited to the above, and an optimum number can be appropriately provided according to the installation space and process conditions.
  • the transport chamber 4030a and the transport chamber 4030b are arranged in parallel between the transport chamber 4029 and the transport chamber 4039. ..
  • the step of the transfer robot 4026 carrying the substrate into the transfer chamber 4030a and the step of the transfer robot 4036 carrying the substrate into the transfer chamber 4030b can be performed at the same time. It can be carried out. Further, the step of the transfer robot 4026 carrying out the substrate from the transfer chamber 4030b and the step of the transfer robot 4036 carrying out the substrate from the transfer chamber 4030a can be performed at the same time. That is, the production efficiency is improved by driving a plurality of transfer robots at the same time.
  • FIG. 29 an example in which one transport chamber has one transport robot and is connected to a plurality of processing chambers is shown, but the structure is not limited to this structure.
  • a plurality of transfer robots may be provided for one transfer room.
  • the transfer chamber 4029 and the transfer chamber 4039 are connected to the vacuum pump and the cryopump via a valve. Therefore, the transfer chamber 4029 and the transfer chamber 4039 use a vacuum pump to evacuate from atmospheric pressure to a low vacuum or a medium vacuum (around several hundred Pa to 0.1 Pa), then switch the valve and use a cryopump. It can be evacuated from medium vacuum to high vacuum or ultra-high vacuum (about 0.1 Pa to 1 ⁇ 10 -7 Pa).
  • cryopumps may be connected in parallel to one transport chamber.
  • Regeneration is a process of releasing molecules (or atoms) stored in a cryopump.
  • Cryopumps should be regenerated on a regular basis because the exhaust capacity will decrease if molecules (or atoms) are stored too much.
  • the processing chamber 4024a, the processing chamber 4024b, the processing chamber 4034a, the processing chamber 4034b, the processing chamber 4034c, the processing chamber 4034d, and the processing chamber 4034e can each perform different processing in parallel. That is, in each processing chamber, the installed substrate can be subjected to film formation treatment, heat treatment, or plasma treatment by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, in the treatment room, the film formation treatment may be performed after the heat treatment or the plasma treatment.
  • the substrate can be transported between treatments without being exposed to the atmosphere, so that it is possible to suppress the adsorption of impurities on the substrate. Further, since the film formation treatment, the heat treatment, or the plasma treatment of different film types can be performed for each treatment chamber, the order of the film formation and the heat treatment can be freely constructed.
  • each processing chamber may be connected to a vacuum pump via a valve.
  • a vacuum pump for example, a dry pump, a mechanical booster pump, or the like can be used.
  • each processing chamber may be connected to a power source capable of generating plasma.
  • a power source capable of generating plasma.
  • a DC power source an AC power source, and a high frequency (RF, microwave, etc.) power source may be provided.
  • a pulse generator may be connected to the DC power supply.
  • processing chamber may be connected to the gas purification device via the gas supply device.
  • the number of gas supply devices and gas purification devices may be as many as the number of gas types.
  • the processing chamber is bonded to a target, a backing plate connected to the target, and a cathode arranged to face the target via the backing plate.
  • a board and a substrate stage may be provided.
  • the substrate stage may include a substrate holding mechanism for holding the substrate, a back surface heater for heating the substrate from the back surface, and the like.
  • the substrate stage is held in a substantially vertical state with respect to the floor surface at the time of film formation, and is held in a substantially horizontal state with respect to the floor surface at the time of substrate delivery.
  • the substrate stage substantially perpendicular to the floor surface, the probability that dust or particles that may be mixed during film formation adheres to the substrate can be suppressed rather than being kept in a horizontal state.
  • the angle of the substrate stage with respect to the floor surface is preferably 80 ° or more and less than 90 °. ..
  • the configuration of the board stage is not limited to the above configuration.
  • the substrate stage may be configured to be substantially horizontal to the floor surface.
  • the target may be arranged below the substrate stage, and the substrate may be arranged between the target and the substrate stage.
  • the substrate stage may be provided with a jig for fixing the substrate so that the substrate does not fall, or a mechanism for fixing the substrate.
  • the protective plate in the processing chamber, it is possible to suppress the accumulation of particles sputtered from the target in an unnecessary region. Further, it is desirable that the adhesive plate is processed so that the accumulated sputtering particles do not peel off. For example, a blast treatment that increases the surface roughness, or unevenness may be provided on the surface of the protective plate.
  • the backing plate has a function of holding the target, and the cathode has a function of applying a voltage (for example, a negative voltage) to the target.
  • a voltage for example, a negative voltage
  • a conductor, an insulator, or a semiconductor can be used as the target.
  • the target is an oxide semiconductor such as a metal oxide
  • an oxide semiconductor film can be formed in the processing chamber.
  • a nitride semiconductor film can be formed by using nitrogen gas as the film forming gas.
  • each processing chamber may be connected to a gas supply device via a gas heating mechanism.
  • the gas heating mechanism is connected to the gas purification device via a gas supply device.
  • a gas having a dew point of ⁇ 80 ° C. or lower, preferably ⁇ 100 ° C. or lower, more preferably ⁇ 120 ° C. or lower can be used, and for example, oxygen gas, nitrogen gas, and rare gas. (Argon gas, etc.) can be used.
  • the gas heating mechanism can heat the gas introduced into the treatment chamber to 40 ° C. or higher and 400 ° C. or lower.
  • the number of gas heating mechanisms, gas supply devices, and gas purification devices may be as many as the number of gas types.
  • each processing chamber may be connected to a turbo molecular pump and a vacuum pump via a valve. Further, a cryotrap may be provided in each processing chamber.
  • the cryotrap is a mechanism that can adsorb molecules (or atoms) with a relatively high melting point such as water. Turbo molecular pumps are excellent in productivity because they stably exhaust large-sized molecules (or atoms) and maintenance frequency is low, but they also have low hydrogen and water exhaust capacity. Therefore, a cryotrap can be used to increase the exhaust capacity for water and the like.
  • the temperature of the cryotrap refrigerator is 100 K or less, preferably 80 K or less. Further, when the cryotrap has a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because efficient exhaust can be performed. For example, the temperature of the first-stage refrigerator may be 100 K or less, and the temperature of the second-stage refrigerator may be 20 K or less.
  • the exhaust method of the processing chamber is not limited to this, and may have the same configuration as the exhaust method (exhaust method of the cryopump and the vacuum pump) shown in the connected transport chamber.
  • the exhaust method of the transport chamber may be the same as that of the processing chamber (exhaust method of the turbo molecular pump and the vacuum pump).
  • a vacuum pump and a cryotrap may be combined.
  • the exhaust method provided in the processing chamber for forming the oxide semiconductor film preferably has at least a function of adsorbing water molecules.
  • the partial pressure of hydrogen molecules is 1 ⁇ 10 ⁇ 2 Pa or less and the partial pressure of water molecules is 1 ⁇ 10 -4 Pa or less.
  • the pressure in the standby state of the processing chamber for forming the oxide semiconductor film is 8.0 ⁇ 10 -5 Pa or less, preferably 5.0 ⁇ 10 -5 Pa or less, more preferably 1.0 ⁇ 10 -5. It is less than or equal to Pa.
  • the values of the above-mentioned partial pressures of hydrogen molecules and water molecules are both values when the processing chamber for sputtering is in the standby state and when the film formation state (plasma is in the discharge state). ..
  • the total pressure and partial pressure of the processing chamber can be measured using a mass spectrometer.
  • a mass spectrometer for example, a quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.
  • the concentration of impurities in the oxide semiconductor film formed can be reduced. ..
  • a part of the structure of the transistor 200 shown in the previous embodiment can be produced by a laminated structure in which a film is continuously formed in-situ. Can be done.
  • the insulator 212, the insulator 214, and the insulator 216 are continuously formed by using the apparatus 4000. Further, the oxide film 230A, the oxide film 230B, and the oxide film 243A are continuously formed by using the apparatus 4000. Further, the conductive film 242A, the insulating film 271A, and the conductive film 248A are continuously formed by using the apparatus 4000.
  • the insulator 212, the insulator 214, and the insulator 216 can be continuously formed without being released to the atmosphere. Further, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be continuously formed without being released to the atmosphere. Further, the conductive film 242A, the insulating film 271A, and the conductive film 248A can be continuously formed without being released to the atmosphere.
  • the processing chamber when heat treatment is performed in the processing chamber, the processing chamber may be provided with a plurality of heating stages capable of storing the substrate.
  • the heating stage may have a multi-stage configuration. By increasing the number of heating stages, a plurality of substrates can be heat-treated at the same time, so that productivity can be improved.
  • the heating mechanism that can be used in the processing chamber may be, for example, a heating mechanism that heats using a resistance heating element or the like. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas.
  • RTA Rapid Thermal Anneal
  • GRTA Rapid Thermal Anneal
  • LRTA Heats an object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps.
  • GRTA heat-treats using a high-temperature gas.
  • an inert gas is used as the gas.
  • the load lock chamber 4020a may be provided with a substrate delivery stage, a backside heater that heats the substrate from the back surface, and the like.
  • the load lock chamber 4020a raises the pressure from the decompressed state to the atmosphere, and when the pressure in the load lock chamber 4020a reaches atmospheric pressure, the substrate transfer stage is transferred from the transfer robot 4018 provided in the atmospheric side substrate transfer chamber 4012 to the substrate. To receive. After that, the load lock chamber 4020a is evacuated to reduce the pressure, and then the transfer robot 4026 provided in the transfer chamber 4029 receives the substrate from the substrate transfer stage.
  • the load lock chamber 4020a is connected to the vacuum pump and the cryopump via a valve.
  • the unload lock chamber 4020b may have the same configuration as the load lock chamber 4020a.
  • the transfer robot 4018 can transfer the substrate between the cassette port 4014 and the load lock chamber 4020a.
  • a mechanism for suppressing the mixing of dust or particles such as a HEPA filter (High Effectivey Particulate Air Filter) may be provided above the atmospheric side substrate transport chamber 4012 and the atmospheric side substrate supply chamber 4010.
  • the cassette port 4014 can store a plurality of boards.
  • a laminated structure having a semiconductor film can be produced by continuous film formation. Therefore, it is possible to produce a semiconductor film having a low defect level density while suppressing impurities such as hydrogen and water incorporated into the semiconductor film.
  • a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) according to one aspect of the present invention.
  • a storage device to which a capacitive element is applied (hereinafter, may be referred to as an OS memory device) will be described.
  • the OS memory device is a storage device having at least a capacitance element and an OS transistor that controls charging / discharging of the capacitance element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.
  • FIG. 30A shows an example of the configuration of the OS memory device.
  • the storage device 1400 has a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a writing circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell.
  • the wiring is the wiring connected to the memory cell of the memory cell array 1470, and will be described in detail later.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 has, for example, a row decoder, a word line driver circuit, and the like, and can select the row to be accessed.
  • a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the storage device 1400 from the outside as power supply voltages. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.
  • the control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for row decoders and column decoders.
  • the control signal CE is a chip enable signal
  • the control signal WE is a write enable signal
  • the control signal RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.
  • the memory cell array 1470 has a plurality of memory cell MCs arranged in a matrix and a plurality of wirings.
  • the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cell MCs in a row, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cell MCs in one row, and the like.
  • FIG. 30A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap under the memory cell array 1470.
  • FIGS. 31A to 31H An example of a memory cell configuration applicable to the above-mentioned memory cell MC will be described with reference to FIGS. 31A to 31H.
  • [DOSRAM] 31A to 31C show an example of a circuit configuration of a DRAM memory cell.
  • a DRAM using a memory cell of a 1OS transistor and 1 capacitance element type may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • the memory cell 1471 shown in FIG. 31A has a transistor M1 and a capacitance element CA.
  • the transistor M1 has a gate (sometimes called a top gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1. Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL when writing and reading data.
  • the wiring BGL functions as wiring for applying a potential to the back gate of the transistor M1.
  • the threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell 1471 shown in FIG. 31A corresponds to the storage device shown in FIG. 25. That is, the transistor M1 corresponds to the transistor 200, and the capacitive element CA corresponds to the capacitive device 292.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 31B.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 having no back gate, as in the memory cell 1473 shown in FIG. 31C.
  • a transistor 200 can be used as the transistor M1 and a capacitance element 100 can be used as the capacitance element CA.
  • an OS transistor as the transistor M1
  • the leakage current of the transistor M1 can be made very small. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cells can be reduced. Moreover, the refresh operation of the memory cell can be eliminated. Further, since the leak current is very small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the holding capacity of the memory cell can be reduced.
  • [NOSRAM] 31D to 31G show a circuit configuration example of a gain cell type memory cell having two transistors and one capacitance element.
  • the memory cell 1474 shown in FIG. 31D includes a transistor M2, a transistor M3, and a capacitance element CB.
  • the transistor M2 has a top gate (sometimes referred to simply as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2. Is connected to the wiring BGL.
  • the second terminal of the capacitive element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitance element CB. It is preferable to apply a low level potential to the wiring CAL during data writing, data retention, and data reading.
  • the wiring BGL functions as wiring for applying an electric potential to the back gate of the transistor M2.
  • the threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.
  • the memory cell 1474 shown in FIG. 31D corresponds to the storage device shown in FIG. 23. That is, the transistor M2 is in the transistor 200, the capacitive element CB is in the capacitive element 100, the transistor M3 is in the transistor 300, the wiring WBL is in the wiring 1003, the wiring WOL is in the wiring 1004, the wiring BGL is in the wiring 1006, and the wiring CAL is in the wiring 1006.
  • the wiring RBL corresponds to the wiring 1002
  • the wiring SL corresponds to the wiring 1001.
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 31E.
  • the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 31F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL, as in the memory cell 1477 shown in FIG. 31G.
  • a transistor 200 can be used as the transistor M2
  • a transistor 300 can be used as the transistor M3
  • a capacitance element 100 can be used as the capacitance element CB.
  • OS transistor an OS transistor
  • the leakage current of the transistor M2 can be made very small.
  • the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cells can be reduced.
  • the refresh operation of the memory cell can be eliminated.
  • the leak current is very small, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in the channel forming region (hereinafter, may be referred to as a Si transistor).
  • the conductive type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a readout transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by stacking the transistor M3 on the transistor M3, so that the occupied area of the memory cell can be reduced and the storage device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • an OS transistor is used for the transistor M2 and the transistor M3, the circuit can be configured by using only the n-type transistor in the memory cell array 1470.
  • FIG. 31H shows an example of a gain cell type memory cell having a 3-transistor and 1-capacity element.
  • the memory cell 1478 shown in FIG. 31H includes transistors M4 to M6 and a capacitive element CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL.
  • Wiring GNDL is a wiring that gives a low level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
  • Transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL.
  • the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not have to have a back gate.
  • the transistor M5 and the transistor M6 may be an n-channel Si transistor or a p-channel Si transistor, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured by using only n-type transistors.
  • the transistor 200 can be used as the transistor M4
  • the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitance element 100 can be used as the capacitance element CC.
  • the leakage current of the transistor M4 can be made very small.
  • the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in the present embodiment are not limited to the above.
  • the arrangement or function of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.
  • FIG. 32 shows various storage devices for each layer.
  • a storage device located in the upper layer is required to have a faster access speed, and a storage device located in the lower layer is required to have a larger storage capacity and a higher recording density.
  • FIG. 32 shows, in order from the top layer, a memory, a SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory that are mixedly loaded as registers in an arithmetic processing unit such as a CPU.
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • 3D NAND memory that are mixedly loaded as registers in an arithmetic processing unit such as a CPU.
  • the memory that is mixedly loaded as a register in an arithmetic processing unit such as a CPU is used for temporary storage of arithmetic results, and therefore is frequently accessed from the arithmetic processing unit. Therefore, an operation speed faster than the storage capacity is required.
  • the register also has a function of holding setting information of the arithmetic processing unit.
  • SRAM is used, for example, for cache.
  • the cache has a function of duplicating and holding a part of the information held in the main memory. By replicating frequently used data to the cache, the access speed to the data can be increased.
  • DRAM is used, for example, in main memory.
  • the main memory has a function of holding programs and data read from the storage.
  • the recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm 2 .
  • the 3D NAND memory is used, for example, for storage.
  • the storage has a function of holding data that needs to be stored for a long period of time and various programs used in the arithmetic processing unit. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density.
  • the recording density of the storage device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 .
  • the storage device of one aspect of the present invention has a high operating speed and can retain data for a long period of time.
  • the storage device of one aspect of the present invention can be suitably used as a storage device located in the boundary area 901 including both the layer in which the cache is located and the layer in which the main memory is located.
  • the storage device of one aspect of the present invention can be suitably used as a storage device located in the boundary area 902 including both the layer in which the main memory is located and the layer in which the storage is located.
  • FIGS. 33A and 33B An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to FIGS. 33A and 33B.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • a technique for integrating a plurality of circuits (systems) on one chip in this way may be referred to as a system on chip (SoC).
  • SoC system on chip
  • the chip 1200 has a CPU 1211, GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • a bump (not shown) is provided on the chip 1200, and as shown in FIG. 33B, the chip 1200 is connected to the first surface of a printed circuit board (Printed Circuit Board: PCB) 1201. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • PCB printed Circuit Board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM shown in the previous embodiment can be used for the DRAM 1221.
  • the NO SRAM shown in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200.
  • the above-mentioned NOSRAM or DOSRAM can be used.
  • GPU1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and product-sum calculation. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, image processing and product-sum calculation can be executed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memory of the CPU 1211 and the GPU 1212, And after the calculation on the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum calculation circuit may be provided in the analog calculation unit 1213.
  • the memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222.
  • the interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface High-Definition Multimedia Interface
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, it is not necessary to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201, the DRAM 1221 provided with the chip 1200 having the GPU 1212, and the motherboard 1203 provided with the flash memory 1222 can be referred to as the GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Further, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (take-out) game machines.
  • a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief network (DEM) are provided by a product-sum calculation circuit using GPU1212. Since a method such as DBN) can be executed, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • the present embodiment shows an example of an electronic component and an electronic device in which the storage device and the like shown in the above embodiment are incorporated.
  • FIG. 34A shows a perspective view of the electronic component 700 and the substrate on which the electronic component 700 is mounted (mounting substrate 704).
  • the electronic component 700 shown in FIG. 34A has a storage device 720 in the mold 711. In FIG. 34A, a part is omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 720 by a wire 714.
  • the electronic component 700 is mounted on, for example, the printed circuit board 702. A plurality of such electronic components are combined and each is electrically connected on the printed circuit board 702 to complete the mounting board 704.
  • the storage device 720 has a drive circuit layer 721 and a storage circuit layer 722.
  • FIG. 34B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of SiP (System in package) or MCM (Multi Chip Module).
  • the electronic component 730 is provided with an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.
  • the electronic component 730 shows an example in which the storage device 720 is used as a wideband memory (HBM: High Bandwidth Memory). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.
  • HBM High Bandwidth Memory
  • the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrode provided on the package substrate 732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode.
  • TSV Three Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
  • the reliability is unlikely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink may be provided so as to be overlapped with the electronic component 730.
  • the heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the heights of the storage device 720 and the semiconductor device 735 are the same.
  • an electrode 733 may be provided on the bottom of the package substrate 732.
  • FIG. 34B shows an example in which the electrode 733 is formed of solder balls.
  • BGA Ball Grid Array
  • the electrode 733 may be formed of a conductive pin.
  • PGA Peripheral Component Interconnect
  • the electronic component 730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Band-GPU
  • PGA Stimble Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFNeged
  • the semiconductor device shown in the above embodiment is, for example, a storage device for various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording / playback devices, navigation systems, etc.).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • 35A to 35E schematically show some configuration examples of the removable storage device.
  • the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 35A is a schematic diagram of the USB memory.
  • the USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like.
  • FIG. 35B is a schematic view of the appearance of the SD card
  • FIG. 35C is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111 and a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 1113.
  • data on the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1114 or the like.
  • FIG. 35D is a schematic view of the appearance of the SSD
  • FIG. 35E is a schematic view of the internal structure of the SSD.
  • the SSD 1150 has a housing 1151, a connector 1152 and a substrate 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1154 or the like.
  • the semiconductor device according to one aspect of the present invention can be used for a processor such as a CPU or GPU, or a chip.
  • 36A to 36H show specific examples of an electronic device including a processor such as a CPU or GPU or a chip according to one aspect of the present invention.
  • the GPU or chip according to one aspect of the present invention can be mounted on various electronic devices.
  • electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage (electronic signage), and large game machines such as pachinko machines.
  • digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be mentioned.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one aspect of the present invention may have an antenna.
  • the display unit can display images, information, and the like.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, It may have the ability to measure voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).
  • the electronic device of one aspect of the present invention can have various functions. For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • 36A to 36H show examples of electronic devices.
  • FIG. 36A illustrates a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5100 has a housing 5101 and a display unit 5102, and as an input interface, a touch panel is provided in the display unit 5102 and buttons are provided in the housing 5101.
  • the information terminal 5100 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, and recognizes characters and figures input by the user on the touch panel provided in the display unit 5102.
  • Examples include an application displayed on the display unit 5102, an application for performing biometric authentication such as a fingerprint and a voice print, and the like.
  • FIG. 36B illustrates the notebook type information terminal 5200.
  • the notebook-type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.
  • the notebook-type information terminal 5200 can execute an application using artificial intelligence by applying the chip of one aspect of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software. Further, by using the notebook type information terminal 5200, it is possible to develop a new artificial intelligence.
  • a smartphone and a notebook-type information terminal are taken as examples of electronic devices, which are shown in FIGS. 36A and 36B, respectively, but information terminals other than the smartphone and the notebook-type information terminal can be applied.
  • information terminals other than smartphones and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop-type information terminals, workstations, and the like.
  • FIG. 36C shows a portable game machine 5300, which is an example of a game machine.
  • the portable game machine 5300 has a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like.
  • the housing 5302 and the housing 5303 can be removed from the housing 5301.
  • the connection unit 5305 provided in the housing 5301 to another housing (not shown)
  • the video output to the display unit 5304 can be output to another video device (not shown). it can.
  • the housing 5302 and the housing 5303 can each function as operation units. This allows a plurality of players to play the game at the same time.
  • the chips shown in the previous embodiment can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.
  • FIG. 36D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
  • a low power consumption game machine can be realized by applying the GPU or chip of one aspect of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the portable game machine 5300 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are defined by the program that the game has, but by applying artificial intelligence to the handheld game machine 5300.
  • Expressions that are not limited to game programs are possible. For example, it is possible to express what the player asks, the progress of the game, the time, and the behavior of the characters appearing in the game.
  • the game player can be constructed anthropomorphically by artificial intelligence. Therefore, by setting the opponent as a game player by artificial intelligence, even one player can play the game. You can play the game.
  • FIGS. 36C and 36D show a portable game machine and a stationary game machine as an example of the game machine
  • the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a throwing machine for batting practice installed in a sports facility, and the like. Can be mentioned.
  • the GPU or chip of one aspect of the present invention can be applied to a large computer.
  • FIG. 36E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 36F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.
  • the supercomputer 5500 has a rack 5501 and a plurality of rack mount type computers 5502.
  • the plurality of computers 5502 are stored in the rack 5501. Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPU or chip described in the above embodiment can be mounted on the substrate.
  • the supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, it is necessary to process a huge amount of calculations at high speed, so power consumption is high and the heat generated by the chip is large.
  • the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer having low power consumption can be realized. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • FIGS. 36E and 36F show a supercomputer as an example of a large computer
  • the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this.
  • Examples of the large-scale computer to which the GPU or chip of one aspect of the present invention is applied include a computer (server) that provides services, a large-scale general-purpose computer (mainframe), and the like.
  • the GPU or chip of one aspect of the present invention can be applied to a moving vehicle and around the driver's seat of the vehicle.
  • FIG. 36G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body.
  • the display panel 5701 attached to the dashboard, the display panel 5702, the display panel 5703, and the display panel 5704 attached to the pillar are shown.
  • the display panel 5701 to the display panel 5703 can provide various other information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, an air conditioner setting, and the like.
  • the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved.
  • the display panel 5701 to 5703 can also be used as a lighting device.
  • the display panel 5704 can supplement the field of view (blind spot) blocked by the pillars by projecting an image from an image pickup device (not shown) provided in the automobile. That is, by displaying the image from the image pickup device provided on the outside of the automobile, the blind spot can be supplemented and the safety can be enhanced. In addition, by projecting an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence
  • the chip can be used, for example, in an automatic driving system of an automobile.
  • the chip can be used in a system for road guidance, danger prediction, and the like.
  • the display panel 5701 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects may include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc., and the chip of one aspect of the present invention is applied to these moving objects. Therefore, a system using artificial intelligence can be provided.
  • FIG. 36H shows an electric freezer / refrigerator 5800 which is an example of an electric appliance.
  • the electric refrigerator / freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric freezer / refrigerator 5800 having artificial intelligence can be realized.
  • the electric freezer / refrigerator 5800 has a function of automatically generating a menu based on the foodstuffs stored in the electric freezer / refrigerator 5800 and the expiration date of the foodstuffs, and is stored in the electric freezer / refrigerator 5800. It can have a function of automatically adjusting the temperature according to the food.
  • electric refrigerators and freezers have been described as an example of electric appliances
  • other electric appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners including air conditioners. Examples include washing machines, dryers, and audiovisual equipment.
  • the electronic device described in the present embodiment the function of the electronic device, the application example of artificial intelligence, its effect, etc. can be appropriately combined with the description of other electronic devices.
  • Body 470 memory unit, 600 semiconductor device, 601 semiconductor device, 610 cell array, 610_n cell array, 610_1 cell array, 700 electronic components, 702 printed board, 704 mounting board, 711 mold, 712 land, 713 electrode pad, 714 wire, 720 memory Equipment, 721 drive circuit layer, 722 storage circuit layer, 730 electronic components, 731 interposer, 732 package board, 733 electrodes, 735 semiconductor devices, 901 boundary area, 902 boundary area, 1001 wiring, 1002 wiring, 1003 wiring, 1004 wiring, 1005 wiring, 1006 wiring

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JP2016201541A (ja) * 2015-04-13 2016-12-01 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2017147445A (ja) * 2016-02-17 2017-08-24 株式会社半導体エネルギー研究所 半導体装置、電子機器
WO2018150295A1 (ja) * 2017-02-15 2018-08-23 株式会社半導体エネルギー研究所 半導体装置
WO2018178793A1 (ja) * 2017-03-29 2018-10-04 株式会社半導体エネルギー研究所 半導体装置、半導体装置の作製方法

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WO2023199181A1 (ja) * 2022-04-15 2023-10-19 株式会社半導体エネルギー研究所 積層体の作製方法、及び半導体装置の作製方法

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