WO2020228104A1 - 漏电保护器的自检芯片 - Google Patents

漏电保护器的自检芯片 Download PDF

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Publication number
WO2020228104A1
WO2020228104A1 PCT/CN2019/093002 CN2019093002W WO2020228104A1 WO 2020228104 A1 WO2020228104 A1 WO 2020228104A1 CN 2019093002 W CN2019093002 W CN 2019093002W WO 2020228104 A1 WO2020228104 A1 WO 2020228104A1
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Prior art keywords
signal
self
counter
chip
trip
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PCT/CN2019/093002
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English (en)
French (fr)
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韩雁
于默涵
程智杰
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Zhejiang University
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Zhejiang University
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Priority to US17/610,282 priority Critical patent/US11581726B2/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/26—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents
    • H02H3/32—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors
    • H02H3/33—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors using summation current transformers
    • H02H3/334—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors using summation current transformers with means to produce an artificial imbalance for other protection or monitoring reasons or remote control
    • H02H3/335—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors using summation current transformers with means to produce an artificial imbalance for other protection or monitoring reasons or remote control the main function being self testing of the device
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/26—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents
    • H02H3/32—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors
    • H02H3/325—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors involving voltage comparison
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/04—Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned
    • H02H3/044—Checking correct functioning of protective arrangements, e.g. by simulating a fault

Definitions

  • the invention relates to the field of integrated circuit design, in particular to a self-check chip for regular self-check of a leakage protector.
  • the leakage protector has become an indispensable auxiliary appliance in production and life.
  • the leakage protector with fault operation makes the user lose the protection of electric shock and electric fire. Since the regular inspection of the current leakage protector requires manual operation, the power supply will be interrupted during the operation, and more than 90% of users do not perform periodic tripping self-checks. The risk of abnormal operation of the leakage protector cannot be ignored.
  • the present invention provides a self-checking chip of a leakage protector.
  • a self-check chip of a leakage protector which is characterized in that it comprises:
  • Power-on reset circuit used to reset the self-check chip after power-on
  • the reference voltage module provides a reference voltage for the comparator module
  • Bias circuit which provides DC bias for reference voltage module, comparator module and ring oscillator
  • Comparator module used to monitor the open circuit condition of the trip coil, the change of the anode voltage of the thyristor and generate the power frequency clock;
  • Ring oscillator providing clock for counting module and digital processing module
  • Counting module used to generate self-check signal, leakage trigger signal, PHASE pin detection signal, count module itself and reset signal of digital processing module;
  • Trip enable signal generation module used to generate trip enable signal
  • Digital processing module used to judge whether the function of the leakage protector chip, mutual inductance coil, thyristor, trip coil, PHASE pin is normal, and any device in the leakage protector chip, mutual inductance coil, thyristor, trip coil, PHASE pin exists Failure, output termination signal.
  • the counting module includes 1s counter, 11min counter, 60ms counter, and 100ms counter.
  • the 1s counter is used to perform the first self-check 1s after the first power-on; the power-on reset signal starts the 1s counter, and after the 1s counter completes counting, it generates a leakage trigger signal to trigger the FAULT TEST pin to output a high level, turn on the transistor, and generate Analog leakage current; self-test signal output high level, during the self-test period, the self-test signal always keeps high level; after completing the first self-test, turn off the 1s counter, until the power-on reset signal is generated again, the 1s counter will be again Turn on.
  • the 11min counter is used to perform a self-test every 11min after the first self-test; the rising edge of the 1s counter output signal starts the 11min counter, after the 11min counter completes counting, a leakage trigger signal is generated to trigger the FAULT TEST pin to output a high level and turn on the transistor , Generate analog leakage current; self-check signal output high level, self-check signal always keep high level during self-check; after finishing self-check, the counter is cleared for 11min.
  • the comparator module includes a first comparator, a second comparator and a third comparator.
  • the first comparator is used to monitor the open circuit condition of the trip coil during the self-test. During the self-test, if the trip coil and the live wire are normal Connected, the first comparator outputs high level; the second comparator is used to monitor the change of the anode voltage of the thyristor during the self-inspection, if the thyristor function is normal, the second comparator outputs a falling edge signal; the third comparator divides the voltage level of the live wire Compare with the internal reference level, generate a square wave clock consistent with the power frequency, and the generated power frequency clock provides clocks for the 1s counter and 11min counter.
  • the 100ms counter is used to generate a PHASE pin detection signal.
  • the 60ms counter is used to trigger the termination signal; when the 1s counter, 11min counter outputs the self-check signal or the 100ms counter outputs the PHASE pin detection signal, turn on the 60ms counter, if the leakage protector chip, mutual inductance coil, thyristor, trip coil, The PHASE pin functions normally, and the digital processing module generates a signal to clear and shut down the 60ms counter; if the leakage protector chip, mutual inductance coil, thyristor, and trip coil function abnormally, the 60ms counter completes counting and triggers the digital processing module to output a termination signal.
  • the trip enable signal generation module is used to generate a trip enable signal.
  • the trip enable signal outputs a high level; during the self-check period, only when the trip is enabled When the energy signal is high, the SCR signal can be output to drive the thyristor to turn on.
  • the digital processing module is used to judge whether the functions of the leakage protector chip, mutual inductance coil, thyristor, trip coil, PHASE pin are normal, if any of the leakage protector chip, mutual inductance coil, thyristor, trip coil, PHASE pin.
  • the device has a fault and outputs a termination signal; every 100ms, the counter generates a PHASE pin detection signal, and the digital processing module detects the output signal of the first comparator. When the first comparator outputs a rising edge signal, the digital processing module outputs a clear signal. The zero signal clears the 60ms counter.
  • the digital processing part detects the signal that the 60ms counter has finished counting and outputs a termination signal; during the time outside the self-check period, the self-check signal is low If the trip signal output of the leakage protector chip is high, the digital processing module triggers the SCR pin to output a high level, that is, the SCR pin output is consistent with the trip signal of the leakage protector chip; during the self-check period, self-check The signal is high.
  • the digital processing module triggers the SCR pin to output a high level; when the self-check chip is in the self-check period, the self-check signal Keep the high level, the FAULT TEST pin outputs a high level to turn on the transistor to generate analog leakage current.
  • the trip enable signal is low, the SCR pin of the self-check chip remains low, and the thyristor anode voltage is the same as the live wire voltage.
  • the second comparator outputs a high level; when the live wire voltage drops from 50V to 10V, when the trip enable signal is high, if the function of the leakage protector chip, mutual inductance coil, thyristor, and trip coil is normal, the mutual inductance coil induces
  • the leakage protector chip processes the induced leakage signal
  • the trip signal of the leakage protector chip outputs a high level
  • the trip signal of the leakage protector chip and the trip enable signal are both at high level.
  • the digital processing module Trigger the SCR pin of the self-checking chip to output high level, turn on the thyristor, the thyristor anode voltage is low, the second comparator outputs low level, and the digital processing module monitors the output signal of the second comparator and the first comparator If the output signal of the second comparator generates a falling edge and the first comparator outputs a rising edge signal, the digital processing module outputs the signal, clears and turns off the 60ms counter, turns off the 1s counter or clears the 11min counter, clears Self-check signal, trip enable signal, trigger the FAULT TEST pin to output a low level to turn off the triode; the leakage protector chip, mutual inductance coil, thyristor, and trip coil are faulty, and the second comparator does not generate a falling edge If the output signal of the second comparator does not generate a falling edge signal within 60ms, the digital processing module does not generate a reset signal for the 60ms counter. After the 60ms counter finishes
  • the beneficial effect of the present invention the self-check of the leakage protector can be performed periodically, and if a fault is found, a termination signal is output. During the self-inspection, it does not affect the normal operation of load appliances. The cost of the peripheral application circuit is relatively low and has market competitiveness.
  • Figure 1 is a structural block diagram of the self-check chip of the present invention
  • Figure 2 is an application circuit diagram of the self-check chip of the present invention.
  • the self-check chip includes:
  • Power-on reset circuit used to reset the self-check chip after power-on and start the 1s counter
  • the reference voltage module provides a reference voltage for the comparator module
  • reference voltage module provides DC bias
  • the comparator module is used to monitor the phase of the live wire voltage and the change of the thyristor anode voltage during the self-check;
  • Ring oscillator providing clock for counting module and digital processing module
  • Counting module used to generate self-check signal, trip enable signal, leakage trigger signal, thyristor anode monitoring signal, counting module and reset signal of digital processing module;
  • the digital processing module is used to judge whether the function of the leakage protector chip, mutual inductance coil, thyristor, and trip coil is normal, and any component of the leakage protector chip, mutual inductance coil, thyristor, and trip coil is faulty, and output a termination signal.
  • Figure 2 is an application circuit diagram of the self-check chip of the present invention. include:
  • Leakage protector chip used to process leakage signals
  • the power supply circuit 4 supplies power for the leakage protector chip 1 and the self-check chip 2;
  • the analog leakage generating circuit 5 generates analog leakage current
  • Trip mechanism 6 mainly composed of trip coil and thyristor
  • Self-checking chip 2 used for regular self-checking of the key components of the leakage protector: leakage protector chip, mutual inductance coil, thyristor, trip coil, PHASE pin.
  • the leakage protector chip 1 inputs a trip signal into the self-check chip 2, and the self-check chip processes the trip signal output by the leakage protector chip.
  • the digital processing module processes the trip signal output by the leakage protector chip to ensure that the maximum current that the trip coil branch can generate is lower than the trip current within the time range when the SCR pin outputs a high level. It will not drive the tripping mechanism to trip during the self-inspection period; outside the self-inspection period, that is, when the self-inspection signal is low, the output of the SCR pin is consistent with the trip signal output by the leakage protector chip.
  • Table 1 it is the SCR pin output truth table. Among them, the self-check signal and the trip enable signal are generated by the counting module of the self-check chip 2, and the TRIP signal is generated by the leakage protector chip 1.
  • the power-on reset circuit After the chip is powered on for the first time, the power-on reset circuit generates a power-on reset signal to reset the self-checking chip, turning on the 1s counter and 100ms counter. After the 100ms counter finishes counting, it triggers the 60ms counter and starts the detection of the PHASE pin. When the rising edge signal of the PHASE pin is detected, the 60ms counter clear signal is output, and the 60ms counter is cleared. If the PHASE pin is not detected Rising edge signal, the 60ms counter continues to count. After the digital processing module detects the signal that the 60ms counter completes the count, an alarm signal is generated and the PHASE pin is detected every 100ms.
  • the FAULT TEST pin After the 1s counter finishes counting, it triggers the FAULT TEST pin to output a high level, turns on the transistor Q 1 in Figure 2 to generate an analog leakage current; triggers the self-test signal to output a high level, and the self-test signal always maintains a high level during the self-test.
  • the self-check signal turns on the 60ms counter.
  • the SCR pin When the trip enable signal is low, the SCR pin remains low, and the SCR TEST pin monitors the voltage of the thyristor anode. If the trip coil is normally connected to the live wire, the voltage of the thyristor anode is higher than the reference voltage.
  • the comparator outputs a high level; when the live wire voltage drops from 50V to 10V, the trip enable signal outputs a high level.
  • the FAULT TEST pin After the 1s counter completes counting, the FAULT TEST pin outputs a high level to turn on the transistor to generate an analog leakage current If the function of the mutual inductance coil and the leakage protector chip is normal, the leakage protector chip trip signal outputs high level.
  • the self-check signal, the leakage protector chip trip signal, and the trip enable signal are all high level, and the SCR pin Output high level, if the thyristor function is normal, the thyristor is turned on, the anode voltage of the thyristor is low, the second comparator outputs a low level, the output signal of the second comparator produces a falling edge, and the trip enable signal is high during the period If any device in the trip coil, thyristor, mutual inductance coil, and leakage protector chip fails, the second comparator does not generate a falling edge signal; during the self-test, it also detects whether the trip coil has an open circuit phenomenon, use the first comparison The voltage divider on R 5 is compared with the internal reference level.
  • the first comparator outputs a high level; when the digital processing module detects the rising edge signal of the first comparator and the second comparator The falling edge signal of the detector, the output shutdown signal is used to clear the 60ms counter and the 1s counter, clear the self-check signal, the trip enable signal, and trigger the FAULT TEST pin to output a low level to turn off the transistor Q 1 ;
  • the second comparator does not produce a falling edge signal during the period when the trip enable signal is at a high level, indicating that there is a fault in the mutual inductance coil, leakage protector chip, thyristor, and trip coil; within 60ms, repeat the test three times, if The second comparator does not generate a falling edge signal within 60ms, the 60ms counter completes counting, and the output signal drives the digital processing module to generate a termination signal.
  • the self-check chip After the first self-inspection is completed, if the function of the trip coil, thyristor, mutual inductance coil, and leakage protector chip is normal, a self-inspection will be performed every 11 minutes after the first self-inspection, and a self-inspection will start after the 11-minute counter completes a count. Repeat the self-inspection process ; If there is a fault in the trip coil, thyristor, mutual inductance coil, and leakage protector chip, the self-check chip outputs a termination signal to disconnect the load from the power supply.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Breakers (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

本发明公开了一种漏电保护器的自检芯片,包括上电复位电路,用于上电后对自检芯片进行复位;参考电压模块,为比较器模块提供参考电压;偏置电路,为参考电压模块、比较器模块、环形振荡器提供直流偏置;比较器模块,用于监测脱扣线圈的开路情况、晶闸管阳极电压的变化以及产生工频时钟;环形振荡器,为计数模块和数字处理模块提供时钟;计数模块,用于产生自检信号、漏电触发信号、PHASE引脚检测信号,计数模块本身以及数字处理模块的复位信号;跳闸使能信号产生模块,用于产生跳闸使能信号;数字处理模块,用于判断漏电保护器芯片、互感线圈、晶闸管的功能是否正常,脱扣线圈以及PHASE引脚是否正常连接,漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚中任何器件存在故障,输出终止信号。本发明能够定期进行漏电保护器的自检,在自检期间,不影响负载的正常工作。

Description

漏电保护器的自检芯片 技术领域
本发明涉及集成电路设计领域,尤其涉及漏电保护器定期自检的自检芯片。
背景技术
随着电器应用的日益普及,电网负载多样化复杂化,用电安全越来越受国家和社会的重视。漏电保护器成为了生产和生活中不可或缺的辅助电器。然而带故障运行的漏电保护器使得用户失去电击和电气火灾的保护。由于现有漏电保护器的定期检查需要人工操作,操作过程中会造成供电中断,超过90%的用户并没有进行周期性的脱扣自检,漏电保护器异常工作的风险不可忽视。
发明内容
为了克服现有技术的不足,本发明提供一种漏电保护器的自检芯片。
一种漏电保护器的自检芯片,其特征在于,包括:
上电复位电路,用于上电后对自检芯片进行复位;
参考电压模块,为比较器模块提供参考电压;
偏置电路,为参考电压模块、比较器模块、环形振荡器提供直流偏置;
比较器模块,用于监测脱扣线圈的开路情况、晶闸管阳极电压的变化以及产生工频时钟;
环形振荡器,为计数模块和数字处理模块提供时钟;
计数模块,用于产生自检信号、漏电触发信号、PHASE引脚检测信号,计数模块本身以及数字处理模块的复位信号;
跳闸使能信号产生模块,用于产生跳闸使能信号;
数字处理模块,用于判断漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚的功能是否正常,漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚中任何器件存在故障,输出终止信号。
所述计数模块包括1s计数器、11min计数器、60ms计数器、100ms计数器。
所述1s计数器用于在首次上电1s后进行首次自检;上电复位信号开启1s计数器,1s计数器完成计数后,产生漏电触发信号触发FAULT TEST引脚输出高电平,导通三极管,产生模拟漏电流;自检信号输出高电平,在自检期间自检信号始终保持高电平;完成首次自检后,关断1s计数器,直到再次产生上电复位信号,1s计数器才会被再次开启。
所述11min计数器用于首次自检后每11min进行一次自检;1s计数器输出信号上升沿开启11min计数器,11min计数器完成计数后,产生漏电触发信号触发FAULT TEST引脚输出高电平,导通三极管,产生模拟漏电流;自检信号输出高电平,自检期间自检信号始终保持高电平;完成自检后,清零11min计数器。
所述比较器模块,包括第一比较器、第二比较器和第三比较器,第一比较器用于监测自检期间脱扣线圈的开路情况,在自检期间,若脱扣线圈与火线正常连接,第一比较器输出高电平;第二比较器用于监测自检期间晶闸管阳极电压的变化,若晶闸管功能正常,第二比较器输出下降沿信号;第三比较器将火线分压电平与内部参考电平进行比较,产生与工频一致的方波时钟,产生的工频时钟为1s计数器和11min计数器提供时钟。
所述100ms计数器用于产生PHASE引脚检测信号。
所述60ms计数器用于触发终止信号;当1s计数器、11min计数器输出自检信号或者100ms计数器输出PHASE引脚检测信号时,开启60ms计数器,若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚的功能正常,数字处理模块产生信号清零关断60ms计数器;若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈的功能异常,60ms计数器完成计数,触发数字处理模块输出终止信号。
所述跳闸使能信号产生模块用于产生跳闸使能信号,在自检期间内,当火线电压由50V下降为10V期间,跳闸使能信号输出高电平;自检期间内,仅当跳闸使能信号为高电平时,才能输出SCR信号驱动晶闸管导通。
所述数字处理模块用于判断漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚的功能是否正常,若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚中任何器件存在故障,输出终止信号;每隔100ms,100ms计数 器产生一次PHASE引脚检测信号,数字处理模块检测第一比较器的输出信号,当第一比较器输出上升沿信号时,数字处理模块输出清零信号清零60ms计数器,若在60ms内没有清零信号的产生,数字处理部分检测到60ms计数器完成计数的信号后输出终止信号;在自检期间以外的时间内,自检信号为低电平,若漏电保护器芯片跳闸信号输出为高电平,数字处理模块触发SCR管脚输出高电平,即SCR管脚输出与漏电保护器芯片的跳闸信号保持一致;在自检期间内,自检信号为高电平,只有当漏电保护器芯片跳闸信号和跳闸使能信号同时为高电平时,数字处理模块触发SCR管脚输出高电平;当自检芯片处于自检周期内,自检信号保持高电平,FAULT TEST管脚输出高电平导通三极管产生模拟漏电流,当跳闸使能信号为低电平,自检芯片SCR管脚保持低电平,晶闸管阳极电压与火线电压相同,第二比较器输出高电平;当火线电压从50V下降至10V期间内,跳闸使能信号为高电平时,若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈的功能正常,互感线圈感应到模拟漏电流,漏电保护器芯片处理感应到的漏电信号,漏电保护器芯片跳闸信号输出高电平,漏电保护器芯片跳闸信号和跳闸使能信号同时为高电平,经过数字处理模块判断后触发自检芯片的SCR管脚输出高电平,导通晶闸管,晶闸管阳极电压为低电平,第二比较器输出低电平,数字处理模块监测第二比较器的输出信号和第一比较器的输出信号,若第二比较器输出信号产生下降沿并且第一比较器输出上升沿信号,数字处理模块输出信号,清零并且关断60ms计数器,关断1s计数器或者清零11min计数器,清零自检信号、跳闸使能信号,触发FAULT TEST管脚输出低电平关断三极管;漏电保护器芯片、互感线圈、晶闸管、脱扣线圈中任何器件存在故障,第二比较器都不产生下降沿信号,若在60ms内,第二比较器输出信号没有下降沿信号产生,数字处理模块不产生60ms计数器的清零信号,60ms计数器完成计数后触发数字处理模块输出终止信号。
本发明的有益效果:能够定期进行漏电保护器的自检,若发现故障,输出终止信号。在自检期间,不影响负载电器的正常工作。外围应用电路的成本比较低,具有市场竞争力。
附图说明
本发明的以上发明内容以及下面的具体实施方式在结合附图阅读时会得到更好的理解。需要说明的是,附图仅作为所请求保护的发明的示例。在附图中,相同的附图标记代表相同或类似的元素。
图1是本发明自检芯片的一种结构框图;
图2是本发明自检芯片的一种应用电路图。
具体实施方式
以下在具体实施方式中详细叙述本发明的详细特征以及优点,其内容足以使任何本领域技术人员了解本发明的技术内容并据以实施,且根据本说明书所揭露的说明书、权利要求及附图,本领域技术人员可轻易地理解本发明相关的目的及优点。
如图1所示,所述自检芯片包括:
上电复位电路,用于上电后对自检芯片进行复位并且开启1s计数器;
参考电压模块,为比较器模块提供参考电压;
偏置电路,参考电压模块提供直流偏置;
比较器模块,用于监测自检期间火线电压的相位和晶闸管阳极电压的变化;
环形振荡器,为计数模块和数字处理模块提供时钟;
计数模块,用于产生自检信号、跳闸使能信号、漏电触发信号、晶闸管阳极监测信号、计数模块以及数字处理模块的复位信号;
数字处理模块,用于判断漏电保护器芯片、互感线圈、晶闸管、脱扣线圈的功能是否正常,漏电保护器芯片、互感线圈、晶闸管、脱扣线圈中任何器件存在故障,输出终止信号。
图2是本发明自检芯片的一种应用电路图。包括:
漏电保护器芯片1,用于处理漏电信号;
互感线圈3,用于感应模拟漏电流;
供电电路4,为漏电保护器芯片1和自检芯片2供电;
模拟漏电产生电路5,产生模拟漏电流;
脱扣机构6,主要由脱扣线圈和晶闸管组成;
自检芯片2,用于对漏电保护器的关键组件:漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚进行定期的自检。
如图2所示,漏电保护器芯片1将跳闸信号输入自检芯片2中,通过自检芯片对漏电保护器芯片输出的跳闸信号进行处理。在自检期间,数字处理模块对漏电保护器芯片输出的跳闸信号进行处理,保证SCR管脚输出高电平的时间范围内,脱扣线圈支路能够产生的最大电流低于脱扣电流,从而不会在自检期间驱动脱扣机构脱扣;在自检期间以外的时间内,即自检信号为低电平时,SCR管脚的输出与漏电保护器芯片输出的跳闸信号保持一致。如表一所示为SCR管脚输出真值表。其中,自检信号和跳闸使能信号由自检芯片2的计数模块产生,TRIP信号由漏电保护器芯片1产生。
表1SCR管脚输出真值表
Figure PCTCN2019093002-appb-000001
下面详细说明自检芯片的工作过程。
如图1所示,芯片首次上电后,上电复位电路产生上电复位信号对自检芯片进行复位,开启1s计数器和100ms计数器。100ms计数器完成计数后,触发60ms计数器,开始进行PHASE引脚的检测,当检测到PHASE引脚的上升沿信号后,输出60ms计数器清零信号,清零60ms计数器,若没有检测到PHASE引脚的上升沿信号,60ms计数器持续计数,数字处理模块检测到60ms计数器完成计数的信号后,产生报警信号,每100ms对PHASE引脚进行一次检测。1s计数器完成计数后,触发FAULT TEST管脚输出高电平,导通图2中三极管Q 1 产生模拟漏电流;触发自检信号输出高电平,在自检期间自检信号始终保持高电平,自检信号开启60ms计数器。将当跳闸使能信号为低电平时,SCR管脚保持低电平,SCR TEST管脚监测晶闸管阳极的电压,若脱扣线圈与火线正常连接,晶闸管阳极电压分压高于参考电压,第二比较器输出高电平;当火线电压从50V下降为10V期间,跳闸使能信号输出高电平,在1s计数器完成计数后,通过触发FAULT TEST管脚输出高电平导通三极管产生模拟漏电流,若互感线圈以及漏电保护器芯片功能正常,漏电保护器芯片跳闸信号输出高电平,此时,自检信号、漏电保护器芯片跳闸信号、跳闸使能信号均为高电平,SCR管脚输出高电平,若晶闸管功能正常,晶闸管导通,晶闸管阳极电压为低电平,第二比较器输出低电平,第二比较器输出信号产生下降沿,跳闸使能信号为高电平期间,脱扣线圈、晶闸管、互感线圈、漏电保护器芯片中任何器件发生故障,第二比较器都不产生下降沿信号;在自检期间,同时检测脱扣线圈是否存在开路现象,利用第一比较器将R 5上的分压与内部参考电平进行比较,若脱扣线圈连接正常,第一比较器输出高电平;当数字处理模块检测到第一比较器的上升沿信号和第二比较器的下降沿信号,输出关断信号用于清零关断60ms计数器和1s计数器,清零自检信号、跳闸使能信号,触发FAULT TEST管脚输出低电平关断三极管Q 1;若第二比较器在脱扣使能信号为高电平期间没有产生下降沿信号,说明互感线圈、漏电保护器芯片、晶闸管、脱扣线圈中有器件存在故障;在60ms内,重复进行三次检测,若第二比较器在60ms内都没有产生下降沿信号,60ms计数器完成计数,输出信号驱动数字处理模块产生终止信号。
完成首次自检后,若脱扣线圈、晶闸管、互感线圈、漏电保护器芯片功能正常,首次自检后每11min进行一次自检,11min计数器完成一次计数后开始一次自检,重复上述自检流程;若脱扣线圈、晶闸管、互感线圈、漏电保护器芯片中有器件存在故障,自检芯片输出终止信号断开负载供电。
这里采用的术语和表述方式只是用于描述,本发明并不应局限于这些术语和表述。使用这些术语和表述并不意味着排除任何示意和描述(或其中部分)的等效特征,应认识到可能存在的各种修改也应包含在权利要求范围内。其他修改、变化和替换也可能存在。相应的,权利要求应视为覆盖所有这些等效物。
同样,需要指出的是,虽然本发明已参照当前的具体实施例来描述,但是 本技术领域中的普通技术人员应当认识到,以上的实施例仅是用来说明本发明,在没有脱离本发明精神的情况下还可做出各种等效的变化或替换,因此,只要在本发明的实质精神范围内对上述实施例的变化、变型都将落在本申请的权利要求书的范围内。

Claims (9)

  1. 一种漏电保护器的自检芯片,其特征在于,包括:
    上电复位电路,用于上电后对自检芯片进行复位;
    参考电压模块,为比较器模块提供参考电压;
    偏置电路,为参考电压模块、比较器模块、环形振荡器提供直流偏置;
    比较器模块,用于监测脱扣线圈的开路情况、晶闸管阳极电压的变化以及产生工频时钟;
    环形振荡器,为计数模块和数字处理模块提供时钟;
    计数模块,用于产生自检信号、漏电触发信号、PHASE引脚检测信号,计数模块本身以及数字处理模块的复位信号;
    跳闸使能信号产生模块,用于产生跳闸使能信号;
    数字处理模块,用于判断漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚的功能是否正常,漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚中任何器件存在故障,输出终止信号。
  2. 如权利要求1所述的自检芯片,其特征在于,所述计数模块包括1s计数器、11min计数器、60ms计数器、100ms计数器。
  3. 如权利要求2所述的自检芯片,其特征在于,所述1s计数器用于在首次上电1s后进行首次自检;上电复位信号开启1s计数器,1s计数器完成计数后,产生漏电触发信号触发FAULT TEST引脚输出高电平,导通三极管,产生模拟漏电流;自检信号输出高电平,在自检期间自检信号始终保持高电平;完成首次自检后,关断1s计数器,直到再次产生上电复位信号,1s计数器才会被再次开启。
  4. 如权利要求2所述的自检芯片,其特征在于,所述11min计数器用于首次自检后每11min进行一次自检;1s计数器输出信号上升沿开启11min计数器,11min计数器完成计数后,产生漏电触发信号触发FAULT TEST引脚输出高电平,导通三极管,产生模拟漏电流;自检信号输出高电平,自检期间自检信号始终保持高电平;完成自检后,清零11min计数器。
  5. 如权利要求1所述的自检芯片,其特征在于,所述比较器模块,包括第 一比较器、第二比较器和第三比较器,第一比较器用于监测自检期间脱扣线圈的开路情况,在自检期间,若脱扣线圈与火线正常连接,第一比较器输出高电平;第二比较器用于监测自检期间晶闸管阳极电压的变化,若晶闸管功能正常,第二比较器输出下降沿信号;第三比较器将火线分压电平与内部参考电平进行比较,产生与工频一致的方波时钟,产生的工频时钟为1s计数器和11min计数器提供时钟。
  6. 如权利要求2所述的自检芯片,其特征在于,所述100ms计数器用于产生PHASE引脚检测信号。
  7. 如权利要求2所述的自检芯片,其特征在于,所述60ms计数器用于触发终止信号;当1s计数器、11min计数器输出自检信号或者100ms计数器输出PHASE引脚检测信号时,开启60ms计数器,若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚的功能正常,数字处理模块产生信号清零关断60ms计数器;若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈的功能异常,60ms计数器完成计数,触发数字处理模块输出终止信号。
  8. 如权利要求1所述的自检芯片,其特征在于,所述跳闸使能信号产生模块用于产生跳闸使能信号,在自检期间内,当火线电压由50V下降为10V期间,跳闸使能信号输出高电平;自检期间内,仅当跳闸使能信号为高电平时,才能输出SCR信号驱动晶闸管导通。
  9. 如权利要求1所述的自检芯片,其特征在于,所述数字处理模块用于判断漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚的功能是否正常,若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈、PHASE引脚中任何器件存在故障,输出终止信号;每隔100ms,100ms计数器产生一次PHASE引脚检测信号,数字处理模块检测第一比较器的输出信号,当第一比较器输出上升沿信号时,数字处理模块输出清零信号清零60ms计数器,若在60ms内没有清零信号的产生,数字处理部分检测到60ms计数器完成计数的信号后输出终止信号;在自检期间以外的时间内,自检信号为低电平,若漏电保护器芯片跳闸信号输出为高电平,数字处理模块触发SCR管脚输出高电平,即SCR管脚输出与漏电保护器芯片的跳闸信号保持一致;在自检期间内,自检信号为高电平,只有当漏电保护器芯片跳闸信号和跳闸使能信号同时为高电平时,数字处理模 块触发SCR管脚输出高电平;当自检芯片处于自检周期内,自检信号保持高电平,FAULT TEST管脚输出高电平导通三极管产生模拟漏电流,当跳闸使能信号为低电平,自检芯片SCR管脚保持低电平,晶闸管阳极电压与火线电压相同,第二比较器输出高电平;当火线电压从50V下降至10V期间内,跳闸使能信号为高电平时,若漏电保护器芯片、互感线圈、晶闸管、脱扣线圈的功能正常,互感线圈感应到模拟漏电流,漏电保护器芯片处理感应到的漏电信号,漏电保护器芯片跳闸信号输出高电平,漏电保护器芯片跳闸信号和跳闸使能信号同时为高电平,经过数字处理模块判断后触发自检芯片的SCR管脚输出高电平,导通晶闸管,晶闸管阳极电压为低电平,第二比较器输出低电平,数字处理模块监测第二比较器的输出信号和第一比较器的输出信号,若第二比较器输出信号产生下降沿并且第一比较器输出上升沿信号,数字处理模块输出信号,清零并且关断60ms计数器,关断1s计数器或者清零11min计数器,清零自检信号、跳闸使能信号,触发FAULT TEST管脚输出低电平关断三极管;漏电保护器芯片、互感线圈、晶闸管、脱扣线圈中任何器件存在故障,第二比较器都不产生下降沿信号,若在60ms内,第二比较器输出信号没有下降沿信号产生,数字处理模块不产生60ms计数器的清零信号,60ms计数器完成计数后触发数字处理模块输出终止信号。
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