WO2020224207A1 - Goa电路及显示面板 - Google Patents

Goa电路及显示面板 Download PDF

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Publication number
WO2020224207A1
WO2020224207A1 PCT/CN2019/115580 CN2019115580W WO2020224207A1 WO 2020224207 A1 WO2020224207 A1 WO 2020224207A1 CN 2019115580 W CN2019115580 W CN 2019115580W WO 2020224207 A1 WO2020224207 A1 WO 2020224207A1
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thin film
film transistor
module
pull
gate
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PCT/CN2019/115580
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English (en)
French (fr)
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薛炎
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020224207A1 publication Critical patent/WO2020224207A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • the horizontal scanning line of AMOLED display panel is driven by an external integrated circuit.
  • the external integrated circuit can control the step-by-step turn-on of the row scanning lines at all levels, and the GOA (Gate Driver on Array) method can be used to drive the horizontal scanning
  • the circuit is integrated on the display panel substrate, which can reduce the number of external ICs, thereby reducing the production cost of the display panel, and can realize the narrow frame of the display device.
  • IGZO has high mobility and good device stability, and is currently widely used in IGZO-GOA circuits.
  • the pixel circuit of the AMOLED panel uses thin film transistors to form a current source to light the panel, and the Vth of the IGZO thin film transistor is prone to shift when subjected to stress, so the pixel circuit needs to use external compensation or internal compensation circuit for Vth compensation, external compensation
  • the pixel circuit requires the GOA circuit to output an ultra-wide pulse signal (>1ms) for Vth detection.
  • the Q point in the GOA circuit is the gate point of the thin film transistor that controls the high level of the output signal. When the Q point is at the high potential, the thin film transistor is in the on state and the output signal remains high. In the actual working process of GOA, if you need to output an ultra-wide pulse signal, the Q point must maintain a high potential for a long time.
  • the pull-up control module is an effective method to reduce the leakage current at the Q point.
  • the pull-up control module is an effective method to reduce the leakage current at the Q point.
  • the circuit of the pull-up control module is more complicated (3 thin film transistors).
  • the GOA circuit usually requires several pull-up control modules, which will increase the GOA circuit
  • the complexity and layout space are not conducive to the narrow frame design of the display.
  • the pull-up control module can reduce the leakage current of the Q point to a certain extent, but it cannot be guaranteed within the ms-level pulse width range Reduce Q point leakage. Therefore, the ability to maintain the potential of the Q point is the key to ensuring the stable output of the GOA circuit.
  • This application provides a GOA circuit and a display panel, which can improve the display quality.
  • the GOA unit of the Nth level includes a pull-up control module, a pull-up module, a downstream module, a pull-down module, a pull-down maintenance module, and a bootstrap capacitor module
  • the pull-up control module is respectively connected to the downstream module and the pull-down maintenance module at point Q, one end of the bootstrap capacitor is connected to the downstream module and the pull-up module, and the pull-down
  • the modules are respectively connected to the download module and the scan signal output terminal of the current stage, and the pull-up modules are respectively connected to the second clock signal line and the scan line of the current stage;
  • the pull-up control module includes a first dual gate MOS tube, the drain of the first double-gate MOS tube is connected to the scan signal output terminal of the N-1th stage GOA unit, and the source of the first double-gate MOS tube is connected to the Q point, so The top gate of the first double-gate MOS transistor is connected to the output terminal of the N-1
  • a display panel includes the GOA circuit described in any one of the above.
  • the pull-up control module as a dual-gate MOS tube to replace the original three thin film transistors, the voltage maintaining capability of the Q point can be improved, the leakage current of the Q point can be reduced, and the display quality can be improved.
  • FIG. 1 is a structural diagram of an N-th GOA unit of a GOA circuit in some embodiments of the present application.
  • FIG. 2 is a voltage timing diagram of the N-th GOA unit in some embodiments of the present application.
  • Fig. 3 is a simulation timing diagram of the Nth-level GOA unit in some embodiments of the present application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, “plurality” means two or more than two, unless specifically defined otherwise.
  • the "above” or “below” of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature.
  • the “below”, “below” and “below” the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • FIG. 1 is a structural diagram of an N-th GOA unit of a GOA circuit in some embodiments of the present application.
  • the GOA circuit includes a plurality of cascaded GOA units.
  • the GOA unit of the Nth stage includes a pull-up control module 101, a pull-up module 105, a download module 104, a pull-down module 106, a pull-down maintenance module 102, and a bootstrap capacitor module 103.
  • the pull-up control module 101 is respectively connected to the Q point with the download module 104, the pull-down maintenance module 102, the bootstrap capacitor module 103, and the pull-up module 105.
  • One end of the bootstrap capacitor module 103 is respectively connected to the downstream module 104 and the pull-up module 105 at point Q, and the pull-down module 106 is connected to the downstream module 104 and the scan signal output terminal OUT( n) connection, the pull-up module 105 is respectively connected to the second clock signal line CK2 and the scan signal output terminal OUT(n).
  • the pull-up control module 101 includes a first double-gate MOS transistor T11, the drain of the first double-gate MOS transistor T11 is connected to the scan signal output terminal of the N-1th stage GOA unit, and the first The source of the double-gate MOS transistor T11 is connected to the Q point, the top gate of the first double-gate MOS transistor T11 is connected to the output terminal of the N-1th stage downstream module, and the first double The bottom gate of the gate MOS transistor T11 is connected to the first clock signal line CK1.
  • the pull-down maintenance module 102 includes a second double-gate MOS transistor, a first thin film transistor T31, a second thin film transistor T32, a third thin film transistor T41, a fourth thin film transistor T42, a fifth thin film transistor T43, and a sixth thin film transistor T44;
  • the drain of the second double-gate MOS transistor is connected to the Q point, the source of the second double-gate MOS transistor is connected to the low-voltage signal line, the gate of the first thin film transistor T31, the second thin film
  • the gate of the transistor T32, the drain of the fifth thin film transistor T43, and the source of the sixth thin film transistor T44 are connected to point QB;
  • the bottom gate of the second double-gate MOS transistor is connected to the fourth clock signal line CK4;
  • the drain of the second thin film transistor T32 is connected to the output terminal of the download module 104 and the bootstrap capacitor module 103.
  • the drain of the third thin film transistor T41 and the drain and gate of the fourth thin film transistor T42 are respectively connected to the high voltage signal line VGH.
  • the gate of the sixth thin film transistor T44 and the source of the fourth thin film transistor T42 And the drain of the third thin film transistor T41 are connected; the gate of the third thin film transistor T41 and the gate of the fifth thin film transistor T43 are connected to the Q point; the first thin film transistor T31 and the second thin film transistor T32 are connected The gate, the sources of the third thin film transistor T41 and the fifth thin film transistor T43 are connected to the low voltage signal line VGL.
  • the bootstrap capacitor module 103 includes a bootstrap capacitor Cbt.
  • the download module 104 includes a seventh thin film transistor T22, the gate of the seventh thin film transistor T22 is connected to the Q point, and the drain of the seventh thin film transistor T22 is connected to the second clock signal line CK2,
  • the source of the seventh thin film transistor T22 serves as the output terminal cout(n) of the downstream module 104.
  • the pull-up module 105 includes an eighth thin film transistor T21, the gate of the eighth thin film transistor T21 is connected to the Q point, and the drain of the eighth thin film transistor T21 is connected to the second clock signal line CK2 Connected, the source of the eighth thin film transistor T21 is connected to the scan signal output terminal OUT(n) of the current stage.
  • the pull-down module 106 includes a ninth thin film transistor T33, the gate of the ninth thin film transistor T33 is connected to the output terminal of the N+2th downstream module 104, and the drain of the ninth thin film transistor T33 is connected to The scanning signal output terminal OUT(n) of this stage is connected, and the source of the ninth thin film transistor T33 is connected to the low voltage signal line VGL.
  • both the first double-gate MOS transistor and the second double-gate MOS transistor are thin film transistors.
  • the first clock signal CK1, the second clock signal CK2 and the fourth clock signal CK4 have a signal period of 4t1, the first clock signal CK1, the second clock signal CK2 and the The pulse width of the fourth clock signal CK4 is t1.
  • the first clock signal is one t1 time earlier than the second clock signal, and the second clock signal is two t1 time earlier than the fourth clock signal.
  • the high-voltage signal line is written from the drain of the first double-gate MOS transistor and at this time
  • the first clock signal is at a high potential
  • the fourth clock signal is at a low potential
  • the Vth of the first double-gate MOS transistor T11 drops to about -20V, therefore, the initial Vgs-Vth voltage of the first double-gate MOS transistor T11 is about 40V
  • the initial voltage of Vgs-Vth in the traditional circuit is about 20V.
  • the first double gate MOS transistor T11 and the second double gate MOS transistor T34 There are two leakage paths at point Q, the first double gate MOS transistor T11 and the second double gate MOS transistor T34.
  • the voltages of the bottom gate potentials CK1 and CK4 are both negative voltages. Therefore, the first double gate The Vth of the MOS transistor T11 and the second double-gate MOS transistor T34 are both 20V, and Vgs-Vth is -40V. Therefore, the first double-gate MOS transistor T11 and the second double-gate MOS transistor T34 have very little leakage current. The point's sustaining voltage can be maintained.
  • This application can effectively maintain the Q-point potential during the Q-point potential maintenance stage, and realize the ultra-wide pulse GOA signal (30ms) output.
  • FIG. 3 is a simulation diagram of the circuit provided by this application. Among them, it includes the following four stages:
  • T1 stage Cout(n-1), Out(n-1), CK1 rises to high potential, Vth of T11 is -20V, high potential is quickly written to point Q, after the potential of point Q is raised to high potential, T21, T22 , T41 and T43 are turned on, QB point is pulled down to low potential, T31 and T32 are turned off, CK4 is low at this time, so the Vth of T34 is 20V, the leakage current of T34 will be very small, the feedback signal Cout(n+2) At a low level, T33 is turned off. Since CK2 is at a low level, the stage transmission signal Cout(n) and the output signal Out(n) are at a low level.
  • T2 stage CK1 and Cout(n-1) drop to a low potential, T11 is completely closed, at this time the Vth of T11 is -20V, and CK2 turns from a low potential to a high potential, so the potential at point Q is maintained to a higher potential.
  • QB maintains a low potential, while CK4 is a low potential.
  • T3 stage CK1 and Cout(n-1) maintain low potential, CK2 drops from high potential to low potential. At this time, the potential at point Q drops, but T21 and T22 remain open, the level transmission signal Cout(n) and output signal Out(n) drops to low level.
  • T4 stage CK1 and Cout(n-1) maintain low potential, CK4 rises to high potential, T33 and T34 are opened, the potential of point Q is pulled to low potential, T21, T22, T41 and T43 are closed, and QB rises to high potential.
  • T31 and T32 are turned on, and the stage transmission potential Cout(n) and the output potential Out(n) remain low.

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  • Physics & Mathematics (AREA)
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Abstract

本申请提供了一种GOA电路，包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容模块；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接于Q点，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描信号输出端连接，上拉模块分别与第二时钟信号线以及本级的扫描线连接；上拉控制模块包括第一双栅极MOS管，第一双栅极MOS管的漏极与第N-1级GOA单元的扫描信号输出端连接，第一双栅极MOS管的源极与Q点连接，第一双栅极MOS管的顶栅极与第N-1级的下传模块的输出端连接，所述第一双栅极MOS管的底栅极与第一时钟信号线连接。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种GOA电路及显示面板。
背景技术
目前AMOLED显示面板的水平扫描线的驱动是由外接集成电路来实现的，外接集成电路可以控制各级行扫描线的逐级开启，而采用GOA(Gate Driver on Array)方法，可以将行扫描驱动电路集成在显示面板基板上，能够减少外接IC的数量，从而降低了显示面板的生产成本，并且能够实现显示装置的窄边框化。IGZO具有高的迁移率，和良好的器件稳定性，目前广泛的应用于IGZO-GOA电路中。
AMOLED面板的像素电路是利用薄膜晶体管组成电流源来点亮面板的，而IGZO-薄膜晶体管受到stress作用时Vth易发生偏移，因而像素电路需要使用外部补偿或内部补偿电路进行Vth补偿，外部补偿像素电路需要GOA电路输出超宽脉冲信号(>1ms)进行Vth探测。GOA电路中Q点是控制输出信号高电平的薄膜晶体管栅极点，当Q点处于高电位时，薄膜晶体管处于开启状态，输出信号保持高电位。在GOA实际工作过程中，如果需要输出超宽脉冲信号，Q点必须长时间维持高电位，由于IGZO-薄膜晶体管为耗尽型薄膜晶体管，薄膜晶体管的Vth偏负，Q点在自举阶段，Q点的电位降低，导致GOA输出失效。通常，上拉控制模块是一种能够减少Q点漏电流的有效方法。
技术问题
上拉控制模块是一种能够减少Q点漏电流的有效方法，然而上拉控制模块的电路较为复杂(3个薄膜晶体管)，GOA电路通常需要采用几个上拉控制模块，这会增加GOA电路的复杂程度和版图空间，不利于显示器的窄边框设计，此外在μs级脉宽范围内，上拉控制模块能够在一定程度上减少Q点的漏电流，然而无法保证在ms级脉宽范围内减少Q点漏电。因此，Q点电位的维持能力是保证GOA电路稳定输出的关键所在。
因此，现有技术存在缺陷，急需改进。
技术解决方案
本申请提供一种GOA电路及显示面板，可以提高显示质量。
本申请提供了一种GOA电路，包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容模块；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接于Q点，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描信号输出端连接，所述上拉模块分别与第二时钟信号线以及本级的扫描线连接；所述上拉控制模块包括第一双栅极MOS管，所述第一双栅极MOS管的漏极与第N-1级GOA单元的扫描信号输出端连接，所述第一双栅极MOS管的源极与所述Q点连接，所述第一双栅极MOS管的顶栅极与第N-1级的下传模块的输出端连接，所 述第一双栅极MOS管的底栅极与第一时钟信号线连接。
一种显示面板，包括上述任一项所述的GOA电路。
有益效果
本申请通过将上拉控制模块设置为双栅极MOS管替换原有的三个薄膜晶体管的方式，可以提高Q点的电压维持能力，可以减少Q点漏电流，提高显示质量。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一些实施例中的一种GOA电路的第N级GOA单元的结构图。
图2是本申请一些实施例中的第N级GOA单元的电压时序图。
图3是本申请一些实施例中的第N级GOA单元的仿真时序图。
本发明的最佳实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有 相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括 第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请同时参阅图1，图1是本申请一些实施例中的一种GOA电路的第N级GOA单元的结构图。
该GOA电路包括多个级联的GOA单元。其中，该第N级所述GOA单元包括上拉控制模块101、上拉模块105、下传模块104、下拉模块106、下拉维持模块102以及自举电容模块103。
其中，该上拉控制模块101分别与所述下传模块104以及所述下拉维持模块102、所述自举电容模块103、所述上拉模块105连接于Q点。自举电容模块103的一端分别与所述下传模块104以及所述上 拉模块105连接于Q点，所述下拉模块106分别与所述下传模块104以及本级的扫描信号输出端OUT(n)连接，所述上拉模块105分别与第二时钟信号线CK2以及扫描信号输出端OUT(n)。
其中，该上拉控制模块101包括第一双栅极MOS管T11，所述第一双栅极MOS管T11的漏极与第N-1级GOA单元的扫描信号输出端连接，所述第一双栅极MOS管T11的源极与所述Q点连接，所述第一双栅极MOS管T11的顶栅极与第N-1级的下传模块的输出端连接，所述第一双栅极MOS管T11的底栅极与第一时钟信号线CK1连接。
其中，该下拉维持模块102包括第二双栅极MOS管、第一薄膜晶体管T31、第二薄膜晶体管T32、第三薄膜晶体管T41、第四薄膜晶体管T42、第五薄膜晶体管T43以及第六薄膜晶体管T44；
所述第二双栅极MOS管的漏极与所述Q点连接，所述第二双栅极MOS管的源极与低电压信号线连接，第一薄膜晶体管T31的栅极、第二薄膜晶体管T32的栅极、第五薄膜晶体管T43的漏极以及第六薄膜晶体管T44的源极连接于QB点；所述第二双栅极MOS管底栅极与第四时钟信号线CK4连接；所述第二薄膜晶体管T32的漏极与所述下传模块104的输出端以及所述自举电容模块103连接。所述第三薄膜晶体管T41的漏极、所述第四薄膜晶体管T42的漏极与栅极分别连接并与高电压信号线VGH连接，第六薄膜晶体管T44的栅极、第四薄膜晶体管T42源极以及第三薄膜晶体管T41的漏极连接；第三薄膜晶体管T41的栅极以及第五薄膜晶体管T43的栅极与所述Q点链接；所述第一薄膜晶体管T31、第二薄膜晶体管T32的栅极、第三薄膜晶体管T41 以及第五薄膜晶体管T43的源极与所述低电压信号线VGL连接。
其中，该自举电容模块103包括自举电容Cbt。
其中，该下传模块104包括第七薄膜晶体管T22，所述第七薄膜晶体管T22的栅极与所述Q点连接，所述第七薄膜晶体管T22的漏极与第二时钟信号线CK2连接，所述第七薄膜晶体管T22的源极作为所述下传模块104的输出端cout(n)。
其中，该上拉模块105包括第八薄膜晶体管T21，所述第八薄膜晶体管T21的栅极与所述Q点连接，所述第八薄膜晶体管T21的漏极与所述第二时钟信号线CK2连接，所述第八薄膜晶体管T21的源极与本级扫描信号输出端OUT(n)连接。
其中，该下拉模块106包括第九薄膜晶体管T33，所述第九薄膜晶体管T33的栅极与第N+2级的下传模块104的输出端连接，所述第九薄膜晶体管T33的漏极与本级扫描信号输出端OUT(n)连接，所述第九薄膜晶体管T33的源极与所述低电压信号线VGL连接。
在一些实施例中，第一双栅极MOS管以及所述第二双栅极MOS管均为薄膜晶体管。
请同时参照图2，该第一时钟信号CK1、所述第二时钟信号CK2以及所述第四时钟信号CK4的信号周期均为4t1，第一时钟信号CK1、所述第二时钟信号CK2以及所述第四时钟信号CK4的信号的脉冲宽度均为t1。第一时钟信号比所述第二时钟信号早一个t1时间，所述第二时钟信号比所述第四时钟信号早两个t1时间。
其中，当第N-1级的扫描信号Out(n-1)的电位升为高电平时， 所述高电压信号线从所述第一双栅极MOS管的漏极写入且此时第一时钟信号为高电位、第四时钟信号为低电位；第一双栅极MOS管T11的Vth降为-20V左右，因而，第一双栅极MOS管T11的初始Vgs-Vth电压约为40V，而传统电路中Vgs-Vth初始电压约为20V。当所述Q点处于维持阶段时，所述第一时钟信号以及所述第四时钟信号的电压均为低电压。Q点存在两个漏电路径，第一双栅极MOS管T11与第二双栅极MOS管T34，此时，底栅电位CK1与CK4的电压均为负电压，因此，，第一双栅极MOS管T11与第二双栅极MOS管T34的Vth均为20V，Vgs-Vth为-40V，因此，第一双栅极MOS管T11与第二双栅极MOS管T34漏电流极少，Q点的维持电压能够维持。
本申请可以在Q点电位维持阶段，能够有效的维持Q点电位，实现超宽脉冲GOA信号(30ms)输出。
请参照图3，图3是本申请所提供的电路的仿真图。其中，其包括以下四个阶段：
T1阶段：Cout(n-1)，Out(n-1)，CK1升为高电位，T11的Vth为-20V，高电位迅速写入Q点，Q点电位被抬升至高电位后，T21，T22，T41及T43打开，QB点被拉低至低电位，T31及T32关闭，此时CK4为低电位，因此T34的Vth为20V，T34的漏电流会极小，反馈信号Cout(n+2)为低电位，T33关闭，由于CK2为低电位，级传信号Cout(n)与输出信号Out(n)为低电位。
T2阶段：CK1及Cout(n-1)降为低电位，T11完全关闭，此时T11的Vth为-20V，CK2由低电位转为高电位，因而Q点的电位被维 持至更高电位，QB维持低电位，同时CK4为低电位，T34的Vth为-20V，T11与T34的Vgs-Vth＝-40V，由于CK2为高电位，级传信号Cout(n)与输出信号G(n)输出高电位。
T3阶段：CK1及Cout(n-1)维持低电位，CK2由高电位降为低电位，此时，Q点电位下降，但是T21与T22维持打开状态，级传信号Cout(n)与输出信号Out(n)降为低电位。
T4阶段：CK1及Cout(n-1)维持低电位，CK4升为高电位，T33与T34打开，Q点电位被拉至低电位，T21，T22，T41及T43关闭，QB升为高电位，T31与T32打开，级传电位Cout(n)与输出电位Out(n)维持低电位。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种GOA电路，其中，包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容模块；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接于Q点，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描信号输出端连接，所述上拉模块分别与第二时钟信号线以及本级的扫描线连接；
    所述上拉控制模块包括第一双栅极MOS管，所述第一双栅极MOS管的漏极与第N-1级GOA单元的扫描信号输出端连接，所述第一双栅极MOS管的源极与所述Q点连接，所述第一双栅极MOS管的顶栅极与第N-1级的下传模块的输出端连接，所述第一双栅极MOS管的底栅极与第一时钟信号线连接；
    所述下拉维持模块包括第二双栅极MOS管、第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管；
    所述第二双栅极MOS管的漏极与所述Q点连接，所述第二双栅极MOS管的源极与低电压信号线连接，第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第五薄膜晶体管的漏极以及第六薄膜晶体管的源极连接于QB点；所述第二双栅极MOS管底栅极与第四时钟信号线连接；所述第二薄膜晶体管的漏极与所述下传模块的输出端以及所述自举电容模块连接；
    所述第三薄膜晶体管的漏极、所述第四薄膜晶体管的漏极与栅极分别连接并与高电压信号线连接，第六薄膜晶体管的栅极、第四薄膜晶体管的源极以及第三薄膜晶体管的漏极连接；第三薄膜晶体管的栅极以及第五薄膜晶体管的栅极与所述Q点链接；所述第一薄膜晶体管、第二薄膜晶体管的栅极、第三薄膜晶体管以及第五薄膜晶体管的源极与所述低电压信号线连接；
    所述自举电容模块包括自举电容；
    所述下传模块包括第七薄膜晶体管，所述第七薄膜晶体管的栅极与所述Q点连接，所述第七薄膜晶体管的漏极与第二时钟信号线连接，所述第七薄膜晶体管的源极作为所述下传模块的输出端。
  2. 一种GOA电路，其中，包括多个级联的GOA单元，第N级所述GOA单元包括上拉控制模块、上拉模块、下传模块、下拉模块、下拉维持模块以及自举电容模块；所述上拉控制模块分别与所述下传模块以及所述下拉维持模块连接于Q点，所述自举电容的一端分别与所述下传模块以及所述上拉模块连接，所述下拉模块分别与所述下传模块以及本级的扫描信号输出端连接，所述上拉模块分别与第二时钟信号线以及本级的扫描线连接；
    所述上拉控制模块包括第一双栅极MOS管，所述第一双栅极MOS管的漏极与第N-1级GOA单元的扫描信号输出端连接，所述第一双栅极MOS管的源极与所述Q点连接，所述第一双栅极MOS管的顶栅极与第N-1级的下传模块的输出端连接，所述第一双栅极MOS管的底栅极与第一时钟信号线连接。
  3. 根据权利要求2所述的GOA电路，其中，所述下拉维持模块包括第二双栅极MOS管、第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管；
    所述第二双栅极MOS管的漏极与所述Q点连接，所述第二双栅极MOS管的源极与低电压信号线连接，第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第五薄膜晶体管的漏极以及第六薄膜晶体管的源极连接于QB点；所述第二双栅极MOS管底栅极与第四时钟信号线连接；所述第二薄膜晶体管的漏极与所述下传模块的输出端以及所述自举电容模块连接；
    所述第三薄膜晶体管的漏极、所述第四薄膜晶体管的漏极与栅极分别连接并与高电压信号线连接，第六薄膜晶体管的栅极、第四薄膜晶体管的源极以及第三薄膜晶体管的漏极连接；第三薄膜晶体管的栅极以及第五薄膜晶体管的栅极与所述Q点链接；所述第一薄膜晶体管、第二薄膜晶体管的栅极、第三薄膜晶体管以及第五薄膜晶体管的源极与所述低电压信号线连接。
  4. 根据权利要求3所述的GOA电路，其中，所述自举电容模块包括自举电容。
  5. 根据权利要求3所述的GOA电路，其中，所述下传模块包括第七薄膜晶体管，所述第七薄膜晶体管的栅极与所述Q点连接，所述第七薄膜晶体管的漏极与第二时钟信号线连接，所述第七薄膜晶体管的源极作为所述下传模块的输出端。
  6. 根据权利要求5所述的GOA电路，其中，所述上拉模块包括 第八薄膜晶体管，所述第八薄膜晶体管的栅极与所述Q点连接，所述第八薄膜晶体管的漏极与所述第二时钟信号线连接，所述第八薄膜晶体管的源极与本级扫描信号输出端连接。
  7. 根据权利要求3所述的GOA电路，其中，所述下拉模块包括第九薄膜晶体管，所述第九薄膜晶体管的栅极与第N+2级的下传模块的输出端连接，所述第九薄膜晶体管的漏极与本级扫描信号输出端连接，所述第九薄膜晶体管的源极与所述低电压信号线连接。
  8. 根据权利要求3所述的GOA电路，其中，所述第一时钟信号、所述第二时钟信号以及所述第四时钟信号的信号周期均为4t1，第一时钟信号、所述第二时钟信号以及所述第四时钟信号的信号的脉冲宽度均为t1；
    所述第一时钟信号比所述第二时钟信号早一个t1时间，所述第二时钟信号比所述第四时钟信号早两个t1时间。
  9. 根据权利要求8所述的GOA电路，其中，当第N-1级的扫描信号的电位升为高电平时，所述高电压信号线从所述第一双栅极MOS管的漏极写入且此时第一时钟信号为高电位、第四时钟信号为低电位；当所述Q点处于维持阶段时，所述第一时钟信号以及所述第四时钟信号的电压均为低电压。
  10. 根据权利要求3所述的GOA电路，其中，所述第一双栅极MOS管以及所述第二双栅极MOS管均为薄膜晶体管。
  11. 一种显示面板，其中，包括如权利要求2所述的GOA电路。
PCT/CN2019/115580 2019-05-07 2019-11-05 Goa电路及显示面板 WO2020224207A1 (zh)

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