WO2020207255A1 - Substrat de matrice et son procédé de fabrication, écran d'affichage à cristaux liquides, et dispositif d'affichage à cristaux liquides - Google Patents

Substrat de matrice et son procédé de fabrication, écran d'affichage à cristaux liquides, et dispositif d'affichage à cristaux liquides Download PDF

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Publication number
WO2020207255A1
WO2020207255A1 PCT/CN2020/081289 CN2020081289W WO2020207255A1 WO 2020207255 A1 WO2020207255 A1 WO 2020207255A1 CN 2020081289 W CN2020081289 W CN 2020081289W WO 2020207255 A1 WO2020207255 A1 WO 2020207255A1
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WIPO (PCT)
Prior art keywords
substrate
liquid crystal
array substrate
pixel electrode
away
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Application number
PCT/CN2020/081289
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English (en)
Chinese (zh)
Inventor
辛昊毅
秦伟达
郭攀
李岩锋
王宁
马凯
陈延青
李伟
宋燕勇
李静
魏威
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2020207255A1 publication Critical patent/WO2020207255A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present disclosure relates to the field of liquid crystal display technology, in particular to an array substrate and a preparation method thereof, a liquid crystal display panel, and a liquid crystal display device.
  • Liquid crystal display (Liquid Crystal Display, referred to as LCD) has become more and more widely used due to its advantages of low power consumption, miniaturization, lightness and thinness.
  • liquid crystal display devices have been used in many fields such as mobile phones, flat panel displays, vehicles, televisions, and public displays.
  • an array substrate including a substrate, a thin film transistor, a flat layer, a pixel electrode, and a filling part.
  • the thin film transistor is arranged on the substrate.
  • the flat layer is arranged on the side of the thin film transistor away from the substrate, and the flat layer has a via hole penetrating the flat layer.
  • the pixel electrode is arranged on a side of the flat layer away from the substrate, and is recessed at the via hole to form a recessed portion, and the recessed portion passes through the via hole to electrically contact the drain of the thin film transistor.
  • At least a part of the filling part is located in the recessed part of the pixel electrode.
  • the part of the filling part located in the recessed part is the first part.
  • the surface of the first part away from the substrate and the surface of the flat layer away from the substrate are in the same plane, or the distance from the surface of the first part away from the substrate to the substrate is greater than that of the flat layer. The distance from the surface of the flat layer away from the substrate to the substrate.
  • the The filling part further includes a second part arranged outside the recessed part.
  • the surface of the second part away from the substrate and the surface of the first part away from the substrate are in the same plane.
  • the material of the filling part and the material of the flat layer are the same.
  • the array substrate further includes a main spacer disposed on a side of the pixel electrode away from the substrate.
  • the material of the filling part is the same as the material of the main spacer.
  • the orthographic projection of the main spacer on the substrate is located within the boundary of the orthographic projection of the recess on the substrate.
  • the main spacer and the part of the filling part located in the recessed part are integrally formed.
  • the array substrate further includes: auxiliary spacers arranged on a side of the pixel electrode away from the substrate.
  • the material of the main spacer and the auxiliary spacer are the same and arranged in the same layer.
  • the array substrate further includes: a common electrode provided between the filling part and the pixel electrode, and an insulating layer provided between the common electrode and the pixel electrode.
  • the common electrode and the insulating layer are recessed at the via hole to form a recessed portion, and at least a part of the filling portion is located in the recessed portion of the common electrode.
  • the material of the filling portion is positive photoresist or negative photoresist.
  • a method for preparing an array substrate including: forming a thin film transistor on a substrate; forming a flat layer on the side of the thin film transistor away from the substrate; and forming a flat layer on the flat layer away from the substrate
  • a pixel electrode is formed on one side of the pixel electrode; a filling portion is formed on the side of the pixel electrode away from the substrate.
  • the flat layer has a via hole penetrating the flat layer.
  • the pixel electrode is recessed at the via hole to form a recessed portion, and the recessed portion of the pixel electrode passes through the via hole to electrically contact the drain of the thin film transistor. At least a part of the filling part is located in the recessed part of the pixel electrode.
  • the part of the filling part located in the recessed part and the main spacer are integrally formed.
  • a liquid crystal display panel including the array substrate described in some of the above embodiments, a counter substrate disposed opposite to the array substrate, and a liquid crystal disposed between the array substrate and the counter substrate Floor.
  • liquid crystal display device including the liquid crystal display panel described in some of the above embodiments.
  • FIG. 1 is a structural diagram of a liquid crystal display device according to some embodiments of the present disclosure
  • FIG. 2A is a structural diagram of an edge-type backlight module according to some embodiments of the present disclosure.
  • 2B is a structural diagram of a direct type backlight module according to some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of area division of a liquid crystal display panel according to an embodiment of the present disclosure
  • Figure 4 is a structural diagram of a liquid crystal display panel in the related art
  • FIG. 5A is a structural diagram of a liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 5B is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • 5C is a top structural view of an array substrate according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of another array substrate provided according to some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 10 is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 12 is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 13 is a structural diagram of another liquid crystal display panel provided according to some embodiments of the present disclosure.
  • FIG. 14 is a flowchart of a method for manufacturing an array substrate according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviation due to, for example, manufacturing.
  • the etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • FIG. 1 shows a structural diagram of a liquid crystal display device.
  • the main structure of the liquid crystal display device includes a frame 1, a cover plate 2, a liquid crystal display panel 3, a backlight module 4, a circuit board 5 and other electronic accessories.
  • the frame 1 surrounds an accommodating space
  • the liquid crystal display panel 3, the backlight module 4, the circuit board 5 and other electronic accessories are arranged in the accommodating space
  • the cover plate 2 is arranged on the open side of the frame 1.
  • the liquid crystal display panel 3 is arranged close to the cover 2 relative to the backlight module 4 and the circuit board 5, the circuit board 5 is arranged away from the cover 2 relative to the liquid crystal display panel 3 and the backlight module 4, and the backlight module 4 is arranged on the liquid crystal display panel 3. Between and circuit board 5.
  • the backlight module 4 includes a light source 41, a light guide plate 42, and an optical film 43 arranged on the light exit side of the light guide plate 42.
  • the optical film 43 may include a diffusion sheet and/or a brightness enhancement film and the like.
  • the brightness enhancement film can be, for example, a prism film (Brightness Enhancement Film, referred to as BEF) or a reflective polarized brightness enhancement film (Dual Brightness Enhancement Film, referred to as DBEF), or a composite brightness enhancement film that combines a prism film and a reflective polarization enhancement film membrane.
  • the shape of the light guide plate 42 may be a wedge shape or a flat plate shape.
  • FIG. 2A illustrates that the shape of the light guide plate 42 is a wedge shape as an example
  • FIG. 2B illustrates that the shape of the light guide plate 42 is a flat shape as an example.
  • the light source 41 may be arranged on the side of the light guide plate 42, as shown in FIG. 2A.
  • the backlight module 4 is called an edge-type backlight module.
  • the light source 41 may also be disposed on the side of the light guide plate 42 far from the light exit side, as shown in FIG. 2B.
  • the backlight module 4 is called a direct type backlight module.
  • the light source 41 may be, for example, a light-emitting diode (Light-Emitting Diode, LED for short).
  • the light source 41 can be a light board made of tiny blue LEDs arranged in an array, and the light-emitting direction of the light board faces the liquid crystal display panel 3.
  • the backlight module 4 may further include a reflective sheet 44, and the reflective sheet 44 may be disposed on a side of the light guide plate 42 far from the light exit side.
  • the reflective sheet 44 may be arranged on the side of the light source 41 away from the light guide plate 42.
  • FIG. 3 shows a schematic diagram of the area division of the liquid crystal display panel 3.
  • the liquid crystal display panel 3 includes a display area (also referred to as AA area) 31 and a peripheral area 32.
  • FIG. 3 takes the display area 31 surrounded by the peripheral area 32 as an example for illustration.
  • the display area 31 includes a plurality of pixel areas 33, and each pixel area 33 includes at least a red sub-pixel area 33A, a green sub-pixel area 33B, and a blue sub-pixel area 33C.
  • the arrangement of the above three sub-pixel regions may be a stripe arrangement, a triangle arrangement or a diagonal arrangement.
  • FIG. 1 shows a schematic diagram of the area division of the liquid crystal display panel 3.
  • the liquid crystal display panel 3 includes a display area (also referred to as AA area) 31 and a peripheral area 32.
  • FIG. 3 takes the display area 31 surrounded by the peripheral area 32 as an example for illustration.
  • the display area 31 includes a plurality of pixel areas 33, and each
  • FIG. 3 illustrates an example in which the arrangement of the red sub-pixel area 33A, the green sub-pixel area 33B, and the blue sub-pixel area 33C is a strip arrangement.
  • the stripe arrangement in the first direction, three red sub-pixel regions 33A, green sub-pixel regions 33B, and blue sub-pixel regions 33C are periodically arranged, and in the second direction, the red sub-pixel regions 33A , The green sub-pixel area 33B and the blue sub-pixel area 33C are arranged in rows, respectively.
  • the liquid crystal display panel 3 includes an array substrate 10 and a counter substrate 20 disposed opposite to each other, and a liquid crystal layer 30 disposed between the array substrate 10 and the counter substrate 20.
  • the array substrate 10 and the counter substrate 20 can be pasted together by the frame sealant 40 so that the liquid crystal layer 30 is confined in the area enclosed by the frame sealant 40.
  • the counter substrate 20 includes a color filter layer 201 disposed on the substrate 200.
  • the counter substrate 20 may also be referred to as a color filter substrate.
  • the color filter layer 201 includes at least a red photoresist unit, a green photoresist unit and a blue photoresist unit.
  • the red photoresist unit, the green photoresist unit and the blue photoresist unit are respectively connected to the sub-pixel areas on the array substrate 31.
  • the substrate 200 of the counter substrate 20 is referred to as the second substrate, and the substrate of the array substrate 10 appearing below is referred to as the first substrate.
  • the counter substrate 20 may further include a black matrix pattern 202 (Black Matrix, BM for short), and the black matrix pattern 202 is used for The red photoresist unit, the green photoresist unit and the blue photoresist unit are spaced apart.
  • a black matrix pattern 202 Black Matrix, BM for short
  • the counter substrate 20 when the counter substrate 20 includes a color filter layer 201 and a black matrix pattern 202, the counter substrate 20 may further include a flat layer (Over Coat, OC for short) 203, which is flat.
  • the layer 203 is disposed on the side of the color filter layer 201 and the black matrix pattern 202 away from the second substrate 200.
  • the flat layer 203 provided on the counter substrate 20 is referred to as the second flat layer in the embodiment of the present disclosure.
  • the manufacturing process of the counter substrate 20 may be, for example: A black matrix pattern 202 is formed on the second substrate 200, and then a color filter layer 201 is formed, and then a second flat layer 203 is formed.
  • the manufacturing process of the counter substrate 20 further includes: forming a second alignment layer on the side of the second flat layer 203 away from the second substrate 200.
  • the manufacturing process of the second alignment layer can be, for example, coating a thin film on the second flat layer 203.
  • the material of the thin film can be, for example, polyimide (PI for short).
  • optical alignment Optical Alignment
  • OA optical Alignment
  • the color filter layer 201 may not be provided on the counter substrate 20, but the color filter layer is provided in the array substrate 10.
  • the array substrate 10 may be called a COA substrate (Color filter on Array, the color filter layer is integrated on the array substrate).
  • the black matrix pattern 202 may also be provided on the array substrate 10, for example, on the substrate of the array substrate 10 (ie, the first substrate 100).
  • the black matrix pattern 202 may be disposed on the opposite substrate 20, for example, on the substrate of the opposite substrate 20 (ie, the second substrate 200).
  • the structure of the array substrate can refer to the structure of the array substrate 10 in FIG. 4.
  • the array substrate 10 is provided with a pixel electrode 101 and a thin film transistor (TFT for short) 102 in each sub-pixel area.
  • the thin film transistor 102 includes an active layer (Active, Act) 1022, a gate (Gate) 1023, a source 1020, and a drain 1021 sequentially disposed on the substrate (ie, the first substrate 100) of the array substrate.
  • the pixel electrode 101 passes through the via hole 1031 that penetrates the first flat layer 103 in the array substrate 10 and is in electrical contact with the drain of the thin film transistor 102.
  • the first substrate 100 of the array substrate 10 and the second substrate 20 of the counter substrate 20 A Main Photo Spacer (Main PS) 105 is arranged between the bottom 200, as shown in FIG. 4.
  • Main PS Main Photo Spacer
  • the size of the via holes 1031 on the first flat layer 103 is larger, and the spacing between the via holes 1031 is relatively large.
  • the main spacer 105 can easily fall into the first In the via hole 1031 on the flat layer 103, see FIG. 4. If the main spacer 105 falls into the through hole 1031 on the first flat layer 103, the thickness of the liquid crystal cell in the display area 31 of the liquid crystal display panel 3 will be reduced, resulting in the liquid crystal cell in the display area 31 of the liquid crystal display panel 3. The thickness does not meet the design requirements.
  • the frame sealant 40 has a supporting effect on the peripheral area of the liquid crystal display panel 3
  • the main spacer 105 falls into the via hole 1031 on the first flat layer 103, which will cause the peripheral area 32 of the liquid crystal display panel 3
  • the thickness of the liquid crystal cell is greater than that of the display area 31, that is, the thickness of the liquid crystal cell in the display area 31 of the liquid crystal display panel 3 and the thickness of the liquid crystal cell in the peripheral area 32 are not uniform.
  • the uneven thickness of the liquid crystal cell will cause problems such as poor brightness uniformity, peripheral mura (spots), and insufficient recovery of the liquid crystal display panel 3.
  • the liquid crystal orientation is disordered at the slope of the via hole 1031 on the first flat layer 103, which causes the liquid crystal display panel 3 to leak light in the dark state.
  • the embodiment of the present disclosure provides an array substrate 10 that can be applied to the above-mentioned liquid crystal display panel 3.
  • the array substrate 10 provided by an embodiment of the present disclosure includes a first substrate 100, a thin film transistor 102 disposed on the first substrate 100, and a thin film transistor 102 disposed on the side of the thin film transistor 102 away from the first substrate 100
  • the first flat layer 103, the pixel electrode 101 and the filling portion 104 disposed on the side of the first flat layer 103 away from the first substrate 100.
  • the first flat layer 103 has a via 1031 penetrating the first flat layer 103, the pixel electrode 101 is recessed at the via 1031 to form a recess 1011, and the recess 1011 of the pixel electrode 101 passes through the via 1031 and the thin film transistor 102.
  • the drain 1021 is in electrical contact, and at least a part of the filling portion 104 is located in the recessed portion 1011 of the pixel electrode 101.
  • the material of the pixel electrode 101 may be, for example, indium tin oxide (Indium Tin Oxide, ITO for short) or indium zinc oxide (Indium Zinc Oxide, IZO for short).
  • the embodiment of the present disclosure can avoid the low thickness of the liquid crystal cell of the liquid crystal display panel 3 due to the main spacer 105 falling into the via hole on the first flat layer 103, and the display area 31 and the periphery of the liquid crystal display panel 3
  • the problem of the uneven thickness of the liquid crystal cell in the area 32 can further improve the poor brightness uniformity, peripheral spots, and insufficient recovery caused by the uneven thickness of the liquid crystal cell.
  • the filling portion 104 is disposed in the recessed portion 1011 of the pixel electrode 101, the problem of the disorder of the liquid crystal orientation caused by the existence of the via hole 1031 on the first flat layer 103 can be improved, thereby improving the liquid crystal display panel in the dark state. 3.
  • the structure of the thin film transistor 102 may be as shown in FIG. 5A, including an active layer 1022, a gate insulating layer (Gate Insulator, GI) 1024, a gate 1023, Inter-layer Dielectric (ILD for short) 1025, source 1020, and drain 1021.
  • GI Gate Insulator
  • ILD Inter-layer Dielectric
  • the material of the gate insulating layer 1024 and the interlayer defining layer 1025 may include, for example, one or more of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy).
  • the aforementioned interlayer delimiting layer 1025 may include a first sublayer delimiting layer and a second sublayer delimiting layer that are stacked, and the material of the first sublayer delimiting layer and the material of the second sublayer delimiting layer are different.
  • the material of the first sub-layer delimiting layer may be silicon oxide
  • the material of the second sub-layer delimiting layer may be silicon nitride.
  • the structure of the thin film transistor 102 may be as shown in FIG. 5B, including a gate electrode 1023, a gate insulating layer 1024, an active layer 1022, a source electrode 1020, and a drain electrode 1021 which are sequentially disposed on the first substrate 100.
  • the gate electrode 1023 is close to the first substrate 100 relative to the active layer 1022, and the source electrode 1020 and the drain electrode 1021 are relative to the active layer 1022.
  • the thin film transistor of this structure can be called a bottom-gate thin film transistor.
  • the structure of the thin film transistor 102 may also be a top-gate thin film transistor.
  • the source and drain of the top-gate thin film transistor are in a direction perpendicular to the display surface of the liquid crystal display panel 3.
  • the source layer is close to the first substrate 100, and the gate is far away from the first substrate 100 relative to the active layer.
  • the active layer is close to the first substrate 100 relative to the gate, and the source and drain are away from the first substrate 100 relative to the gate.
  • the array substrate 10 further includes gate lines 111 and data lines 112. As shown in FIG. 5C, the gate line 111 is electrically connected to the gate electrode 1023 of the thin film transistor 102, and the data line 112 is electrically connected to the source electrode 1020 of the thin film transistor 102. The data line may also be electrically connected to the drain of the thin film transistor 102, which is not limited in the embodiment of the present disclosure.
  • the portion of the filling portion 104 located in the recess portion 1011 of the pixel electrode 101 is referred to as the first portion 1041.
  • the filling part 104 may only include the first part, that is, the filling part 104 is only provided in the recess 1011 of the pixel electrode 101.
  • the first part in order to ensure that the thickness of the liquid crystal cell in the display area 31 of the liquid crystal display panel 3 can meet the design requirements, in some embodiments, the first part can be arranged flush with the first flat layer 103, that is, the first part is far away
  • the surface of the first substrate 100 and the surface of the first flat layer 103 away from the first substrate 100 are in the same plane. In this way, it can be avoided that the height of the filling portion 104 provided in the recess 1011 of the pixel electrode 101 is too small, causing the main spacer 105 to fall into the pixel electrode 101 when the array substrate 10 and the counter substrate 20 are aligned.
  • the problem of insufficient liquid crystal cell thickness in the display area 31 of the liquid crystal display panel 3 caused by the concave portion 1011 of the liquid crystal display panel 3 makes the liquid crystal cell thickness of the display area 31 of the liquid crystal display panel 3 meet the design requirements and solves the problem of the display area of the display panel 3.
  • the problem of uneven thickness of the liquid crystal cell 31 and the peripheral area 32 is the problem of uneven thickness of the liquid crystal cell 31 and the peripheral area 32.
  • the first portion 1041 of the filling portion 104 may be set slightly higher than the first flat layer 103, that is, the first portion 1041 of the filling portion 104 is far from the surface of the first substrate 100 to The distance of the first substrate 100 is greater than the distance from the surface of the first flat layer 103 away from the first substrate 100 to the first substrate 100.
  • the filling portion 104 may also include a second portion 1042 disposed outside the recessed portion 1011 of the pixel electrode 101.
  • the second part 1042 of the filling part 104 can be arranged flush with the first part 1041, so that the second part of the filling part 104 is away from the surface of the first substrate 100 and the first part of the filling part 104
  • the surface 1041 away from the first substrate 100 is in the same plane, so the main spacer 105 can be prevented from falling into the recessed portion 1011 of the pixel electrode 101, which may cause insufficient thickness of the liquid crystal cell in the display area 31 of the liquid crystal display panel 3 and display
  • the thickness of the liquid crystal cell in the display area 31 and the peripheral area 32 of the panel 3 is uneven.
  • the material of the filling part 104 may be the same as the material of the first flat layer 103.
  • the material of the filling portion 104 and the first flat layer 103 may be positive photoresist or negative photoresist, which is not limited in the embodiment of the present disclosure.
  • the array substrate 10 may further include a main spacer 105 disposed on the side of the pixel electrode 101 away from the first substrate 100.
  • the main spacer may not be provided on the counter substrate 20.
  • the main spacer 105 in order to prevent the main spacer 105 from affecting the display effect of the liquid crystal display panel 3, the main spacer 105 is opposite to the black matrix pattern 202, that is, the main spacer 105 is on the black matrix pattern 202.
  • the orthographic projection of is located within the boundary of the black matrix pattern 202.
  • the embodiment of the present disclosure does not limit the material of the main spacer 105, for example, it may be positive photoresist or negative photoresist.
  • the main spacer 105 can be formed by coating a photoresist layer, mask exposure, and developing processes.
  • the alignment difficulty of the array substrate 10 and the counter substrate 20 during packaging can be reduced, thereby improving the alignment accuracy and ensuring the liquid crystal display panel 3.
  • the liquid crystal cell thickness difference between the display area 31 and the peripheral area 32 is small, which ensures the uniformity of the liquid crystal cell thickness of the liquid crystal display panel 3.
  • the main spacer 105 and the pixel electrode 101 can be recessed
  • the portions 1011 are arranged oppositely so that the orthographic projection of the main spacer 105 on the first substrate 10 is within the boundary of the orthographic projection of the recessed portion 1011 of the pixel electrode 101 on the first substrate 100.
  • the contact area between the main spacer 105 and the counter substrate 20 is the largest, and the support strength of the main spacer 105 is the highest, so the main spacer 105 It can better support the counter substrate 20, improve the misalignment of the counter substrate 20 caused by external force impact, and reduce light leakage.
  • the material of the filling portion 104 and the material of the main spacer 105 may be the same or different.
  • the main spacer 105 and the part of the filling part 104 located in the recess 1011 of the pixel electrode 101 are integrally formed.
  • the filling part 104 only includes the first part 1041, the main spacer 105 and the filling part 104 can be formed at the same time when the array substrate 10 is manufactured, thereby simplifying the manufacturing process and improving production efficiency.
  • the above-mentioned "simultaneous formation of the filling portion 104 and the main spacer 105" may be, for example, forming a layer of photosensitive material on the pixel electrode 101, and using a patterning process to mask and develop the photosensitive material layer to simultaneously form the filling portion 104 And the main spacer 105.
  • the main spacer 105 and the first part 1041 of the filling part 104 are integrally formed, which can prevent the main spacer 105 from falling off the array substrate 10 or the counter substrate 20, thereby improving the LCD panel 3 quality.
  • the main spacer 105 may be formed first, and then the filling part 104; or the filling part 104 may be formed first, and then the main spacer 105 .
  • an auxiliary spacer 106 is provided on the side of the second flat layer 203 of the counter substrate 20 away from the second substrate 200.
  • the auxiliary spacer 106 and the main spacer 105 can jointly buffer the impact of the external pressure on the liquid crystal display panel 3, so that the liquid crystal display panel 3 maintains a certain cell thickness.
  • the height of the main spacer 105 is greater than the height of the auxiliary spacer 106, and the height difference between the main spacer 105 and the auxiliary spacer 106 can make the liquid crystal display panel 3 have a certain amount of deformation, thereby making the liquid crystal display The panel 3 can withstand a certain external impact.
  • the auxiliary spacer 106 may also be disposed on the side of the pixel electrode 101 of the array substrate 10 away from the first substrate 100. On this basis, the auxiliary spacer 106 may not be provided on the opposite substrate 20.
  • the surface level difference of the counter substrate 20 may be less than 0.1 ⁇ m.
  • the material of the main spacer 105 and the auxiliary spacer 106 are the same and arranged in the same layer.
  • “same layer arrangement” refers to forming a film layer for forming a specific pattern using the same film forming process, and then simultaneously forming the main spacer 105 and the auxiliary spacer 106 through one patterning process using the same mask.
  • a patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be different. Or have different thicknesses.
  • the main spacer 105 and the auxiliary spacer 106 are the same and are arranged in the same layer, the main spacer 105 and the auxiliary spacer 106 can be formed at the same time, thereby simplifying the manufacturing process of the liquid crystal display panel 3.
  • the orthographic projections of the main spacer 105 and the auxiliary spacer 106 on the black matrix pattern 202 are equal. It is located within the boundary of the black matrix pattern 202.
  • the array substrate 10 further includes a common electrode 107 disposed on the first substrate 100.
  • the material of the common electrode 107 may be, for example, indium tin oxide or indium zinc oxide.
  • the common electrode 107 and the pixel electrode 101 can generate a horizontal electric field or fringe electric field, which can drive the liquid crystal layer 30 in the liquid crystal layer 30.
  • the liquid crystal molecules rotate, so that the light transmittance of the liquid crystal layer 30 can be changed.
  • the pixel electrode 101 and the common electrode 107 can be arranged in the same layer.
  • the pixel electrode 101 and the common electrode 107 can adopt a comb-tooth structure including a plurality of strip-shaped sub-electrodes, and the strip-shaped sub-electrodes of the pixel electrode 101 and the common electrode 107 are mutually connected. staggered.
  • the pixel electrode 101 and the common electrode 107 may be arranged in different layers.
  • the common electrode 107 can be arranged between the filling portion 104 and the pixel electrode 101, and a separating electrode 101 and the common electrode 107 can also be arranged between the pixel electrode 101 and the common electrode 107.
  • the common electrode 107 may also be provided between the thin film transistor 102 and the pixel electrode 101, and between the common electrode 107 and the thin film transistor 102 may also be provided for separating the thin film transistor 102 and the pixel electrode. 101 of the second insulating layer.
  • the common electrode 107 and the first insulating layer 108 are recessed at the via hole 1031 to form a recess, and the filling portion At least a part of 104 is located in the recess of the common electrode 107.
  • the array substrate 10 may further include the thin film transistor 102 and the first substrate.
  • the light shielding layer (LS) 109 between the substrates 100 and the orthographic projection of the active layer 1022 of the thin film transistor 102 on the light shielding layer 109 and the light shielding layer 109 have an overlapping area.
  • the light shielding layer 109 can prevent light from irradiating the active layer 1022 to generate photo-generated carriers, which affects the performance of the thin film transistor 102.
  • the array substrate 10 may further include a buffer layer (Buffer) 110 disposed between the light shielding layer 109 and the thin film transistor 102.
  • Buffer buffer layer
  • the arrangement of the buffer layer 110 can not only make the surface on which the thin film transistor 102 is arranged, and shield the defects of the first substrate 100, but also can prevent impurity ions from penetrating into the first substrate 100 to cause various defects of the device. .
  • a light shielding layer 109, a buffer layer 110, an active layer 1022, and a gate insulating layer are sequentially formed on the first substrate 100.
  • the active layer 1022, the gate insulating layer 1024, the gate 1023, the interlayer defining layer 1025, the source 1020 and the drain 1021 constitute the thin film transistor 102.
  • a first flat layer 103 is formed on the source electrode 1020 and the drain electrode 1021, and a via hole 1031 is formed on the first flat layer 103 to expose the drain electrode 1021 of the thin film transistor 102.
  • a pixel electrode 101 is formed on the first flat layer 103, and the pixel electrode 101 passes through the via hole 1031 on the first flat layer 103 and electrically contacts the drain 1021 of the thin film transistor 102.
  • a first insulating layer 108 and a common electrode 107 are sequentially formed on the pixel electrode 101. On the common electrode 107 and at a position facing the via hole 1031 on the first flat layer 103, the filling portion 104 and the main spacer 105 are simultaneously formed through an integral molding process.
  • the manufacturing process of the array substrate 10 may further include: forming a first alignment layer on the side of the main spacer 105 away from the first substrate 100.
  • the manufacturing process of the first alignment layer may be, for example, coating a first alignment layer film on the side of the main spacer 105 away from the first substrate 100.
  • the material of the first alignment layer film may be polyimide, for example, After that, the first alignment layer film is photo-aligned to form a first alignment layer.
  • sealant 40 can be formed on the surface of the array substrate 10 close to the liquid crystal layer 30 or the surface of the counter substrate 20 close to the liquid crystal layer 30, and the sealant 40 can be formed on the array substrate 10
  • Liquid crystal (LC) is filled between the counter substrate 20 and the liquid crystal layer 30 to form a liquid crystal layer 30, and then the array substrate 10 and the counter substrate 20 are vacuum aligned to form a liquid crystal display panel mother board.
  • the liquid crystal display panel mother board includes a plurality of liquid crystal display panel units. After cutting the liquid crystal display panel mother board, a plurality of liquid crystal display panels 3 can be formed.
  • the liquid crystal display panel 3 may further include an upper polarizer 50 disposed on the side of the counter substrate 20 away from the liquid crystal layer 30 and a lower polarizer 50 disposed on the side of the array substrate 10 away from the liquid crystal layer 30.
  • the transmission axes of the polarizer 60, the upper polarizer 50 and the lower polarizer 60 are perpendicular or parallel to each other.
  • the light transmission axes of the upper polarizer 50 and the lower polarizer 60 are perpendicular to each other as an example.
  • the display of the liquid crystal display device The principle is: the backlight module 4 emits white light, passes through the lower polarizer 60 to form white polarized light with a specific polarization direction, enters the liquid crystal display panel 3, and is filtered by the color filter layer 201 to form red, green and blue polarized light.
  • the polarized light When the polarization direction of the polarized light is perpendicular to the polarization direction of the upper polarizer 50, the polarized light cannot pass through the upper polarizer; when the polarization direction of the polarized light is parallel to the polarization direction of the upper polarizer 50, the polarized light can pass through On the polarizer 50, the intensity of the emitted light is the strongest at this time.
  • the specific molecular arrangement direction can change the polarization direction of the polarized light.
  • the arrangement direction of the liquid crystal molecules is controlled by the electric field generated between the pixel electrode 101 and the common electrode 107, it rotates. At this time, the direction of the polarized light passing through the liquid crystal molecules also changes, so that the amount of polarized light emitted from the upper polarizer 50 can be controlled.
  • the pixel electrode 101 and the common electrode 107 regularly control the rotation of the liquid crystal molecules according to the electrical signals applied to the respective electrodes, the light of the red, green and blue sub-pixels will regularly pass through the upper polarizer 50 and finally form a color image.
  • the above-mentioned light path propagation sequence is: exit from the backlight module 4 and sequentially pass through the lower polarizer 60, the array substrate 10, the liquid crystal layer 30, the opposite substrate 20, and the upper polarizer 50.
  • the embodiment of the present disclosure also provides a preparation method of the array substrate.
  • the preparation method includes:
  • a pixel electrode 101 is formed on the side of the first flat layer 103 away from the first substrate 100, the pixel electrode 101 is recessed at the via hole to form a recess 1011, and the recess 1011 of the pixel electrode 101 passes through the via hole and the thin film transistor 102
  • the drain 1021 is in electrical contact.
  • the part (that is, the first part 1041) of the filling part 104 located in the recessed part 1011 and the main spacer are integrally formed. ⁇ 105 ⁇ 105.
  • the array substrate preparation method provided by the embodiment of the present disclosure can be used to prepare the array substrate 10 in the above-mentioned embodiment, the technical effects that can be obtained can refer to the above-mentioned embodiment of the array substrate 10, which will not be repeated here.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

La présente invention concerne un substrat de matrice et son procédé de fabrication, un écran d'affichage à cristaux liquides et un dispositif d'affichage à cristaux liquides. Le substrat de matrice comporte un substrat, un transistor à couches minces, une couche de planarisation, une électrode de pixel, et une partie de remplissage . Le transistor à couches minces est disposé sur le substrat. La couche de planarisation est disposée sur le transistor à couches minces sur un côté éloigné du substrat, et la couche de planarisation comporte un trou d'interconnexion qui pénètre dans la couche de planarisation. L'électrode de pixel est disposée sur la couche de planarisation au niveau d'un côté éloigné du substrat, et est évidée au niveau du trou d'interconnexion pour former une partie en retrait, ladite partie en retrait pénétrant dans le trou d'interconnexion et étant en contact électrique avec l'électrode de drain du transistor à couches minces. Au moins une partie de la partie de remplissage se trouve à l'intérieur de la partie en retrait de l'électrode de pixel.
PCT/CN2020/081289 2019-04-09 2020-03-26 Substrat de matrice et son procédé de fabrication, écran d'affichage à cristaux liquides, et dispositif d'affichage à cristaux liquides WO2020207255A1 (fr)

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CN109870855A (zh) * 2019-04-09 2019-06-11 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及液晶显示装置
CN110034132B (zh) * 2019-06-12 2019-10-29 成都京东方光电科技有限公司 一种阵列基板、显示面板及显示装置
CN110941123A (zh) * 2019-11-07 2020-03-31 深圳市华星光电半导体显示技术有限公司 Coa型阵列基板及其制造方法
CN111208677A (zh) * 2020-03-16 2020-05-29 Tcl华星光电技术有限公司 阵列基板及液晶显示面板
CN111766733A (zh) * 2020-07-31 2020-10-13 京东方科技集团股份有限公司 透明显示面板及其制备方法、显示装置
CN113064304B (zh) * 2021-03-29 2022-09-20 京东方科技集团股份有限公司 液晶显示面板及其制作方法、液晶显示装置
CN114217481B (zh) * 2021-12-30 2022-12-23 绵阳惠科光电科技有限公司 显示面板和显示装置
WO2023225980A1 (fr) * 2022-05-27 2023-11-30 京东方科技集团股份有限公司 Écran d'affichage à cristaux liquides et dispositif d'affichage
CN115236902B (zh) * 2022-06-16 2023-11-28 京东方科技集团股份有限公司 阵列基板、液晶显示面板及液晶显示装置
WO2024020767A1 (fr) * 2022-07-26 2024-02-01 京东方科技集团股份有限公司 Substrat de réseau et son procédé de préparation, cellule à cristaux liquides et dispositif d'affichage
WO2024045076A1 (fr) * 2022-08-31 2024-03-07 京东方科技集团股份有限公司 Substrat de réseau et son procédé de fabrication, et panneau à cristaux liquides

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