WO2020154976A1 - 电路设计版图和电镜扫描图像的配准方法及系统、电路设计版图和其成像误差计算方法及电子设备 - Google Patents

电路设计版图和电镜扫描图像的配准方法及系统、电路设计版图和其成像误差计算方法及电子设备 Download PDF

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Publication number
WO2020154976A1
WO2020154976A1 PCT/CN2019/073986 CN2019073986W WO2020154976A1 WO 2020154976 A1 WO2020154976 A1 WO 2020154976A1 CN 2019073986 W CN2019073986 W CN 2019073986W WO 2020154976 A1 WO2020154976 A1 WO 2020154976A1
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Prior art keywords
electron microscope
image
design layout
pattern
circuit design
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PCT/CN2019/073986
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English (en)
French (fr)
Inventor
闫歌
李强
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深圳晶源信息技术有限公司
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Priority to PCT/CN2019/073986 priority Critical patent/WO2020154976A1/zh
Priority to CN201910117849.XA priority patent/CN111507055B/zh
Publication of WO2020154976A1 publication Critical patent/WO2020154976A1/zh
Priority to US17/389,394 priority patent/US12062196B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G06T5/20—Image enhancement or restoration using local operators
    • G06T5/30—Erosion or dilatation, e.g. thinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/30—Determination of transform parameters for the alignment of images, i.e. image registration
    • G06T7/33—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
    • G06T7/337—Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods involving reference images or patches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/40—Filling a planar surface by adding surface attributes, e.g. colour or texture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G06T5/70—Denoising; Smoothing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/13—Edge detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/30—Determination of transform parameters for the alignment of images, i.e. image registration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10056—Microscopic image
    • G06T2207/10061—Microscopic image from scanning electron microscope
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Definitions

  • the invention relates to the field of integrated circuit manufacturing, in particular to a method and system for registering a circuit design layout and an electron microscope scanned image, a circuit design layout, a method for calculating imaging errors thereof, and electronic equipment.
  • OPC Optical Proximity Correction
  • the present invention proposes a method and system for registering the circuit design layout and the electron microscope scan image, the circuit design layout and its imaging error calculation method and electronic equipment.
  • a method for registering a circuit design layout and a scanning electron microscope image includes: Step S1: Provide a circuit to be registered The design layout and the electron microscope scan image.
  • the circuit design layout to be registered includes at least one design pattern, and the electron microscope scan image to be registered includes at least one scan pattern corresponding to the at least one design pattern; the design pattern covers its corresponding Scan the pattern;
  • Step S2 Process the circuit design layout to be registered to obtain a binary image of the design layout, the gray value of the design pattern area in the binary image of the design layout is 1, and the external gray value is 0; to be registered
  • the scanning image processing of the electron microscope obtains the binary image of the electron microscope scanning, the gray value in the scanning pattern area of the electron microscope scanning binary image is 1, and the external gray value is 0;
  • Step S3 the binary image of the design layout and the electron microscope scanning two Gaussian filtering is performed on the value image to maximize the gray value at the central axis of the area corresponding to the design pattern and the scan pattern;
  • step S4 registration is performed according to the central axis of the design pattern and the scan pattern.
  • step S1 includes: step S11: obtaining the coordinates of the scanning pattern in the electron microscope scanned image to be registered; step S12: determining the corresponding area in the circuit design layout to be registered according to the coordinates; and step S13: correcting The area extends a distance D to obtain a design pattern corresponding to the scanning pattern, and D is less than or equal to 50 nm.
  • step S2 includes step Sa0: smoothing the design pattern in the circuit design layout to be registered; step S2 includes step Sa1: internal filling the design pattern to obtain a binary image of the design layout, The gray value in the design pattern area in the binary image of the design layout is 1, and the outer gray value is 0.
  • Step S2 includes: Step Sb1: Perform contour extraction on the electron microscope scanned image to be registered; and Step Sb2: Fill the scanning pattern internally to obtain an electron microscope scanned binary image, and the electron microscope scans the scanning pattern area in the binary image
  • the gray value of is 1, and the external gray value is 0.
  • step Sb1 includes steps Sb1-1 and Sb1-2, or includes steps Sb1-1' and Sb1-2', and steps Sb1-1 and Sb1-2 are: Step Sb1-1: through edge detection in image processing The algorithm obtains the edge of the scan pattern; and Step Sb1-2: performs expansion and erosion processing to obtain the outline of the scan pattern; Steps Sb1-1' and Sb1-2' are: Step Sb1-1': the electron microscope scanned image to be registered Corrosion processing is performed; and step Sb1-2': obtaining the contour of the scan pattern through the edge detection algorithm in the image processing.
  • step Sb1 includes: step Sb1-a: setting a grayscale threshold; and step Sb1-b: comparing the pixel value of the pixel in the electron microscope scanned image to be registered with the grayscale threshold to obtain the outline of the scan pattern .
  • the binary image of the design layout is subjected to Gaussian filtering to obtain the first image; the electron microscope scans the binary image and performs Gaussian filtering to obtain the second image; in step S4, an image template matching method is used to register the design pattern and the scanned pattern, and the image Template matching methods include normalized correlation system It is the image gray value of (x′,y′) in the electron microscope scan image, the pixel position of the electron microscope scan image on the circuit design layout is (x+x′,y+y′), and the pixel value is I(x+x ′, y+y′).
  • the present invention also provides a registration system for a circuit design layout and an electron microscope scan image, including: an input module for inputting and providing the circuit design layout to be registered and the electron microscope scan image.
  • the circuit design layout to be registered includes at least one design Pattern
  • the scanning electron microscope image to be registered includes at least one scanning pattern corresponding to the at least one design pattern; the design pattern covers its corresponding scanning pattern;
  • a binary image processing module for the circuit design layout to be registered Process to obtain a binary image of the design layout, the gray value of the design pattern area in the binary image of the design layout is 1, and the external gray value is 0; and used to process the electron microscope scan image to be registered to obtain the electron microscope scan binary image Image, the gray value in the scanning pattern area of the electron microscope scanned binary image is 1, and the external gray value is 0;
  • Gaussian filter module used to perform Gaussian filtering on the design layout binary image and the electron microscope scanned binary image to make The gray value is the largest at the central axis of the area corresponding to the design pattern and
  • the present invention also provides a circuit design layout and its imaging error calculation method.
  • the circuit design layout and its imaging error calculation method include: Step P1: Use the circuit design layout and the registration method of the electron microscope scan image as described above to design The pattern and the scanning pattern are registered, and the scanning electron microscope image corresponds to the imaging of the circuit design layout on the substrate; and Step P2: calculating the error between the design pattern and the scanning pattern to obtain the circuit design layout and its imaging error.
  • the present invention also provides an electronic device including a memory and a processor, and a computer program is stored in the memory, and the computer program is configured to execute the above-mentioned circuit design layout and its imaging error calculation method when running;
  • the processor is configured to execute the circuit design layout and its imaging error calculation method as described above through the computer program.
  • the method for registering the circuit design layout and the electron microscope scan image obtained by the present invention obtains the design layout binary image and the electron microscope scan binary image by processing the circuit design layout to be registered and the electron microscope scan image Then, Gaussian filtering is performed on the binary image of the design layout and the binary image scanned by the electron microscope to maximize the gray value at the central axis of the area corresponding to the design pattern and the scanning pattern, and the registration is performed according to the central axis of the design pattern and the scanning pattern.
  • the registration method has the advantages of fast and accurate registration.
  • the design pattern covers its corresponding scanning pattern, which ensures the accuracy of registration.
  • the edge detection algorithm is combined with the expansion processing and the corrosion processing, or the adaptive threshold binarization is used to make the extracted contour more accurate, thereby ensuring the accuracy of the registration.
  • the registration system of the circuit design layout and the scanning image of the electron microscope also has the above advantages. Furthermore, the circuit design layout and its imaging error calculation method and electronic equipment have the advantages of accurate registration and accurate error calculation.
  • FIG. 1 is a schematic flowchart of a method for registering a circuit design layout and an electron microscope scanned image according to a first embodiment of the present invention.
  • Fig. 2 is a schematic flowchart of step S1 in Fig. 1.
  • 3A and 3B are schematic diagrams of the flow of step S2 in FIG. 1.
  • 4A, 4B, and 4C are schematic flowcharts of the modified implementation manner of step Sb1 in FIG. 3B;
  • 5A to 5J are specific examples of the registration method of the circuit design layout and the electron microscope scan image of the first embodiment.
  • FIG. 6 is a schematic diagram of the module of the registration system of the circuit design layout and the scanning image of the electron microscope according to the second embodiment of the present invention.
  • FIG. 7 is a detailed module diagram of the binary image processing module according to the second embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of the circuit design layout and the imaging error calculation method of the third embodiment of the present invention.
  • FIG. 9 is a schematic diagram of modules of an electronic device according to a fourth embodiment of the present invention.
  • the registration method of the circuit design layout and the electron microscope scan image 20.
  • the first embodiment of the present invention provides a method 10 for registering a circuit design layout and an electron microscope scan image.
  • the circuit design layout and its imaging corresponding electron microscope scan image can be registered.
  • the registration method 10 of the circuit design layout and the scanning electron microscope image includes:
  • Step S1 Provide a circuit design layout to be registered and an electron microscope scan image
  • the circuit design layout to be registered includes at least one design pattern
  • the electron microscope scan image to be registered includes at least one scan pattern corresponding to the at least one design pattern ;
  • the design pattern covers its corresponding scanning pattern;
  • Step S2 The circuit design layout to be registered is processed to obtain a binary image of the design layout.
  • the gray value in the design pattern area is 1, and the external gray value is 0;
  • the electron microscope to be registered is scanned Image processing obtains an electron microscope scanned binary image, the gray value of the scanning pattern area in the electron microscope scanned binary image is 1, and the external gray value is 0;
  • Step S3 Gaussian filtering is performed on the binary image of the design layout and the binary image scanned by the electron microscope to maximize the gray value at the central axis of the area corresponding to the design pattern and the scan pattern;
  • Step S4 Perform registration according to the design pattern and the central axis of the scan pattern.
  • Step S1 includes:
  • Step S11 Obtain the coordinates of the scan pattern in the electron microscope scan image to be registered
  • Step S12 Determine the corresponding area in the circuit design layout to be registered according to the coordinates.
  • Step S13 extend the distance D to the area to obtain a design pattern corresponding to the scan pattern.
  • step S12 the general position of the design pattern can be obtained according to the coordinates of the scanning pattern in the scanning electron microscope image. It can be understood that the circuit design layout and the electron microscope scan image to be registered can be a complete image corresponding to a certain integrated circuit or a part of the complete image.
  • D is less than or equal to 60 nm, more preferably D is less than or equal to 50 nm.
  • the design pattern after the extended distance D can usually cover its corresponding scanning pattern to facilitate accurate registration results.
  • step S2 obtaining a binary image of the design layout includes:
  • Step Sa0 smoothing the design pattern in the circuit design layout to be registered.
  • Step Sa1 Fill the design pattern internally to obtain a binary image of the design layout.
  • the gray value in the design pattern area is 1 and the outer gray value is 0.
  • the purpose of the smoothing process is to smoothly process the corners between the sides of the design pattern, for example, a right angle in the design pattern becomes a rounded corner after being smoothed.
  • step Sa1 the interior of the design pattern is filled with white, and then the scanning electron microscope image is binarized to obtain a binary image of the design layout.
  • the gray value in the design pattern area is 1, and the outer gray The degree value is 0.
  • the smoothed electron microscopy scanned image can also be binarized first, and then the pixels inside the design pattern are filled to obtain a binary image of the design layout.
  • the gray value in the design pattern area is 1, and the outer gray value is 0.
  • Filling before the binarization treatment or filling after the binarization treatment belongs to the scope of this step Sa1.
  • step S2 obtaining an electron microscope scanned binary image includes:
  • Step Sb0 Perform denoising processing on the scanned electron microscope image to be registered
  • Step Sb1 perform contour extraction on the scanned electron microscope image to be registered.
  • Step Sb2 Fill the scanning pattern internally to obtain an electron microscope scanned binary image.
  • the gray value in the scanning pattern area is 1, and the external gray value is 0.
  • step Sb0 can be omitted.
  • Methods of denoising processing include but are not limited to median filtering, mean filtering or Gaussian filtering.
  • step Sb1 includes:
  • Step Sb1-1 Obtain the edge of the scan pattern through the edge detection algorithm in image processing.
  • Step Sb1-2 performing expansion treatment and etching treatment to obtain the contour of the scan pattern.
  • the edge detection algorithm includes, but is not limited to, obtaining the edge of the scanning pattern through a gradient algorithm.
  • the contour of the scan pattern in the electron microscope scanned image usually has a certain width
  • two edges are usually detected by the edge detection algorithm.
  • the pixels between the two edges can be filled up by the expansion process.
  • a contour with a certain width is obtained, and the contour with a certain width is etched to obtain the contour of the scan pattern with a narrower width. .
  • the contour of the scan pattern obtained by processing in this manner is more accurate.
  • step Sb1 includes:
  • Step Sb1-1' Corrosion processing is performed on the scanned electron microscope image to be registered.
  • Step Sb1-2' Obtain the contour of the scan pattern through the edge detection algorithm in image processing.
  • step Sb1-1' the electron microscope scan image to be registered is corroded to refine the scan pattern contour width , To avoid the situation of two edges appearing in edge detection.
  • an adaptive threshold binarization is used to extract a contour, which includes:
  • Step Sb1-a setting the gray scale threshold
  • Step Sb1-b The pixel value of the pixel of the electron microscope scanned image to be registered is compared with the gray threshold value to obtain the outline of the scan pattern.
  • the scanning electron microscope image to be registered may be segmented to divide the image into a plurality of blocks before contour extraction is performed.
  • the number of blocks is 2-8, preferably 4 .
  • step S3 the binary image of the design layout is subjected to Gaussian filtering to obtain the first image; the electron microscope scans the binary image and performs Gaussian filtering to obtain the second image; the gray value of the central axis of the design pattern in the first image is the largest, that is The central axis is the brightest, and the gray value of the central axis of the scanning pattern in the second image is the largest, that is, the central axis is the brightest.
  • an image template matching method is used to register the design pattern and the scan pattern.
  • the image template matching method includes a normalized correlation coefficient matching method, and calculating The size of the picture is w*h (h ⁇ H, w ⁇ W).
  • x′ and y′ determine the pixel position in T image (1 ⁇ x′ ⁇ w, 1 ⁇ y′ ⁇ h), T(x′,y′) is the image gray of (x′,y′) in T image Degree value.
  • Figure 5A is the scanning electron microscope image provided in the example
  • Figure 5B is the design layout to be registered provided in the example
  • the design layout to be registered in Figure 5B is After smoothing, the right angle becomes a rounded corner
  • Figure 5C is obtained.
  • the gray value in the design pattern area is 1, and the outer gray value is 0.
  • Gaussian filtering is performed on the scanning electron microscope image in Fig.
  • the scanning pattern is filled internally to obtain a binary image 5F scanned by the electron microscope.
  • Gaussian filtering is performed on FIGS. 5D and 5F to obtain FIGS. 5G and 5H.
  • the gray value is the largest at the central axis of the area corresponding to the design pattern and scan pattern in Figs. 5G and 5H.
  • FIGS. 5I and 5J the design pattern and the scan pattern are registered.
  • the second embodiment of the present invention provides a registration system 20 for a circuit design layout and an electron microscope scanned image.
  • the registration system 20 for a circuit design layout and an electron microscope scan image includes an input module 21 and a binary image processing module 22 , Gaussian filtering module 23 and registration module 24.
  • the input module 21 is used to input and provide a circuit design layout to be registered and an electron microscope scan image.
  • the circuit design layout to be registered includes at least one design pattern, and the electron microscope scan image to be registered includes at least one corresponding to the at least one design pattern.
  • the binary image processing module 22 is used to process the circuit design layout to be registered to obtain a binary image of the design layout, the gray value of the design pattern area in the binary image of the design layout is 1, and the external gray value is 0; and It is used for processing the electron microscope scanning image to be registered to obtain the electron microscope scanning binary image, the gray value in the scanning pattern area of the electron microscope scanning binary image is 1, and the external gray value is 0.
  • the Gaussian filter module 23 is used to perform Gaussian filtering on the binary image of the design layout and the binary image scanned by the electron microscope to maximize the gray value at the central axis of the area corresponding to the design pattern and the scan pattern.
  • the registration module 24 is used to perform registration according to the design pattern and the central axis of the scan pattern.
  • the binary image processing module 22 includes a smoothing processing module 221, a first filling and binarization module 222, a denoising processing module 223, a contour extraction module, and a second filling and binarization module 225.
  • the smoothing processing module 221 is used for smoothing the design patterns in the circuit design layout to be registered.
  • the first filling and binarization module 222 is used to fill the design pattern internally to obtain a binary image of the design layout. In the binary image of the design layout, the gray value in the design pattern area is 1 and the outer gray value is 0.
  • the denoising processing module 223 performs denoising processing on the electron microscope scanned image to be registered.
  • the contour extraction module 224 is used to perform contour extraction on the electron microscope scanned image to be registered.
  • the second filling and binarization module 225 is used to internally fill the scanning pattern to obtain an electron microscope scanned binary image. In the electron microscope scanned binary image, the gray value in the scanning pattern area is 1, and the external gray value is 0
  • the registration system 20 for the circuit design layout and the scanning electron microscope image protected by this embodiment can be used to implement the method 10 for registering the circuit design layout and the scanning electron microscope image provided by the first embodiment.
  • the functions mentioned in the registration method 10 of the circuit design layout and the scanning electron microscope image can be performed by the corresponding modules in the registration system 20 of the circuit design layout and the scanning electron microscope image.
  • the third embodiment of the present invention provides a circuit design layout and its imaging error calculation method 30, which is used to calculate the error between the circuit design layout and its imaging.
  • the circuit design layout and its imaging error calculation method 30 include:
  • Step P1 register the design pattern and the scan pattern, the scanning image of the electron microscope corresponds to the imaging of the circuit design layout on the substrate; the substrate may be a silicon wafer.
  • Step P2 Calculate the error between the design pattern and the scan pattern to obtain the circuit design layout and its imaging error.
  • Step P1 can use the registration method 10 of the circuit design layout and the scanning electron microscope image described in the first embodiment to register the design pattern and the scanning pattern, and the scanning electron microscope image corresponds to the imaging of the circuit design layout on the substrate.
  • the present invention provides an electronic device 40, which includes a memory 42 and a processor 41, and a computer program is stored in the memory 42.
  • the computer program is configured to execute the circuit design layout and its imaging described in the third embodiment when running. Error calculation method 30;
  • the processor is configured to execute the circuit design layout and the imaging error calculation method 30 described in the third embodiment through the computer program.
  • the method for registering the circuit design layout and the electron microscope scan image obtained by the present invention obtains the design layout binary image and the electron microscope scan binary image by processing the circuit design layout to be registered and the electron microscope scan image Image, and then Gaussian filtering the binary image of the design layout and the binary image of the scanning electron microscope to make the gray value of the central axis of the area corresponding to the design pattern and the scan pattern the largest, and register according to the central axis of the design pattern and scan pattern .
  • the registration method has the advantages of fast and accurate registration.
  • the design pattern covers its corresponding scanning pattern, which ensures the accuracy of registration.
  • the edge detection algorithm is combined with the expansion processing and the corrosion processing, or the adaptive threshold binarization is used to make the extracted contour more accurate, thereby ensuring the accuracy of the registration.
  • the registration system of the circuit design layout and the scanning image of the electron microscope also has the above advantages. Furthermore, the circuit design layout and its imaging error calculation method and electronic equipment have the advantages of accurate registration and accurate error calculation.
  • the process described above with reference to the flowchart can be implemented as a computer software program.
  • the disclosed embodiments of the present invention include a computer program product, which includes a computer program carried on a computer storage medium, and the computer program contains program code for executing the method shown in the flowchart.
  • the computer program may be downloaded and installed from the network through the communication part, and/or installed from a removable medium.
  • the computer program executes the aforementioned functions defined in the method of the present application.
  • the computer memory described in this application may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two.
  • the computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable Programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in a baseband or as a part of a carrier wave, and a computer-readable program code is carried therein.
  • This propagated data signal can take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • the computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium.
  • the computer-readable medium may send, propagate or transmit the program for use by or in combination with the instruction execution system, apparatus, or device .
  • the program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.
  • the computer program code used to perform the operations of this application can be written in one or more programming languages or a combination thereof.
  • the programming language includes object-oriented programming languages-such as Java, Smalltalk, C++, and also conventional Procedural programming language-such as "C" language or similar programming language.
  • the program code can be executed entirely on the user's computer, partly on the user's computer, executed as an independent software package, partly on the user's computer and partly executed on a remote computer, or entirely executed on the remote computer or server.
  • the remote computer can be connected to the user’s computer through any kind of network including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, using an Internet service provider to pass Internet connection).
  • LAN local area network
  • WAN wide area network
  • Internet service provider for example, using an Internet service provider to pass Internet connection.
  • each block in the flowchart or block diagram can represent a module, program segment, or part of code
  • the module, program segment, or part of code contains one or more for realizing the specified logic function Executable instructions.
  • the functions marked in the block may also occur in a different order from the order marked in the drawings. For example, two blocks shown in succession can actually be executed substantially in parallel, or they can sometimes be executed in the reverse order, depending on the functions involved.
  • each block in the block diagram and/or flowchart, and the combination of the blocks in the block diagram and/or flowchart can be implemented by a dedicated hardware-based system that performs the specified functions or operations Or it can be realized by a combination of dedicated hardware and computer instructions.

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Abstract

本发明提供电路设计版图和电镜扫描图像的配准方法，包括步骤S1：提供待配准的电路设计版图及电镜扫描图像；步骤S2：对待配准的电路设计版图进行处理获得设计版图二值图像；对待配准的电镜扫描图像处理获得电镜扫描二值图像；步骤S3：对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大；及步骤S4：根据设计图案及扫描图案的中心轴线进行配准。本发明还提供电路设计版图和电镜扫描图像的配准系统、电路设计版图和其成像误差计算方法及电子设备，电路设计版图和电镜扫描图像的配准方法及系统、电路设计版图和其成像误差计算方法及电子设备具有配准精确，误差计算精准等优点。

Description

电路设计版图和电镜扫描图像的配准方法及系统、电路设计版图和其成像误差计算方法及电子设备 【技术领域】
本发明涉及集成电路制造领域，特别涉及电路设计版图和电镜扫描图像的配准方法及系统、电路设计版图和其成像误差计算方法及电子设备。
【背景技术】
随着掩膜上图形特征尺寸的持续变小，光的衍射现象逐渐显著，这样造成的在硅片上的成像产生变形和无法分辨的现象，这种现象被称作光学临近效应(Optical Proximity Effect)。为提高成像质量，人们可以对掩膜上的图形进行优化来校正光学邻近效应，即OPC(Optical Proximity Correction)。因此，OPC在半导体设备制造的光刻工艺中扮演着很重要的角色。
然而，由于光刻的电路设计版图越来越复杂，对于关键尺寸的测量要求也变得更加复杂和多样化，以便表征关键的OPC模型。SEM(scanning electron microscope，扫描电子显微镜)是测量半导体工艺中形成的精细图案尺寸的基本工具，尤其是CD-SEM(关键尺寸扫描电子显微镜)可以测量高精度的半导体设备。为了更精准的测量实际生产的半导体设备的关键尺寸与电路设计版图的差异，首先需要将SEM扫描半导体设备获得的电镜扫描图像与电路设计版图进行对准。然而，在配准过程中存在配准困难的问题，在现有的配准方法中，目前尚没有基于电路设计版图和电镜扫描图像的快速高效的配准方法。
【发明内容】
为克服目前电路设计版图和电镜扫描图像配准困难的问题，本发明提出了电路设计版图和电镜扫描图像的配准方法及系统、电路设计版图和其成像误差计算方法及电子设备。
本发明提供了一种解决上述技术问题的技术方案：一种电路设计版图和电镜扫描图像的配准方法，电路设计版图和电镜扫描图像的配准方法包括：步骤S1：提供 待配准的电路设计版图及电镜扫描图像，待配准的电路设计版图包括至少一设计图案，待配准的电镜扫描图像包括与所述至少一设计图案对应的至少一扫描图案；所述设计图案覆盖其对应的扫描图案；步骤S2：对待配准的电路设计版图进行处理获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0；对待配准的电镜扫描图像处理获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0；步骤S3：对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大；及步骤S4：根据设计图案及扫描图案的中心轴线进行配准。
优选地，步骤S1包括：步骤S11：获取待配准的电镜扫描图像中的扫描图案之坐标；步骤S12：根据所述坐标确定待配准的电路设计版图中对应的区域；及步骤S13：对所述区域扩展距离D以获得扫描图案对应的设计图案，D小于等于50nm。
优选地，步骤S2之前或步骤S2中包括步骤Sa0：对待配准的电路设计版图中的设计图案进行平滑处理；步骤S2中包括步骤Sa1：对设计图案进行内部填充，获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0。
优选地，步骤S2包括：步骤Sb1：对待配准的电镜扫描图像进行轮廓提取；及步骤Sb2：对扫描图案进行内部填充，获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0。
优选地，步骤Sb1包括步骤Sb1-1及Sb1-2，或包括步骤Sb1-1’及Sb1-2’，步骤Sb1-1及Sb1-2为：步骤Sb1-1：通过图像处理中的边缘检测算法获取扫描图案的边缘；及步骤Sb1-2：进行膨胀处理及腐蚀处理获得扫描图案的轮廓；步骤Sb1-1’及Sb1-2’为：步骤Sb1-1’：对待配准的电镜扫描图像进行腐蚀处理；及步骤Sb1-2’：通过图像处理中的边缘检测算法获取扫描图案的轮廓。
优选地，步骤Sb1包括：步骤Sb1-a：设定灰度阈值；及步骤Sb1-b：将待配准的电镜扫描图像中的像素点的像素值与灰度阈值比较以获得扫描图案的轮廓。
优选地，设计版图二值图像进行高斯滤波后获得第一图像；电镜扫描二值图像进行高斯滤波获得第二图像； 在步骤S4中采用图像模板匹配方法对设计图案及扫描图案进行配准，图像模板匹配方法包括归一化的相关性系
Figure PCTCN2019073986-appb-000001
是电镜扫描图像中(x′，y′)的图像灰度值，电镜扫描图像在电路设计版图上的像素位置为(x+x′，y+y′)，像素值为I(x+x′，y+y′)。
本发明还提供一种电路设计版图和电镜扫描图像的配准系统，包括：输入模块，用于输入提供待配准的电路设计版图及电镜扫描图像，待配准的电路设计版图包括至少一设计图案，待配准的电镜扫描图像包括与所述至少一设计图案对应的至少一扫描图案；所述设计图案覆盖其对应的扫描图案；二值图像处理模块，用于对待配准的电路设计版图进行处理获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0；及用于对待配准的电镜扫描图像处理获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0；高斯滤波模块；用于对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大；及配准模块；用于根据设计图案及扫描图案的中心轴线进行配准。
本发明还提供一种电路设计版图和其成像误差计算方法，电路设计版图和其成像误差计算方法包括：步骤P1：采用如权上所述的电路设计版图和电镜扫描图像的配准方法对设计图案和扫描图案进行配准，电镜扫描图像对应于电路设计版图在基片上的成像；及步骤P2：计算设计图案与扫描图案之间的误差以获得电路设计版图和其成像误差。
本发明还提供一种电子设备，包括存储器和处理器，所述存储器中存储有计算机程序，所述计算机程序被设置为运行时执行如上所述的电路设计版图和其成像误差计算方法；所述处理器被设置为通过所述计算机程序执行如上所述的电路设计版图和其成像误差计算方法。
与现有技术相比，本发明所提供的电路设计版图和电镜扫描图像的配准方法通过对将待配准的电路设计版 图及电镜扫描图像进行处理获得设计版图二值图像和电镜扫描二值图像，再对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大，根据设计图案及扫描图案的中心轴线进行配准。该配准方法具有配准快速精准的优点。
在配准步骤S1中，设计图案覆盖其对应的扫描图案，保障了配准的精确性。
对待配准的电路设计版图中的设计图案进行平滑处理可以使得不可避免的误差存在被预先剔除，在电路设计版图和其成像误差计算中所获得的误差计算结果能更接近用户所想要了解的误差程度。
在待配准的电镜扫描图像的轮廓提取中，通过边缘检测算法结合膨胀处理及腐蚀处理，或通过自适应阈值二值化以使得提取的轮廓更加准确，进而保障了配准的精确性。
电路设计版图和电镜扫描图像的配准系统同样具有以上优点。进一步，电路设计版图和其成像误差计算方法及电子设备具有配准精确，误差计算精准等优点。
【附图说明】
图1为本发明第一实施例电路设计版图和电镜扫描图像的配准方法流程示意图。
图2为图1中步骤S1的流程示意图。
图3A和图3B为图1中步骤S2的流程示意图。
图4A、4B及4C为图3B中步骤Sb1的变形施方式的流程示意图；
图5A至图5J为第一实施例电路设计版图和电镜扫描图像的配准方法之具体示例。
图6为本发明第二实施例电路设计版图和电镜扫描图像的配准系统的模块示意图。
图7为本发明第二实施例二值图像处理模块的详细的模块示意图。
图8为本发明第三实施例电路设计版图和其成像误差计算方法的流程示意图。
图9为本发明第四实施例电子设备的模块示意图。
附图标记说明：
10、电路设计版图和电镜扫描图像的配准方法；20、电路设计版图和电镜扫描图像的配准系统；21、输入模块；22、二值图像处理模块；23、高斯滤波模块；24、配准模块；221、平滑处理模块；223、去噪处理模块；222、第一填充及二值化模块；224，轮廓提取模块；225、第二填充及二值化模块；30、电路设计版图和其成像误差计算方法；40、电子设备；41、处理器；42、存储器。
【具体实施方式】
为了使本发明的目的，技术方案及优点更加清楚明白，以下结合附图及实施实例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
第一实施例
请参阅图1，本发明第一实施例提供一种电路设计版图和电镜扫描图像的配准方法10，通过该方法可以对电路设计版图和其成像对应的电镜扫描图像进行配准。
电路设计版图和电镜扫描图像的配准方法10包括：
步骤S1：提供待配准的电路设计版图及电镜扫描图像，待配准的电路设计版图包括至少一设计图案，待配准的电镜扫描图像包括与所述至少一设计图案对应的至少一扫描图案；所述设计图案覆盖其对应的扫描图案；
步骤S2：对待配准的电路设计版图进行处理获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0；对待配准的电镜扫描图像处理获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0；
步骤S3：对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大；及
步骤S4：根据设计图案及扫描图案的中心轴线进行配准。
请参阅图2，步骤S1包括：
步骤S11：获取待配准的电镜扫描图像中的扫描图案之坐标；
步骤S12：根据所述坐标确定待配准的电路设计版图中对应的区域；及
步骤S13：对所述区域扩展距离D以获得扫描图案对 应的设计图案。
由于电镜扫描图像与电路设计版图中的图案坐标差异不会太大，因此，在步骤S12中，根据电镜扫描图像中的扫描图案之坐标可以获得设计图案的大体位置。可以理解待配准的电路设计版图及电镜扫描图像可以是对应某一集成电路的完整图像，也可以是完整图像中的局部。
在步骤S13中，D小于等于60nm，进一步优选D小于等于50nm。经过扩展距离D的设计图案通常可以覆盖其对应的扫描图案以方便获得精确配准结果。
请参阅图3A，在步骤S2中，获取设计版图二值图像包括：
步骤Sa0：对待配准的电路设计版图中的设计图案进行平滑处理；及
步骤Sa1：对设计图案进行内部填充，获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0。
可以理解，平滑处理的目的在平滑处理设计图案边与边之间的转角部分，如设计图案中的直角经过平滑处理后变成倒圆角。
在步骤Sa1中，对设计图案内部进行白色填充，再将电镜扫描图像二值化处理以获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0。可以理解，在该步骤中，也可以是先对平滑处理后的电镜扫描图像进行二值化处理，然后对设计图案内部的像素进行填充以获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0。于二值化处理前进行填充或二值化处理后进行填充均属于该步骤Sa1范围中。
请参阅图3B，在步骤S2中，获取电镜扫描二值图像包括：
步骤Sb0：对待配准的电镜扫描图像进行去噪处理；
步骤Sb1：对待配准的电镜扫描图像进行轮廓提取；及
步骤Sb2：对扫描图案进行内部填充，获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0。
作为一种选择，步骤Sb0可以省略。去噪处理的方法包括但不限于中值滤波，均值滤波或高斯滤波等。
请参阅图4A，作为一种实施方式，步骤Sb1包括：
步骤Sb1-1：通过图像处理中的边缘检测算法获取扫描图案的边缘；及
步骤Sb1-2：进行膨胀处理及腐蚀处理获得扫描图案的轮廓。
在步骤Sb1-1中，所述边缘检测算法包括但不限于通过梯度算法获取扫描图案的边缘。但由于电镜扫描图像中的扫描图案轮廓通常具有一定宽度，因此，通过边缘检测算法通常会检测到两条边缘。在步骤Sb1-2，可以通过膨胀处理将两条边缘之间的像素填充满，此时，获得具有一定宽度的轮廓，对具有一定宽度的轮廓进行腐蚀处理可获得宽度变窄的扫描图案的轮廓。经过该种方式的处理所获得的扫描图案的轮廓较为精准。
请参阅图4B，作为另一种实施方式，步骤Sb1包括：
步骤Sb1-1’：对待配准的电镜扫描图像进行腐蚀处理；及
步骤Sb1-2’：通过图像处理中的边缘检测算法获取扫描图案的轮廓。
由于电镜扫描图像中的扫描图案轮廓通常具有一定宽度，其会导致扫描图像的轮廓获取不够精准，在步骤Sb1-1’中，对待配准的电镜扫描图像进行腐蚀处理以细化扫描图案轮廓宽度，避免在边缘检测中出现两条边缘的情形。
请参阅图4C，作为一种具体实施方式，步骤Sb1中采用自适应阈值二值化提取轮廓，其包括：
步骤Sb1-a：设定灰度阈值；及
步骤Sb1-b：将待配准的电镜扫描图像的像素点的像素值与灰度阈值比较以获得扫描图案的轮廓。
在步骤Sb1中，待配准的电镜扫描图像在进行轮廓提取先可以先进行图像分割以将图像分位多个区块，优选地，所述区块个数为2-8个，优选4个。
在步骤S3中，设计版图二值图像进行高斯滤波后获得第一图像；电镜扫描二值图像进行高斯滤波获得第二图像；第一图像中设计图案所在区域之中心轴线处灰度值最大，即其中心轴线处最亮，第二图像中扫描图案所在区域之中心轴线处灰度值最大，即其中心轴线处最亮。
在步骤S4中，作为一种实施方式，采用图像模板匹配方法对设计图案及扫描图案进行配准。优选地，图像 模板匹配方法包括归一化的相关性系数匹配方法，计算
Figure PCTCN2019073986-appb-000002
图大小为w*h(h≤H，w≤W)。x′及y′确定T图中的像素位置(1≤x′≤w，1≤y′≤h)，T(x′，y′)就是T图中(x′，y′)的图像灰度值。1≤x＜＝W-w+1，1≤y＜＝H-h+1，在I图中以坐标(x，y)为左下角取一块大小为w*h的子图，那么这个子图上每个像素位置就可以表示为(x+x′，y+y′)，像素值为I(x+x′，y+y′)。通过所述归一化的相关性系数匹配方法计算量小，匹配精准。
请参阅图5A至图5J，作为一种具体示例，图5A为示例中提供的电镜扫描图像，图5B为示例中提供的待配准的设计版图，图5B中的待配准的设计版图经过平滑处理后直角变成倒圆角，获得图5C。对图5C中的计图案进行内部填充，获得设计版图二值图像5D，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0。对图5A中的电镜扫描图像进行高斯滤波，具体地，采用的是17*17的高斯核，sigma＝2进行高斯滤波；对去噪处理后的图像进行轮廓提取获得图5E，对图5E中的扫描图案进行内部填充，获得电镜扫描二值图像5F。对图5D及图5F进行高斯滤波获得图5G和5H，本示例中，采用81*81的高斯核，sigma＝40的高斯滤波器进行高斯滤波。图5G和5H中设计图案及扫描图案对应的区域之中心轴线处灰度值最大。如图5I及5J所示，对设计图案及扫描图案进行配准。
第二实施例
请参阅图6，本发明第二实施例提供一种电路设计版图和电镜扫描图像的配准系统20，电路设计版图和电镜扫描图像的配准系统20包括输入模块21、二值图像处理模块22、高斯滤波模块23及配准模块24。
输入模块21用于输入提供待配准的电路设计版图及电镜扫描图像，待配准的电路设计版图包括至少一设计图案，待配准的电镜扫描图像包括与所述至少一设计图案对应的至少一扫描图案；所述设计图案覆盖其对应的扫描图案。
二值图像处理模块22用于对待配准的电路设计版图 进行处理获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0；及用于对待配准的电镜扫描图像处理获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0。
高斯滤波模块23用于对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大。
配准模块24用于根据设计图案及扫描图案的中心轴线进行配准。
作为一种实施例，二值图像处理模块22包括平滑处理模块221及第一填充及二值化模块222，去噪处理模块223、轮廓提取模块及第二填充及二值化模块225。
平滑处理模块221用于对待配准的电路设计版图中的设计图案进行平滑处理。第一填充及二值化模块222用于对设计图案进行内部填充，获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0。去噪处理模块223对待配准的电镜扫描图像进行去噪处理。轮廓提取模块224用于对待配准的电镜扫描图像进行轮廓提取。第二填充及二值化模块225用于对扫描图案进行内部填充，获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0
可以理解本实施例所保护的电路设计版图和电镜扫描图像的配准系统20可用于执行第一实施例所提供的电路设计版图和电镜扫描图像的配准方法10。电路设计版图和电镜扫描图像的配准方法10中所提及的功能可以通过电路设计版图和电镜扫描图像的配准系统20中相应的模块执行。
第三实施例
本发明第三实施例提供一种电路设计版图和其成像误差计算方法30，其用于计算电路设计版图和其成像之间的误差。电路设计版图和其成像误差计算方法30包括：
步骤P1：对设计图案和扫描图案进行配准，电镜扫描图像对应于电路设计版图在基片上的成像；基片可以是硅片。
步骤P2：计算设计图案与扫描图案之间的误差以获 得电路设计版图和其成像误差。
步骤P1可以采用第一实施例所述的电路设计版图和电镜扫描图像的配准方法10对设计图案和扫描图案进行配准，电镜扫描图像对应于电路设计版图在基片上的成像。
第四实施例
本发明提供一种电子设备40，包括存储器42和处理器41，所述存储器42中存储有计算机程序，所述计算机程序被设置为运行时执行第三实施例所述的电路设计版图和其成像误差计算方法30；
所述处理器被设置为通过所述计算机程序执行第三实施例所述的电路设计版图和其成像误差计算方法30。
与现有技术相比，本发明所提供的电路设计版图和电镜扫描图像的配准方法通过对将待配准的电路设计版图及电镜扫描图像进行处理获得设计版图二值图像和电镜扫描二值图像，再对对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大，根据设计图案及扫描图案的中心轴线进行配准。该配准方法具有配准快速精准的优点。
在配准步骤S1中，设计图案覆盖其对应的扫描图案，保障了配准的精确性。
对待配准的电路设计版图中的设计图案进行平滑处理可以使得不可避免的误差存在被预先剔除，在电路设计版图和其成像误差计算中所获得的误差计算结果能更接近用户所想要了解的误差程度。
在待配准的电镜扫描图像的轮廓提取中，通过边缘检测算法结合膨胀处理及腐蚀处理，或通过自适应阈值二值化以使得提取的轮廓更加准确，进而保障了配准的精确性。
电路设计版图和电镜扫描图像的配准系统同样具有以上优点。进一步，电路设计版图和其成像误差计算方法及电子设备具有配准精确，误差计算精准等优点。
根据本发明公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本发明公开的实施例包括一种计算机程序产品，其包括承载在计算 机存储介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分从网络上被下载和安装，和/或从可拆卸介质被安装。在该计算机程序被处理器执行时，执行本申请的方法中限定的上述功能。需要说明的是，本申请所述的计算机存储器可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本申请中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本申请中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请的操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言-诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言-诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意 种类的网络——包括局域网(LAN)或广域网(WAN)-连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
附图中的流程图和模块图，图示了按照本申请各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，该模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的原则之内所作的任何修改，等同替换和改进等均应包含本发明的保护范围之内。

Claims (10)

  1. 一种电路设计版图和电镜扫描图像的配准方法，其特征在于：电路设计版图和电镜扫描图像的配准方法包括：
    步骤S1：提供待配准的电路设计版图及电镜扫描图像，待配准的电路设计版图包括至少一设计图案，待配准的电镜扫描图像包括与所述至少一设计图案对应的至少一扫描图案；所述设计图案覆盖其对应的扫描图案；
    步骤S2：对待配准的电路设计版图进行处理获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0；对待配准的电镜扫描图像处理获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0；
    步骤S3：对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大；及
    步骤S4：根据设计图案及扫描图案的中心轴线进行配准。
  2. 如权利要求1所述的电路设计版图和电镜扫描图像的配准方法，其特征在于：步骤S1包括：
    步骤S11：获取待配准的电镜扫描图像中的扫描图案之坐标；
    步骤S12：根据所述坐标确定待配准的电路设计版图中对应的区域；及
    步骤S13：对所述区域扩展距离D以获得扫描图案对应的设计图案，D小于等于50nm。
  3. 如权利要求1所述的电路设计版图和电镜扫描图像的配准方法，其特征在于：步骤S2之前或步骤S2中包括步骤Sa0：对待配准的电路设计版图中的设计图案进行平滑处理；
    步骤S2中包括步骤Sa1：对设计图案进行内部填充，获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0。
  4. 如权利要求1所述的电路设计版图和电镜扫描图像的配准方法，其特征在于：步骤S2包括：
    步骤Sb1：对待配准的电镜扫描图像进行轮廓提取；及
    步骤Sb2：对扫描图案进行内部填充，获得电镜扫描 二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0。
  5. 如权利要求4所述的电路设计版图和电镜扫描图像的配准方法，其特征在于：步骤Sb1包括步骤Sb1-1及Sb1-2，或包括步骤Sb1-1’及Sb1-2’，
    步骤Sb1-1及Sb1-2为：
    步骤Sb1-1：通过图像处理中的边缘检测算法获取扫描图案的边缘；及
    步骤Sb1-2：进行膨胀处理及腐蚀处理获得扫描图案的轮廓；
    步骤Sb1-1’及Sb1-2’为：
    步骤Sb1-1’：对待配准的电镜扫描图像进行腐蚀处理；及
    步骤Sb1-2’：通过图像处理中的边缘检测算法获取扫描图案的轮廓。
  6. 如权利要求4所述的电路设计版图和电镜扫描图像的配准方法，其特征在于：步骤Sb1包括：
    步骤Sb1-a：设定灰度阈值；及
    步骤Sb1-b：将待配准的电镜扫描图像中的像素点的像素值与灰度阈值比较以获得扫描图案的轮廓。
  7. 如权利要求1所述的电路设计版图和电镜扫描图像的配准方法，其特征在于：设计版图二值图像进行高斯滤波后获得第一图像；电镜扫描二值图像进行高斯滤波获得第二图像；
    在步骤S4中采用图像模板匹配方法对设计图案及扫描图案进行配准，图像模板匹配方法包括归一化的相关
    Figure PCTCN2019073986-appb-100001
    计版图，x′及y′确定电镜扫描图像中的像素位置，T(x′，y′)是电镜扫描图像中(x′，y′)的图像灰度值，电镜扫描图像在电路设计版图上的像素位置为(x+x′，y+y′)，像素值为I(x+x′，y+y′)。
  8. 一种电路设计版图和电镜扫描图像的配准系统，其特征在于：包括：
    输入模块，用于输入提供待配准的电路设计版图及电镜扫描图像，待配准的电路设计版图包括至少一设计 图案，待配准的电镜扫描图像包括与所述至少一设计图案对应的至少一扫描图案；所述设计图案覆盖其对应的扫描图案；
    二值图像处理模块，用于对待配准的电路设计版图进行处理获得设计版图二值图像，该设计版图二值图像中设计图案区域内的灰度值为1，外部灰度值为0；及用于对待配准的电镜扫描图像处理获得电镜扫描二值图像，该电镜扫描二值图像中扫描图案区域内的灰度值为1，外部灰度值为0；
    高斯滤波模块；用于对设计版图二值图像及电镜扫描二值图像进行高斯滤波以使得设计图案及扫描图案对应的区域之中心轴线处灰度值最大；及
    配准模块；用于根据设计图案及扫描图案的中心轴线进行配准。
  9. 一种电路设计版图和其成像误差计算方法，其特征在于：电路设计版图和其成像误差计算方法包括：
    步骤P1：采用如权利要求1-7任一项所述的电路设计版图和电镜扫描图像的配准方法对设计图案和扫描图案进行配准，电镜扫描图像对应于电路设计版图在基片上的成像；及
    步骤P2：计算设计图案与扫描图案之间的误差以获得电路设计版图和其成像误差。
  10. 一种电子设备，包括存储器和处理器，其特征在于：所述存储器中存储有计算机程序，所述计算机程序被设置为运行时执行权利要求9中所述的电路设计版图和其成像误差计算方法；
    所述处理器被设置为通过所述计算机程序执行权利要求9中所述的电路设计版图和其成像误差计算方法。
PCT/CN2019/073986 2019-01-30 2019-01-30 电路设计版图和电镜扫描图像的配准方法及系统、电路设计版图和其成像误差计算方法及电子设备 WO2020154976A1 (zh)

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