WO2020147941A1

WO2020147941A1 - Inductor-capacitor resonant circuit

Info

Publication number: WO2020147941A1
Application number: PCT/EP2019/050976
Authority: WO
Inventors: Marijan HERCEG; Tomislav MATIC
Original assignee: Nokia Technologies Oy
Current assignee: Nokia Technologies Oy
Priority date: 2019-01-15
Filing date: 2019-01-15
Publication date: 2020-07-23
Anticipated expiration: 2021-07-15

Abstract

An apparatus, method and computer program is described comprising means for detecting a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit (14) and means (25) for switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit (14) based on a phase signal and a data signal, wherein data is transmitted to a primary resonant circuit (12) as a result of the switching of the terminals of the capacitor.

Description

Inductor-Capacitor Resonant Circuit

Field

The present specification relates to inductor-capacitor resonant circuits, such as parallel inductor-capacitor resonant circuits for use in wireless power and data transfer systems.

Background

Simultaneous wireless power and data transfer systems are known, for example in systems in which power is transferred to a device and data is transferred from the device. However, there remains a need for alternative and improved systems in this field.

Summary

In a first aspect, this specification describes an apparatus (such as a secondaiy resonant circuit of a system comprising a primaiy resonant circuit and the secondaiy resonant circuit), the apparatus comprising: a parallel inductor-capacitor resonant circuit;

means for detecting a phase of a current and/or a voltage in the parallel inductor- capacitor resonant circuit; and means for switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal (e.g. as output by the phase detecting means) and a data signal.

Some embodiments provide means for generating a modulator signal based on the phase signal and the data signal. The said means for switching terminals of the capacitor may comprise a first switch and a second switch, wherein the first switch and the second switch are controlled by the modulator signal.

The phase signal may indicate a periodic cycle for switching terminals of the capacitor. Further, some embodiments further comprise means for defining the periodic cycle dependent on a data rate of the data to be transmitted.

The means for switching the terminals of the capacitor may switch said terminals from a default position to a reversed position for a first time period, and may then switch the terminals back to the default position after the first time period. In some embodiments, the parallel inductor-capacitor resonant circuit is comprised within a wearable implant device. Indeed, the apparatus (e.g. the secondary resonant circuit) may be comprised within such a wearable implant device. The said means may comprise: at least one processor; and at least one memory including computer program code, the at least one memory and the computer program configured, with the at least one processor, to cause the performance of the apparatus.

In a second aspect, this specification describes a system comprising: a primary resonant circuit comprising a serial inductor-capacitor resonant circuit; a secondaiy resonant circuit comprising: a parallel inductor-capacitor resonant circuit; means for detecting a phase of a current and/or a voltage in the parallel inductor-capacitor resonant circuit; and means for switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal (e.g. as output by the phase detecting means) and a data signal, wherein data is transmitted to the primary resonant circuit as a result of the switching of the terminals of the capacitor. The primaiy resonant circuit may further comprise an envelope detector for decoding a signal received from the secondary resonant circuit to determine an estimate of the data transmitted.

The secondary resonant circuit may further comprise means for generating a modulator signal based on the phase signal and the data signal. The said means for switching terminals of the capacitor may comprise a first switch and a second switch, wherein the first switch and the second switch are controlled by the modulator signal.

The phase signal may indicate a periodic cycle for switching terminals of the capacitor. Further, some embodiments further comprise means for defining the periodic cycle dependent on a data rate of the data to be transmitted. The means for switching the terminals of the capacitor may switch said terminals from a default position to a reversed position for a first time period, and then switches the terminals back to the default position after the first time period.

In some embodiments, the parallel inductor-capacitor resonant circuit is comprised within a wearable implant device. Indeed, the secondary resonant circuit may be comprised within a wearable implant device. The said means may comprise: at least one processor; and at least one memoiy including computer program code, the at least one memory and the computer program configured, with the at least one processor, to cause the performance of the apparatus.

In a third aspect, the specification describes a method comprising: detecting a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit of a secondary resonant circuit; and switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal (e.g. as detected in the phase detecting step) and a data signal, wherein data is transmitted to a primary resonant circuit as a result of the switching of the terminals of the capacitor.

The method may further comprise generating a modulator signal based on the phase signal and the data signal. Further, switching terminals of the capacitor may comprise switching a first switch and a second switch under the control of the modulator signal.

The phase signal may indicate a periodic cycle for switching terminals of the capacitor and the method may further comprise defining the periodic cycle dependent on a data rate of the data to be transmitted.

Switching the terminals of the capacitor may comprise switching said terminals from a default position to a reversed position for a first time period, and then switching the terminals back to the default position after the first time period. The method may further comprise decoding a signal received at the primary resonant circuit from the secondaiy resonant circuit to determine an estimate of the data transmitted from the secondary resonant circuit to the primary resonant circuit.

In a fourth aspect, this specification describes any apparatus configured to perform any method as described with reference to the third aspect.

In a fifth aspect, this specification describes computer-readable instructions which, when executed by computing apparatus, cause the computing apparatus to perform any method as described with reference to the third aspect. In a sixth aspect, this specification describes a computer program comprising instructions for causing an apparatus to perform at least the following: detecting a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit (e.g. of a secondary resonant circuit); and switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal (e.g. as detected in the phase detecting step) and a data signal, wherein data is transmitted to a primary resonant circuit as a result of the switching of the terminals of the capacitor.

In a seventh aspect, this specification describes a computer-readable medium (such as a non-transitoiy computer readable medium) comprising program instructions stored thereon for performing at least the following: detecting a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit (e.g. of a secondary resonant circuit); and switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal (e.g. as detected in the phase detecting step) and a data signal, wherein data is transmitted to a primary resonant circuit as a result of the switching of the terminals of the capacitor.

In a eighth aspect, this specification describes an apparatus comprising: at least one processor; and at least one memory including computer program code which, when executed by the at least one processor, causes the apparatus to: detect a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit (e.g. of a secondary resonant circuit); and switch terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal (e.g. as detected in the phase detecting step) and a data signal, wherein data is transmitted to a primary resonant circuit as a result of the switching of the terminals of the capacitor.

In an ninth aspect, this specification describes an apparatus (such as a control module or a server) comprising: a first control module (such as a phase detector) for detecting a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit (e.g. of a secondaiy resonant circuit); and a switching arrangement for switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal (e.g. as detected by the first control module) and a data signal. The apparatus may be configured to transmit data to a primary resonant circuit as a result of the switching, by the switching arrangement, of the terminals of the capacitor.

Brief description of the drawings Example embodiments will now be described, by way of non-limiting examples, with reference to the following schematic drawings, in which:

FIG. l is a block diagram of a system in accordance with an example embodiment; FIG. 2 is a block diagram of a system in accordance with an example embodiment;

FIG. 3 is a block diagram of an implementation of a secondaiy resonant circuit in accordance with an example embodiment;

FIG. 4 is a flow chart showing an algorithm in accordance with an example

embodiment;

FIG. 5 is a block diagram of an implementation of a primary resonant circuit in accordance with an example embodiment;

FIG. 6 is a flow chart showing an algorithm in accordance with an example

embodiment;

FIGs. 7 and 8 show plots of waveforms in accordance with example embodiments; FIG. 9 is a block diagram of components of a system in accordance with an example embodiment; and

FIGS. IOA and loB show tangible media, respectively a removable memory unit and a compact disc (CD) storing computer-readable code which when run by a computer perform operations according to example embodiments.

Detailed description

FIG. l is a block diagram of a system, indicated generally by the reference numeral to, in accordance with an example embodiment. The system to comprises a primary resonant circuit 12 and a secondary resonant circuit 14. In the use of the system, power may be transferred from the primaiy resonant circuit 12 to the secondaiy resonant circuit 14 and data may be transferred from the secondary resonant circuit to the primary resonant circuit. Thus, the system 10 can be used for simultaneous wireless power and data transfer. By way of example, the secondary resonant circuit may be an implant, such as an implant of a biomedical system. Such an implant may therefore be able to receive power wirelessly and to provide data wirelessly. In an alternative implementation, the secondary resonant circuit may be a radio frequency identification (RFID) device. The system 10 may be implemented using near-field inductive coupling, with the primary resonant circuit including a power source and a serial inductor-capacitor resonant circuit and the secondary resonant circuit including a parallel inductor- capacitor resonant circuit followed by a rectifier.

Data transfer from the secondary resonant circuit 14 to the primary resonant circuit 12 may be achieved using load shift keying modulation (LSK). In LSK, data may be transmitted by short-circuiting the parallel LC circuit at the secondary resonant circuit if a bit“1” is to be sent and not short-circuiting the parallel LC circuit at the secondary resonant circuit if a bit“o” is to be sent. (Of course, this arrangement could be reversed, with short-circuiting being used to transmit a bit“o”.)

The effect of the short-circuiting may be detected at the primaiy resonant circuit by sensing the changes of the primary coil current. During the transmission of bit“1”, a loss of power occurs at the secondaiy resonant circuit, since the input to the rectifier is short-circuited and therefore no power can be acquired. This arrangement can be a limiting factor on data transmission rates, since, as data rates increase, the time during which the LC circuit is likely to be short-circuited may increase.

FIG. 2 is a block diagram of a system, indicated generally by the reference numeral 20, in accordance with an example embodiment. The system includes example

implementations of the primary resonant circuit 12 and the secondary resonant circuit 14 described above.

The primary resonant circuit 12 comprises a voltage source 21, a serial inductor- capacitor (LC) circuit 22 and a first control circuit 23. The secondary resonant circuit 14 comprises a parallel inductor-capacitor (LC) circuit 24, a switching arrangement 25, a second control circuit 26 and a rectifier 27.

As discussed above, power is transferred from the primaiy resonant circuit 12 to the secondary resonant circuit 14. Specifically, the output of voltage source 21 (Vs) is fed to the serial inductor-capacitor circuit 22. The frequency of the voltage source 21 may be equal to the resonant frequency (f_s) of the serial inductor-capacitor circuit 22, which is

1

given by the equation: f_s =

27JV(L₁ C₁) (where Li and Cl are the inductance and capacitance of the serial inductor-capacitor circuit 22 respectively). The inductance (L ) of the serial inductor-capacitor circuit 22 of the primary resonant circuit 12 and the inductance (L₂) of the parallel inductor-capacitor circuit 24 of the secondary resonant circuit 14 are coupled with a coupling coefficient k. The parallel inductor-capacitor circuit 24 may have the same resonant frequency f_s as the serial inductor-capacitor circuit 22 in order to maximize the power transfer between primaiy and secondaiy resonant circuits 12 and 14. The power transferred from the serial inductor-capacitor circuit 22 to the parallel inductor-capacitor circuit 24 is harvested by the rectifier circuit 27, which rectifier circuit may, for example, convert AC power signals induced at the parallel inductor-capacitor circuit 24 into DC power signals.

FIG. 3 is a block diagram of an implementation of the secondaiy resonant circuit 14 in accordance with an example embodiment. The secondary resonant circuit 14 comprises an inductor 31 and a capacitor 32 (that collectively form the parallel inductor-capacitor circuit 24 discussed above), a first switch 33 and a second switch 34 (that collectively form the switching arrangement 25), a phase detector 35 and a modulator 36 (that collectively form the second control circuit 26), and a load resistance 37 (that models the effect of the rectifier 27).

The first switch 33 and the second switch 34 work together to swap the connections of the capacitor 32 of the parallel inductor-capacitor circuit, depending on the output of the modulator 36. The modulator 36 generates the signal(s) controlling the switches 33 and 34 depending on both the data signal to be transmitted and the output of the phase detector 35. Thus, the connections of the capacitor 32 are switched depending on the data to be transmitted by the secondary resonant circuit 14. The phase detector 35 provides an output depending on the phase of the voltage and/ or current signals at the parallel inductor-capacitor circuit of the secondary resonant circuit 14.

As discussed further below, the phase detector 35 may be a simple circuit, which generates one or more outputs depending on local voltage and/or current signals (i.e. signals within the secondary resonant circuit 14). Similarly, the modulator 36 may implement a simple logic. Accordingly, implementing the secondary resonant circuit 14 is relatively straightforward.

FIG. 4 is a flow chart showing an algorithm, indicated generally by the reference numeral 40, in accordance with an example embodiment. The algorithm 40 is implemented at the secondaiy resonant circuit 14. The algorithm 40 starts at operation 42, where the phase of the voltages and/or currents of the parallel inductor-capacitor circuit 24 are determined. The operation 42 is implemented by the phase detector 35. For example, the phase detector 35 may provide a signal to the modulator 35 indicating when the voltage across the capacitor 32 (Vc₂ as shown in FIG. 3) is at a maximum (or indicating when the current flowing through the inductor 31 (the current I_L2 as shown in FIG. 3) is at a zero-crossing). In one example embodiment, the phase detector 35 provides a signal to the modulator 35 after a defined number of instances of a voltage maximum or current zero-crossing (wherein the defined number may be a definable parameter).

Next, at operation 44, a switching signal in modulated, based on the data input received at the modulator 36 and the phase determined in the operation 42. The switching signal instructs the terminals of the capacitor 32 to be switched for half a cycle of the voltages/current induced in the parallel inductor-capacitor circuit of the secondaiy resonant circuit.

Finally, at operation 46, the terminals of the capacitor 32 of the parallel inductor- capacitor circuit 24 are switched depending on the output of the operation 44.

In one implementation, in order to transmit a data“1”, the connections of the capacitor 32 are switched for the last half-cycle of the voltages/current induced in the parallel inductor-capacitor circuit 24 of the secondary resonant circuit 14. This switch results in the phase of the current through the inductor 31 (i.e. the current IL₂) reversing. As a result, the current flowing through the inductor of the serial inductor-capacitor circuit

22 of the primary resonant circuit is increased, which increase can be detected at the primary resonant circuit 12.

Thus, the second control circuit 26 referred to above may be implemented by using zero-crossing detection and simple logic circuitiy.

FIG. 5 is a block diagram of an implementation of the primary resonant circuit 12 in accordance with an example embodiment. As shown in FIG. 5, the voltage source 21 is modelled by a voltage source 51 (having a voltage Vs) and a source resistance 52 (having a resistance Rs), the serial inductor-capacitor resonant circuit 22 is implemented by an inductor 53 (having an inductance L ) and a capacitor 54 (having a capacitance CO, and the first control circuit 23 is implemented by an envelope detector 55 and a decoder 56.

FIG. 6 is a flow chart showing an algorithm, indicated generally by the reference numeral 60, in accordance with an example embodiment.

The algorithm 60 starts at operation 62, where an envelope of the voltage across the inductor 53 (the voltage V_LI shown in FIG. 5) is determined (using the envelope detector 55, which envelope detector receives input from either side of the inductor 53). As discussed above, the voltage across the inductor 53 is affected by the switching of the capacitor 32 in response to the data signal received at the secondary resonant circuit. Thus, the envelope of the voltage V_LI is indicative of the data signal.

At operation 64, the data is decoded to provide the data output of the primary resonant circuit 12. Thus, the decoder 66 generates the data output that seeks to regenerate the data originally transmitted by the second resonant circuit 14.

FIG. 7 shows plots, indicated generally by the reference numeral 70, of waveforms in accordance with an example embodiment. The plot 70 includes a first plot 70a

(showing currents and voltages in the secondaiy resonant circuit 14) and a second plot 70b (showing currents and voltages in the primary resonant circuit 12). The plots 70 were generated in simulations of a 13.56 MHz inductive link.

The first plot 70a includes a first waveform 71a showing the voltage (Vc₂) across the capacitor 32 of the parallel inductor-capacitor circuit 24, a second waveform 72a showing the current (IL₂) in the inductor 31 of the parallel inductor-capacitor circuit 24, and a third waveform 73a showing a switching voltage (V_SWitch) output by the modulator 36 to the switches 33 and 34 of the switching arrangement 25 of the secondary resonant circuit.

Similarly, the second plot 70b includes a first waveform 71b showing the voltage (V_LI) across the inductor 53 of the serial inductor-capacitor circuit 22, a second waveform 72b showing the current (ILO in the inductor 53 of the serial inductor-capacitor circuit 22, and a third waveform 73b showing a switching voltage (V_SWitch) output by the envelope detector 55 of the primary resonant circuit. In one example embodiment, to send a data bit“1”, the capacitance C₂ of the secondary resonant circuit is switched (effectively turned upside down) with respect to L₂ at the point where the voltage across the capacitor (Vc₂) is at maximum (at that point current I_L2 is zero). The capacitor is switched for the last half of cycle of the induced voltages and current (T_SWitch=i/ (2f_s)). As a result, the phase of current I_L2 is switched by 180 degrees, which as a consequence will cause the increase of current I . As shown in the plot 70a, this switching of the phase of the current occurs in synchronism with the switching signal (as indicated, for example, by the reference 73a). As shown in the second plot 70b, the switching of the capacitance C₂ of the secondary resonant circuit causes an increase in the inductor current 72b at the primaiy resonant circuit. As a consequence, the inductor voltage 71b at the primary resonant circuit increases. Therefore, by using an envelope detector for measuring the inductor voltage, the received data can be estimated.

In the example plot 70a, only data“i”s are sent (which could be seen as a worst-case scenario). Data is sent every fourth cycle, such that the data rate is 3.39 Mb/s.

Whilst the capacitor is switched, the energy acquired at the secondaiy resonant circuit 14 may be slightly reduced (due to a conflict of the current I_L2 caused by the switching of the capacitor C₂ and the part of the current contributed by a coupling of L and L₂), but will not be lost entirely.

As noted above, the capacitor switching may take place at a period starting and ending at a zero-crossing of the current (IL₂) flowing through the inductor 31. Accordingly, the phase detector 35 may simply be required to identify selected zero crossings of the inductor current.

FIG. 8 shows plots, indicated generally by the reference numeral 80, of waveforms in accordance with an example embodiment. The plot 80 includes a first plot 80a

(showing currents and voltages in the secondaiy resonant circuit 14) and a second plot 80b (showing currents and voltages in the primary resonant circuit 12). As with the plots 70 described above, the plots 80 were generated in simulations of a 13.56 MHz inductive link. In the plots 80, the waveforms are shown for a data rate equal to 6.73 Mb/ s (such that data changes on eveiy second signal cycle). The phase detector 35 is used for determining when the terminals of the capacitor should be switched, in the event that switching is required (i.e. depending on the data signal). Thus, the phase detector 35 provides a signal indicating a periodic cycle for switching terminals of the capacitor. The periodic signal is dependent on the data rate of the data to be transmitted. Thus, the periodic signal occurs twice as often in the plots

80 than in the plots 70. Other data rates are possible. Moreover, an arrangement for setting data rates could be provided.

As discussed above, the second control circuit 26 of the secondaiy resonant circuit 14 that is used to transfer data to the primaiy resonant circuit 12 may be implemented using a simple phase detector and modulator logic arrangement. Similarly, the first control circuit 23 of the primary resonant circuit 12 may be implemented using a simple envelope detection arrangement. Implementations of, and modifications to, the principles described herein are therefore relatively straightforward.

For completeness, FIG. 9 is a schematic diagram of components of one or more of the example embodiments described previously, which hereafter are referred to generically as processing systems 300. A processing system 300 may have a processor 302, a memory 304 closely coupled to the processor and comprised of a RAM 314 and ROM 312, and, optionally, user input 310 and a display 318. The processing system 300 may comprise one or more network/apparatus interfaces 308 for connection to a network/apparatus, e.g. a modem which may be wired or wireless. Interface 308 may also operate as a connection to other apparatus such as device/ apparatus which is not network side apparatus. Thus direct connection between devices/apparatus without network participation is possible. User input 310 and display 318 may be connected to a remote processor like ground control station. Remote connection may be LTE or 5G type fast connection between remote processor and processor.

The processor 302 is connected to each of the other components in order to control operation thereof.

The memory 304 may comprise a non-volatile memory, such as a hard disk drive (HDD) or a solid state drive (SSD). The ROM 312 of the memory 314 stores, amongst other things, an operating system 315 and may store software applications 316. The RAM 314 of the memory 304 is used by the processor 302 for the temporary storage of data. The operating system 315 may contain code which, when executed by the processor implements aspects of the algorithms 40 and 60 described above. The code may, for example, determine data rates for modulation and detection of signals for data transfer. Moreover, a user interface for adjusting such data transfer rates could readily be implemented (e.g. using the user inputs 310 and the display 318). Note that in the case of small device/ apparatus the memory can be most suitable for small size usage i.e. not always hard disk drive (HDD) or solid state drive (SSD) is used.

The processor 302 may take any suitable form. For instance, it may be a

microcontroller, a plurality of microcontrollers, a processor, or a plurality of

processors.

The processing system 300 may be a standalone computer, a server, a console, or a network thereof. The processing system 300 and needed structural parts may be all inside device/apparatus such as IoT device/apparatus i.e. embedded to very small size.

In some example embodiments, the processing system 300 may also be associated with external software applications. These may be applications stored on a remote server device/apparatus and may run partly or exclusively on the remote server

device/apparatus. These applications maybe termed cloud-hosted applications. The processing system 300 may be in communication with the remote server

device/apparatus in order to utilize the software application stored there.

FIGS. 10A and 10B show tangible media, respectively a removable memoiy unit 365 and a compact disc (CD) 368, storing computer-readable code which when run by a computer may perform methods according to example embodiments described above. The removable memory unit 365 may be a memory stick, e.g. a USB memory stick, having internal memory 366 storing the computer-readable code. The memory 366 may be accessed by a computer system via a connector 367. The CD 368 may be a CD- ROM or a DVD or similar. Other forms of tangible storage media may be used.

Tangible media can be any device/ apparatus capable of storing data/ information which data/information can be exchanged between devices/ apparatus/network.

Embodiments of the present invention may be implemented in software, hardware, application logic or a combination of software, hardware and application logic. The software, application logic and/ or hardware may reside on memoiy, or any computer media. In an example embodiment, the application logic, software or an instruction set is maintained on any one of various conventional computer-readable media. In the context of this document, a“memory” or“computer-readable medium” may be any non-transitory media or means that can contain, store, communicate, propagate or transport the instructions for use by or in connection with an instruction execution system, apparatus, or device, such as a computer.

Reference to, where relevant,“computer-readable storage medium”,“computer program product”,“tangibly embodied computer program” etc., or a“processor” or “processing circuitry” etc. should be understood to encompass not only computers having differing architectures such as single/multi-processor architectures and sequencers/parallel architectures, but also specialised circuits such as field

programmable gate arrays FPGA, application specify circuits ASIC, signal processing devices/apparatus and other devices/apparatus. References to computer program, instructions, code etc. should be understood to express software for a programmable processor firmware such as the programmable content of a hardware device/ apparatus as instructions for a processor or configured or configuration settings for a fixed function device/apparatus, gate array, programmable logic device/apparatus, etc.

As used in this application, the term“circuitry” refers to all of the following: (a) hardware-only circuit implementations (such as implementations in only analogue and/or digital circuitry) and (b) to combinations of circuits and software (and/or firmware), such as (as applicable): (i) to a combination of processor(s) or (ii) to portions of processor(s)/software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a server, to perform various functions) and (c) to circuits, such as a microprocessor(s) or a portion of a microprocessor(s), that require software or firmware for operation, even if the software or firmware is not physically present.

If desired, the different functions discussed herein may be performed in a different order and/ or concurrently with each other. Furthermore, if desired, one or more of the above-described functions may be optional or may be combined. Similarly, it will also be appreciated that the flow diagrams of Figures 4 and 6 are examples only and that various operations depicted therein may be omitted, reordered and/or combined. It will be appreciated that the above described example embodiments are purely illustrative and are not limiting on the scope of the invention. Other variations and modifications will be apparent to persons skilled in the art upon reading the present specification. For example, it would be possible to extend the principles described herein to other applications, such as the control of robots or similar objects. Moreover, the disclosure of the present application should be understood to include any novel features or any novel combination of features either explicitly or implicitly disclosed herein or any generalization thereof and during the prosecution of the present application or of any application derived therefrom, new claims may be formulated to cover any such features and/or combination of such features.

Although various aspects of the invention are set out in the independent claims, other aspects of the invention comprise other combinations of features from the described example embodiments and/or the dependent claims with the features of the

independent claims, and not solely the combinations explicitly set out in the claims.

It is also noted herein that while the above describes various examples, these descriptions should not be viewed in a limiting sense. Rather, there are several variations and modifications which may be made without departing from the scope of the present invention as defined in the appended claims.

Claims

Claims: l. An apparatus comprising:

a parallel inductor-capacitor resonant circuit;

means for detecting a phase of a current and/ or a voltage in the parallel inductor-capacitor resonant circuit; and

means for switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal and a data signal.

2. An apparatus as claimed in claim l, further comprising means for generating a modulator signal based on the phase signal and the data signal.

3. An apparatus as claimed in claim 2, wherein the means for switching terminals of the capacitor comprises a first switch and a second switch, wherein the first switch and the second switch are controlled by the modulator signal.

4. An apparatus as claimed in any one of the preceding claims, wherein the phase signal indicates a periodic cycle for switching terminals of the capacitor.

5. An apparatus as claimed in claim 4, further comprising means for defining the periodic cycle dependent on a data rate of the data to be transmitted.

6. An apparatus as claimed in any one of the preceding claims, wherein the means for switching the terminals of the capacitor switches said terminals from a default position to a reversed position for a first time period, and then switches the terminals back to the default position after the first time period.

7. An apparatus as claimed in any one of the preceding claims, wherein the parallel inductor-capacitor resonant circuit is comprised within a wearable implant device.

8. A system comprising:

a primary resonant circuit comprising a serial inductor-capacitor resonant circuit;

a secondary resonant circuit comprising:

a parallel inductor-capacitor resonant circuit; means for detecting a phase of a current and/or a voltage in the parallel inductor-capacitor resonant circuit; and

means for switching terminals of a capacitor of the parallel inductor- capacitor resonant circuit based on a phase signal and a data signal, wherein data is transmitted to the primary resonant circuit as a result of the switching of the terminals of the capacitor.

9. A system as claimed in claim 8, wherein the primary resonant circuit further comprises an envelope detector for decoding a signal received from the secondaiy resonant circuit to determine an estimate of the data transmitted.

10. A system as claimed in claim 8 or claim 9, wherein the secondaiy resonant circuit further comprises means for generating a modulator signal based on the phase signal and the data signal.

11. An system as claimed in any one claims 8 to 10, wherein the means for switching the terminals of the capacitor switches said terminals from a default position to a reversed position for a first time period, and then switches the terminals back to the default position after the first time period.

12. An apparatus or a system as claimed in any one of the preceding claims, wherein the means comprise:

at least one processor; and

at least one memoiy including computer program code, the at least one memory and the computer program configured, with the at least one processor, to cause the performance of the apparatus.

13. A method comprising:

detecting a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit of a secondary resonant circuit; and

switching terminals of a capacitor of the parallel inductor-capacitor resonant circuit based on a phase signal and a data signal, wherein data is transmitted to a primary resonant circuit as a result of the switching of the terminals of the capacitor.

14. A method as claimed in claim 13, further comprising generating a modulator signal based on the phase signal and the data signal.

15. A method as claimed in claim 14, wherein switching terminals of the capacitor comprises switching a first switch and a second switch under the control of the modulator signal.

16. A method as claimed in any one of claims 13 to 15, wherein the phase signal indicates a periodic cycle for switching terminals of the capacitor, the method further comprising defining the periodic cycle dependent on a data rate of the data to be transmitted.

17. A method as claimed in any one of claims 13 to 16, wherein switching the terminals of the capacitor comprises switching said terminals from a default position to a reversed position for a first time period, and then switching the terminals back to the default position after the first time period.

18. A method as claimed in any one of claims 13 to 17, further comprises decoding a signal received at the primary resonant circuit from the secondary resonant circuit to determine an estimate of the data transmitted from the secondary resonant circuit to the primaiy resonant circuit.

19. A computer readable medium comprising program instructions stored thereon for performing at least the following:

detecting a phase of a current and/or a voltage in a parallel inductor-capacitor resonant circuit; and