WO2020147106A1 - 一种新型增强型半导体器件及其制备方法 - Google Patents

一种新型增强型半导体器件及其制备方法 Download PDF

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WO2020147106A1
WO2020147106A1 PCT/CN2019/072317 CN2019072317W WO2020147106A1 WO 2020147106 A1 WO2020147106 A1 WO 2020147106A1 CN 2019072317 W CN2019072317 W CN 2019072317W WO 2020147106 A1 WO2020147106 A1 WO 2020147106A1
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layer
nitride
barrier layer
epitaxial
gate
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刘扬
何亮
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中山大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Definitions

  • the invention relates to the technical field of semiconductor devices, and more specifically, to a novel enhanced semiconductor device and a preparation method thereof.
  • the third-generation semiconductor materials represented by GaN materials have a lot of room for development in high temperature, high frequency, radiation resistance, and high power applications due to the advantages of wide band gap, high thermal conductivity, and high breakdown electric field.
  • GaN-based electronic devices usually use high-concentration and high-mobility two-dimensional electron gas at the AlGaN/GaN heterostructure interface to work, so that the device has the advantages of small on-resistance, large output current, and fast switching speed.
  • this AlGaN/GaN heterostructure high two-dimensional electron gas, 2DEG
  • the device is naturally turned on when the external gate bias is zero, which is a depletion operation.
  • the p-type gate device has begun to be industrialized.
  • the main companies implementing this structure device are Panasonic Corporation of Japan, EPC Corporation of the United States and GaN Systems Corporation of Canada.
  • Panasonic has prepared p-type gate devices with better threshold voltage characteristics (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.64, NO.3, by combining the technical solutions of etching grooves, secondary growth and etching p-type layers).
  • SiO 2 is easily decomposed to produce Si and O elements at high temperatures, and they diffuse into the epitaxial layer to easily form a donor type Doping, which causes leakage and seriously affects the quality of the epitaxial crystal, and the influence of the mask layer on the kinetics of epitaxial growth cannot be ignored.
  • the hole concentration of the p-GaN layer is generally not high, and the current mainstream reported value is basically not higher than 1 ⁇ 10 18 cm -3 .
  • the Al composition of the AlGaN barrier layer under the p-GaN layer is generally required to be less than 20% and The thickness is less than 18nm, which is conducive to the realization of enhanced operation, but at the same time it will increase the resistance of the access area, and the relatively thin AlGaN barrier layer will also make the doping elements (such as magnesium) in the p-type GaN layer more It is easy to diffuse into the channel, which affects the reliability of the device.
  • the present invention provides a new type of enhanced semiconductor device that can achieve higher threshold voltage, lower on-resistance, lower leakage current, and more stable Working status.
  • the technical solution adopted by the present invention is: a new type of enhanced semiconductor device, including a substrate, a semiconductor epitaxial layer grown on the substrate, a gate, a source and a drain.
  • the epitaxial layer includes, from bottom to top, a nitride nucleation layer, a nitride stress buffer layer, a nitride channel layer, a primary epitaxial nitride barrier layer, and a p-type nitride layer and a secondary epitaxial nitride potential Barrier layer;
  • the p-type nitride layer is only retained on the primary epitaxial nitride barrier layer in the gate region to achieve pinch-off of the two-dimensional electron gas channel under the gate; secondary epitaxy without mask, secondary
  • the epitaxial nitride barrier layer is grown on the p-type nitride layer in the primary epitaxial barrier layer and the gate region.
  • the p-type nitride outside the gate region is etched, leaving the p-type nitride in the gate region to achieve pinch off of the gate channel.
  • the secondary growth process has no mask effect, and the secondary epitaxial nitride barrier layer is grown on the p-type nitride layer in the primary epitaxial barrier layer and the gate region to achieve a high conduction access area.
  • the thickness and composition of the primary epitaxial nitride barrier layer and the secondary epitaxial nitride barrier layer better gate turn-off capability and high conduction gate-source access area and gate-drain access area are realized .
  • this method can effectively repair the access area damage caused by etching, and the requirements for the etching process are also reduced.
  • an enhanced semiconductor device with high threshold voltage, high conduction capability and high stability is realized.
  • the substrate is any one of Si substrate, sapphire substrate, silicon carbide substrate, GaN self-supporting substrate or AlN.
  • the nitride stress buffer layer is any one or a combination of AlN, AlGaN, GaN, and SiN; the nitride nucleation layer is an Al nitride layer.
  • the nitride channel layer is a GaN or AlGaN layer.
  • the primary epitaxial nitride barrier layer is one or a combination of any of AlGaN, AlInN, InGaN, AlInGaN, and AlN, the Al composition is 1%-30%, and the thickness is 1nm-30nm ;
  • the secondary epitaxial nitride barrier layer is one or a combination of any of AlGaN, AlInN, InGaN, AlInGaN, and AlN, the Al composition is 1%-40%, and the thickness is 1nm-40nm ;
  • the p-type nitride layer is GaN, AlGaN, AlInN or AlInGaN, and the thickness is not less than 5 nm.
  • a layer of AlN space isolation layer is inserted between the primary epitaxial nitride barrier layer and the nitride channel layer, and the thickness of the AlN space isolation layer is 0.3nm-3nm.
  • an AlN barrier layer is inserted between the p-type nitride layer and the primary epitaxial nitride barrier layer, and the thickness of the AlN barrier layer is 0.3nm-5nm.
  • the aluminum composition of the secondary epitaxial nitride barrier layer is generally higher than that of the primary epitaxial nitride barrier layer.
  • the p-type nitride layer in the gate region is retained, and the primary epitaxial nitride barrier layer in the region outside the p-type nitride layer in the gate region is partially removed, leaving the thickness of the primary epitaxial nitride barrier layer It is 1-30nm.
  • a cap layer and a passivation layer are still grown on the secondary epitaxial nitride barrier layer;
  • the cap layer is GaN with a thickness of 0.5-8 nm;
  • the passivation layer is SiN, The thickness is 1-100nm.
  • the source and drain are ohmic contacts
  • the gate is ohmic contact or Schottky contact.
  • the gate metal can be directly in contact with the secondary epitaxial nitride barrier layer, or after etching away a part of the secondary epitaxial nitride barrier layer above the p-type nitride layer, and then with the p-type nitride layer
  • the layers are in direct contact.
  • the present invention also provides a method for preparing a novel enhanced semiconductor device, which includes the following steps:
  • a gate metal is formed on the p-type nitride layer in the gate region.
  • the patent of the present invention proposes the use of an etching scheme combined with secondary growth technology: first, dry etching is used to remove the p-type nitride layer outside the gate area and part of the primary epitaxial nitride barrier layer, and retain the p-type nitride in the gate area Layer and primary epitaxial nitride barrier layer to achieve pinch off of the gate channel.
  • MOCVD Metal Organic Chemical Vapor deposition
  • the side surface of the p-type nitride layer (non-polar surface or semi-polar surface, almost no 2DEG) and the upper side of the p-type nitride layer in the gate region will also grow a secondary epitaxial barrier layer, due to the loss of holes in the p-type nitride layer To do its best, the shutdown can be fully guaranteed on these two sides.
  • the primary epitaxial barrier layer and the secondary epitaxial barrier layer of the device can be redesigned, including the composition of aluminum in the barrier layer and the thickness design of the barrier layer, so as to achieve a significant improvement in switching characteristics.
  • the beneficial effect is: the invention provides a new type of enhanced semiconductor device and its preparation method, which adopts secondary epitaxy technology, which is also the nitride of the gate area and the access area outside the gate.
  • the barrier layer design provides feasibility. By designing the primary epitaxial nitride barrier layer and the secondary epitaxial nitride barrier layer structure, it is reasonable to realize the turn-off characteristics of the heterojunction channel under the gate and the gate at the same time.
  • the conductivity of the heterojunction channel in the access area outside the area is an advantage that the existing etching scheme or selected area epitaxial p-GaN scheme does not have.
  • the technology of the present invention can finally effectively realize an enhanced device with high threshold voltage, high conduction performance, low leakage and high stability.
  • FIG. 1 is a schematic diagram of the structure of an enhanced device in an existing etching scheme.
  • Fig. 2 is a schematic diagram of the structure of an enhancement mode device in the existing selective area epitaxial p-GaN solution.
  • FIG. 12 is a schematic diagram of the device structure of Embodiment 1 of the present invention.
  • 3-12 are schematic diagrams of the process of the device manufacturing method of Embodiment 1 of the present invention.
  • FIG. 13 is a schematic diagram of the device structure of Embodiment 2 of the present invention.
  • FIG. 14 is a schematic diagram of the device structure of Embodiment 3 of the present invention.
  • Embodiment 15 is a schematic diagram of the device structure of Embodiment 4 of the present invention.
  • FIG. 16 is a schematic diagram of the device structure of Embodiment 5 of the present invention.
  • FIG. 17 is a schematic diagram of the device structure of Embodiment 6 of the present invention.
  • FIG. 18 is a schematic diagram of the device structure of Embodiment 7 of the present invention.
  • FIG. 19 is a schematic diagram of the device structure of Embodiment 8 of the present invention.
  • Embodiment 9 is a schematic diagram of the device structure of Embodiment 9 of the present invention.
  • FIG. 21 is a schematic diagram of the device structure of Embodiment 10 of the present invention.
  • FIG. 22 is a schematic diagram of the device structure of Embodiment 11 of the present invention.
  • FIG. 23 is a schematic diagram of the device structure of Embodiment 12 of the present invention.
  • FIG. 24 is a schematic diagram of the device structure of Embodiment 13 of the present invention.
  • FIG. 12 is a schematic diagram of the device structure of this embodiment.
  • a semiconductor enhancement type transistor includes a substrate 1, a semiconductor epitaxial layer grown on the substrate 1, a gate 10, a source 8 and a drain 9.
  • the epitaxial layer includes a nitride nucleation layer 2, a nitride stress buffer layer 3, a nitride channel layer 4, a primary epitaxial nitride barrier layer 5, a p-type nitride layer 6 and a secondary epitaxial layer from bottom to top Nitride barrier layer 7.
  • the p-type nitride layer 6 remains only on the primary epitaxial nitride barrier layer 5 in the gate 10 region, so that the two-dimensional electron gas channel under the gate 10 is pinched off.
  • the secondary epitaxy has no mask, and the secondary epitaxial nitride barrier layer 7 is grown on the p-type nitride layer 6 in the region of the primary epitaxial barrier layer and the gate electrode 10.
  • the manufacturing method of the above-mentioned semiconductor enhancement transistor is shown in Fig. 3 to Fig. 12, and includes the following steps:
  • Source 8 and drain 9 ohmic contact metals on the source 8 and drain 9 regions, as shown in FIG. 11;
  • FIG. 12 is a schematic diagram of the device structure of Embodiment 1.
  • FIG. 12 is a schematic diagram of the device structure of Embodiment 1.
  • FIG. 13 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 only in that: in Embodiment 2, a nitride channel layer 4 and a primary epitaxial nitride barrier layer 5 are also sandwiched
  • the AlN space isolation layer 11 has a thickness of 0.3-3 nm. Used to improve the channel two-dimensional electron gas characteristics.
  • Fig. 14 is a schematic diagram of the device structure of this embodiment, which is different from the structure of embodiment 1 only in that: embodiment 1 is that the part of the primary epitaxial nitride barrier layer 5 outside the gate 10 area is removed, and In Embodiment 3, the part of the primary epitaxial nitride barrier layer 5 outside the gate electrode 10 area remains intact. Compared with Embodiment 1, Embodiment 3 requires a more severe etching scheme, such as more advanced equipment, or self-terminating etching conditions containing oxygen or fluorine.
  • FIG. 15 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 only in that: Embodiment 1 is that the part of the primary epitaxial nitride barrier layer 5 outside the gate 10 area is removed, and In Embodiment 4, the primary epitaxial nitride barrier layer 5 outside the gate 10 area is completely removed. In Embodiment 4, before the secondary epitaxial nitride barrier layer 7 is grown, the thin AlN space isolation layer 11 can also be grown to a thickness of 0.3-3 nm.
  • Figure 16 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 only in that: Embodiment 1 is that the part of the primary epitaxial nitride barrier layer 5 outside the gate 10 area is removed, and In Embodiment 5, the primary epitaxial nitride barrier layer 5 outside the gate 10 area is completely removed, and part of the nitride channel layer 4 is further removed. In Embodiment 5, before the secondary epitaxial nitride barrier layer 7 is grown, the thin AlN space isolation layer 11 can also be grown to a thickness of 0.3-3 nm.
  • FIG. 17 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 only in that: Embodiment 1 is that the part of the primary epitaxial nitride barrier layer 5 outside the gate 10 region is removed, and In Embodiment 6, the primary epitaxial nitride barrier layer 5 outside the gate 10 area is completely removed, and part of the nitride channel layer 4 is further removed, and a layer of secondary epitaxial nitrogen is sandwiched in the secondary growth. CVD channel layer 12. Wherein, the thickness of the secondary epitaxial nitride channel layer 12 is 1-10 nm. In Embodiment 6, before the secondary epitaxial nitride barrier layer 7 is grown, the thin AlN space isolation layer 11 can also be grown to a thickness of 0.3-3 nm.
  • FIG. 18 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 only in that: in Embodiment 7, the secondary epitaxial nitride barrier layer 7 in the ohmic contact region is etched, and it can be further etched. In the primary epitaxial nitride barrier layer 5 to achieve better ohmic contact characteristics, the final barrier layer thickness remaining is 1-10 nm.
  • Figure 19 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 only in that: in Embodiment 8, there is an in-situ grown cap layer or passivation layer on the secondary epitaxial nitride barrier layer 7 ⁇ 13 ⁇ The layer 13.
  • the cap layer is GaN with a thickness of 0-8nm.
  • the in-situ passivation layer is SiN x , SiO 2 , Al 2 O 3 , AlO x N y , GaO x , GaO x N y , and the thickness is 0-100 nm.
  • FIG. 20 is a schematic diagram of the device structure of this embodiment, which differs from the structure of Embodiment 1 only in that: in Embodiment 9, there is an ex-situ grown passivation layer 14 on the secondary epitaxial nitride barrier layer 7 .
  • the passivation layer 14 is a high-k dielectric such as SiN x , SiO 2 , Al 2 O 3 , or a laminated structure thereof, and the growth process is LPCVD, PECVD, RTCVD, ALD, PEALD, etc.
  • FIG. 21 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 and Embodiment 9 only in that: in Embodiment 10, the device gate 10 includes a field plate structure.
  • FIG. 22 is a schematic diagram of the device structure of this embodiment, which is different from Embodiment 1 and Embodiment 10 only in that: in Embodiment 10, the device source 8 includes a field plate structure.
  • FIG. 23 is a schematic diagram of the device structure of this embodiment, which is different from the structure of Embodiment 1 only in that: in Embodiment 1, the shape of the p-type nitride layer 6 is rectangular; in Embodiment 12, the p-type nitride layer The shape 6 is trapezoidal. In addition, it is obvious that the shape of the p-type nitride can also be an arc shape, a stepped shape, and the like.
  • FIG. 24 is a schematic diagram of the device structure of this embodiment, which is different from Embodiment 1 only in that: in Embodiment 1, the metal of the gate 10 directly contacts the secondary epitaxial nitride barrier layer 7. In Embodiment 13, a part of the secondary epitaxial barrier layer on the p-type nitride barrier layer is etched to open, and the metal of the gate 10 can directly contact the p-type nitride barrier layer.
  • the depth of the etching opening can be variable: first, the depth of the etching opening can be smaller than the thickness of the secondary epitaxial barrier layer, and the etching depth is 1-30nm; second, the depth of the etching opening can be greater than the secondary epitaxial potential
  • the thickness of the barrier layer, that is, the p-type nitride layer 6 can also be etched, and the depth of the p-type nitride layer 6 is preferably in the range of 1-10 nm.
  • the width of the etching opening is variable, that is, the opening width is less than or equal to the width of the p-type nitride layer 6.
  • the core content of the present invention is the second epitaxial barrier layer after the p-type nitride layer is etched.
  • the requirements for the etching process can be reduced, and on the other hand, the primary epitaxial nitride barrier layer and the secondary epitaxial barrier layer can be designed.
  • the thickness and composition of the nitride barrier layer thereby obtaining an enhanced device with high threshold voltage, high conduction capability, and high stability.
  • the present invention only uses several device structures to clarify related technologies, but it is still feasible in other similar device solutions that have undergone deformation or combination, and will not be described here.

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Abstract

本发明涉及一种新型增强型半导体器件及其制备方法。该器件包括衬底、半导体外延层、栅极、源极和漏极。所述外延层包括氮化物成核层、氮化物应力缓冲层、氮化物沟道层、一次外延氮化物势垒层、p型氮化物层和二次外延氮化物势垒层。通过刻蚀，保留栅极区域p型氮化物，实现栅极沟道的夹断。通过无掩膜二次外延，二次外延氮化物势垒层生长于一次外延势垒层和栅极区域p型氮化物层之上，实现高导通接入区。二次外延可有效修复刻蚀损伤，对刻蚀工艺的要求也降低。且通过调控一次外延氮化物势垒层和二次外延氮化物势垒层的厚度和组分，实现更优的栅极关断和接入区导通能力。本发明可实现高阈值电压、高导通、高稳定性、低漏电的增强型半导体器件。

Description

一种新型增强型半导体器件及其制备方法 技术领域
本发明涉及半导体器件技术领域，更为具体的，涉及一种新型增强型半导体器件及其制备方法。
背景技术
以GaN材料为代表的第三代半导体材料由于禁带宽度宽、热导率高、击穿电场高等优点，在高温、高频、抗辐射、大功率应用领域具有很大的发展空间。
GaN基电子器件通常利用AlGaN/GaN异质结构界面处高浓度、高迁移率的二维电子气工作，使器件具有导通电阻小、输出电流大、开关速度快的优点。然而，也正是由于这一AlGaN/GaN异质结构(高的二维电子气，2DEG)，使得器件在外加栅偏压为零的情况下，也天然处于开启状态，即为耗尽型操作。
高性能常增强型器件的实现是GaN基电子器件面临的一个重要挑战，其要求具备更正的阈值电压，以简化器件外围电路、保证系统失效安全，从而确保器件能可靠的工作。实现常关型器件的一般思路是保留接入区高导通的2DEG，即不影响器件的导通电阻，同时耗尽栅极下方沟道2DEG，以实现器件栅极在不施加电压情况下也处于关断状态。目前，业界普遍采用3种方法实现常关型GaN基器件(IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.64,NO.3,MARCH 2017,Page 779-795)：(1)绝缘槽栅结构(MOSFET)，(2)共源共栅级联结构(Cascode)(3)p型栅结构(p-GaN gate，如图1所示)。
上述结构中，由于p型栅器件结构简单、阈值电压稳定性好等优点备受学术界和产业界关注。目前，p型栅器件已经开始产业化，推行该结构器件的主要公司有日本的Panasonic公司、美国的EPC公司及加拿大的GaN Systems公司。特别是Panasonic公司采用结合刻蚀凹槽、二次生长及刻蚀p型层的技术方案制备了阈值电压特性更好的p型栅器件(IEEE TRANSACTIONS ON ELECTRON DEVICES,VOL.64,NO.3,MARCH 2017，Page1026-1031)。目前，关于p型栅常关型AlGaN/GaN HEMT器件的实现，业界主要采用刻蚀技术方案，该技术由于容易实现成为业界普遍采用的方法，然而该方法存在许多不足，如在刻蚀去除接入区p-GaN材料时，由于刻蚀均匀性差以及存在过刻蚀的问题，且刻蚀会对AlGaN势垒层表面带来晶格损伤并引入额外缺陷能级，会使接入区2DEG的电学特性发生退化，从而影响器件的性能均一性和稳定性。另一种技术方案选择区域生长p-GaN技术也被采用(如图2所示)，即在AlGaN/GaN异质结构上进行p-GaN层的选择区域生长，从而实现栅极区域形成p-GaN层，而接入区无p-GaN层的结构(Materials Science in  Semiconductor Processing,Vol.78,2018,Pages 96-106)。然而，受制于外延生长动力学的影响，当器件的栅长较小时，即生长窗口很窄时，p-GaN材料选区生长难以控制且掺杂不均匀等缺点，目前在这些方面没有突破性进展。而且选区生长需要额外在晶圆表面形成图形化的掩膜层，最普遍采用的是SiO 2掩膜层，高温下SiO 2易分解产生Si和O元素，它们扩散至外延层中易于形成施主型掺杂，从而导致漏电并严重影响外延晶体质量，还有掩膜层对外延生长动力学的影响也是不可忽视的。此外，p-GaN层空穴浓度普遍不高，目前主流报道值基本不高于1×10 18cm -3，因此p-GaN层下方AlGaN势垒层的Al组分普遍要求低于20％和厚度低于18nm，这有利于实现增强型操作，但是同时会导致接入区的电阻增大，而相对薄的AlGaN势垒层也会使得p型GaN层中的掺杂元素(如镁)更容易扩散至沟道，进而影响到器件的可靠性。
发明内容
本发明为克服上述现有技术所述的至少一种缺陷，提供一种新型增强型半导体器件，能实现更高的阈值电压、更低的导通电阻、更低的漏电流，以及更稳定的工作状态。
为解决上述技术问题，本发明采用的技术方案是：一种新型增强型半导体器件，包括衬底、生长在衬底上的半导体外延层、栅极、源极以及漏极。其中，所述外延层，自下至上包括氮化物成核层、氮化物应力缓冲层、氮化物沟道层、一次外延氮化物势垒层，以及p型氮化物层和二次外延氮化物势垒层；所述的p型氮化物层仅保留在栅极区域一次外延氮化物势垒层之上，实现栅极下方二维电子气沟道的夹断；二次外延无掩膜，二次外延氮化物势垒层生长于一次外延势垒层和栅极区域的p型氮化物层之上。
蚀栅极区域以外的p型氮化物，留下栅极区域的p型氮化物，实现栅极沟道的夹断。二次生长过程无掩膜影响，二次外延氮化物势垒层生长于一次外延势垒层和栅极区域的p型氮化物层之上，实现高导通接入区。同时通过调控一次外延氮化物势垒层和二次外延氮化物势垒层的厚度和组分，实现更优的栅极关断能力以及高导通的栅源接入区和栅漏接入区。并且此方法可以有效的修复刻蚀带来的接入区损伤，对刻蚀工艺的要求也降低。最终实现高阈值电压、高导通能力、高稳定性的增强型半导体器件。
进一步的，所述衬底为Si衬底、蓝宝石衬底、碳化硅衬底、GaN自支撑衬底或AlN中的任一种。
进一步的，所述的氮化物应力缓冲层为含AlN、AlGaN、GaN、SiN的任一种或组合；所述的氮化物成核层为含Al氮化物层。
进一步的，所述的氮化物沟道层为GaN或AlGaN层。
进一步的，所述的一次外延氮化物势垒层为AlGaN、AlInN、InGaN、AlInGaN、AlN 中的一种或任意几种的组合材料，Al组分为1％-30％，厚度为1nm-30nm；
进一步的，所述的二次外延氮化物势垒层为AlGaN、AlInN、InGaN、AlInGaN、AlN中的一种或任意几种的组合，Al组分为1％-40％，厚度为1nm-40nm；
进一步的，所述的p型氮化物层为GaN、AlGaN、AlInN或AlInGaN，厚度不低于5nm。
进一步的，所述的一次外延氮化物势垒层和氮化物沟道层之间还插入有一层AlN空间隔离层，AlN空间隔离层厚度为0.3nm-3nm。
进一步的，所述的p型氮化物层与一次外延氮化物势垒层之间还插入有一层AlN阻挡层，AlN阻挡层厚度为0.3nm-5nm。
进一步的，所述的二次外延氮化物势垒层铝组分一般高于一次外延氮化物势垒层。
进一步的，栅极区域的p型氮化物层被保留，而栅极区域的p型氮化物层下方之外区域的一次外延氮化物势垒层被部分去除，剩余一次外延氮化物势垒层厚度为1-30nm。
进一步的，所述的二次外延氮化物势垒层之上还在位生长盖帽层和钝化层；所述的盖帽层为GaN，厚度为0.5-8nm；所述的钝化层为SiN，厚度为1-100nm。
进一步的，所述的源极和漏极为欧姆接触，栅极为欧姆接触或肖特基接触。
进一步的，所述的栅极金属可以直接与二次外延氮化物势垒层接触，或者在刻蚀掉p型氮化物层上方部分二次外延氮化物势垒层后，进而与p型氮化物层直接接触。
本发明还提供一种新型增强型半导体器件的制备方法，包括以下步骤：
S1.在衬底上生长氮化物成核层；
S2.在衬底上生长氮化物成核层；
S3.在氮化物应力缓冲层生长氮化物沟道层；
S4.在氮化物沟道层上生长一次外延氮化物势垒层；
S5.在一次外延氮化物势垒层上生长p型氮化物层；
S6.通过光刻图形化以及刻蚀的方法，形成p型栅极结构；
S7.生长二次外延氮化物势垒层；
S8.高温退火激活p型氮化物层中的受主掺杂元素；
S9.干法刻蚀完成器件隔离，同时刻蚀出源极和漏极欧姆接触区；
S10.在源极和漏极区域上形成源极和漏极欧姆接触金属；
S11.在栅极区域p型氮化物层上形成栅极金属。
在背景技术中提到传统的刻蚀方案制备p型栅增强型器件，对设备和工艺要求非常苛刻，存在过刻蚀以及刻蚀损伤带来的问题，这会严重劣化器件特性。本发明专利提出采用刻蚀方案结合二次生长技术：首先通过干法刻蚀去除栅极区域以外的p型氮化物层以及部分 一次外延氮化物势垒层，保留栅极区域的p型氮化物层以及一次外延氮化物势垒层，从而实现栅极沟道的夹断。然后进行二次外延，MOCVD在线高温修复一次外延势垒层的刻蚀损伤(可以在氮气、氨气或其混合气体环境下)，再生长二次外延氮化物势垒层，从而实现栅区之外的高导通能力接入区沟道，该二次外延过程没有掩膜，二次外延势垒层为整面生长于晶圆表面，可以消除掩膜对二次生长的影响。栅极区域的p型氮化物层的侧面(非极性面或半极性面，几乎不会产生2DEG)和上面也会生长二次外延势垒层，由于p型氮化物层中空穴的耗尽作用，在这两个面也可完全保证关断。再而，可以通过对器件一次外延势垒层和二次外延势垒层进行再设计，包括势垒层中铝元素的组分以及势垒层的厚度设计，从而达到开关特性的显著提升。
与现有技术相比，有益效果是：本发明提供的一种新型增强型半导体器件及其制备方法，采用二次外延技术，这也为栅极区域和栅极以外接入区区域的氮化物势垒层设计提供了可行性，通过设计一次外延氮化物势垒层和二次外延氮化物势垒层结构，从而合理的同时实现了栅极下方异质结沟道的关断特性和栅极区域之外接入区异质结沟道的导电能力，这一优势是采用目前已有的刻蚀方案或选区外延p-GaN方案所不具备的。本发明技术最终能有效实现高阈值电压、高导通性能、低漏电、高稳定性的增强型器件。
附图说明
图1为现有刻蚀方案中增强型器件的结构示意图。
图2为现有选区外延p-GaN方案中增强型器件的结构示意图。
图12为本发明实施例1的器件结构示意图。
图3-12为本发明实施例1的器件制作方法工艺示意图。
图13为本发明实施例2的器件结构示意图。
图14为本发明实施例3的器件结构示意图。
图15为本发明实施例4的器件结构示意图。
图16为本发明实施例5的器件结构示意图。
图17为本发明实施例6的器件结构示意图。
图18为本发明实施例7的器件结构示意图。
图19为本发明实施例8的器件结构示意图。
图20为本发明实施例9的器件结构示意图。
图21为本发明实施例10的器件结构示意图。
图22为本发明实施例11的器件结构示意图。
图23为本发明实施例12的器件结构示意图。
图24为本发明实施例13的器件结构示意图。
图中，1-衬底；2-氮化物成核层；3-氮化物应力缓冲层；4-氮化物沟道层；5-一次外延氮化物势垒层；6-p型氮化物层；7-二次外延氮化物势垒层；8-源极；9-漏极；10-栅极；11-AlN空间隔离层；12-二次外延的氮化物沟道层；13-盖帽层或在位钝化层；14-钝化层；15-源极场板；16-跨接介质层；17-漏极厚电极；18-SiO 2掩膜层。
具体实施方式
附图仅用于示例性说明，不能理解为对本发明的限制；为了更好说明本实施例，附图某些部件会有省略、放大或缩小，并不代表实际产品的尺寸；对于本领域技术人员来说，附图中某些公知结构及其说明可能省略是可以理解的。附图中描述位置关系仅用于示例性说明，不能理解为对本发明的限制。
实施例1：
如图12所示为本实施例的器件结构示意图，一种半导体增强型晶体管，包括衬底1、生长在衬底1上的半导体外延层、栅极10、源极8以及漏极9。所述外延层，自下至上包括氮化物成核层2、氮化物应力缓冲层3、氮化物沟道层4、一次外延氮化物势垒层5，以及p型氮化物层6和二次外延氮化物势垒层7。p型氮化物层6仅保留在栅极10区域一次外延氮化物势垒层5之上，实现栅极10下方二维电子气沟道的夹断。二次外延无掩膜，二次外延氮化物势垒层7生长于一次外延势垒层和栅极10区域的p型氮化物层6之上。
上述半导体增强型晶体管的制作方法如图3-图12所示，包括以下步骤：
S1.在衬底1上生长氮化物成核层2，如图3所示；
S2.在氮化物成核层2上生长氮化物应力缓冲层3，如图4所示；
S3.在氮化物应力缓冲层3生长氮化物沟道层4，如图5所示；
S4.在氮化物沟道层4上生长一次外延氮化物势垒层5，如图6所示；
S5.在一次外延氮化物势垒层5上生长p型氮化物层6，如图7所示；
S6.通过光刻图形化以及刻蚀的方法，将栅极10区域之外的p型氮化物层6全部去除，并去除栅极10区域之外的部分一次外延氮化物势垒层5，如图8所示；
S8.高温在线退火修复刻蚀造成的晶格损伤，进而二次外延氮化物势垒层7的生长，如图9所示；
S9.高温退火激活p型氮化物层6中的受主掺杂元素；
S11.干法刻蚀完成器件隔离，如图10所示；
S12.在源极8和漏极9区域上形成源极8和漏极9欧姆接触金属，如图11所示；
S13.在栅极10区域p型氮化物层6上形成栅极10金属，如图12所示。
至此，即完成了整个器件的制备过程。图12即为实施例1的器件结构示意图。
实施例2
如图13所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例2中氮化物沟道层4和一次外延氮化物势垒层5之间还夹入了一层AlN空间隔离层11，其厚度为0.3-3nm。用于提高沟道二维电子气特性。
实施例3
如图14所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例1为中，去除了栅极10区域之外的部分一次外延氮化物势垒层5，而实施例3中栅极10区域之外的部分一次外延氮化物势垒层5完整保留。相比于实施例1，实施例3要求更加苛刻的刻蚀方案，如更先进的设备，或含氧或含氟的自终止刻蚀条件。
实施例4
如图15所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例1为中，去除了栅极10区域之外的部分一次外延氮化物势垒层5，而实施例4中栅极10区域之外的一次外延氮化物势垒层5全部去除。实施例4中，在生长二次外延氮化物势垒层7之前，也可先生长薄层AlN空间隔离层11，其厚度为0.3-3nm。
实施例5
如图16所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例1为中，去除了栅极10区域之外的部分一次外延氮化物势垒层5，而实施例5中栅极10区域之外的一次外延氮化物势垒层5全部去除，并进一步去除了部分氮化物沟道层4。实施例5中，在生长二次外延氮化物势垒层7之前，也可先生长薄层AlN空间隔离层11，其厚度为0.3-3nm。
实施例6
如图17所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例1为中，去除了栅极10区域之外的部分一次外延氮化物势垒层5，而实施例6中栅极10区域之外的一次外延氮化物势垒层5全部去除，并进一步去除了部分氮化物沟道层4，进而在二次生长中夹入了一层二次外延的氮化物沟道层12。其中，二次外延的氮化物沟道层12的厚度为1-10nm。实施例6中，在生长二次外延氮化物势垒层7之前，也可先生长薄层AlN空间隔离层11，其厚度为0.3-3nm。
实施例7
如图18所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例7中，欧姆接触区域二次外延氮化物势垒层7被刻蚀，也可进一步刻蚀到一次外延氮化物势垒层5 中，以实现更好的欧姆接触特性，最终保留的势垒层厚度为1-10nm。
实施例8
如图19所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例8中，二次外延氮化物势垒层7之上还有在位生长的盖帽层或钝化层13。盖帽层为GaN，厚度为0-8nm。在位钝化层为SiN x，SiO 2，Al 2O 3，AlO xN y，GaO x，GaO xN y，厚度为0-100nm。
实施例9
如图20所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例9中，二次外延氮化物势垒层7之上还有离位生长的钝化层14。钝化层14为SiN x，SiO 2，Al 2O 3等高k介质，或其叠层结构，生长工艺为LPCVD、PECVD、RTCVD、ALD、PEALD等。
实施例10
如图21所示为本实施例的器件结构示意图，其与实施例1和实施例9结构区别仅在于：实施例10中，器件栅极10含场板结构。
实施例11
如图22所示为本实施例的器件结构示意图，其与实施例1和实施例10结构区别仅在于：实施例10中，器件源极8含场板结构。
实施例12
如图23所示为本实施例的器件结构示意图，其与实施例1结构区别仅在于：实施例1中，p型氮化物层6的形状为矩形；实施例12中，p型氮化物层的形6状为梯形。此外，显然p型氮化物形状也可以为弧形、阶梯型等结构。
实施例13
如图24所示为本实施例的器件结构示意图，其与实施例1区别仅在于：实施例1中，栅极10金属直接与二次外延氮化物势垒层7接触。实施例13中，对p型氮化物势垒层上的部分二次外延势垒层进行刻蚀开口，栅极10金属可直接与p型氮化物势垒层接触。此外，显然刻蚀开口的深度可变：其一，刻蚀开口深度可小于二次外延势垒层的厚度，刻蚀深度为1-30nm；其二，刻蚀开口深度可大于二次外延势垒层的厚度，即p型氮化物层6亦可被刻蚀，p型氮化物层6被刻蚀深度范围1-10nm为佳。再而，刻蚀开口的宽度可变，即开口宽度小于或等于p型氮化物层6的宽度。
显然，本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定。本发明的核心内容为p型氮化物层刻蚀后再二次外延势垒层，一方面可以降低对刻蚀工艺的要求，另一方面可以通过设计一次外延氮化物势垒层和二次外延氮化物势垒层的厚度和组分，进而得到高阈值电压、高导通能力、高稳定性的增强型器件。本 发明仅借助了几种器件结构来进行相关技术的阐明，而在其它类似的经过变形或结合的器件方案中依然可行，在此不进行一一说明。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动，各实施方式中的技术方案包括步骤次序、材料种类和参数的选择、工艺方法和参数的选择等，都可以适当变化组合，各实施方案间也可适当组合，形成本领域技术人员可以理解的其他实施方案。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (10)

  1. 一种新型增强型半导体器件，包括衬底(1)、生长在衬底(1)上的半导体外延层、栅极(10)、源极(8)以及漏极(9)；其特征在于，所述外延层，自下至上包括氮化物成核层(2)、氮化物应力缓冲层(3)、氮化物沟道层(4)、一次外延氮化物势垒层(5)，以及p型氮化物层(6)和二次外延氮化物势垒层(7)；所述的p型氮化物层(6)仅保留在栅极(10)区域一次外延氮化物势垒层(5)之上，实现栅极(10)下方二维电子气沟道的夹断；所述二次外延氮化物势垒层(7)生长过程无掩膜；所述二次外延氮化物势垒层(7)位于一次外延氮化物势垒层(5)和栅极(10)区域的p型氮化物层(6)之上。
  2. 根据权利要求1所述的一种新型增强型半导体器件，其特征在于，所述衬底(1)为Si衬底(1)、蓝宝石衬底(1)、碳化硅衬底(1)、GaN自支撑衬底(1)或AlN中的任一种；所述的氮化物应力缓冲层(3)为含AlN、AlGaN、GaN、SiN的任一种或组合；所述的氮化物成核层(2)为含Al氮化物层；所述的氮化物沟道层(4)为GaN或AlGaN层。
  3. 根据权利要求1所述的一种新型增强型半导体器件，其特征在于，所述的一次外延氮化物势垒层(5)为AlGaN、AlInN、InGaN、AlInGaN、AlN中的一种或任意几种的组合材料，Al组分为1％-30％，厚度为1nm-30nm；所述的二次外延氮化物势垒层(7)为AlGaN、AlInN、InGaN、AlInGaN、AlN中的一种或任意几种的组合，Al组分为1％-40％，厚度为1nm-40nm；所述的p型氮化物层(6)为GaN、AlGaN、AlInN或AlInGaN，厚度不低于5nm。
  4. 根据权利要求3所述的一种新型增强型半导体器件，其特征在于，所述的一次外延氮化物势垒层(5)和氮化物沟道层(4)之间还插入有一层AlN空间隔离层(11)，AlN空间隔离层(11)厚度为0.3nm-3nm。
  5. 根据权利要求3所述的一种新型增强型半导体器件，其特征在于，所述的p型氮化物层(6)与一次外延氮化物势垒层(5)之间还插入有一层AlN阻挡层，AlN阻挡层厚度为0.3nm-5nm。
  6. 根据权利要求3所述的一种新型增强型半导体器件，其特征在于，所述的二次外延氮化物势垒层(7)铝组分高于一次外延氮化物势垒层(5)。
  7. 根据权利要求1至6任一项所述的一种新型增强型半导体器件，其特征在于，栅极(10)区域的p型氮化物层(6)被保留，而栅极(10)区域的p型氮化物层(6)下方之外区域的一次外延氮化物势垒层(5)被部分去除，一次外延氮化物势垒层(5)厚度为1-30nm。
  8. 根据权利要求7所述的一种新型增强型半导体器件，其特征在于，所述的二次外延氮化物势垒层(7)之上还在位生长盖帽层或钝化层(13)；所述的盖帽层为GaN，厚度为0.5-8nm；所述的钝化层为SiN x，SiO2，Al 2O 3，AlO xN y，GaO x，GaO xN y，厚度为1-100nm。
  9. 根据权利要求8所述的一种新型增强型半导体器件，其特征在于，所述的源极(8)和漏极(9)为欧姆接触，栅极(10)为欧姆接触或肖特基接触；所述的栅极(10)金属可以直接与二次外延氮化物势垒层(7)接触，或者在刻蚀掉p型氮化物层(6)上方的部分二次外延氮化物势垒层(7)后，进而栅极(10)金属可与p型氮化物层(6)直接接触。
  10. 一种新型增强型半导体器件的制备方法，其特征在于，包括以下步骤：
    S1.在衬底(1)上生长氮化物成核层(2)；
    S2.在氮化物成核层(2)上生长氮化物应力缓冲层(3)；
    S3.在氮化物应力缓冲层(3)生长氮化物沟道层(4)；
    S4.在氮化物沟道层(4)上生长一次外延氮化物势垒层(5)；
    S5.在一次外延氮化物势垒层(5)上生长p型氮化物层(6)；
    S6.通过光刻图形化以及刻蚀的方法，形成p型栅极(10)结构；
    S7.生长二次外延氮化物势垒层(7)；
    S8.高温退火激活p型氮化物层(6)中的受主掺杂元素；
    S9.干法刻蚀完成器件隔离，同时刻蚀出源极(8)和漏极(9)欧姆接触区；
    S10.在源极(8)和漏极(9)区域上形成源极(8)和漏极(9)欧姆接触金属；
    S11.在栅极(10)区域的p型氮化物层(6)上形成栅极(10)金属。
PCT/CN2019/072317 2019-01-15 2019-01-18 一种新型增强型半导体器件及其制备方法 WO2020147106A1 (zh)

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