WO2020143275A1 - 一种改进型反激变换器 - Google Patents

一种改进型反激变换器 Download PDF

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Publication number
WO2020143275A1
WO2020143275A1 PCT/CN2019/112992 CN2019112992W WO2020143275A1 WO 2020143275 A1 WO2020143275 A1 WO 2020143275A1 CN 2019112992 W CN2019112992 W CN 2019112992W WO 2020143275 A1 WO2020143275 A1 WO 2020143275A1
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Prior art keywords
capacitor
tube
transformer
cathode
anode
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PCT/CN2019/112992
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English (en)
French (fr)
Inventor
王志燊
江清辉
余逸群
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广州金升阳科技有限公司
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Publication of WO2020143275A1 publication Critical patent/WO2020143275A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the invention relates to a flyback converter, in particular to a flyback converter that can realize ZVS.
  • Flyback circuits are widely used in low-power power supplies due to their simple structure, low cost, and easy design.
  • a common flyback circuit since the voltage between the drain and the source is not 0 when the MOS tube is turned on, the turn-on loss is large, which affects the increase in the switching frequency of the topology and limits the volume of the topology. If zero-voltage turn-on, that is, ZVS, can be achieved, the performance of the flyback circuit can be improved.
  • the technical problem solved by the present invention is to overcome the shortcomings of the existing methods, and an improved flyback circuit is proposed, all MOS tubes can realize ZVS, and the control is simple.
  • the first technical solution of the present invention is: an improved flyback converter, including unidirectional conduction device, MOS transistor Q1, MOS transistor Q2, transformer and secondary side rectifier filter circuit, anode of unidirectional conduction device and transformer
  • the different-named end of the primary winding is connected to the positive end of the voltage source
  • the cathode of the unidirectional conducting device is connected to the drain of the MOS tube Q2
  • the source of the MOS tube Q2 is connected to the same-named end of the transformer primary winding and the drain of the MOS tube Q1, the MOS tube
  • the source of Q1 is connected to the negative terminal of the voltage source
  • the secondary side of the transformer passes through the rectifier filter circuit to output the voltage Vo; it is characterized by: it also includes a capacitor C1, one end of the capacitor C1 is connected to the anode of the unidirectional conduction device, and the other end of the capacitor C1 is connected Cathode of unidirectional conducting device.
  • the second technical solution of the present invention is: an improved flyback converter, including unidirectional conduction device, MOS transistor Q1, MOS transistor Q2, transformer and secondary side rectifier filter circuit, anode of unidirectional conduction device and transformer
  • the different-named end of the primary winding is connected to the positive end of the voltage source
  • the source of the MOS tube Q2 is connected to the same-named end of the transformer primary winding and the drain of the MOS tube Q1
  • the source of the MOS tube Q1 is connected to the negative end of the voltage source
  • the output voltage Vo after passing through the rectifying and filtering circuit is characterized in that it further includes a capacitor C1, and the cathode of the unidirectional conducting device is connected to the drain of the MOS transistor Q2 through the capacitor C1.
  • the unidirectional conduction device is a diode D1
  • the anode of the diode D1 is used as the anode of the unidirectional conduction device
  • the cathode of the diode D1 is used as the cathode of the unidirectional conduction device.
  • the unidirectional conducting device is a TVS tube
  • the anode of the TVS tube serves as the anode of the unidirectional conducting device
  • the cathode of the TVS tube serves as the cathode of the unidirectional conducting device.
  • the unidirectional conducting device is a TVS tube
  • the anode of the TVS tube serves as the anode of the unidirectional conducting device
  • the cathode of the TVS tube serves as the cathode of the unidirectional conducting device.
  • it further includes a diode D3, the anode of the diode D3 is connected to the anode of the TVS tube, and the cathode of the diode D3 is connected to the drain of the MOS tube Q2.
  • the unidirectional conducting device is a voltage stabilizing tube
  • the anode of the voltage regulating tube is used as the anode of the unidirectional conducting device
  • the cathode of the voltage regulating tube is used as the cathode of the unidirectional conducting device
  • the improved flyback converter It also includes a capacitor Cc.
  • One end of the capacitor Cc is respectively connected to the cathode of the voltage stabilizing tube and the other end of the capacitor C1, and the other end of the capacitor Cc is connected to the drain of the MOS tube Q2.
  • the improved flyback converter further includes a resistor R1, one end of the resistor R1 is connected to the cathode of the regulator tube, and the other end of the resistor R1 is connected to one end of the capacitor Cc and the other end of the capacitor C1.
  • the invention only needs to connect a capacitor in parallel with the diode, without using synchronous rectification, and can realize the ZVS of the primary side MOS tube under the condition of constant frequency control.
  • the added capacitor can absorb the energy of leakage inductance when the main power tube is turned off, which helps reduce the voltage spike of the main MOS tube.
  • the transformer will release energy to the secondary side.
  • the secondary side current drops to zero, the energy of the transformer is released.
  • the added capacitor will release the energy to reverse the excitation of the transformer, causing the transformer to generate
  • the reverse excitation current provides the basis for the ZVS of the main MOSFET. Therefore, the added capacitor can not only absorb the leakage inductance energy and reduce the voltage spike, but also provide the reverse excitation energy for the transformer to achieve ZVS, with low cost and large effect.
  • the solution proposed by the present invention overcomes the deficiency that the ordinary flyback circuit cannot achieve ZVS.
  • a MOS tube, a diode and a capacitor are added to realize the ZVS of the primary MOS tube.
  • the added MOS tube drives and the flyback circuit
  • the main MOS tube driver is complementary, the control is simple, and the added MOS tube can also realize ZVS.
  • the solution proposed in the present invention can turn the high-frequency oscillation generated by the transformer leakage inductance and the main MOS tube parasitic capacitance into low-frequency oscillation when the main MOS tube is turned off, and eliminate When the converter enters DCM, the excitation inductance and the oscillation generated by the parasitic capacitance of the main MOS tube help to improve EMI.
  • Figure 1 is a schematic diagram of a flyback circuit in the prior art
  • FIG. 2 is a circuit schematic diagram of the first embodiment of the present invention.
  • FIG. 3 is a circuit simulation working curve diagram of the first embodiment of the present invention.
  • FIG. 4 is a circuit schematic diagram of a second embodiment of the present invention.
  • FIG. 5 is a circuit simulation working curve diagram of the second embodiment of the present invention.
  • FIG. 6 is a circuit schematic diagram of a third embodiment of the present invention.
  • FIG. 7 is a circuit schematic diagram of a fourth embodiment of the present invention.
  • FIG. 8 is a circuit schematic diagram of a fifth embodiment of the present invention.
  • FIG. 9 is a circuit schematic diagram of a sixth embodiment of the present invention.
  • the inventive concept of the present invention is to add a capacitor, absorb leakage inductance energy, and provide reverse excitation energy for the transformer, and provide a basis for ZVS.
  • the driving of the two MOS tubes is complementary driving, and the control is simple.
  • FIG. 2 is a schematic diagram of the first embodiment of the power stage of the flyback circuit of the present invention.
  • the voltage source Vin is the external input voltage
  • Vo is the output voltage
  • the resistance R is the load of the flyback circuit.
  • the improved flyback circuit of the invention is composed of a capacitor C1, a diode D1, a MOS tube Q1, a MOS tube Q2, a transformer T, a diode D2, and an output capacitor C2.
  • the positive end of the voltage source Vin is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain of the MOS tube Q2, the source of the MOS tube Q2 is connected to the drain of the MOS tube Q1, and the source of the MOS tube Q1 is connected to the voltage
  • the negative terminal of the source Vin is connected.
  • One end of the capacitor C1 is connected to the anode of the diode D1, the other end of the capacitor C1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the primary side of the transformer T, and the primary side of the primary side of the transformer T is connected to the MOS transistor Q2
  • the source is connected, the secondary side of the transformer T is connected to the anode of the diode D2 with the same name, the cathode of the diode D2 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the secondary end of the transformer T, and the one end of the capacitor C2 is connected to One end of the load resistor R is connected, and the other end of the capacitor C2 is connected to the other end of the load resistor R.
  • Figure 1 is a patent of Rompower. Compared with Figure 1, Figure 2 adds a capacitor C1.
  • the secondary side can achieve ZVS of MOS transistor Q1 without using synchronous rectification. And the driving of the two MOS tubes is complementary, and the control is simple.
  • the circuit of this solution is simulated.
  • the input voltage is 240V
  • the output voltage is 12V
  • the output power is 30W
  • the switching frequency is 65kHz
  • the capacitor C1 is 2.2nF
  • the transformer excitation inductance is 450uH
  • the leakage inductance is 18uH
  • the turns ratio is 38:5
  • the capacitor C2 is 1000uF.
  • the air ratio and working curve are shown in Figure 3.
  • the MOS transistors Q1 and Q2 use complementary drive, and the working principle is as follows:
  • the MOS transistor Q1 In the t0 ⁇ t1 stage, the MOS transistor Q1 is turned on, the MOS transistor Q2 is turned off, the input voltage Vin excites the transformer T, and the secondary diode D2 is turned off;
  • Stage t1 ⁇ t2 this stage is the dead time driven by two MOS transistors, MOS transistor Q1 is turned off, MOS transistor Q2 is turned on through the body diode, and its parasitic capacitance is discharged. Therefore, MOS transistor Q2 can realize ZVS, leakage inductance energy transmission In the capacitor C1, the leakage inductance and the capacitance C1 oscillate; at the same time, the leakage inductance energy and the excitation energy charge the parasitic capacitance of the MOS tube Q1.
  • the secondary diode D2 is turned on, and the excitation energy is transmitted to the secondary side;
  • the excitation current continues to decrease, and the excitation energy continues to be transmitted to the secondary side.
  • the primary capacitor C1 and the transformer leakage inductance resonate.
  • the excitation current drops to 0, the secondary current also drops to 0, and the primary clamping voltage disappears. ;
  • Stage t5 ⁇ t6, this stage is the dead time driven by the two MOS transistors.
  • the MOS transistor Q2 is turned off, the choke loop is disconnected, the reverse current is used to extract the charge on the parasitic capacitance Cds1 of the MOS transistor Q1, and the voltage of Vds1 gradually When it drops to 0, the MOS transistor Q1 is turned on at t6 to realize ZVS.
  • FIG. 4 is a circuit schematic diagram of a second embodiment of the invention.
  • the voltage waveform of the main MOS transistor Vds of the circuit of the second embodiment is significantly improved, which helps to further improve EMI; but because the TVS tube added by the second embodiment has a large loss, the circuit of the first embodiment is compared The circuit efficiency of the second embodiment is low.
  • the positive end of the voltage source Vin is connected to one end of the TVS tube Ds, the other end of the TVS tube Ds is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain of the MOS tube Q2, and the source of the MOS tube Q2 is connected to the MOS tube
  • the drain of Q1 is connected, and the source of the MOS transistor Q1 is connected to the negative terminal of the voltage source Vin.
  • the anode of the TVS tube Ds is connected to the primary side of the transformer T, the primary side of the transformer T is connected to the source of the MOS tube Q2, the secondary side of the transformer T is connected to the anode of the diode D2, and the cathode of the diode D2 It is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the secondary end of the transformer T, the one end of the capacitor C2 is connected to one end of the load resistor R, and the other end of the capacitor C2 is connected to the other end of the load resistor R.
  • the MOS transistor Q1 In the t0 ⁇ t1 stage, the MOS transistor Q1 is turned on, the MOS transistor Q2 is turned off, the input voltage Vin excites the transformer T, and the secondary diode D2 is turned off;
  • Stage t1 ⁇ t2 this stage is the dead time driven by two MOS transistors, MOS transistor Q1 is turned off, MOS transistor Q2 is turned on through the body diode, and its parasitic capacitance is discharged. Therefore, MOS transistor Q2 can realize ZVS, leakage inductance energy transmission Into the capacitor C1; at the same time, the leakage inductance energy and the excitation energy charge the parasitic capacitance of the MOS tube Q1.
  • the secondary diode D2 is turned on, and the excitation energy is transmitted to the secondary side;
  • the excitation current continues to decrease, and the excitation energy continues to be transmitted to the secondary side.
  • the primary capacitor C1 and the TVS tube Ds are clamped at nVo.
  • the excitation current drops to 0, the secondary current also drops to 0, and the primary clamping voltage disappears;
  • the voltage Vc1 at the end of the capacitor C1 is discharged, and a reverse current of a certain value is generated.
  • the reverse current flows through the choke circuit, that is, through the capacitor C1, the MOS tube Q2, the excitation inductance, and the TVS tube Ds.
  • the parasitic capacitance of the MOS transistor Q1 is discharged, and the drain-source voltage Vds1 is clamped after dropping to Vin.
  • Stage t4 ⁇ t5 this stage is the dead time driven by the two MOS transistors.
  • the MOS transistor Q2 is turned off, the choke loop is disconnected, and the reverse current is used to extract the charge on the parasitic capacitance Cds1 of the MOS transistor Q1.
  • the voltage of Vds1 gradually When it drops to 0, the MOS transistor Q1 is turned on at t6 to realize ZVS.
  • FIG. 6 is a circuit schematic diagram of a third embodiment of the present invention. This embodiment differs from the first embodiment in that the diode D1 is replaced with a TVS tube Ds.
  • the positive end of the voltage source Vin is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain of the MOS tube Q2, the source of the MOS tube Q2 is connected to the drain of the MOS tube Q1, and the source of the MOS tube Q1 is connected to the voltage
  • the negative terminal of the source Vin is connected.
  • One end of the capacitor C1 is connected to the anode of the TVS tube Ds, the other end of the capacitor C1 is connected to the cathode of the TVS tube Ds, the anode of the diode D1 is connected to the primary side of the transformer T, and the primary side of the transformer T has the same name and the MOS tube
  • the source of Q2 is connected, the secondary end of the transformer T has the same name as the anode of the diode D2, the cathode of the diode D2 is connected with one end of the capacitor C2, the other end of the capacitor C2 is connected with the secondary end of the transformer T, and the capacitor C2 One end is connected to one end of the load resistance R, and the other end of the capacitor C2 is connected to the other end of the load resistance R.
  • FIG. 7 is a circuit schematic diagram of a fourth embodiment of the present invention. This embodiment adds a diode D3 to the second embodiment.
  • the positive terminal of the voltage source Vin is connected to the anode of the diode D3, the cathode of the diode D3 is connected to the drain of the MOS tube Q2, the source of the MOS tube Q2 is connected to the drain of the MOS tube Q1, and the source of the MOS tube Q1 is connected to the voltage source
  • the negative terminal of Vin is connected.
  • the anode of the diode D3 is connected to the anode of the TVS tube Ds
  • the cathode of the TVS tube Ds is connected to one end of the capacitor C1
  • the other end of the capacitor C1 is connected to the cathode of the diode D3.
  • the anode of the TVS tube Ds is connected to the primary side of the transformer T, the primary side of the transformer T is connected to the source of the MOS tube Q2, the secondary side of the transformer T is connected to the anode of the diode D2, and the cathode of the diode D2 It is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the secondary end of the transformer T, the one end of the capacitor C2 is connected to one end of the load resistor R, and the other end of the capacitor C2 is connected to the other end of the load resistor R.
  • This circuit is a solution integrating the circuits of the first embodiment and the second embodiment, and the waveform of the voltage Vds between the drain and the source of the main MOS tube is optimized between the two solutions.
  • its working principle is mainly different: when the main MOS tube is turned off, the leakage inductance charges the capacitor C1 to oscillate, but due to the existence of the TVS tube (which uses a low-voltage TVS tube), the voltage at the capacitor C1 terminal will be very high It quickly stabilizes and eliminates oscillations.
  • FIG. 8 is a circuit schematic diagram of a fifth embodiment of the invention.
  • the positive terminal of the voltage source Vin is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to one end of the capacitor Cc, the other end of the capacitor Cc is connected to the drain of the MOS tube Q2, and the source of the MOS tube Q2 is connected to the MOS tube Q1 The drain is connected, and the source of the MOS transistor Q1 is connected to the negative terminal of the voltage source Vin.
  • One end of the capacitor C1 is connected to the anode of the voltage regulator Dc, the other end of the capacitor C1 is connected to the cathode of the voltage regulator Dc, the anode of the voltage regulator Dc is connected to the different end of the primary side of the transformer T, and the primary side of the transformer T has the same name
  • the terminal is connected to the source of the MOS tube Q2, the secondary side of the transformer T is connected to the anode of the diode D2, the cathode of the diode D2 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the secondary end of the transformer T
  • One end of the capacitor C2 is connected to one end of the load resistor R, and the other end of the capacitor C2 is connected to the other end of the load resistor R.
  • the circuit of the fifth embodiment replaces the TVS tube with a voltage stabilizing tube, and adds a capacitor Cc to protect the voltage stabilizing tube and prevent the voltage stabilizing tube from burning out due to overcurrent.
  • FIG. 9 is a circuit schematic diagram of a sixth embodiment of the present invention. This embodiment refers to the fifth embodiment and adds a resistor R1.
  • the positive terminal of the voltage source Vin is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to one end of the capacitor Cc, the other end of the capacitor Cc is connected to the drain of the MOS tube Q2, and the source of the MOS tube Q2 is connected to the MOS tube Q1 The drain is connected, and the source of the MOS transistor Q1 is connected to the negative terminal of the voltage source Vin.
  • One end of the capacitor C1 is connected to the anode of the voltage stabilizing tube Dc
  • the cathode of the voltage stabilizing tube Dc is connected to one end of the resistor R1
  • the other end of the resistor R1 is connected to the other end of the capacitor C1.
  • the anode of the voltage regulator tube Dc is connected to the different-named end of the primary side of the transformer T.
  • the primary-named end of the transformer T is connected to the source of the MOS tube Q2.
  • the secondary-named end of the transformer T is connected to the anode of the diode D2.
  • the cathode is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the different end of the secondary side of the transformer T, one end of the capacitor C2 is connected to one end of the load resistor R, and the other end of the capacitor C2 is connected to the other end of the load resistor R.
  • the working principle of this circuit is similar to the fifth embodiment.
  • the main difference is that in the fifth embodiment, the main MOS tube is turned off, and the regulator tube cannot stabilize the voltage. Adding a resistor can make the regulator tube regulate normally.

Abstract

本发明提供了一种改进型反激变换器，在原边续流回路的基础上只需增加一只电容，无需采用同步整流，就可在恒频控制的情况下实现原边MOS管的ZVS。所添加的电容，可以在主功率管关断时，吸收漏感的能量，有助于降低主MOS管的电压尖峰。在主MOS管关断过程中，变压器会向副边释放能量，当副边电流下降为零，变压器的能量释放完毕，此时，所添加的电容会释放能量对变压器反向激磁，使得变压器产生反向的励磁电流，为实现主MOSFET的ZVS提供基础。

Description

一种改进型反激变换器 技术领域
本发明涉及一种反激变换器，特别涉及一种可实现ZVS的反激变换器。
背景技术
反激电路由于结构简单、成本低廉、容易设计等优点，广泛应用于小功率电源。普通的反激电路，由于MOS管导通时漏极和源极之间的电压不为0，因此开通损耗较大，影响了该拓扑的开关频率提高，限制了拓扑的体积下降。如果可以实现零电压开通，即ZVS，则可以提升反激电路的性能。
Rompower公司通过对反激电路进行改进，实现了ZVS。该公司的专利(专利号US7450402B2)采用输出同步整流，通过延长同步整流管的导通时间，使得副边电流反向，从而实现原边MOS管的ZVS，但该方案只能采用变频控制，不同负载的工作频率不相同。后来该公司对方案进行改进，在专利US20140334194A1中，如图1，通过引入原边续流回路，使得可以采用恒频控制的方式实现ZVS，但该方案依然需要采用副边同步整流控制，需要对副边电流进行采样，在副边电流反向并且达到一定值才关断同步整流管，控制复杂度高。
发明内容
有鉴于此，本发明解决的技术问题是克服现有方法的不足，提出一种改进型反激电路，所有MOS管都可以实现ZVS，并且控制简单。
本发明的第一种技术方案为：一种改进型反激变换器，包括单向导通器件、MOS管Q1、MOS管Q2、变压器和副边整流滤波电路，单向导通器件的阳极和变压器的原边绕组异名端连接电压源正端，单向导通器件的阴极连接MOS管Q2的漏极，MOS管Q2的源极连接变压器的原边绕组同名端和MOS管Q1的漏极，MOS管Q1的源极连接电压源负端；变压器的副边经过整流滤波电路后输出电压Vo；其特征在于：还包括电容C1，电容C1的一端连接单向导通器件的阳极，电容C1的另一端连接单向导通器件的阴极。
本发明的第二种技术方案为：一种改进型反激变换器，包括单向导通器件、MOS管Q1、MOS管Q2、变压器和副边整流滤波电路，单向导通器件的阳极和变 压器的原边绕组异名端连接电压源正端，MOS管Q2的源极连接变压器的原边绕组同名端和MOS管Q1的漏极，MOS管Q1的源极连接电压源负端；变压器的副边经过整流滤波电路后输出电压Vo；其特征在于：还包括电容C1，单向导通器件的阴极通过电容C1连接到MOS管Q2的漏极。
优选的，根据第一种技术方案，所述的单向导通器件为二极管D1，二极管D1的阳极作为单向导通器件的阳极，二极管D1的阴极作为单向导通器件的阴极。
优选的，根据第一种技术方案，所述的单向导通器件为TVS管，TVS管的阳极作为单向导通器件的阳极，TVS管的阴极作为单向导通器件的阴极。
优选的，根据第二种技术方案，所述的单向导通器件为TVS管，TVS管的阳极作为单向导通器件的阳极，TVS管的阴极作为单向导通器件的阴极。
优选的，还包括二极管D3，二极管D3的阳极连接TVS管的阳极，二极管D3的阴极连接MOS管Q2的漏极。
优选的，所述的单向导通器件为稳压管，稳压管的阳极作为单向导通器件的阳极，稳压管的阴极作为单向导通器件的阴极；所述的改进型反激变换器还包括电容Cc，电容Cc的一端分别连接稳压管的阴极和电容C1的另一端，电容Cc的另一端连接MOS管Q2的漏极。
优选的，所述的改进型反激变换器还包括电阻R1，电阻R1的一端连接稳压管的阴极，电阻R1的另一端连接电容Cc的一端和电容C1的另一端。
本发明在原边续流回路的基础上，只需在二极管上并联一个电容，无需采用同步整流，就可在恒频控制的情况下实现原边MOS管的ZVS。所添加的电容，可以在主功率管关断时，吸收漏感的能量，有助于降低主MOS管的电压尖峰。在主MOS管关断过程中，变压器会向副边释放能量，当副边电流下降为零，变压器的能量释放完毕，此时，所添加的电容会释放能量对变压器反向激磁，使得变压器产生反向的励磁电流，为实现主MOSFET的ZVS提供基础。因此，添加的电容既可以吸收漏感能量减小电压尖峰，又可以为变压器提供反向激磁能量从而实现ZVS，成本低，作用大。
本发明所提的方案，克服了普通反激电路无法实现ZVS的不足，添加一个MOS管、一个二极管以及一个电容，实现了原边MOS管的ZVS，所添加的MOS管 驱动与反激电路的主MOS管驱动互补，控制简单，并且所添加的MOS管也可以实现ZVS。从主MOS管的漏源极电压Vds波形来看，本发明所提方案，可以将主MOS管关断时，变压器漏感和主MOS管寄生电容产生的高频振荡变为低频振荡，并且消除变换器进入DCM时，励磁电感与主MOS管寄生电容产生的振荡，有助于改善EMI。
附图说明
图1为现有技术的反激电路原理图；
图2为本发明第一实施例电路原理图；
图3为本发明第一实施例电路仿真工作曲线图；
图4为本发明第二实施例电路原理图；
图5为本发明第二实施例电路仿真工作曲线图；
图6为本发明第三实施例电路原理图；
图7为本发明第四实施例电路原理图；
图8为本发明第五实施例电路原理图；
图9为本发明第六实施例电路原理图。
具体实施方式
本发明的发明构思为添加一电容，吸收漏感能量，并且为变压器提供反向激磁能量，为ZVS提供基础，两MOS管的驱动为互补驱动，控制简单。
第一实施例
图2为本发明反激电路功率级第一实施例原理图。电压源Vin是外部输入电压，Vo是输出电压，电阻R是反激电路的负载。该发明的改进型反激电路由电容C1、二极管D1、MOS管Q1、MOS管Q2、变压器T、二极管D2和输出电容C2构成。
该实施例的连接关系如下：
电压源Vin的正端与电容C1的一端相连，电容C1的另一端与MOS管Q2的漏极相连，MOS管Q2的源极与MOS管Q1的漏极相连，MOS管Q1的源极与电压源Vin的负端相连。电容C1的一端与二极管D1的阳极相连，电容C1的另一端与二极管D1的阴极相连，二极管D1的阳极与变压器T的原边异名端相连，变 压器T的原边同名端与MOS管Q2的源极相连，变压器T的副边同名端与二极管D2的阳极相连，二极管D2的阴极与电容C2的一端相连，电容C2的另一端与变压器T的副边异名端相连，电容C2的一端与负载电阻R的一端相连，电容C2的另一端与负载电阻R的另一端相连。
图1为Rompower公司的专利，图2与图1相比，增加了电容C1，副边无需采用同步整流，就可以实现MOS管Q1的ZVS。而且两MOS管的驱动是互补的，控制简单。
对本方案的电路进行仿真，输入电压240V，输出电压12V，输出功率30W，开关频率65kHz，电容C1为2.2nF，变压器励磁电感450uH，漏感18uH，匝比38:5，电容C2为1000uF，占空比，工作曲线如图3。MOS管Q1、Q2采用互补驱动，工作原理如下：
t0～t1阶段，MOS管Q1导通，MOS管Q2关断，输入电压Vin对变压器T激磁，副边二极管D2截止；
t1～t2阶段，此阶段是两MOS管驱动的死区时间，MOS管Q1关断，MOS管Q2通过体二极管导通，其寄生电容放电，所以，MOS管Q2可以实现ZVS，漏感能量传到电容C1中，漏感和电容C1振荡；同时漏感能量和励磁能量对MOS管Q1寄生电容充电，在本阶段后期，副边二极管D2导通，励磁能量传输到副边；
t2～t3阶段，励磁电流持续下降，励磁能量持续传输到副边，原边电容C1和变压器漏感谐振，t3时刻励磁电流降为0，副边电流也降为0，原边钳位电压消失；
t3～t4阶段，电容C1端电压Vc1放电至0，产生一定值的反向电流，同时MOS管Q1漏源极电压Vds1降至Vin。
t4～t5阶段，t4时刻，电容C1储存的能量放完，Vc1电压降为零，产生的固定值反向电流通过扼流回路流通，即通过MOS管Q2、励磁电感和二极管D1流通，Vds1电压维持在Vin。
t5～t6阶段，此阶段是两MOS管驱动的死区时间，t5时刻MOS管Q2关断，扼流回路断开，反向电流用于抽取MOS管Q1寄生电容Cds1上的电荷，Vds1电压逐渐降为0，t6时刻MOS管Q1开通，实现ZVS。
第二实施例
图4为本发明第二实施例电路原理图。相对第一实施例电路，第二实施例电路主MOS管Vds电压波形改善明显，有助于进一步改善EMI；但是由于第二实施例增加的TVS管产生损耗较大，所以对比第一实施例电路，第二实施例电路效率较低。
该实施例的连接关系如下：
电压源Vin的正端与TVS管Ds的一端相连，TVS管Ds的另一端与电容C1的一端相连，电容C1的另一端和MOS管Q2的漏极相连，MOS管Q2的源极与MOS管Q1的漏极相连，MOS管Q1的源极与电压源Vin的负端相连。TVS管Ds的阳极与变压器T的原边异名端相连，变压器T的原边同名端与MOS管Q2的源极相连，变压器T的副边同名端与二极管D2的阳极相连，二极管D2的阴极与电容C2的一端相连，电容C2的另一端与变压器T的副边异名端相连，电容C2的一端与负载电阻R的一端相连，电容C2的另一端与负载电阻R的另一端相连。
对本方案的电路进行仿真，输入电压240V，输出电压12V，输出功率30W，开关频率65kHz，电容C1为22uF，变压器励磁电感450uH，漏感18uH，匝比n为38:5，电容C2为1000uF，占空比，工作曲线如图5。MOS管Q1、Q2采用互补驱动，工作原理如下：
t0～t1阶段，MOS管Q1导通，MOS管Q2关断，输入电压Vin对变压器T激磁，副边二极管D2截止；
t1～t2阶段，此阶段是两MOS管驱动的死区时间，MOS管Q1关断，MOS管Q2通过体二极管导通，其寄生电容放电，所以，MOS管Q2可以实现ZVS，漏感能量传到电容C1中；同时漏感能量和励磁能量对MOS管Q1寄生电容充电，在本阶段后期，副边二极管D2导通，励磁能量传输到副边；
t2～t3阶段，励磁电流持续下降，励磁能量持续传输到副边，原边电容C1和TVS管Ds钳位在nVo。t3时刻励磁电流降为0，副边电流也降为0，原边钳位电压消失；
t3～t4阶段，电容C1端电压Vc1放电，产生一定值的反向电流，反向电流通过扼流回路流通，即通过电容C1、MOS管Q2、励磁电感和TVS管Ds流通。t3时刻，MOS管Q1的寄生电容放电，漏源极电压Vds1降至Vin后钳位住。
t4～t5阶段，此阶段是两MOS管驱动的死区时间，t5时刻MOS管Q2关断，扼流回路断开，反向电流用于抽取MOS管Q1寄生电容Cds1上的电荷，Vds1电压逐渐降为0，t6时刻MOS管Q1开通，实现ZVS。
第三实施例
图6为本发明第三实施例电路原理图，该实施例与第一实施例不同的是，将二极管D1替换为TVS管Ds。
该实施例的连接关系如下：
电压源Vin的正端与电容C1的一端相连，电容C1的另一端与MOS管Q2的漏极相连，MOS管Q2的源极与MOS管Q1的漏极相连，MOS管Q1的源极与电压源Vin的负端相连。电容C1的一端与TVS管Ds的阳极相连，电容C1的另一端与TVS管Ds的阴极相连，二极管D1的阳极与变压器T的原边异名端相连，变压器T的原边同名端与MOS管Q2的源极相连，变压器T的副边同名端与二极管D2的阳极相连，二极管D2的阴极与电容C2的一端相连，电容C2的另一端与变压器T的副边异名端相连，电容C2的一端与负载电阻R的一端相连，电容C2的另一端与负载电阻R的另一端相连。
该电路的工作原理与第二实施例相同，此处不再赘述。
第四实施例
图7为本发明第四实施例电路原理图，该实施例是在第二实施例的基础上增加了一只二极管D3。
该实施例的连接关系如下：
电压源Vin的正端与二极管D3的阳极相连，二极管D3的阴极与MOS管Q2的漏极相连，MOS管Q2的源极与MOS管Q1的漏极相连，MOS管Q1的源极与电压源Vin的负端相连。二极管D3的阳极与TVS管Ds的阳极相连，TVS管Ds的阴极与电容C1的一端相连，电容C1的另一端与二极管D3的阴极相连。TVS管Ds的阳极与变压器T的原边异名端相连，变压器T的原边同名端与MOS管Q2的源极相连，变压器T的副边同名端与二极管D2的阳极相连，二极管D2的阴极与电容C2的一端相连，电容C2的另一端与变压器T的副边异名端相连，电容C2的一端与负载电阻R的一端相连，电容C2的另一端与负载电阻R的另一端相连。
该电路是第一实施例和第二实施例电路整合的一种方案，主MOS管漏极与源极间电压Vds波形优化介于两个方案之间。对比第一实施例，其工作原理主要不同在于，主MOS管关断时，漏感对电容C1充电发生振荡，但由于TVS管(采用的是低压TVS管)的存在，电容C1端电压会很快趋于稳定，消除振荡。
第五实施例
图8为本发明第五实施例电路原理图。
该实施例的连接关系如下：
电压源Vin的正端与电容C1的一端相连，电容C1的另一端与电容Cc的一端相连，电容Cc的另一端与MOS管Q2的漏极相连，MOS管Q2的源极与MOS管Q1的漏极相连，MOS管Q1的源极与电压源Vin的负端相连。电容C1的一端与稳压管Dc的阳极相连，电容C1的另一端与稳压管Dc的阴极相连，稳压管Dc的阳极与变压器T的原边异名端相连，变压器T的原边同名端与MOS管Q2的源极相连，变压器T的副边同名端与二极管D2的阳极相连，二极管D2的阴极与电容C2的一端相连，电容C2的另一端与变压器T的副边异名端相连，电容C2的一端与负载电阻R的一端相连，电容C2的另一端与负载电阻R的另一端相连。
相对第三实施例电路，第五实施例电路将TVS管换成稳压管，并添加一个电容Cc来保护稳压管，防止稳压管过流烧毁。
该电路的工作原理与第三实施例类似，主要差别是，添加的电容Cc两端维持一固定值电压。
第六实施例
图9为本发明第六实施例电路原理图，该实施例是指第五实施例的基础上，增加一只电阻R1。
该实施例的连接关系如下：
电压源Vin的正端与电容C1的一端相连，电容C1的另一端与电容Cc的一端相连，电容Cc的另一端与MOS管Q2的漏极相连，MOS管Q2的源极与MOS管Q1的漏极相连，MOS管Q1的源极与电压源Vin的负端相连。电容C1的一端与稳压管Dc的阳极相连，稳压管Dc的阴极与电阻R1的一端相连，电阻R1的另一端与电容C1的另一端相连。稳压管Dc的阳极与变压器T的原边异名端相连，变压器T的原边同名端与MOS管Q2的源极相连，变压器T的副边同名端与二极 管D2的阳极相连，二极管D2的阴极与电容C2的一端相连，电容C2的另一端与变压器T的副边异名端相连，电容C2的一端与负载电阻R的一端相连，电容C2的另一端与负载电阻R的另一端相连。
该电路的工作原理与第五实施例类似，主要差别是，第五实施例在主MOS管关断，稳压管稳压不住，添加一个电阻，可以使稳压管正常稳压，主MOS管Vds电压波形优化。
以上仅是本发明优选的实施方式，本发明所属领域的技术人员还可以对上述具体实施方式进行变更和修改。比如，将二极管、TVS管、稳压管替换为其他单向导通的元器件，也同样是与本发明相同的构思。因此，本发明并不局限于上面揭示和描述的具体控制方式，对本发明的一些修改和变更也应当落入本发明的权利要求的保护范围内。此外，尽管本说明书中使用了一些特定的术语，但这些术语只是为了方便说明，并不对本发明构成任何限制。

Claims (8)

  1. 一种改进型反激变换器，包括单向导通器件、MOS管Q1、MOS管Q2、变压器和副边整流滤波电路，单向导通器件的阳极和变压器的原边绕组异名端连接电压源正端，单向导通器件的阴极连接MOS管Q2的漏极，MOS管Q2的源极连接变压器的原边绕组同名端和MOS管Q1的漏极，MOS管Q1的源极连接电压源负端；变压器的副边经过整流滤波电路后输出电压Vo；其特征在于：还包括电容C1，电容C1的一端连接单向导通器件的阳极，电容C1的另一端连接单向导通器件的阴极。
  2. 一种改进型反激变换器，包括单向导通器件、MOS管Q1、MOS管Q2、变压器和副边整流滤波电路，单向导通器件的阳极和变压器的原边绕组异名端连接电压源正端，MOS管Q2的源极连接变压器的原边绕组同名端和MOS管Q1的漏极，MOS管Q1的源极连接电压源负端；变压器的副边经过整流滤波电路后输出电压Vo；其特征在于：还包括电容C1，单向导通器件的阴极通过电容C1连接到MOS管Q2的漏极。
  3. 根据权利要求1所述的一种改进型反激变换器，其特征在于：所述的单向导通器件为二极管D1，二极管D1的阳极作为单向导通器件的阳极，二极管D1的阴极作为单向导通器件的阴极。
  4. 根据权利要求1所述的一种改进型反激变换器，其特征在于：所述的单向导通器件为TVS管，TVS管的阳极作为单向导通器件的阳极，TVS管的阴极作为单向导通器件的阴极。
  5. 根据权利要求2所述的一种改进型反激变换器，其特征在于：所述的单向导通器件为TVS管，TVS管的阳极作为单向导通器件的阳极，TVS管的阴极作为单向导通器件的阴极。
  6. 根据权利要求5所述的一种改进型反激变换器，其特征在于：还包括二极管D3，二极管D3的阳极连接TVS管的阳极，二极管D3的阴极连接MOS管Q2的漏极。
  7. 根据权利要求1所述的一种改进型反激变换器，其特征在于：所述的单向导通器件为稳压管，稳压管的阳极作为单向导通器件的阳极，稳压管的阴极 作为单向导通器件的阴极；所述的改进型反激变换器还包括电容Cc，电容Cc的一端分别连接稳压管的阴极和电容C1的另一端，电容Cc的另一端连接MOS管Q2的漏极。
  8. 根据权利要求7所述的一种改进型反激变换器，其特征在于：所述的改进型反激变换器还包括电阻R1，电阻R1的一端连接稳压管的阴极，电阻R1的另一端连接电容Cc的一端和电容C1的另一端。
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