WO2020133581A1 - 过流保护电路及显示装置 - Google Patents

过流保护电路及显示装置 Download PDF

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WO2020133581A1
WO2020133581A1 PCT/CN2019/071097 CN2019071097W WO2020133581A1 WO 2020133581 A1 WO2020133581 A1 WO 2020133581A1 CN 2019071097 W CN2019071097 W CN 2019071097W WO 2020133581 A1 WO2020133581 A1 WO 2020133581A1
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circuit
main control
output
potential
control circuit
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French (fr)
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张良
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present application relates to the field of display technology, in particular to an overcurrent protection circuit and a display device.
  • GDL Gate driverless, no gate drive liquid crystal display panels
  • the GDL circuit is composed of two parts: level shifter IC (boost integrated circuit) and shift register (shift register), level shifter IC is set on the driver board, shift register is set on the LCD panel, level shifter IC transmits CLK (Clock) The signal is given to shift to complete the driving of the liquid crystal display panel.
  • the level shifter IC is installed on the driver board so that the frame length of the LCD panel can be reduced.
  • an overcurrent protection circuit and a display device are provided.
  • the overcurrent protection circuit includes:
  • the main control circuit is respectively connected to the input terminal and the output terminal, and is configured to convert the low-potential logic signal input from the input terminal into a high-potential drive signal and output through the output terminal;
  • a current detection circuit connected between the main control circuit and the output terminal and configured to detect the output current of the output terminal
  • the delay circuit is respectively connected to the current detection circuit and the main control circuit, and is set to set a time for the current detection circuit to transmit the output current to the main control circuit;
  • the main control circuit is further configured to calculate an effective value of the output current to control whether the high-potential drive signal is output according to the effective value.
  • the delay circuit is further configured to determine whether the high-potential drive signal is level-switched according to the output current, and when the high-potential drive signal is level-switched, the delay Set a time to set the current detection circuit to transmit the output current to the main control circuit when the high-potential drive signal level switch reaches a preset time.
  • the time that the current detection circuit transmits the output current is greater than the preset time.
  • the current detection circuit includes a current detection element connected between the main control circuit and the output terminal and a current conversion element connected to the current detection element; the current conversion element is provided To detect the voltage of the current detection element and calculate the output current of the output terminal according to the voltage.
  • the current detection element is a resistor
  • the main control circuit includes a calculation element configured to calculate an effective value of the output current based on the output current.
  • the main control circuit further includes a potential boosting circuit configured to convert the low-potential logic signal input from the input terminal into a high-potential drive signal.
  • the low-level logic signal is a logic signal.
  • the high-potential driving signal is an analog signal.
  • the absolute value of the potential of the high potential drive signal is greater than the absolute value of the potential of the low potential logic signal.
  • the main control circuit further includes a controller configured to determine whether the effective value is greater than a preset effective value, and when the effective value is greater than the preset effective value, control the The high potential drive signal stops outputting.
  • the controller is further configured to modify the preset effective value.
  • the overcurrent protection circuit includes:
  • the main control circuit is respectively connected to the input terminal and the output terminal, and is configured to convert the low-potential logic signal input from the input terminal into a high-potential drive signal and output through the output terminal;
  • a current detection circuit connected between the main control circuit and the output terminal and configured to detect the output current of the output terminal
  • the delay circuit is respectively connected to the current detection circuit and the main control circuit, and is set to set a time for the current detection circuit to transmit the output current to the main control circuit;
  • the main control circuit is further configured to calculate an effective value of the output current to control whether the high-potential drive signal is output according to the effective value;
  • the delay circuit is further configured to determine whether the high-potential drive signal is level-switched according to the output current, and when the high-potential drive signal is level-switched, delay a preset time to set the The current detection circuit transmits the output current to the main control circuit when the high-potential drive signal level switch reaches a preset time.
  • a display device including a booster integrated circuit, a drive circuit board, a display panel, and a shift register; the booster integrated circuit includes the overcurrent protection circuit described above; the booster integrated circuit is provided on the A driving circuit board, the shift register is disposed on both sides of the display panel.
  • the display panel is a liquid crystal display panel.
  • the display panel includes an active array substrate, a color filter layer substrate, and a liquid crystal layer formed between the two substrates.
  • the shift register is disposed on the active array substrate.
  • the active array and the color filter layer are formed on the same substrate.
  • FIG. 1 is a schematic block diagram of an overcurrent protection circuit provided by an embodiment
  • FIG. 2 is a schematic block diagram of an overcurrent protection circuit provided by another embodiment
  • FIG. 3 is a waveform diagram of a high-potential drive signal and output current provided by an embodiment
  • FIG. 4 is a circuit diagram of a potential lifting unit provided by another embodiment
  • FIG. 5 is a waveform diagram of a low potential logic signal and a high potential drive signal provided by another embodiment
  • FIG. 6 is a schematic block diagram of a display device provided by another embodiment.
  • FIG. 1 is a functional block diagram of an overcurrent protection circuit provided by this application.
  • the overcurrent protection circuit includes a main control circuit 10, a current detection circuit 20, and a delay circuit 30.
  • the main control circuit 10 is connected to the input terminal VIN and the output terminal VOUT, respectively.
  • the main control circuit 10 is used to convert a low-level logic signal input from the input terminal VIN into a high-level drive signal and output it through the output terminal VOUT.
  • the current detection circuit 20 is connected to the main control circuit 10 and the output terminal VOUT.
  • the current detection circuit 20 is used to detect the output current of the output terminal VOUT.
  • the delay circuit 30 is connected to the current detection circuit 20 and the main control circuit 10 respectively.
  • the delay circuit 30 is used to set a time for the current detection circuit 20 to transmit the output current to the main control circuit.
  • the main control circuit 10 is also used to calculate the effective value of the output current to control whether the high-potential drive signal is output according to the effective value.
  • the low potential logic signal is a logic signal
  • the high potential drive signal is an analog signal.
  • the absolute value of the potential of the high potential drive signal is greater than the absolute value of the potential of the low potential logic signal.
  • the overcurrent protection circuit is applied to a booster integrated circuit, the output terminal VOUT is connected to a shift register provided on a display panel, and the high-potential drive signal is output to the shift register through the output terminal VOUT And drive the display panel through the shift register, and the output current is the drive current of the display panel.
  • the input terminal VIN is an input port of the overcurrent protection circuit
  • the output terminal VOUT is an output port of the overcurrent protection circuit
  • the high-potential driving signal includes high level and low level in one period, when the high-potential driving signal changes from high level to low level or from low level to high level
  • the output current of the output terminal VOUT is extremely large. If the output current of the output terminal VOUT is detected at this time and the high-potential drive signal is controlled to stop output according to the output current, the output current at that time cannot be It reflects the true state of the current output by the booster integrated circuit to the display panel, so it may cause the main control circuit 10 to make a erroneous judgment on the output current, thereby causing a false shutdown of the display panel.
  • the delay circuit 30 is also used to determine whether the high-potential drive signal is level-switched according to the output current, and when the high-potential drive signal is level-switched, delay a preset time to set the
  • the current detection circuit 20 transmits the output current to the main control circuit 10 when the high-potential drive signal level switch reaches a preset time.
  • the delay circuit 30 sets a delay preset time so that the current detection circuit 20 transmits the output current at a time to avoid the high-potential drive signal changing from high level to low level or from low level At the moment when it reaches a high level, the output current transmitted to the main control circuit 10 can better reflect the true state of the current output by the booster integrated circuit to the display panel.
  • the current detection circuit 20 transmits the output current for a time greater than the preset time. As shown in FIG.
  • the delay time set by the delay circuit 30 is T1, during which the current detection circuit 20 does not transmit the output Current to the main control circuit 10, the current detection circuit 20 transmits the currently detected output current to the main control circuit 10 within T2 time after the delay time T1 ends, where T2 is greater than T1.
  • the currently detected output current refers to the output current detected by the current detection circuit 20 in real time within T2 time.
  • the current detection circuit 20 detects the output current of the output terminal VOUT during the entire period of the high-potential drive signal, that is, the current detection circuit 20 continuously detects the output of the output terminal VOUT Current.
  • the current detection circuit 20 includes a current detection element 22 connected between the main control circuit 10 and the output terminal VOUT, and a current conversion element 21 connected to the current detection element 22.
  • the current conversion element 21 is used to detect the voltage of the current detection element 22 and calculate the output current of the output terminal according to the voltage.
  • the current detection element 22 is a resistor R.
  • the current through the resistor R that is, the current output from the output terminal VOUT, has high detection accuracy and a simple detection circuit.
  • the output current of the output terminal VOUT detected by the current detection circuit 20 is transmitted to the main control circuit 10 through the delay circuit 30.
  • the main control circuit 10 includes a calculation element 11 for calculating the effective value of the output current based on the output current transmitted by the current detection circuit 20.
  • the main control circuit 10 further includes a potential raising circuit 12 for converting a low-potential logic signal input from the input terminal VIN into a high-potential driving signal.
  • the potential boosting circuit 12 includes a first electronic switch Q1, a second electronic switch Q2, a third electronic switch Q3, a fourth electronic switch Q4, a fifth electronic switch Q5, a sixth electronic switch Q6, Electronic switch Q7 and eighth electronic switch Q8.
  • the first terminal of the first electronic switch Q1 receives the low potential signal A
  • the second terminal of the first electronic switch Q1 is connected to the first power supply VDD
  • the third terminal of the first electronic switch Q1 is connected to the first The first end of the four electronic switches Q4 is connected.
  • the first end of the second electronic switch Q2 receives the inverted signal of the low potential signal A
  • the second end of the second electronic switch Q2 is connected to the second end of the first electronic switch Q1, and the third end of the second electronic switch Q2 is connected to the first end of the third electronic switch Q3.
  • the second end of the third electronic switch Q3 is connected to the second end of the fourth electronic switch Q4 and the second power supply VGL, and the third end of the third electronic switch Q3 is also connected to the first electronic switch Q1 The third end of the connection.
  • the third terminal of the fourth electronic switch Q4 is also connected to the third terminal of the second electronic switch Q2.
  • the second end of the fifth electronic switch Q5 is connected to the third power supply VGH, and the third end of the fifth electronic switch Q5 is connected to the first end of the sixth electronic switch Q6.
  • the second end of the sixth electronic switch Q6 is connected to the second end of the fifth electronic switch Q5, and the third end of the sixth electronic switch Q6 is connected to the first end of the fifth electronic switch Q5.
  • the first end of the seventh electronic switch Q7 is connected to the third end of the second electronic switch Q2, the second end of the seventh electronic switch Q7 is connected to the second power supply VGL, and the seventh electronic switch Q7
  • the third end of is connected to the first end of the sixth electronic switch Q6.
  • the first end of the eighth electronic switch Q8 is connected to the third end of the first electronic switch Q1, and the second end of the eighth electronic switch Q8 is connected to the second end of the seventh electronic switch Q7,
  • the third terminal of the eighth electronic switch Q8 is connected to the third terminal of the sixth electronic switch Q6.
  • the signal at the first end of the third electronic switch Q3 and the signal at the first end of the fourth electronic switch Q4 are mutually inverse signals, that is, the signal at the first end of the seventh electronic switch Q7 and the signal
  • the signals at the first terminal of the eighth electronic switch Q8 are inverted signals. As shown in FIG.
  • the signals at the first terminal of the third electronic switch Q3 and the signals at the first terminal of the seventh electronic switch Q7 Is B, the signal at the first end of the fourth electronic switch Q4 and the signal at the first end of the eighth electronic switch Q8 are The third terminal of the sixth electronic switch Q6 outputs a high potential signal C.
  • the working principle of the potential boosting circuit 12 is as follows:
  • the low-potential signal A includes a low level and a high level in one cycle.
  • the first power supply VDD is a positive voltage DC power supply and the voltage is the absolute value of the high level of the low potential signal A.
  • the second power supply VGL is a negative voltage DC power supply and the absolute value of the voltage is greater than the absolute value of the low level of the low potential signal A.
  • the third power supply VGH is a positive voltage DC power supply and the voltage is greater than the voltage of the first power supply VDD.
  • the first electronic switch Q1 When the low potential signal A is at a high level, the inverted signal of the low potential signal A Low level, the first electronic switch Q1 is turned off, the second electronic switch Q2 is turned on, the third electronic switch Q3 is turned on, the seventh electronic switch Q7 is turned on, and the fourth electronic switch Q4 and the eighth electronic switch Q8 are turned off, because the seventh electronic switch Q7 is turned on, and thus the sixth electronic switch Q6 is turned on, the third terminal of the sixth electronic switch Q6 and the third power supply VGH is turned on, the third terminal of the sixth electronic switch Q6 outputs a high level and the voltage is the voltage of the third power supply VGH.
  • the inverted signal of the low potential signal A Is high, the first electronic switch Q1 is turned on, the second electronic switch Q2 is turned off, the third electronic switch Q3 is turned off, the seventh electronic switch Q7 is turned off, the fourth electronic switch Q4 and The eighth electronic switch Q8 is turned on, and because the eighth electronic switch Q8 is turned on, the third terminal of the sixth electronic switch Q6 is connected to the second power supply VGL, and the sixth terminal of the sixth electronic switch Q6 The three terminals output a low level and the voltage is the voltage of the second power supply VGL.
  • the potential boosting circuit 12 converts the input low potential signal A with a lower absolute potential value into a high potential signal C with a higher absolute potential value for output, and the sixth electronic switch Q6
  • the high level signal C output from the third terminal is the third power supply VGH
  • the low level is the second power supply VGL.
  • the potential boosting circuit 12 converts a low potential signal with a low absolute potential value into a high potential signal with a high absolute potential value, so that the high potential signal can have a sufficient voltage to drive the display panel.
  • the main control circuit 10 further includes a controller 13 for judging whether the effective value is greater than a preset effective value, and when the effective value is greater than the preset effective value, controlling the high potential drive The signal stops outputting.
  • the effective value of the output current is proportional to the heat value of the line in the display panel.
  • the effective value is greater than the preset effective value, that is, the heat value in the display panel will cause the display panel to burn out, and the controller 13 controls the high The potential drive signal stops outputting to stop driving the display panel, thereby preventing the display panel from being burned.
  • the controller 13 is also used to modify the preset effective value according to actual needs. As shown in FIG. 2, the controller 13 may set the effective value of the output current from OCP to OCP', thereby improving the protection accuracy of the overcurrent protection circuit.
  • the present application further provides a display device, which includes a boost integrated circuit 300, a driving circuit board 400, a display panel 500, and a shift register 600.
  • the GDL circuit includes a boost integrated circuit 300 and a shift register 600.
  • the booster integrated circuit 300 includes the overcurrent protection circuit.
  • the booster integrated circuit 300 is disposed on the driving circuit board 400, and the shift register 600 is disposed on both sides of the display panel 500. Since the shift register 600 occupies a small area, the GDL architecture
  • the display panel can achieve ultra-narrow bezels.
  • the display panel 500 may be, for example, a TFT-LCD (Thin Film Transistor Liquid Crystal Display) display panel, an OLED (Organic Light-Emitting Diode, organic light emitting diode) display panel, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diodes) display panels, curved display panels or other display panels.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • OLED Organic Light-Emitting Diode, organic light emitting diode
  • QLED Quantum Dot Light Emitting Diodes, quantum dot light-emitting diodes
  • the active array (TFT) and the color filter layer (CF) may be formed on the same substrate.
  • the display panel 500 is a liquid crystal display panel.
  • the display panel 500 includes an active array (TFT) substrate 501, a color filter (CF) substrate 502, and a substrate formed in two The liquid crystal layer between the substrates.
  • the shift register 600 is disposed on the active array substrate 501.
  • the above-mentioned over-current protection circuit and display device detect the output current through the current detection circuit, and set the time for the current detection circuit to transmit the output current through the delay circuit, and indirectly set the time for the current detection circuit to detect the output current, so as to drive the display panel Effective detection of current; the effective value of the output current is also calculated by the main control circuit, so as to control whether the high-potential drive signal is output according to the effective value, so as to avoid the LCD panel being burned due to excessive heat generation when the effective value is greater than the preset effective value.

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Abstract

一种过流保护电路，包括主控电路（10）、电流检测电路（20）及延时电路（30）；主控电路（10）与输入端（VIN）及输出端（VOUT）连接，用于将输入端（VIN）输入的低电位逻辑信号转换成高电位驱动信号并通过输出端（VOUT）输出；电流检测电路（20）与主控电路（10）及输出端（VOUT）连接，用于检测输出端（VOUT）的输出电流；延时电路（30）与电流检测电路（20）及主控电路（10）连接，用于设置电流检测电路（20）传输输出电流至主控电路（10）的时间；主控电路（10）还用于计算输出电流（VOUT）的有效值，以根据有效值控制高电位驱动信号是否输出。

Description

过流保护电路及显示装置
本申请要求于2018年12月27日提交中国专利局、申请号为2018116108118、申请名称为“过流保护电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别涉及一种过流保护电路及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着人们对窄边框电视的需求越来越强烈，GDL(Gate driver less，无栅极驱动)的液晶显示面板越来越受到欢迎。GDL电路由level shifter IC(升压集成电路)和shift register(移位寄存器)两部分组成，level shifter IC设置于驱动板上，shift register设置于液晶显示面板上，level shifter IC传输CLK(Clock)信号给shift register完成对液晶显示面板的驱动。level shifter IC设置于驱动板使得液晶显示面板的边框长度可以减小。
液晶显示面板在工作中由于制造工艺的缺陷，可能会出现驱动电流过大的现象，而现有的GDL电路缺乏对液晶显示面板的驱动电流的有效检测，液晶显示面板容易因驱动电流过大导致发热量过大而烧毁。
发明内容
根据本申请的各种实施例，提供一种过流保护电路及显示装置。
一种过流保护电路，所述过流保护电路包括：
主控电路，分别与输入端及输出端连接，设置为将所述输入端输入的低电位逻辑信号转换成高电位驱动信号并通过所述输出端输出；
电流检测电路，连接于所述主控电路与所述输出端之间，设置为检测所述输出端的输出电流；以及
延时电路，分别与所述电流检测电路及所述主控电路连接，设置为设置所述电流检测电路传输所述输出电流至所述主控电路的时间；
所述主控电路还设置为计算所述输出电流的有效值，以根据所述有效值控制所述高电位驱动信号是否输出。
在其中一个实施例中，所述延时电路还设置为根据所述输出电流判断所述高电位驱动信号是否发生电平切换，并当所述高电位驱动信号发生电平切换时，延时预设时间，以设置所述电流检测电路在所述高电位驱动信号发生电平切换达到预设时间再传输所述输出电流至所述主控电路。
在其中一个实施例中，在所述高电位驱动信号的一个周期内，所述电流检测电路传输所述输出电流的时间大于所述预设时间。
在其中一个实施例中，所述电流检测电路包括连接于所述主控电路与所述输出端之间的电流检测元件及与所述电流检测元件连接的电流转换元件；所述电流转换元件设置为检测所述电流检测元件的电压并根据所述电压计算所述输出端的输出电流。
在其中一个实施例中，所述电流检测元件为电阻。
在其中一个实施例中，所述主控电路包括计算元件，所述计算元件设置为根据所述输出电流计算输出电流的有效值。
在其中一个实施例中，所述主控电路还包括电位提升电路，所述电位提 升电路设置为将所述输入端输入的低电位逻辑信号转换成高电位驱动信号。
在其中一个实施例中，所述低电位逻辑信号为逻辑信号。
在其中一个实施例中，所述高电位驱动信号为模拟信号。
在其中一个实施例中，所述高电位驱动信号的电位绝对值大于所述低电位逻辑信号的电位绝对值。
在其中一个实施例中，所述主控电路还包括控制器，所述控制器设置为判断所述有效值是否大于预设有效值，并当所述有效值大于预设有效值时，控制所述高电位驱动信号停止输出。
在其中一个实施例中，所述控制器还设置为修改所述预设有效值。
一种过流保护电路，所述过流保护电路包括：
主控电路，分别与输入端及输出端连接，设置为将所述输入端输入的低电位逻辑信号转换成高电位驱动信号并通过所述输出端输出；
电流检测电路，连接于所述主控电路与所述输出端之间，设置为检测所述输出端的输出电流；以及
延时电路，分别与所述电流检测电路及所述主控电路连接，设置为设置所述电流检测电路传输所述输出电流至所述主控电路的时间；
所述主控电路还设置为计算所述输出电流的有效值，以根据所述有效值控制所述高电位驱动信号是否输出；
所述延时电路还设置为根据所述输出电流判断所述高电位驱动信号是否发生电平切换，并当所述高电位驱动信号发生电平切换时，延时预设时间，以设置所述电流检测电路在所述高电位驱动信号发生电平切换达到预设时间再传输所述输出电流至所述主控电路。
一种显示装置，所述显示装置包括升压集成电路、驱动电路板、显示面 板及移位寄存器；所述升压集成电路包括上述的过流保护电路；所述升压集成电路设置于所述驱动电路板，所述移位寄存器设置于所述显示面板的两侧。
在其中一个实施例中，所述显示面板为液晶显示面板。
在其中一个实施例中，所述显示面板包括主动阵列基板、彩色滤光层基板与形成于两基板之间的液晶层。
在其中一个实施例中，所述移位寄存器设置于所述主动阵列基板上。
在其中一个实施例中，主动阵列及彩色滤光层形成于同一基板上。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一个实施例提供的过流保护电路的原理框图；
图2为另一个实施例提供的过流保护电路的原理框图；
图3为一个实施例提供的高电位驱动信号和输出电流的波形图；
图4为另一个实施例提供的电位提升单元的电路图；
图5为另一个实施例提供的低电位逻辑信号和高电位驱动信号的波形图；
图6为另一个实施例提供的显示装置的原理框图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。
下面结合附图，对本申请的具体实施方式进行详细描述。
请参阅图1，图1为本申请提供的过流保护电路的原理框图。所述过流保护电路包括主控电路10、电流检测电路20及延时电路30。
所述主控电路10分别与输入端VIN及输出端VOUT连接。所述主控电路10用于将所述输入端VIN输入的低电位逻辑信号转换成高电位驱动信号并通过所述输出端VOUT输出。
所述电流检测电路20与所述主控电路10及所述输出端VOUT连接。所述电流检测电路20用于检测所述输出端VOUT的输出电流。
所述延时电路30分别与所述电流检测电路20及所述主控电路10连接。所述延时电路30用于设置所述电流检测电路20传输所述输出电流至所述主控电路的时间。
所述主控电路10还用于计算所述输出电流的有效值，以根据所述有效值控制所述高电位驱动信号是否输出。
所述低电位逻辑信号为逻辑信号，所述高电位驱动信号为模拟信号。所述高电位驱动信号的电位绝对值大于所述低电位逻辑信号的电位绝对值。所述过流保护电路应用于升压集成电路中，所述输出端VOUT与设置于显示面板上的移位寄存器连接，所述高电位驱动信号通过所述输出端VOUT输出至所述移位寄存器，并通过所述移位寄存器驱动显示面板，所述输出电流即显示面板的驱动电流。
需要说明的是，所述输入端VIN为所述过流保护电路的输入端口，所述输出端VOUT为所述过流保护电路的输出端口。
请参阅图3，所述高电位驱动信号在一个周期内包括高电平及低电平，当所述高电位驱动信号由高电平转换至低电平或由低电平转换至高电平的瞬间，所述输出端VOUT的输出电流极大，若此时检测所述输出端VOUT的输出电流并根据所述输出电流控制所述高电位驱动信号停止输出，因此时的所述输出电流并不能反映所述升压集成电路输出至显示面板的电流的真实状态，因此会引起所述主控电路10对所述输出电流的误判断，从而引起显示面板的误关机。
所述延时电路30还用于根据所述输出电流判断所述高电位驱动信号是否发生电平切换，并当所述高电位驱动信号发生电平切换时，延时预设时间，以设置所述电流检测电路20在所述高电位驱动信号发生电平切换达到预设时间再传输所述输出电流至所述主控电路10。
所述延时电路30通过设置延时预设时间使得所述电流检测电路20传输所述输出电流的时间避开所述高电位驱动信号由高电平转换至低电平或由低 电平转换至高电平的瞬间，进而传输至所述主控电路10的输出电流更能反映所述升压集成电路输出至显示面板的电流的真实状态。在所述高电位驱动信号的一个周期内，所述电流检测电路20传输所述输出电流的时间大于所述预设时间。如图3所示，所述高电位驱动信号由高电平转换至低电平时，所述延时电路30设置的延时时间为T1，在此期间所述电流检测电路20不传输所述输出电流至所述主控电路10，所述电流检测电路20在延时时间T1结束后的T2时间内传输当前检测到的输出电流至所述主控电路10，其中，T2大于T1。当前检测到的输出电流是指所述电流检测电路20在T2时间内实时检测到的输出电流。
需要说明的是，所述电流检测电路20在所述高电位驱动信号的整个周期内均检测所述输出端VOUT的输出电流，也即所述电流检测电路20持续检测所述输出端VOUT的输出电流。
所述电流检测电路20包括连接于所述主控电路10与所述输出端VOUT之间的电流检测元件22及与所述电流检测元件22连接的电流转换元件21。所述电流转换元件21用于检测所述电流检测元件22的电压并根据所述电压计算所述输出端的输出电流。
在一实施例中，所述电流检测元件22为电阻R。
通过检测电阻R两端的电压，进而根据欧姆定律计算通过电阻R的电流，通过电阻R的电流即所述输出端VOUT输出的电流，检测精度高，检测电路简单。
可以理解的，所述电流检测电路20检测到的所述输出端VOUT的输出电流通过所述延时电路30传输至所述主控电路10。
所述主控电路10包括计算元件11，所述计算元件11用于根据所述电流 检测电路20传输的输出电流计算输出电流的有效值。所述电流检测电路20将在T2时间内检测到的所述输出端VOUT的输出电流传输至所述计算元件11，所述计算元件11根据T2时间内的若干个输出电流计算输出电流的有效值。若所述电流检测电路20检测到的若干个输出电流为I1、I2、…、In，则所述输出电流的有效值为Irms＝﹛[(I1)^2+(I2)^2+…+(In)^2]/n﹜^(1/2)。
所述主控电路10还包括电位提升电路12，所述电位提升电路12用于将所述输入端VIN输入的低电位逻辑信号转换成高电位驱动信号。
请参阅图4，所述电位提升电路12包括第一电子开关Q1、第二电子开关Q2、第三电子开关Q3、第四电子开关Q4、第五电子开关Q5、第六电子开关Q6、第七电子开关Q7及第八电子开关Q8。所述第一电子开关Q1的第一端接收低电位信号A，所述第一电子开关Q1的第二端与第一电源VDD连接，所述第一电子开关Q1的第三端与所述第四电子开关Q4的第一端连接。所述第二电子开关Q2的第一端接收所述低电位信号A的反相信号
Figure PCTCN2019071097-appb-000001
所述第二电子开关Q2的第二端与所述第一电子开关Q1的第二端连接，所述第二电子开关Q2的第三端与所述第三电子开关Q3的第一端连接。所述第三电子开关Q3的第二端与所述第四电子开关Q4的第二端及第二电源VGL连接，所述第三电子开关Q3的第三端还与所述第一电子开关Q1的第三端连接。所述第四电子开关Q4的第三端还与所述第二电子开关Q2的第三端连接。所述第五电子开关Q5的第二端与第三电源VGH连接，所述第五电子开关Q5的第三端与所述第六电子开关Q6的第一端连接。所述第六电子开关Q6的第二端与所述第五电子开关Q5的第二端连接，所述第六电子开关Q6的第三端与所述第五电子开关Q5的第一端连接。所述第七电子开关Q7的第一端与所述第二电子开关Q2的第三端连接，所述第七电子开关Q7的第二端与第二电源 VGL连接，所述第七电子开关Q7的第三端与所述第六电子开关Q6的第一端连接。所述第八电子开关Q8的第一端与所述第一电子开关Q1的第三端连接，所述第八电子开关Q8的第二端与所述第七电子开关Q7的第二端连接，所述第八电子开关Q8的第三端与所述第六电子开关Q6的第三端连接。所述第三电子开关Q3的第一端的信号与所述第四电子开关Q4的第一端的信号互为反相信号，即所述第七电子开关Q7的第一端的信号与所述第八电子开关Q8的第一端的信号互为反相信号，如图4所示，所述第三电子开关Q3的第一端的信号及所述第七电子开关Q7的第一端的信号为B，所述第四电子开关Q4的第一端的信号及所述第八电子开关Q8的第一端的信号为
Figure PCTCN2019071097-appb-000002
所述第六电子开关Q6的第三端输出高电位信号C。
所述电位提升电路12的工作原理如下：
所述低电位信号A在一个周期内包括低电平及高电平。所述第一电源VDD为正电压直流电源且电压为所述低电位信号A的高电平的绝对值。所述第二电源VGL为负电压直流电源且电压的绝对值大于所述低电位信号A的低电平的绝对值。所述第三电源VGH为正电压直流电源且电压大于所述第一电源VDD的电压。
当所述低电位信号A为高电平时，所述低电位信号A的反相信号
Figure PCTCN2019071097-appb-000003
为低电平，所述第一电子开关Q1截止，所述第二电子开关Q2导通，所述第三电子开关Q3导通，所述第七电子开关Q7导通，所述第四电子开关Q4及所述第八电子开关Q8截止，由于所述第七电子开关Q7导通，进而所述第六电子开关Q6导通，所述第六电子开关Q6的第三端与所述第三电源VGH导通，所述第六电子开关Q6的第三端输出高电平且电压为所述第三电源VGH的电压。
当所述低电位信号A为低电平时，所述低电位信号A的反相信号
Figure PCTCN2019071097-appb-000004
为高电平，所述第一电子开关Q1导通，所述第二电子开关Q2截止，所述第三电子开关Q3截止，所述第七电子开关Q7截止，所述第四电子开关Q4及所述第八电子开关Q8导通，由于所述第八电子开关Q8导通，所述第六电子开关Q6的第三端与所述第二电源VGL连接，所述第六电子开关Q6的第三端输出低电平且电压为所述第二电源VGL的电压。
综上所述，请参阅图5，所述电位提升电路12将输入的电位绝对值较低的低电位信号A转换成电位绝对值较高的高电位信号C输出，所述第六电子开关Q6的第三端输出的高电位信号C的高电平为所述第三电源VGH，低电平为所述第二电源VGL。所述电位提升电路12将电位绝对值较低的低电位信号转换成电位绝对值较高的高电位信号，使得所述高电位信号能够有足够的电压驱动显示面板。
所述主控电路10还包括控制器13，所述控制器13用于判断所述有效值是否大于预设有效值，并当所述有效值大于预设有效值时，控制所述高电位驱动信号停止输出。所述输出电流的有效值与显示面板内的线路的发热量成正比，所述有效值大于预设有效值即显示面板内的发热量会引起显示面板烧毁，所述控制器13控制所述高电位驱动信号停止输出，以停止驱动显示面板，从而避免显示面板烧毁。
所述控制器13还用于根据实际需要修改所述预设有效值。如图2所示，所述控制器13可以将输出电流的有效值由OCP设置为OCP’，从而提高所述过流保护电路的保护精度。
请参阅图6，本申请还提供一种显示装置，所述显示装置包括升压集成电路300、驱动电路板400、显示面板500及移位寄存器600。
GDL电路包括升压集成电路300及移位寄存器600。所述升压集成电路300包括所述过流保护电路。所述升压集成电路300设置于所述驱动电路板400，所述移位寄存器600设置于所述显示面板500的两侧，由于所述移位寄存器600占的面积很小，因此，GDL架构的显示面板可以做到超窄的边框。
本申请中，显示面板500可例如为TFT-LCD(Thin Film Transistor Liquid Crystal Displayer，薄膜晶体管液晶显示器)显示面板、OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)显示面板、曲面显示面板或其他显示面板。
在一实施例中，所述主动阵列(TFT)及所述彩色滤光层(CF)可形成于同一基板上。
在一实施例中，所述显示面板500为液晶显示面板，所述显示面板500包括主动阵列(thin film transistor，TFT)基板501、彩色滤光层(color filter，CF)基板502与形成于两基板之间的液晶层。所述移位寄存器600设置于所述主动阵列基板501上。
上述的过流保护电路及显示装置，通过电流检测电路检测输出电流，并通过延时电路设置电流检测电路传输输出电流的时间，进而间接设置电流检测电路检测输出电流的时间，达到对显示面板驱动电流的有效检测；还通过主控电路计算输出电流的有效值，从而根据有效值控制高电位驱动信号是否输出，避免有效值大于预设有效值时，液晶显示面板因发热量过大而烧毁。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种过流保护电路，所述过流保护电路包括：
    主控电路，分别与输入端及输出端连接，设置为将所述输入端输入的低电位逻辑信号转换成高电位驱动信号并通过所述输出端输出；
    电流检测电路，连接于所述主控电路与所述输出端之间，设置为检测所述输出端的输出电流；以及
    延时电路，分别与所述电流检测电路及所述主控电路连接，设置为设置所述电流检测电路传输所述输出电流至所述主控电路的时间；
    所述主控电路还设置为计算所述输出电流的有效值，以根据所述有效值控制所述高电位驱动信号是否输出。
  2. 根据权利要求1所述的过流保护电路，其中，所述延时电路还设置为根据所述输出电流判断所述高电位驱动信号是否发生电平切换，并当所述高电位驱动信号发生电平切换时，延时预设时间，以设置所述电流检测电路在所述高电位驱动信号发生电平切换达到预设时间再传输所述输出电流至所述主控电路。
  3. 根据权利要求2所述的过流保护电路，其中，在所述高电位驱动信号的一个周期内，所述电流检测电路传输所述输出电流的时间大于所述预设时间。
  4. 根据权利要求1所述的过流保护电路，其中，所述电流检测电路包括连接于所述主控电路与所述输出端之间的电流检测元件及与所述电流检测元件连接的电流转换元件；所述电流转换元件设置为检测所述电流检测元件的电压并根据所述电压计算所述输出端的输出电流。
  5. 根据权利要求4所述的过流保护电路，其中，所述电流检测元件为电 阻。
  6. 根据权利要求1所述的过流保护电路，其中，所述主控电路包括计算元件，所述计算元件设置为根据所述输出电流计算输出电流的有效值。
  7. 根据权利要求1所述的过流保护电路，其中，所述主控电路还包括电位提升电路，所述电位提升电路设置为将所述输入端输入的低电位逻辑信号转换成高电位驱动信号。
  8. 根据权利要求1所述的过流保护电路，其中，所述低电位逻辑信号为逻辑信号。
  9. 根据权利要求1所述的过流保护电路，其中，所述高电位驱动信号为模拟信号。
  10. 根据权利要求7所述的过流保护电路，其中，所述高电位驱动信号的电位绝对值大于所述低电位逻辑信号的电位绝对值。
  11. 根据权利要求1所述的过流保护电路，其中，所述主控电路还包括控制器，所述控制器设置为判断所述有效值是否大于预设有效值，并当所述有效值大于预设有效值时，控制所述高电位驱动信号停止输出。
  12. 根据权利要求11所述的过流保护电路，其中，所述控制器还设置为修改所述预设有效值。
  13. 一种过流保护电路，所述过流保护电路包括：
    主控电路，分别与输入端及输出端连接，设置为将所述输入端输入的低电位逻辑信号转换成高电位驱动信号并通过所述输出端输出；
    电流检测电路，连接于所述主控电路与所述输出端之间，设置为检测所述输出端的输出电流；以及
    延时电路，分别与所述电流检测电路及所述主控电路连接，设置为设置 所述电流检测电路传输所述输出电流至所述主控电路的时间；
    所述主控电路还设置为计算所述输出电流的有效值，以根据所述有效值控制所述高电位驱动信号是否输出；
    所述延时电路还设置为根据所述输出电流判断所述高电位驱动信号是否发生电平切换，并当所述高电位驱动信号发生电平切换时，延时预设时间，以设置所述电流检测电路在所述高电位驱动信号发生电平切换达到预设时间再传输所述输出电流至所述主控电路。
  14. 一种显示装置，所述显示装置包括升压集成电路、驱动电路板、显示面板及移位寄存器；所述升压集成电路包括过流保护电路，所述过流保护电路包括主控电路、电流检测电路及延时电路；所述主控电路分别与输入端及输出端连接，设置为将所述输入端输入的低电位逻辑信号转换成高电位驱动信号并通过所述输出端输出；所述电流检测电路连接于所述主控电路与所述输出端之间，设置为检测所述输出端的输出电流；所述延时电路分别与所述电流检测电路及所述主控电路连接，设置为设置所述电流检测电路传输所述输出电流至所述主控电路的时间；所述主控电路还设置为计算所述输出电流的有效值，以根据所述有效值控制所述高电位驱动信号是否输出；所述升压集成电路设置于所述驱动电路板，所述移位寄存器设置于所述显示面板的两侧。
  15. 根据权利要求14所述的显示装置，其中，所述显示面板为液晶显示面板。
  16. 根据权利要求15所述的显示装置，其中，所述显示面板包括主动阵列基板、彩色滤光层基板与形成于两基板之间的液晶层。
  17. 根据权利要求16所述的显示装置，其中，所述移位寄存器设置于所 述主动阵列基板上。
  18. 根据权利要求15所述的显示装置，其中，主动阵列及彩色滤光层形成于同一基板上。
PCT/CN2019/071097 2018-12-27 2019-01-10 过流保护电路及显示装置 Ceased WO2020133581A1 (zh)

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