WO2020103725A1 - 差分输入电路及放大电路、显示装置 - Google Patents

差分输入电路及放大电路、显示装置

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Publication number
WO2020103725A1
WO2020103725A1 PCT/CN2019/117509 CN2019117509W WO2020103725A1 WO 2020103725 A1 WO2020103725 A1 WO 2020103725A1 CN 2019117509 W CN2019117509 W CN 2019117509W WO 2020103725 A1 WO2020103725 A1 WO 2020103725A1
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WIPO (PCT)
Prior art keywords
transistor
terminal
signal
output
sub
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Application number
PCT/CN2019/117509
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English (en)
French (fr)
Inventor
王糖祥
Original Assignee
京东方科技集团股份有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/771,289 priority Critical patent/US11005428B2/en
Publication of WO2020103725A1 publication Critical patent/WO2020103725A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45542—Indexing scheme relating to differential amplifiers the IC comprising bias stabilisation means, e.g. DC level stabilisation, and temperature coefficient dependent control, e.g. by DC level shifting

Definitions

  • the present disclosure relates to the technical field of analog circuits, and in particular, to a differential input circuit, an amplifier circuit, and a display device.
  • the transconductance of the differential input circuit is related to the differential input voltage.
  • a plurality of transistors are used in a differential input circuit with a constant transconductance, and these transistors are controlled by different control signals.
  • the purpose of the present disclosure is to provide a differential input circuit, an amplifier circuit, and a display device.
  • a differential input circuit including:
  • a first power supply sub-circuit for outputting a first signal, a second signal and a third signal under the control of the first bias signal, the third signal is transmitted to the first node;
  • a second power supply sub-circuit connected to the first power supply sub-circuit, receiving the first signal, and outputting a fourth signal and a fifth signal, the fifth signal is transmitted to the second node;
  • the first shunt subcircuit connects the fourth signal output terminal, the differential input signal terminal and the first node that output the fourth signal, and is used for transmitting the fourth signal to the first node under the control of the differential input signal of the differential input signal terminal ;
  • a second shunt sub-circuit connected to the second signal output terminal, the differential input signal terminal and the second node that output the second signal, for transmitting the second signal to the second node under the control of the differential input signal of the differential input signal terminal ;
  • the first output sub-circuit is connected to the differential input signal terminal, the first node and the differential output terminal, and is used to output the first output signal under the control of the differential input signal at the differential input signal terminal;
  • the second sub-circuit output connected to the differential input signal terminal and a differential output node for outputting a second output signal to control the differential input signal at input terminal of the differential input signal.
  • the first power sub-circuit includes:
  • the first transistor the first end is connected to the first power supply end, the control end is connected to the first bias signal end, and the second end is connected to the second power supply sub-circuit;
  • the second transistor the first end is connected to the first power supply end, the control end is connected to the first bias signal end, and the second end is connected to the second shunt subcircuit;
  • the third transistor has a first terminal connected to the first power terminal, a control terminal connected to the first bias signal terminal, and a second terminal connected to the first output sub-circuit.
  • the aspect ratio of the first transistor, the second transistor, and the third transistor is 4: 3: 4.
  • the second power sub-circuit includes:
  • a fourth transistor, the first terminal and the control terminal receive the first signal, and the second terminal is connected to the second power terminal;
  • a fifth transistor the first end is connected to the first shunt circuit, the control end is connected to the first signal end, and the second end is connected to the second power supply end;
  • the sixth transistor has a first terminal connected to the second output sub-circuit, a control terminal connected to the first signal terminal, and a second terminal connected to the second power terminal.
  • the aspect ratio of the fourth transistor, the fifth transistor, and the sixth transistor is 4: 3: 4.
  • the first transistor, the second transistor, and the third transistor are P-type metal oxide semiconductor field effect transistors, and the fourth transistor, fifth transistor, and sixth transistor are N-type metal oxides Semiconductor field effect transistor;
  • the first transistor, the second transistor, and the third transistor are N-type metal oxide semiconductor field effect transistors, and the four transistors, the fifth transistor, and the sixth transistor are P-type metal oxide semiconductor field effect transistors.
  • the differential input signal includes a first sub-differential signal and a second sub-differential signal
  • the first output signal includes a first output positive signal and a first output negative signal
  • the second output The signal includes a second output positive signal and a second output negative signal
  • the first output sub-circuit includes:
  • the first differential transistor pair includes:
  • a seventh transistor the first terminal is connected to the first node, the control terminal is connected to the first sub-differential signal, and the second terminal outputs the first output positive signal;
  • An eighth transistor the first terminal is connected to the first node, the control terminal is connected to the second sub-differential signal, and the second terminal outputs the first output negative signal;
  • the second output sub-circuit includes:
  • the second differential transistor pair includes:
  • a ninth transistor the first terminal is connected to the second node, the control terminal is connected to the first sub-differential signal, and the second terminal outputs the second output positive signal;
  • the first terminal is connected to the second node
  • the control terminal is connected to the second sub-differential signal
  • the second terminal outputs the second output negative signal.
  • the first shunt sub-circuit includes
  • the third differential transistor pair includes:
  • the first terminal is connected to the fourth signal output terminal, the control terminal is connected to the first sub-differential signal, and the second terminal is connected to the first node;
  • a twelfth transistor the first terminal is connected to the fourth signal output terminal, the control terminal is connected to the second sub-differential signal, and the second terminal is connected to the first node;
  • the second shunt sub-circuit includes
  • the fourth differential transistor pair includes:
  • the first terminal is connected to the second signal output terminal, the control terminal is connected to the first sub-differential signal, and the second terminal is connected to the second node;
  • the first terminal is connected to the second signal output terminal
  • the control terminal is connected to the second sub-differential signal
  • the second terminal is connected to the second node.
  • the seventh transistor, the eighth transistor, the thirteenth transistor, and the fourteenth transistor are P-type metal oxide semiconductor field effect transistors, and the ninth transistor, tenth transistor, tenth transistor One transistor and the twelfth transistor are N-type metal oxide semiconductor field effect transistors;
  • the seventh transistor, the eighth transistor, the thirteenth transistor and the fourteenth transistor are N-type metal oxide semiconductor field effect transistors, and the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor It is a P-type metal oxide semiconductor field effect transistor.
  • the second power supply sub-circuit is a current mirror power supply, and can output the same current signal as the first power supply sub-circuit.
  • the first power sub-circuit includes: a first transistor, a first terminal connected to the first power terminal, a control terminal connected to the first bias signal terminal, and a second terminal connected to the second power sub circuit;
  • the second transistor the first end is connected to the first power supply terminal, the control end is connected to the first bias signal terminal, the second end is connected to the second shunt subcircuit;
  • the third transistor the first end is connected to the first power supply terminal, and the control end is connected to the first A bias signal terminal, the second terminal is connected to the first output sub-circuit,
  • the second power sub-circuit includes: a fourth transistor, a first terminal and a control terminal receive the first signal, the second terminal is connected to the second power terminal; a fifth transistor, the first terminal is connected to the first shunt sub-circuit, control The terminal is connected to the first signal terminal, the second terminal is connected to the second power terminal; the sixth transistor, the first terminal is connected to the second output sub-circuit, the control terminal is connected to the first signal terminal, and the second terminal is connected to the second power terminal,
  • the first differential transistor pair of the first output sub-circuit includes a seventh transistor, a first terminal is connected to the first node, a control terminal is connected to the first sub-differential signal, and a second terminal outputs the first output signal; An eighth transistor, the first terminal is connected to the first node, the control terminal is connected to the second sub-differential signal, and the second terminal outputs the first output signal,
  • the second output sub-circuit includes a second differential transistor pair, including: a ninth transistor, a first terminal connected to the second node, a control terminal connected to the first sub-differential signal, and a second terminal to output the second output signal A tenth transistor, the first end is connected to the second node, the control end is connected to the second sub-differential signal, and the second end outputs the second output signal,
  • the first shunt sub-circuit includes a third differential transistor pair, including: an eleventh transistor, a first terminal connected to the fourth signal output terminal, a control terminal connected to the first sub-differential signal, and a second terminal connected to the first node; In a twelfth transistor, the first terminal is connected to the fourth signal output terminal, the control terminal is connected to the second sub-differential signal, and the second terminal is connected to the first node,
  • the second shunt sub-circuit includes a fourth differential transistor pair, including: a thirteenth transistor, a first terminal connected to the second signal output terminal, a control terminal connected to the first sub-differential signal, and a second terminal connected to the second node; In the fourteenth transistor, the first terminal is connected to the second signal output terminal, the control terminal is connected to the second sub-differential signal, and the second terminal is connected to the second node.
  • the first transistor, second transistor, third transistor, seventh transistor, eighth transistor, thirteenth transistor, and fourteenth transistor are P-type metal oxide semiconductor field effect transistors
  • the fourth transistor, fifth transistor, sixth transistor, ninth transistor, tenth transistor, eleventh transistor and twelfth transistor are N-type metal oxide semiconductor field effect transistors
  • the first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the thirteenth transistor and the fourteenth transistor are N-type metal oxide semiconductor field effect transistors, and the four transistors and the fifth transistor
  • the transistor, sixth transistor, ninth transistor, tenth transistor, eleventh transistor and twelfth transistor are P-type metal oxide semiconductor field effect transistors.
  • an amplifier circuit including the above-mentioned differential input circuit.
  • a display device including the above-mentioned amplifier circuit.
  • a driving method of a differential input circuit for driving a differential input circuit comprising:
  • the first shunt module, the second shunt module, the first output module and the second output module are controlled by the differential input signal, so that when the differential input signal changes, the transconductance of the differential input circuit is constant.
  • the first power sub-circuit includes: a first transistor, a first terminal connected to the first power terminal, a control terminal connected to the first bias signal terminal, and a second terminal connected to the second power sub circuit;
  • the second transistor the first end is connected to the first power supply terminal, the control end is connected to the first bias signal terminal, the second end is connected to the second shunt subcircuit;
  • the third transistor the first end is connected to the first power supply terminal, the control end is connected to the first A bias signal terminal, the second terminal is connected to the first output sub-circuit,
  • the second power sub-circuit includes: a fourth transistor, a first terminal and a control terminal receive the first signal, the second terminal is connected to the second power terminal; a fifth transistor, the first terminal is connected to the first shunt sub-circuit, control The terminal is connected to the first signal terminal, the second terminal is connected to the second power terminal; the sixth transistor, the first terminal is connected to the second output sub-circuit, the control terminal is connected to the first signal terminal, and the second terminal is connected to the second power terminal,
  • the first differential transistor pair of the first output sub-circuit includes a seventh transistor, a first terminal is connected to the first node, a control terminal is connected to the first sub-differential signal, and a second terminal outputs the first output signal; An eighth transistor, the first terminal is connected to the first node, the control terminal is connected to the second sub-differential signal, and the second terminal outputs the first output signal,
  • the second output sub-circuit includes a second differential transistor pair, including: a ninth transistor, a first terminal connected to the second node, a control terminal connected to the first sub-differential signal, and a second terminal to output the second output signal A tenth transistor, the first end is connected to the second node, the control end is connected to the second sub-differential signal, and the second end outputs the second output signal,
  • the first shunt sub-circuit includes a third differential transistor pair, including: an eleventh transistor, a first terminal connected to the fourth signal output terminal, a control terminal connected to the first sub-differential signal, and a second terminal connected to the first node; In a twelfth transistor, the first terminal is connected to the fourth signal output terminal, the control terminal is connected to the second sub-differential signal, and the second terminal is connected to the first node,
  • the second shunt sub-circuit includes a fourth differential transistor pair, including: a thirteenth transistor, a first terminal connected to the second signal output terminal, a control terminal connected to the first sub-differential signal, and a second terminal connected to the second node; In the fourteenth transistor, the first terminal is connected to the second signal output terminal, the control terminal is connected to the second sub-differential signal, and the second terminal is connected to the second node,
  • the first transistor, second transistor, third transistor, seventh transistor, eighth transistor, thirteenth transistor, and fourteenth transistor are P-type metal oxide semiconductor field effect transistors
  • the fourth transistor, fifth The transistor, sixth transistor, ninth transistor, tenth transistor, eleventh transistor and twelfth transistor are N-type metal oxide semiconductor field effect transistors
  • the first transistor, the second transistor, the third transistor, the seventh transistor, the eighth transistor, the thirteenth transistor and the fourteenth transistor are N-type metal oxide semiconductor field effect transistors, and the four transistors and the fifth transistor
  • the transistor, sixth transistor, ninth transistor, tenth transistor, eleventh transistor and twelfth transistor are P-type metal oxide semiconductor field effect transistors
  • the method also includes:
  • the N-type metal oxide semiconductor field effect transistor When the voltage of the differential input signal is low and the current output by the first transistor T1 under the control of the first bias signal is 8I, the N-type metal oxide semiconductor field effect transistor is turned off, and the P-type metal oxide semiconductor The field effect transistor is turned on and is in the saturation region. At this time, the transconductance of the differential input circuit is
  • the N-type metal oxide semiconductor field effect transistor When the voltage of the differential input signal is high and the current output by the first transistor T1 under the control of the first bias signal is 8I, the N-type metal oxide semiconductor field effect transistor is turned on and is in the saturation region, P-type The metal oxide semiconductor field effect transistor is turned off, and the transconductance of the differential input circuit is
  • the N-type metal oxide semiconductor field effect transistor is turned on and is in the saturation region
  • P-type The metal-oxide-semiconductor field-effect transistor is turned on and is in the saturation region.
  • Kp and Kn are the transconductance coefficients of the P-type metal oxide semiconductor field effect transistor and the N-type metal oxide semiconductor field effect transistor, respectively, and I is the reference value representing the output current of the transistor.
  • the low level indicates that the differential input voltage is between 0 and Vthn + VB;
  • the intermediate level indicates that the differential input voltage ranges from Vthn + VB to VA +
  • the high level indicates that the differential input voltage is between VA +
  • Vthn represents the threshold voltage of the N-type metal oxide semiconductor field effect transistor
  • Vthp represents the threshold voltage of the P-type metal oxide semiconductor field effect transistor
  • VA represents the level of the first node
  • VB represents the level of the second node
  • VDD represents the level of the first power supply terminal.
  • FIG. 1 is a schematic diagram of a differential output circuit with constant transconductance provided in a comparative example of the present disclosure
  • FIG. 2 is a schematic diagram of a differential input circuit provided by an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another differential input circuit provided by an exemplary embodiment of the present disclosure.
  • FIG. 4 is a schematic flowchart of a method for driving a differential input circuit according to an exemplary embodiment of the present disclosure.
  • a constant transconductance circuit is to make the transconductance constant under different input voltages by changing the tail current of the input pair tube.
  • M1 and M0 are NMOS (N-type metal oxide Semiconductor field effect transistor) differential input pair
  • M7 and M8 are PMOS (P-type metal oxide semiconductor field effect transistor) differential input pairs
  • M4 and M9 are their current sources, adjust the circuit parameters to make the tail current equal.
  • M5 and M6 are switch tubes, the gate voltages of which are Vb2 and Vb1, M2 and M3, M9 and M10 respectively form a 3 times current mirror, and the leakage current of M5 and M6 is amplified by 3 times through the switch control NMOS differential input pair and Source electrode of PMOS (P-type metal oxide semiconductor field effect transistor) differential input pair.
  • PMOS P-type metal oxide semiconductor field effect transistor
  • the input voltage is in the range of rail-to-rail
  • the micro current of the changed PMOS differential input pair and NMOS differential input pair changes its drain current to change its transconductance
  • VA and VB are A node
  • the voltage of node B, Vthn and Vthp are the threshold voltage of NMOS and PMOS differential input pair respectively
  • Itail refers to the tail current.
  • the NMOS differential input pair When the differential input voltage is between 0 and Vthn + VB, the NMOS differential input pair is cut off because Vgs is lower than Vthn, and the PMOS differential input pair is in the saturation region.
  • the total input transconductance is:
  • the PMOS differential input pair When the differential input voltage is between VA +
  • the transconductance in this case is:
  • the transconductance of the input differential pair is constant in the entire range, which is the principle of constant transconductance of the current mirror of 3 times.
  • the accuracy of the gate voltage Vb1 and Vb2 of the switch requiring a three-fold tail current source is higher, which is more difficult to produce in the circuit, and in the manufacturing process, power supply voltage and temperature and other conditions Under change, the required voltage offset and the generated offset voltage are changing. In some extreme cases, the generated offset voltage may not meet the circuit requirements, which will greatly limit the performance of the circuit.
  • a single NMOS and PMOS are used as the current source.
  • the two switch tubes are required to be in the off state, and the leakage current is small, then the switch tube channel is required to be long enough and the width to length ratio is sufficient; and when the input voltage common mode voltage is in an extreme case Next, the switch is required to be turned on and the on-resistance is sufficiently small, which requires its channel to be short enough and the width-to-length ratio large enough. This pair of contradictions is not easy to reconcile. In some circuit analysis, it is often seen that the switch tube is turned on and the drain source voltage is too large, which causes the tail current source tube to be in the linear region. In summary, the accurate bias voltages Vb1 and Vb2 increase the complexity of the circuit design, and in some extreme process, environment, and power supply conditions, the generated bias voltage may no longer meet the circuit requirements.
  • the differential input circuit includes:
  • the first power module 110 is configured to output a first signal, a second signal, and a third signal under the control of the first bias signal Vbp, and the third signal is transmitted to the first node P1;
  • the second power module 120 is connected to the first power module 110, receives the first signal, and outputs a fourth signal and a fifth signal, and the fifth signal is transmitted to the second node P2;
  • the first shunt module 130 is connected to the fourth signal output terminal, the differential input signal Vg terminal and the first node P1, and is used to transmit the fourth signal to the first node P1 under the control of the differential input signal Vg;
  • the second shunt module 140 connects the second signal output terminal, the differential input signal Vg terminal and the second node P2, and is used to transmit the second signal to the second node P2 under the control of the differential input signal Vg;
  • the first output module 150 is connected to the differential input signal Vg terminal, the first node P1 and the differential output terminal, and is used to output a first output signal under the control of the differential input signal Vg.
  • the first output signal may include a first output positive current Iout1 + and The first output negative current Iout1-;
  • the second output module 160 is connected to the differential input signal Vg terminal, the second node P2 and the differential output terminal, and is used to output a second output signal under the control of the differential input signal Vg.
  • the second output signal may include a second output positive current Iout2 + and The second output negative current Iout2-.
  • the second power module 120 is a current mirror power supply, and can output the same current signal as the first power module 110.
  • the first output module 150 When the voltage of the differential input signal Vg is low, the first output module 150 is turned on, the first shunt module 130 and the second output module 160 are turned off, and the differential signal is output through the first output module 150; when the differential input signal Vg is At a high level, the second output module 160 is turned on, the second shunt module 140 and the first output module 150 are turned off, and a differential signal is output through the second output module 160.
  • the transconductance is constant.
  • the first output module 150, the second output module 160, the first shunt module 130, and the second shunt module 140 are all turned on, and at this time, the first shunt module 130 shunts the third signal
  • the shunted signal is output through the first output module 150, the second shunt module 140 shunts the fifth signal, and the shunted signal is output through the second output module 160 to achieve constant transconductance under this condition.
  • the differential input circuit controls the first power module 110 to output the first signal, the second signal and the third signal through the first bias signal Vbp, and the second power module 120 receives the first signal and outputs the fourth signal and
  • the fifth signal controls the first shunt module 130, the second shunt module 140, the first output module 150, and the second output module 160 through the differential input signal Vg, so that when the differential input signal Vg changes, the transconductance of the differential input circuit is constant
  • the first shunt module 130, the second shunt module 140, the first output module 150, and the second output module 160 are all controlled by the differential input signal Vg, there are few control signals, which makes the circuit control simple and easy to implement.
  • the first power module 110 includes: a first transistor T1, a second transistor T2, and a third transistor T3; a first terminal of the first transistor T1 is connected to the first power terminal VDD, and a control terminal is connected to the first The bias signal Vbp terminal, the second terminal is connected to the second power module 120; the first terminal of the second transistor T2 is connected to the first power terminal VDD, the control terminal is connected to the first bias signal Vbp terminal, and the second terminal is connected to the second shunt module 140; The first terminal of the third transistor T3 is connected to the first power supply terminal VDD, the control terminal is connected to the first bias signal Vbp terminal, and the second terminal is connected to the first output module 150.
  • the ratio of the width-to-length ratio (W / L) of the first transistor T1, the second transistor T2, and the third transistor T3 is 4: 3: 4.
  • the second power module 120 includes: a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; the first terminal and the control terminal of the fourth transistor T4 are connected to the first signal output terminal, and the second terminal is connected to the second power terminal VSS;
  • the first terminal of the fifth transistor T5 is connected to the first shunt module 130, the control terminal is connected to the first signal terminal, and the second terminal is connected to the second power terminal VSS;
  • the first terminal of the sixth transistor T6 is connected to the second output module 160, and the control terminal
  • the first signal terminal is connected, and the second terminal is connected to the second power terminal VSS.
  • the aspect ratio of the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 is 4: 3: 4.
  • the differential input signal Vg may include a first sub-differential signal Vn and a second sub-differential signal Vp; the first output module 150 is used to output a first output current, similar to the embodiment described with reference to FIG. 2, the first output current includes the first Output positive current and first output negative current.
  • the first output module 150 may be composed of PMOS, so the first output positive current and the first output negative current included in the first output current are marked as Ioutp + and Ioutp-, respectively.
  • the first output module 150 may include a first differential transistor pair including a seventh transistor T7 and an eighth transistor T8; the first end of the seventh transistor T7 is connected to the first node, The control terminal is connected to the first sub-differential signal Vn, the second terminal is used to output a first output positive current Ioutp +; the first terminal of the eighth transistor T8 is connected to the first node, and the control terminal is connected to the second sub-differential signal Vp, The two terminals are used to output a first output negative current Ioutp-.
  • the second output module 160 is used to output a second output current. Similar to the embodiment described with reference to FIG. 2, the second output current includes a second output positive current and a second output negative current.
  • the second output module 160 may be composed of NMOS, so the second output positive current and the second output negative current included in the second output current are marked as Ioutp + and Ioutp-, respectively.
  • the second output module 160 may include: a second differential transistor pair including a ninth transistor T9 and a tenth transistor T10, and a first end of the ninth transistor T9 is connected to the second node ,
  • the control terminal is connected to the first sub-differential signal Vn, the second terminal is used to output a second output positive current Ioutn +;
  • the first terminal of the tenth transistor T10 is connected to the second node, and the control terminal is connected to the second sub-differential signal Vp,
  • the second terminal is used to output a second output negative current Ioutn-.
  • the first shunt module 130 includes a third differential transistor pair including: an eleventh transistor T11 and a twelfth transistor T12; a first terminal of the eleventh transistor T11 is connected to a fourth signal output terminal and a control terminal Connected to the first sub-differential signal Vn, the second terminal is connected to the first node; the first terminal of the twelfth transistor T12 is connected to the fourth signal output terminal, the control terminal is connected to the second sub-differential signal Vp, and the second terminal is connected to the first node;
  • the second shunt module 140 includes a fourth differential transistor pair including: a thirteenth transistor T13 and a fourteenth transistor T14; the first end of the thirteenth transistor T13 is connected to the second signal output end and the control end The first sub-differential signal Vn is connected, the second terminal is connected to the second node; the first end of the fourteenth transistor T14 is connected to the second signal output terminal, the control terminal is connected to the second sub-differential signal Vp, and the second terminal is connected to the second node.
  • the seventh transistor T7, the eighth transistor T8, the thirteenth transistor T13, and the fourteenth transistor T14 are PMOS, and the ninth transistor T9, the tenth The transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are NMOS;
  • the seventh transistor T7, the eighth transistor T8, the thirteenth transistor T13 and the fourteenth transistor T14 may be PMOS of the same size
  • the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 may be NMOS of the same size.
  • the ratio of the aspect ratio of the first transistor T1, the second transistor T2 and the third transistor T3 is 4: 3: 4, the aspect ratio of the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 The ratio is 4: 3: 4. It is assumed that under the control of the first bias signal Vbp, the first transistor T1 outputs 8I current, the second transistor T2 outputs 6I current, the third transistor T3 outputs 8I current, and the second power module 120 is a current mirror power supply, so The fourth transistor T4 also outputs a current of 8I.
  • the parameter "I" represents the reference value of the output current of the transistor, which is determined by the driving capability of the Vbp signal input in the previous stage, and may be, for example, 1 microampere, 2 microamperes, and so on.
  • the common-mode voltage of the differential input signal is between 0 and Vthn + VP2, that is, the voltage of the differential input signal Vg is low, the NMOS is turned off, the PMOS is turned on and is in the saturation region, that is, the seventh transistor T7 and the eighth transistor T8 is turned on, and the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned off.
  • the total current flowing through the seventh transistor T7 and the eighth transistor T8 is 8I, flowing through the first The currents of the nine transistor T9 and the tenth transistor T10 are zero.
  • the transconductance of the differential input circuit is Among them, VP2 is the voltage at the second node P2 in FIG. 3, and Vthn is the threshold voltage of the NMOS.
  • the common-mode voltage of the differential input signal is between VP1 +
  • the transistor T10 is turned on, the seventh transistor T7, the eighth transistor T8, the thirteenth transistor T13 and the fourteenth transistor T14 are turned off.
  • the total current flowing through the ninth transistor T9 and the tenth transistor T10 is 8I, flowing through The currents of the seventh transistor T7 and the eighth transistor T8 are zero, and the transconductance of the differential input circuit is Among them, VP1 is the voltage at the first node P1 in FIG. 3, and Vthp is the threshold voltage of the PMOS.
  • the NMOS pair and the PMOS pair are turned on at the same time and are in the saturation region, which is the seventh Until the fourteenth transistor T14 is turned on, at this time, the first shunt module 130 shunts 6I of current from the third transistor T3, the total current output by the first output module 150 is 2I, and the second shunt module 140 from the fifth Transistor T5 distributes 6I of current, the total current output by the second output module 160 is 2I, and the transconductance of the differential circuit is
  • the transconductance of the differential input circuit in the above three stages are all
  • the transconductance is constant within the rail-to-rail input range.
  • Kp and Kn represent the proportionality coefficients of PMOS and NMOS, respectively, so-called transconductance coefficients.
  • Kp and Kn may be related to at least one of the following circuit size parameters and electrical parameters: carrier mobility, capacitance per unit area of the gate oxide layer, and width-to-length ratio of the transistor.
  • the seventh transistor T7, the eighth transistor T8, the thirteenth transistor T13, and the fourteenth transistor T14 are NMOS
  • the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are PMOS.
  • the first transistor T1, the second transistor T2 and the third transistor T3 may be NMOS, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 may be PMOS; or the first transistor T1, the second transistor T2 and the third transistor T3 may be a PMOS, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be NMOS;
  • each transistor may be a gate, the first terminal may be a source, and the second terminal may be a drain; or, the control terminal of each transistor may be a gate, the first terminal may be a drain, and the second terminal may As the source.
  • each transistor may also be an enhancement mode transistor or a depletion mode transistor, which is not specifically limited in this example embodiment.
  • the present disclosure also provides a driving method of a differential input circuit for driving the differential input circuit as described in any of the foregoing embodiments.
  • the driving method includes:
  • the second power module 120 receives the first signal, and outputs the fourth signal and the fifth signal through the differential input signal Vg controls the first shunt module 130, the second shunt module 140, the first output module 150, and the second output module 160, so that when the differential input signal Vg changes, the transconductance of the differential input circuit is constant, and because the first shunt module 130 2.
  • the second shunt module 140, the first output module 150, and the second output module 160 are all controlled by the differential input signal Vg, which has fewer control signals, making circuit control simple and easy to implement.
  • the first shunt module 130, the second shunt module 140, the first output module 150, and the second output module 160 are all controlled by the differential input signal Vg, which avoids the requirement of the comparative example of the present disclosure
  • the accuracy of the gate voltages Vb1 and Vb2 seen by the switch of the three-fold tail current source is high, which results in complicated control and difficulty in manufacturing. Under changes in manufacturing process, power supply voltage and temperature, the required voltage offset and the generated offset voltage are changing. In some extreme cases, the generated offset voltage may not meet the circuit requirements, limiting circuit performance The problem.
  • multiple transistors are used as the current source, and a single transistor is used as the current source. When the voltage of the differential input signal Vg changes, the drain-source voltage of the switch tube is large, which sometimes forces its tail current source tube into the linear region, which affects Current accuracy.
  • Exemplary embodiments of the present disclosure also provide an amplification circuit including the differential input circuit provided by the embodiments of the present disclosure.
  • the amplifying circuit may also include components such as comparators, resistors, and encoding circuits, as they are all related technologies in the prior art and will not be repeated here.
  • Exemplary embodiments of the present disclosure also provide a display device including the amplification circuit provided by the embodiments of the present disclosure.
  • the display device may include, for example, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and any other product or component with a display function.
  • the differential input circuit controls the first power module to output the first signal, the second signal and the third signal through the first bias signal, and the second power module receives the first signal and outputs the fourth signal and the fifth signal ,
  • the first shunt module, the second shunt module, the first output module, and the second output module are controlled by the differential input signal, so that when the differential input signal changes, the transconductance of the differential input circuit is constant, and because the first shunt module, the first
  • the second shunt module, the first output module and the second output module are all controlled by differential input signals, and the control signals are few, which makes the circuit control simple and easy to implement, simplifies the manufacturing process and saves costs.

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Abstract

一种差分输入电路及放大电路、显示装置，所述差分输入电路包括：第一电源模块(110)、第二电源模块(120)、第一分流模块(130)、第二分流模块(140)、第一输出模块(150)和第二输出块(160)；通过第一偏置信号(Vbp)控制第一电源模块(110)输出第一信号、第二信号和第三信号，第二电源模块(120)接收第一信号，并输出第四信号和第五信号，通过差分输入信号(Vg)控制第一分流模块(130)、第二分流模块(140)、第一输出模块(150)和第二输出模块(160)，使得第一输出模块(150)和第二输出模块(160)在差分输入信号(Vg)控制下输出输出信号。

Description

差分输入电路及放大电路、显示装置
相关申请的交叉引用
本申请要求于2018年11月23日递交的中国专利申请第201811409497.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及模拟电路技术领域，具体而言，涉及一种差分输入电路及放大电路、显示装置。
背景技术
随着技术的发展和进步，在模拟电路中放大器的应用越来越广泛，在轨到轨放大器中，差分输入电路的跨导与差分输入电压相关。
目前，跨导恒定的差分输入电路中采用了多个晶体管，并且这些晶体管采用不同的控制信号进行控制。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种差分输入电路及放大电路、显示装置。
根据本公开的第一方面，提供一种差分输入电路，所述差分输入电路包括：
第一电源子电路，用于在第一偏置信号的控制下输出第一信号、第二信号和第三信号，所述第三信号被传输至第一节点；
第二电源子电路，和所述第一电源子电路连接，接收所述第一信号，并输出第四信号和第五信号，所述第五信号被传输至第二节点；
第一分流子电路，连接输出所述第四信号的第四信号输出端、差 分输入信号端和第一节点，用于在差分输入信号端的差分输入信号控制下将第四信号传输至第一节点；
第二分流子电路，连接输出所述第二信号的第二信号输出端、差分输入信号端和第二节点，用于在差分输入信号端的差分输入信号控制下将第二信号传输至第二节点；
第一输出子电路，连接差分输入信号端、第一节点和差分输出端，用于在差分输入信号端的差分输入信号控制下输出第一输出信号；
第二输出子电路，连接差分输入信号端，第二节点和差分输出端，用于在差分输入信号端的差分输 入信号控制下输出第二输出信号。
根据本公开的一实施方式，
所述第一电源子电路包括：
第一晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二电源子电路；
第二晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二分流子电路；
第三晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第一输出子电路。
根据本公开的一实施方式，所述第一晶体管、第二晶体管和第三晶体管的宽长比的比值为4:3:4。
根据本公开的一实施方式，
所述第二电源子电路包括：
第四晶体管，第一端和控制端接收所述第一信号，第二端连接第二电源端；
第五晶体管，第一端连接第一分流子电路，控制端连接第一信号端，第二端连接第二电源端；
第六晶体管，第一端连接第二输出子电路，控制端连接第一信号端，第二端连接第二电源端。
根据本公开的一实施方式，所述第四晶体管、第五晶体管和第六晶体管的宽长比的比值为4:3:4。
根据本公开的一实施方式，所述第一晶体管、第二晶体管、第三 晶体管为P型金属氧化物半导体场效应晶体管，所述第四晶体管、第五晶体管、第六晶体管为N型金属氧化物半导体场效应晶体管；
或者所述第一晶体管、第二晶体管、第三晶体管为N型金属氧化物半导体场效应晶体管，所述四晶体管、第五晶体管、第六晶体管为P型金属氧化物半导体场效应晶体管。
根据本公开的一实施方式，所述差分输入信号包括第一子差分信号和第二子差分信号，所述第一输出信号包括第一输出正信号和第一输出负信号，所述第二输出信号包括第二输出正信号和第二输出负信号；
所述第一输出子电路包括：
第一差分晶体管对，包括：
第七晶体管，第一端连接于所述第一节点，控制端连接第一子差分信号，第二端输出所述第一输出正信号；
第八晶体管，第一端连接于所述第一节点，控制端连接第二子差分信号，第二端输出所述第一输出负信号；
所述第二输出子电路包括：
第二差分晶体管对，包括：
第九晶体管，第一端连接于所述第二节点，控制端连接第一子差分信号，第二端输出所述第二输出正信号；
第十晶体管，第一端连接于所述第二节点，控制端连接第二子差分信号，第二端输出所述第二输出负信号。
根据本公开的一实施方式，所述第一分流子电路，包括
第三差分晶体管对，包括：
第十一晶体管，第一端连接所述第四信号输出端，控制端连接第一子差分信号，第二端连接第一节点；
第十二晶体管，第一端连接所述第四信号输出端，控制端连接第二子差分信号，第二端连接第一节点；
所述第二分流子电路，包括
第四差分晶体管对，包括：
第十三晶体管，第一端连接所述第二信号输出端，控制端连接第 一子差分信号，第二端连接第二节点；
第十四晶体管，第一端连接所述第二信号输出端，控制端连接第二子差分信号，第二端连接第二节点。
根据本公开的一实施方式，所述第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为P型金属氧化物半导体场效应晶体管，所述第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为N型金属氧化物半导体场效应晶体管；
或者所述第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为N型金属氧化物半导体场效应晶体管，所述第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为P型金属氧化物半导体场效应晶体管。
根据本公开的一实施方式，所述第二电源子电路为电流镜电源，能够输出和所述第一电源子电路相同的电流信号。
根据本公开的一实施方式，所述第一电源子电路包括：第一晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二电源子电路；第二晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二分流子电路；第三晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第一输出子电路，
所述第二电源子电路包括：第四晶体管，第一端和控制端接收所述第一信号，第二端连接第二电源端；第五晶体管，第一端连接第一分流子电路，控制端连接第一信号端，第二端连接第二电源端；第六晶体管，第一端连接第二输出子电路，控制端连接第一信号端，第二端连接第二电源端，
所述第一输出子电路第一差分晶体管对，包括：第七晶体管，第一端连接于所述第一节点，控制端连接第一子差分信号，第二端输出所述第一输出信号；第八晶体管，第一端连接于所述第一节点，控制端连接第二子差分信号，第二端输出所述第一输出信号，
所述第二输出子电路包括第二差分晶体管对，包括：第九晶体管，第一端连接于所述第二节点，控制端连接第一子差分信号，第二 端输出所述第二输出信号；第十晶体管，第一端连接于所述第二节点，控制端连接第二子差分信号，第二端输出所述第二输出信号，
所述第一分流子电路包括第三差分晶体管对，包括：第十一晶体管，第一端连接所述第四信号输出端，控制端连接第一子差分信号，第二端连接第一节点；第十二晶体管，第一端连接所述第四信号输出端，控制端连接第二子差分信号，第二端连接第一节点，
所述第二分流子电路包括第四差分晶体管对，包括：第十三晶体管，第一端连接所述第二信号输出端，控制端连接第一子差分信号，第二端连接第二节点；第十四晶体管，第一端连接所述第二信号输出端，控制端连接第二子差分信号，第二端连接第二节点。
根据本公开的一实施方式，所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为P型金属氧化物半导体场效应晶体管，所述第四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为N型金属氧化物半导体场效应晶体管；
或者所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为N型金属氧化物半导体场效应晶体管，所述四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为P型金属氧化物半导体场效应晶体管。
根据本公开的第二方面，提供一种放大电路，包括上述的差分输入电路。
根据本公开的第三方面，提供一种显示装置，包括上述的放大电路。
根据本公开的第四方面，提供一种差分输入电路的驱动方法，用于驱动根据本公开前述方面的差分输入电路，所述方法包括：
通过第一偏置信号控制第一电源模块输出第一信号、第二信号和第三信号，第二电源模块接收第一信号，并输出第四信号和第五信号；
通过差分输入信号控制第一分流模块、第二分流模块、第一输出 模块和第二输出模块，使得在差分输入信号变化时，实现差分输入电路跨导恒定。
根据本公开的一个实施例，所述第一电源子电路包括：第一晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二电源子电路；第二晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二分流子电路；第三晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第一输出子电路，
所述第二电源子电路包括：第四晶体管，第一端和控制端接收所述第一信号，第二端连接第二电源端；第五晶体管，第一端连接第一分流子电路，控制端连接第一信号端，第二端连接第二电源端；第六晶体管，第一端连接第二输出子电路，控制端连接第一信号端，第二端连接第二电源端，
所述第一输出子电路第一差分晶体管对，包括：第七晶体管，第一端连接于所述第一节点，控制端连接第一子差分信号，第二端输出所述第一输出信号；第八晶体管，第一端连接于所述第一节点，控制端连接第二子差分信号，第二端输出所述第一输出信号，
所述第二输出子电路包括第二差分晶体管对，包括：第九晶体管，第一端连接于所述第二节点，控制端连接第一子差分信号，第二端输出所述第二输出信号；第十晶体管，第一端连接于所述第二节点，控制端连接第二子差分信号，第二端输出所述第二输出信号，
所述第一分流子电路包括第三差分晶体管对，包括：第十一晶体管，第一端连接所述第四信号输出端，控制端连接第一子差分信号，第二端连接第一节点；第十二晶体管，第一端连接所述第四信号输出端，控制端连接第二子差分信号，第二端连接第一节点，
所述第二分流子电路包括第四差分晶体管对，包括：第十三晶体管，第一端连接所述第二信号输出端，控制端连接第一子差分信号，第二端连接第二节点；第十四晶体管，第一端连接所述第二信号输出 端，控制端连接第二子差分信号，第二端连接第二节点，
所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为P型金属氧化物半导体场效应晶体管，所述第四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为N型金属氧化物半导体场效应晶体管；
或者所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为N型金属氧化物半导体场效应晶体管，所述四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为P型金属氧化物半导体场效应晶体管，
所述方法还包括：
当差分输入信号的电压为低电平，且在第一偏置信号的控制下为第一晶体管T1输出的电流为8I时，N型金属氧化物半导体场效应晶体管截止，P型金属氧化物半导体场效应晶体管开启且处于饱和区，此时差分输入电路的跨导为
Figure PCTCN2019117509-appb-000001
当差分输入信号的电压为高电平，且在第一偏置信号的控制下为第一晶体管T1输出的电流为8I时，N型金属氧化物半导体场效应晶体管开启且处于饱和区，P型金属氧化物半导体场效应晶体管截止，此时差分输入电路的跨导为
Figure PCTCN2019117509-appb-000002
当差分输入信号的电压为中间电平，且在第一偏置信号的控制下为第一晶体管T1输出的电流为8I时，N型金属氧化物半导体场效应晶体管开启且处于饱和区，P型金属氧化物半导体场效应晶体管开启且处于饱和区，此时差分输入电路的跨导为
Figure PCTCN2019117509-appb-000003
其中，Kp和Kn分别为P型金属氧化物半导体场效应晶体管和N型金属氧化物半导体场效应晶体管的跨导系数，I为表示晶体管的输出电流的基准值。
根据本公开的一个实施例，所述低电平表示差分输入电压在0到Vthn+VB之间；
所述中间电平表示差分输入电压在Vthn+VB到VA+|Vthp|；
所述高电平表示差分输入电压在VA+|Vthp|到VDD之间，
其中，Vthn表示N型金属氧化物半导体场效应晶体管的阈值电压，Vthp表示P型金属氧化物半导体场效应晶体管的阈值电压，VA表示第一节点的电平，VB表示第二节点的电平，VDD表示第一电源端的电平。
根据本公开的一个实施例，调节P型金属氧化物半导体场效应晶体管和N型金属氧化物半导体场效应晶体管的尺寸参数，使得K P＝K N。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
本节提供本公开中描述的技术的各种实现或示例的概述，并不是所公开技术的全部范围或所有特征的全面公开。
附图说明
通过参照附图来详细描述其示例实施例，本公开的上述和其它特征及优点将变得更加明显。
图1为本公开对比例提供的一种跨导恒定的差分输出电路的示意图；
图2为本公开示例性实施例提供的一种差分输入电路的示意图；
图3为本公开示例性实施例提供的另一种差分输入电路的示意图；
图4为本公开示例性实施例提供的一种差分输入电路的驱动方法的示意性流程图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反， 提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组元、材料、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现、材料或者操作以避免模糊本公开的各方面。
附图中所示的方框图仅仅是功能实体，不一定必须与物理上独立的实体相对应。即，可以采用软件形式来实现这些功能实体，或在一个或多个软件硬化的模块中实现这些功能实体或功能实体的一部分，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
在本公开对比例中，一种恒定跨导电路是通过改变输入对管的尾电流来使其在不同输入电压下跨导恒定，如图1所示，M1和M0为NMOS(N型金属氧化物半导体场效应晶体管)差分输入对，M7和M8为PMOS(P型金属氧化物半导体场效应晶体管)差分输入对，M4和M9分别为其为电流源，调节电路参数使其尾电流相等。
M5和M6为开关管，其栅压分别为Vb2和Vb1，M2和M3、M9和M10分别构成一个3倍电流镜，通过开关控制将M5和M6的漏电流放大3倍值NMOS差分输入对和PMOS(P型金属氧化物半导体场效应晶体管)差分输入对的源电极。
其工作原理如下：输入电压在轨到轨范围内是，变化的PMOS差分输入对和NMOS差分输入对的微电流使其漏极电流改变从而使其跨导变化，VA和VB分别为A节点和B节点的电压，Vthn和Vthp分别NMOS和PMOS差分输入对管的阈值电压，Itail指的是尾电流。
当差分输入电压在0到Vthn+VB之间时，NMOS差分输入对管因为Vgs低于Vthn从而截止，PMOS差分输入对管处于饱和区，总 的输入跨导为：
Figure PCTCN2019117509-appb-000004
当差分输入电压在Vthn+VB到VA+|Vthp|时，NMOS差分输入对管和PMOS差分输入对管均开启，此时总的跨导为：
Figure PCTCN2019117509-appb-000005
Figure PCTCN2019117509-appb-000006
当差分输入电压在VA+|Vthp|到VDD之间时，PMOS差分输入对管因为Vgs低于Vthp从而截止，NMOS差分输入对管处于饱和区，此时中的跨导为：
Figure PCTCN2019117509-appb-000007
此时实现了输入差分对在全范围内跨导恒定，这就是3倍电流镜跨导恒定的原理。但是发明人发现在该结构中，要求3倍尾电流源的开关看的栅压Vb1和Vb2的精度较高，这在电路中是较难产生的，且在制造工艺、电源电压及温度等条件变化下，其所需的电压偏置和产生的偏置电压都在变化，在某些极限情况下产生的偏置电压可能不符合电路要求，这将极大的限制电路性能。另一方面，单独使用一个NMOS和PMOS作为电流源，在随共模输入电压变化时，A和B点的电压会使其电流值变化，特别是当开关管开启的状态下，开关管的漏源电压较大，有时会迫使其尾电流源管M4和M9进入线性区，从而影响电流精度。
此外，当差分输入电压处于中间值，要求两个开关管处于关断状态下，漏电流小，则要求开关管沟道足够长且宽长比足够下；而当输入电压共模电压在极端情况下，则要求开关管开启且导通电阻足够小，这就要求其沟道足够短且宽长比足够大。这对矛盾不易调和，在一些电路分析中长出现开关管在开启同时漏源电压太大而导致尾电流源管处于线性区。综上，精确的偏置电压Vb1和Vb2增加电路设计的复杂程度，且在一些极端的工艺、环境、电源情况下，产生的该偏置电压可能不再符合电路要求。
本公开示例性实施例首先提供一种差分输入电路，如图2所示，所述差分输入电路包括：
第一电源模块110，用于在第一偏置信号Vbp的控制下输出第一信号、第二信号和第三信号，所述第三信号被传输至第一节点P1；
第二电源模块120，和所述第一电源模块110连接，接收所述第一信号，并输出第四信号和第五信号，所述第五信号被传输至第二节点P2；
第一分流模块130，连接第四信号输出端、差分输入信号Vg端和第一节点P1，用于在差分输入信号Vg控制下将第四信号传输至第一节点P1；
第二分流模块140，连接第二信号输出端、差分输入信号Vg端和第二节点P2，用于在差分输入信号Vg控制下将第二信号传输至第二节点P2；
第一输出模块150，连接差分输入信号Vg端、第一节点P1和差分输出端，用于在差分输入信号Vg控制下输出第一输出信号，第一输出信号可以包括第一输出正电流Iout1+和第一输出负电流Iout1-；
第二输出模块160，连接差分输入信号Vg端，第二节点P2和差分输出端，用于在差分输入信号Vg控制下输出第二输出信号，第二输出信号可以包括第二输出正电流Iout2+和第二输出负电流Iout2-。
其中，第二电源模块120为电流镜电源，能够输出和第一电源模块110相同的电流信号。当差分输入信号Vg的电压为低电平时，第一输出模块150导通，第一分流模块130和第二输出模块160关断，通过第一输出模块150输出差分信号；当差分输入信号Vg为高电平时，第二输出模块160导通，第二分流模块140和第一输出模块150关断，通过第二输出模块160输出差分信号。通过控制第一输出模块150和第二输出模块160的自身参数，实现跨导恒定。当差分输入信号Vg处于中间水平时，第一输出模块150、第二输出模块160、第一分流模块130和第二分流模块140均导通，此时第一分流模块130对第三信号进行分流，分流后的信号通过第一输出模块150输出，第二分流模块140对第五信号进行分流，分流后的信号通过第二输出模块160输出，以实现在该条件下，跨导恒定。
本公开提供的差分输入电路，通过第一偏置信号Vbp控制第一电源模块110输出第一信号、第二信号和第三信号，第二电源模块120接收第一信号，并输出第四信号和第五信号，通过差分输入信号 Vg控制第一分流模块130、第二分流模块140、第一输出模块150和第二输出模块160，使得在差分输入信号Vg变化时，实现差分输入电路跨导恒定，并且由于第一分流模块130、第二分流模块140、第一输出模块150和第二输出模块160均由差分输入信号Vg控制，控制信号少，使得电路控制简单，易实现。
下面将对本公开实施例提供的差分输入电路的各模块进行详细说明：
如图3所示，所述第一电源模块110包括：第一晶体管T1、第二晶体管T2和第三晶体管T3；第一晶体管T1的第一端连接第一电源端VDD，控制端连接第一偏置信号Vbp端，第二端连接第二电源模块120；第二晶体管T2的第一端连接第一电源端VDD，控制端连接第一偏置信号Vbp端，第二端连接第二分流模块140；第三晶体管T3的第一端连接第一电源端VDD，控制端连接第一偏置信号Vbp端，第二端连接第一输出模块150。其中，第一晶体管T1、第二晶体管T2和第三晶体管T3的宽长比(W/L)的比值为4:3:4。
第二电源模块120包括：第四晶体管T4、第五晶体管T5和第六晶体管T6；第四晶体管T4的第一端和控制端连接第一信号输出端，第二端连接第二电源端VSS；第五晶体管T5的第一端连接第一分流模块130，控制端连接第一信号端，第二端连接第二电源端VSS；第六晶体管T6的第一端连接第二输出模块160，控制端连接第一信号端，第二端连接第二电源端VSS。其中，所述第四晶体管T4、第五晶体管T5和第六晶体管T6的宽长比的比值为4:3:4。
差分输入信号Vg可以包括第一子差分信号Vn和第二子差分信号Vp；第一输出模块150用于输出第一输出电流，与参照图2描述的实施例类似，第一输出电流包括第一输出正电流和第一输出负电流。在本实施例中，第一输出模块150可以由PMOS组成，因此相应地将第一输出电流包括的第一输出正电流和第一输出负电流分别标注为Ioutp+和Ioutp-。具体地说，第一输出模块150可以包括第一差分晶体管对，该第一差分晶体管对包括第七晶体管T7和第八晶体管T8；第七晶体管T7的第一端连接于所述第一节点，控制端连接第一子差 分信号Vn，第二端用于输出第一输出正电流Ioutp+；第八晶体管T8的第一端连接于所述第一节点，控制端连接第二子差分信号Vp，第二端用于输出第一输出负电流Ioutp-。
所述第二输出模块160用于输出第二输出电流，与参照图2描述的实施例类似，第二输出电流包括第二输出正电流和第二输出负电流。在本实施例中，第二输出模块160可以由NMOS组成，因此相应地将第二输出电流包括的第二输出正电流和第二输出负电流分别标注为Ioutp+和Ioutp-。具体地说，第二输出模块160可以包括：第二差分晶体管对，该第二差分晶体管对包括第九晶体管T9和第十晶体管T10，第九晶体管T9的第一端连接于所述第二节点，控制端连接第一子差分信号Vn，第二端用于输出第二输出正电流Ioutn+；第十晶体管T10的第一端连接于所述第二节点，控制端连接第二子差分信号Vp，第二端用于输出第二输出负电流Ioutn-。
第一分流模块130包括第三差分晶体管对，该第三差分晶体管对包括：第十一晶体管T11和第十二晶体管T12；第十一晶体管T11的第一端连接第四信号输出端，控制端连接第一子差分信号Vn，第二端连接第一节点；第十二晶体管T12的第一端连接第四信号输出端，控制端连接第二子差分信号Vp，第二端连接第一节点；
第二分流模块140包括第四差分晶体管对，该第四差分晶体管对包括：第十三晶体管T13和第十四晶体管T14；第十三晶体管T13的第一端连接第二信号输出端，控制端连接第一子差分信号Vn，第二端连接第二节点；第十四晶体管T14的第一端连接第二信号输出端，控制端连接第二子差分信号Vp，第二端连接第二节点。
在本公开实施例提供的一种可行的实施方式中，所述第七晶体管T7、第八晶体管T8、第十三晶体管T13和第十四晶体管T14为PMOS，所述第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12为NMOS；
其中，第七晶体管T7、第八晶体管T8、第十三晶体管T13和第十四晶体管T14可以是尺寸相同的PMOS，第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12可以是尺寸相同 的NMOS。
由于，第一晶体管T1、第二晶体管T2和第三晶体管T3的宽长比的比值为4:3:4，所述第四晶体管T4、第五晶体管T5和第六晶体管T6的宽长比的比值为4:3:4。假设在第一偏置信号Vbp的控制下为第一晶体管T1输出8I的电流，第二晶体管T2输出6I的电流，第三晶体管T3输出8I的电流，第二电源模块120为电流镜电源，因此第四晶体管T4也输出8I的电流。在本实施例中，参数“I”表示晶体管的输出电流的基准值，由前一级输入的Vbp信号的驱动能力决定，例如可以为1微安，2微安等。
当差分输入信号的共模电压为0到Vthn+VP2之间，即差分输入信号Vg的电压为低电平时，NMOS截止，PMOS开启且处于饱和区，也即是第七晶体管T7和第八晶体管T8导通，第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12截止，此时，流过第七晶体管T7和第八晶体管T8的总电流为8I，流过第九晶体管T9和第十晶体管T10的电流为零。此时，差分输入电路的跨导为
Figure PCTCN2019117509-appb-000008
其中，VP2为图3中第二节点P2处的电压，Vthn为NMOS的阈值电压。
当差分输入信号的共模电压为VP1+|Vthp|到VDD之间，即差分输入信号Vg的电压为高电平时，PMOS截止，NMOS开启且处于饱和区，也即是第九晶体管T9和第十晶体管T10导通，第七晶体管T7、第八晶体管T8、第十三晶体管T13和第十四晶体管T14截止，此时，流过第九晶体管T9和第十晶体管T10的总电流为8I，流过第七晶体管T7和第八晶体管T8的电流为零，差分输入电路的跨导为
Figure PCTCN2019117509-appb-000009
Figure PCTCN2019117509-appb-000010
其中，VP1为图3中第一节点P1处的电压，Vthp为PMOS的阈值电压。
当差分输入信号的共模电压在Vthn+VP2到VP1+|Vthp|之间，即差分输入信号Vg的电压处于中间水平，NMOS对管和PMOS对管同时开启且处于饱和区，也即是第七至第十四晶体管T14均导通，此 时，第一分流模块130从第三晶体管T3中分流出6I的电流，第一输出模块150输出的总电流为2I，第二分流模块140从第五晶体管T5分流出6I的电流，第二输出模块160输出的总电流为2I，差分电路的跨导为
Figure PCTCN2019117509-appb-000011
通过调节NMOS和PMOS的尺寸参数，可以使得Kp＝Kn＝K，因此在上述的三个阶段差分输入电路的跨导均为
Figure PCTCN2019117509-appb-000012
从而实现了在轨到轨输入范围内跨导恒定。在本实施例中，Kp和Kn分别表示PMOS和NMOS的比例系数，即所谓的跨导系数。根据本公开的实施例，Kp和Kn可以与以下电路尺寸参数和电学参数中的至少一项相关：载流子迁移率，栅氧化层单位面积电容、晶体管的宽长比。
在本公开实施例提供的另一种可行的实施方式中，第七晶体管T7、第八晶体管T8、第十三晶体管T13和第十四晶体管T14为NMOS，所述第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12为PMOS。
第一晶体管T1、第二晶体管T2和第三晶体管T3可以是NMOS，第四晶体管T4、第五晶体管T5和第六晶体管T6可以是PMOS；或者第一晶体管T1、第二晶体管T2和第三晶体管T3可以是PMOS，第四晶体管T4、第五晶体管T5和第六晶体管T6可以是NMOS；
各个晶体管的控制端可以为栅极、第一端可以为源极、第二端可以为漏极；或者，各个晶体管的控制端可以为栅极、第一端可以为漏极、第二端可以为源极。此外，各个晶体管还可以为增强型晶体管或者耗尽型晶体管，本示例实施方式对此不作具体限定。
本公开实施例中的提到的模块可以理解为是子电路。
本公开还提供了一种差分输入电路的驱动方法，用于驱动如前述任意实施例所述的差分输入电路。参照图4，所述驱动方法包括：
通过第一偏置信号Vbp控制第一电源模块110输出第一信号、第二信号和第三信号，第二电源模块120接收第一信号，并输出第四 信号和第五信号，通过差分输入信号Vg控制第一分流模块130、第二分流模块140、第一输出模块150和第二输出模块160，使得在差分输入信号Vg变化时，实现差分输入电路跨导恒定，并且由于第一分流模块130、第二分流模块140、第一输出模块150和第二输出模块160均由差分输入信号Vg控制，控制信号少，使得电路控制简单，易实现。
关于所述驱动方法各步骤的更具体的描述已经在前述描述差分输入电路的实施例中详细阐述过，因此在这里将不再赘述。
本公开实施例提供的差分输入电路中，第一分流模块130、第二分流模块140、第一输出模块150和第二输出模块160均通过差分输入信号Vg控制，避免了本公开对比例中要求3倍尾电流源的开关看的栅压Vb1和Vb2的精度较高，导致的控制复杂，制造难度大。在制造工艺、电源电压及温度等条件变化下，其所需的电压偏置和产生的偏置电压都在变化，在某些极限情况下产生的偏置电压可能不符合电路要求，限制电路性能的问题。并且采用多个晶体管作为电流源，单独使用一个晶体管作为电流源，在随差分输入信号Vg电压变化时，开关管的漏源电压较大，有时会迫使其尾电流源管进入线性区，从而影响电流精度。
本公开示例性实施例还提供一种放大电路，包括本公开实施例提供的差分输入电路。当然在实际应用中，该放大电路还可以包括比较器、电阻和编码电路等元器件，因其均为现有技术在此不复赘述。
本公开示例性实施例还提供一种显示装置，包括本公开实施例提供的放大电路。所述显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开提供的差分输入电路，通过第一偏置信号控制第一电源模块输出第一信号、第二信号和第三信号，第二电源模块接收第一信号，并输出第四信号和第五信号，通过差分输入信号控制第一分流模块、第二分流模块、第一输出模块和第二输出模块，使得在差分输入信号变化时，实现差分输入电路跨导恒定，并且由于第一分流模块、 第二分流模块、第一输出模块和第二输出模块均由差分输入信号控制，控制信号少，使得电路控制简单，易实现，简化了制作工艺，节约成本。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (18)

  1. 一种差分输入电路，包括：
    第一电源子电路，用于在第一偏置信号的控制下输出第一信号、第二信号和第三信号，所述第三信号被传输至第一节点；
    第二电源子电路，和所述第一电源子电路连接，接收所述第一信号，并输出第四信号和第五信号，所述第五信号被传输至第二节点；
    第一分流子电路，连接输出所述第四信号的第四信号输出端、差分输入信号端和第一节点，用于在差分输入信号端的差分输入信号控制下将第四信号传输至第一节点；
    第二分流子电路，连接输出所述第二信号的第二信号输出端、差分输入信号端和第二节点，用于在差分输入信号端的差分输入信号控制下将第二信号传输至第二节点；
    第一输出子电路，连接差分输入信号端、第一节点和差分输出端，用于在差分输入信号端的差分输入信号控制下输出第一输出信号；
    第二输出子电路，连接差分输入信号端，第二节点和差分输出端，用于在差分输入信号端的差分输 入信号控制下输出第二输出信号。
  2. 如权利要求1所述的差分输入电路，其中，所述第一电源子电路包括：
    第一晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二电源子电路；
    第二晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二分流子电路；
    第三晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第一输出子电路。
  3. 如权利要求2所述的差分输入电路，其中，所述第一晶体管、第二晶体管和第三晶体管的宽长比的比值为4:3:4。
  4. 如权利要求2所述的差分输入电路，其中，所述第二电源子电路包括：
    第四晶体管，第一端和控制端接收所述第一信号，第二端连接第二电源端；
    第五晶体管，第一端连接第一分流子电路，控制端连接第一信号端，第二端连接第二电源端；
    第六晶体管，第一端连接第二输出子电路，控制端连接第一信号端，第二端连接第二电源端。
  5. 如权利要求4所述的差分输入电路，其中，所述第四晶体管、第五晶体管和第六晶体管的宽长比的比值为4:3:4。
  6. 如权利要求5所述的差分输入电路，其中，所述第一晶体管、第二晶体管、第三晶体管为P型金属氧化物半导体场效应晶体管，所述第四晶体管、第五晶体管、第六晶体管为N型金属氧化物半导体场效应晶体管；
    或者所述第一晶体管、第二晶体管、第三晶体管为N型金属氧化物半导体场效应晶体管，所述四晶体管、第五晶体管、第六晶体管为P型金属氧化物半导体场效应晶体管。
  7. 如权利要求1所述的差分输入电路，其中，所述差分输入信号包括第一子差分信号和第二子差分信号，所述第一输出信号包括第一输出正信号和第一输出负信号，所述第二输出信号包括第二输出正信号和第二输出负信号；
    所述第一输出子电路包括：
    第一差分晶体管对，包括：
    第七晶体管，第一端连接于所述第一节点，控制端连接第一子差分信号，第二端输出所述第一输出正信号；
    第八晶体管，第一端连接于所述第一节点，控制端连接第二子差分信号，第二端输出所述第一输出负信号；
    所述第二输出子电路包括：
    第二差分晶体管对，包括：
    第九晶体管，第一端连接于所述第二节点，控制端连接第一子差分信号，第二端输出所述第二输出正信号；
    第十晶体管，第一端连接于所述第二节点，控制端连接第二子差分信号，第二端输出所述第二输出负信号。
  8. 如权利要求7所述的差分输入电路，其中，所述第一分流子 电路，包括
    第三差分晶体管对，包括：
    第十一晶体管，第一端连接所述第四信号输出端，控制端连接第一子差分信号，第二端连接第一节点；
    第十二晶体管，第一端连接所述第四信号输出端，控制端连接第二子差分信号，第二端连接第一节点；
    所述第二分流子电路，包括
    第四差分晶体管对，包括：
    第十三晶体管，第一端连接所述第二信号输出端，控制端连接第一子差分信号，第二端连接第二节点；
    第十四晶体管，第一端连接所述第二信号输出端，控制端连接第二子差分信号，第二端连接第二节点。
  9. 如权利要求8所述的差分输入电路，其中：
    所述第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为P型金属氧化物半导体场效应晶体管，所述第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为N型金属氧化物半导体场效应晶体管；
    或者所述第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为N型金属氧化物半导体场效应晶体管，所述第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为P型金属氧化物半导体场效应晶体管。
  10. 如权利要求1所述的差分输入电路，其中所述第二电源子电路为电流镜电源，能够输出和所述第一电源子电路相同的电流信号。
  11. 如权利要求1所述的差分输入电路，其中，
    所述第一电源子电路包括：第一晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二电源子电路；第二晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二分流子电路；第三晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第一输出子电路，
    所述第二电源子电路包括：第四晶体管，第一端和控制端接收所 述第一信号，第二端连接第二电源端；第五晶体管，第一端连接第一分流子电路，控制端连接第一信号端，第二端连接第二电源端；第六晶体管，第一端连接第二输出子电路，控制端连接第一信号端，第二端连接第二电源端，
    所述第一输出子电路第一差分晶体管对，包括：第七晶体管，第一端连接于所述第一节点，控制端连接第一子差分信号，第二端输出所述第一输出信号；第八晶体管，第一端连接于所述第一节点，控制端连接第二子差分信号，第二端输出所述第一输出信号，
    所述第二输出子电路包括第二差分晶体管对，包括：第九晶体管，第一端连接于所述第二节点，控制端连接第一子差分信号，第二端输出所述第二输出信号；第十晶体管，第一端连接于所述第二节点，控制端连接第二子差分信号，第二端输出所述第二输出信号，
    所述第一分流子电路包括第三差分晶体管对，包括：第十一晶体管，第一端连接所述第四信号输出端，控制端连接第一子差分信号，第二端连接第一节点；第十二晶体管，第一端连接所述第四信号输出端，控制端连接第二子差分信号，第二端连接第一节点，
    所述第二分流子电路包括第四差分晶体管对，包括：第十三晶体管，第一端连接所述第二信号输出端，控制端连接第一子差分信号，第二端连接第二节点；第十四晶体管，第一端连接所述第二信号输出端，控制端连接第二子差分信号，第二端连接第二节点。
  12. 如权利要求11所述的差分输入电路，其中：
    所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为P型金属氧化物半导体场效应晶体管，所述第四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为N型金属氧化物半导体场效应晶体管；
    或者所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为N型金属氧化物半导体场效应晶体管，所述四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为P型金属氧化物 半导体场效应晶体管。
  13. 一种放大电路，包括权利要求1-12任一项所述的差分输入电路。
  14. 一种显示装置，包括权利要求13所述的放大电路。
  15. 一种差分输入电路的驱动方法，用于驱动如权利要求1所述的差分输入电路，所述方法包括：
    通过第一偏置信号控制第一电源模块输出第一信号、第二信号和第三信号，第二电源模块接收第一信号，并输出第四信号和第五信号；
    通过差分输入信号控制第一分流模块、第二分流模块、第一输出模块和第二输出模块，使得在差分输入信号变化时，实现差分输入电路跨导恒定。
  16. 如权利要求15所述的方法，其中：
    所述第一电源子电路包括：第一晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二电源子电路；第二晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第二分流子电路；第三晶体管，第一端连接第一电源端，控制端连接第一偏置信号端，第二端连接第一输出子电路，
    所述第二电源子电路包括：第四晶体管，第一端和控制端接收所述第一信号，第二端连接第二电源端；第五晶体管，第一端连接第一分流子电路，控制端连接第一信号端，第二端连接第二电源端；第六晶体管，第一端连接第二输出子电路，控制端连接第一信号端，第二端连接第二电源端，
    所述第一输出子电路第一差分晶体管对，包括：第七晶体管，第一端连接于所述第一节点，控制端连接第一子差分信号，第二端输出所述第一输出信号；第八晶体管，第一端连接于所述第一节点，控制端连接第二子差分信号，第二端输出所述第一输出信号，
    所述第二输出子电路包括第二差分晶体管对，包括：第九晶体管，第一端连接于所述第二节点，控制端连接第一子差分信号，第二 端输出所述第二输出信号；第十晶体管，第一端连接于所述第二节点，控制端连接第二子差分信号，第二端输出所述第二输出信号，
    所述第一分流子电路包括第三差分晶体管对，包括：第十一晶体管，第一端连接所述第四信号输出端，控制端连接第一子差分信号，第二端连接第一节点；第十二晶体管，第一端连接所述第四信号输出端，控制端连接第二子差分信号，第二端连接第一节点，
    所述第二分流子电路包括第四差分晶体管对，包括：第十三晶体管，第一端连接所述第二信号输出端，控制端连接第一子差分信号，第二端连接第二节点；第十四晶体管，第一端连接所述第二信号输出端，控制端连接第二子差分信号，第二端连接第二节点，
    所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为P型金属氧化物半导体场效应晶体管，所述第四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为N型金属氧化物半导体场效应晶体管；
    或者所述第一晶体管、第二晶体管、第三晶体管、第七晶体管、第八晶体管、第十三晶体管和第十四晶体管为N型金属氧化物半导体场效应晶体管，所述四晶体管、第五晶体管、第六晶体管、第九晶体管、第十晶体管、第十一晶体管和第十二晶体管为P型金属氧化物半导体场效应晶体管，
    所述方法还包括：
    当差分输入信号的电压为低电平，且在第一偏置信号的控制下为第一晶体管T1输出的电流为8I时，N型金属氧化物半导体场效应晶体管截止，P型金属氧化物半导体场效应晶体管开启且处于饱和区，此时差分输入电路的跨导为
    Figure PCTCN2019117509-appb-100001
    当差分输入信号的电压为高电平，且在第一偏置信号的控制下为第一晶体管T1输出的电流为8I时，N型金属氧化物半导体场效应晶体管开启且处于饱和区，P型金属氧化物半导体场效应晶体管截止， 此时差分输入电路的跨导为
    Figure PCTCN2019117509-appb-100002
    当差分输入信号的电压为中间电平，且在第一偏置信号的控制下为第一晶体管T1输出的电流为8I时，N型金属氧化物半导体场效应晶体管开启且处于饱和区，P型金属氧化物半导体场效应晶体管开启且处于饱和区，此时差分输入电路的跨导为
    Figure PCTCN2019117509-appb-100003
    其中，Kp和Kn分别为P型金属氧化物半导体场效应晶体管和N型金属氧化物半导体场效应晶体管的跨导系数，I为表示晶体管的输出电流的基准值。
  17. 如权利要求16所述的方法，其中，
    所述低电平表示差分输入电压在0到Vthn+VB之间；
    所述中间电平表示差分输入电压在Vthn+VB到VA+|Vthp|；
    所述高电平表示差分输入电压在VA+|Vthp|到VDD之间，
    其中，Vthn表示N型金属氧化物半导体场效应晶体管的阈值电压，Vthp表示P型金属氧化物半导体场效应晶体管的阈值电压，VA表示第一节点的电平，VB表示第二节点的电平，VDD表示第一电源端的电平。
  18. 如权利要求16所述的方法，其中，调节P型金属氧化物半导体场效应晶体管和N型金属氧化物半导体场效应晶体管的尺寸参数，使得K P＝K N。
PCT/CN2019/117509 2018-11-23 2019-11-12 差分输入电路及放大电路、显示装置 WO2020103725A1 (zh)

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