WO2020076159A1

WO2020076159A1 - A circuit arranged for providing a delayed output signal from an input signal, as well as corresponding devices and methods

Info

Publication number: WO2020076159A1
Application number: PCT/NL2019/050677
Authority: WO
Inventors: Peter G.M. BALTUS; Carlos Antonio MENDES DA COSTA JR.; Chu Wang
Original assignee: Eindhoven Technical University
Current assignee: Eindhoven Technical University
Priority date: 2018-10-12
Filing date: 2019-10-14
Publication date: 2020-04-16
Anticipated expiration: 2021-04-12

Abstract

An Circuit (21) arranged for providing a delayed output signal (OUT) from an input signal (IN), wherein the circuit comprises n (4) branches in a sequence of branch 1 to n (4),each having an input and an output, wherein each branch (Branch 1, 2, 3, 4) comprises a sampling switch (SI, S2, S3, S4) connected to the input, a release switch (S5, S6, S7, S8) connected to the sampling switch and the output, and having an energy-storing component (Cl, C2, C3, C4) connected in between the sampling switch and the release switch, wherein each of the branches are connected to each other via the respective inputs (common input IN) as well as via the respective outputs (common output OUT), a controller (not shown in fig. 2) arranged for providing a clock signal, the clock signal having a sequence formed by a repetition of each time n pulses subsequently numbered pulse 1 to pulse n, wherein, following a repetitive loop along each of the branches each time following the sequence of the n branches from branch 1 to branch n, each one of the n pulses is provided to the sampling switch of the branch having the same sequence number as the respective one pulse, and is also provided to the release switch of a different branch of the sequence of n branches such that the release switches are activated in the same sequence within the loop as the sampling switches.

Description

Title

A circuit arranged for providing a delayed output signal from an input signal, as well as corresponding devices and methods.

Technical field

The present disclosure relates to the field of wireless data communications methods and devices. More specifically, it relates to wideband true time delay communication techniques and devices.

Background

State-of-the-art True Time Delays, TTD, rely on transmission lines, LC filters or gm-c all-pass filters to deliver time delays for a signal with specific center frequency and bandwidth. The large size, power consumption and limited bandwidth that come along with these traditional TTD can be acceptable for some high-end applications such as radio astronomy and military purposes, but it is a discouragement to consumer applications that could benefit from wideband TTD such as car radars for autonomous driving or cognitive radio for smartphones.

Current products usually present a constant group delay, i.e. a varying time delay over frequency. Another few options are able to deliver a constant time delay over a wide range of frequency such as Coaxial Delay Lines, CDL, at a cost of size. Analog shift register, also known as bucket brigade electronics, are yet another way to achieve time delay, but with limited bandwidth.

Most of the TTDs nowadays are, however, LC-based phase shifters with different characteristics and design focuses. Aiming either on low power, large delay, compact size, or even resulting in both compact and low power design or low power and large delay, this architecture may be suitable for mm-wave applications. However, TTDs for Industrial, Scientific and Medical, ISM, Ultra High Frequency, UHF, applications have only limited and power hungry options, e.g. compact cascadable gm-C all-pass TTD.

Following the above, there is a need for a TTD architecture that is able to deliver a low power, wideband, large delay, tuneable, compact, CMOS-scalable true time delay cell to allow, amongst other, reliable, low latency wireless sensor networks, through wideband beamforming.

Summary

It is an object of the present disclosure to provide for a interleaved circuit for providing a delayed output signal from an input signal.

Other objects of the present disclosure include devices and methods for providing a delayed output signal from an input signal.

In a first aspect, there is provided an Interleaved Circuit arranged for providing a delayed output signal from an input signal, wherein the interleaved circuit comprises:

n branches in a sequence of branch 1 to n, each having an input and an output, wherein each branch comprises a sampling switch connected to the input, a release switch connected to the sampling switch and the output, and having an energy-storing component connected in between the sampling switch and the release switch, wherein each of the branches are connected to each other via their inputs as well as via their outputs;

a controller arranged for providing a clock signal, the clock signal having a sequence formed by a repetition of each time n pulses subsequently numbered pulse 1 to pulse n,

wherein, following a repetitive loop along each of the branches each time following the sequence of the n branches from branch 1 to branch n,

each one of the n pulses is provided to the sampling switch of the branch having the same sequence number as the respective one pulse, and is also provided to the release switch of a different branch of the sequence of n branches such that the release switches are activated in the same sequence within the loop as the sampling switches.

Following the above, the present disclosure may provide for an interleaved switched capacitor circuit that samples and holds a wideband signal for virtually any amount of time delay. The circuit may be composed of a set of interleaved Field Effect Transistor, FET, switches, or any type of electronic switch, that sample and store the input signal on energy-storing components, for example sampling capacitors, to be released afterwards by multiplexed releasing FET switches, or any other type of electronic switches, causing a wideband programmable time delay for any input signal below Nyquist frequency. This circuit can be incorporated in a radio frequency receiver or transmitter. But eventually, it can be used to delay any type of signal, audio, video, etc.

Following the above, in other words, the pulses 1 to n are respectively provided to the sampling switches of the n branches following the sequence of the branches and in the loop, starting from one of the n branches, and the same pulses 1 to n are also respectively provided to the release switches of the n branches following the same sequence of the branches but starting from a different branch.

By starting from a different branch, a delay in the output signal is obtained.

Consider the situation in which n equals 4. This entails that there are 4 branches, numbered 1 to 4, wherein each branch has a sampling switch as well as a release switch. In accordance with the present disclosure, the sampling switches of the branches may be activated in a particular order, for example, first the sampling switch of branch 1 , followed by the sampling switch of branch 2, followed by the sampling switch of branch 3 and then followed by the sampling switch of branch 4. This process is continuously repeated. The order in which the sampling switches are activated corresponds to 1 - 2 - 3 - 4.

The release switches may be activated in the same order, but with a particular offset. For example, the release switch of branch 2 may be activated at the same time as the sampling switch of branch 1. This would lead to the following order 2 - 3 - 4 - 1 for the release switches.

The above may also be explained as follows. The rotating order in which the sample switches are activated may be kept fixed. The amount of delay that is required may be set by changing the circularly offset of the release switches. The release switches may be activated in the same rotating order as the sample switches, but with a different circularly offset. The circularly offset determines the delay that is obtained. So, let’s consider the situation in which the sample switches are activated as follows: 1 , 2, 3 ,4. In case of a 1 tau delay, the release switches may be activated as 4, 1 , 2, 3. In case of a 2 tau delay, the release switches may be activated as 3, 4, 1 , 2. In case of a 3 tau delay, the release switches may be activated as 2, 3, 4, 1.

In a further example, the controller is arranged to provide n non overlapping clock signals, wherein each of the n clock signals is provided to the sampling switch of the branch having the same sequence number as the respective one clock signal, and is also provided to the release switch of a different branch of the sequence of n branches such that the release switches are activated in the same sequence within the loop as the sampling switches.

The controller may, for example, have n output terminals, wherein each output terminal is arranged to provide for a clock signal. Each of these clock signals are non-overlapping. This entails that each clock signal has a duty cycle which may equal at most 1/n. It may be beneficial if the duty cycles of each of the clock signals are the same. This may ensure that each branch has the same transfer properties with respect to its input and its output.

Following the above, the circuit is based, at least partly, on the concept to sample an analogue input signal and to store it in a cascade of interconnected capacitors controlled by a set of complementary clocked switches. Every sample taken may be stored in a capacitor and passed on to the next capacitor as the signal evolves in time and the complementary clocks trigger the switches, just like water in a bucket-brigade manner, thus allowing for a clock-controllable analogue delay.

The circuit in accordance with the present disclosure may be provided using sub-micron CMOS technology. The advantages of sub-micron CMOS technology, i.e. faster and more energy efficient circuits, along with the use of n-path structure has allowed to create an interleaved switched capacitor circuit for wideband true time delay.

The invention may also be described as follows. The former serial connection known architectures is now split into interleaved N-path cells with their inputs and outputs lines combined. The input signal is sequentially sampled by the non-overlapping sampling switches and each sample is stored in the corresponding capacitor. At a non-sequential order, the release switches, SRN, are activated and the samples released with a certain delay. The order of which the release switches are activated along with the clock frequency sets the desired time delay.

In an example, one of:

the switches and the energy-storing components are integrated in a silicon die developed, for example, in CMOS 40 nm;

the switches and the energy-storing components are implemented as discrete components on a Printed Circuit Board, PCB. In a further example, the energy-storing components are any of capacitors, and/or inductors.

In a second aspect, there is provided a differential interleaved circuit comprising two interleaved circuits in accordance with any of the previous examples, wherein

each of the energy-storing components are connected, at one end, to a sampling switch and a release switch of a first of the two interleaved circuits, and at a second end, opposite to the first end, to a sampling switch and a release switch of a second of the two interleaved circuits.

The advantages and benefits as explained with respect to the examples provided with the first aspect of the present disclosure are also applicable to the second aspect of the present disclosure.

In a third aspect, there is provided an integrated circuit comprises an interleaved circuit in accordance with any of the examples as provided above.

In a fourth aspect, there is provided a method for operating an interleaved circuit in accordance with any of the examples as provided above, wherein the method comprises the steps of:

providing, by the controller, the clock signal, the clock signal having a sequence formed by a repetition of each time n pulses subsequently numbered pulse 1 to pulse n,

wherein the step of providing comprises that each one of the n pulses is provided to the sampling switch of the branch having the same sequence number as the respective one pulse, and is also provided to the release switch of a different branch of the sequence of n branches such that the release switches are activated in the same sequence within the loop as the sampling switches.

In a further example, the step of providing comprises:

providing, by the controller, n non-overlapping clock signals, wherein each of the n clock signals is provided to the sampling switch of the branch having the same sequence number as the respective one clock signal, and is also provided to the release switch of a different branch of the sequence of n branches such that the release switches are activated in the same sequence within the loop as the sampling switches. Typically, n = 4.

In yet another example, one of: the switches and the energy-storing components are integrated in a silicon die;

the switches and the energy-storing components are implemented as discrete components on a Printed Circuit Board, PCB.

In a further example, the energy-storing components are any of capacitors, and/or inductors or combinations thereof.

In a fifth aspect, there is provided a computer program product comprising a computer readable medium having instructions stored thereon which, when executed by a controller, cause the controller to implement a method in accordance with any of the examples as provided above.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Brief description of the Drawings

Figure 1 shows a known architecture based on a so called Bucket- Brigade Devices, BBD;

Figure 2 shows an interleaved circuit in accordance with the present disclosure;

Figure 3 shows a flow chart resulting from a method in accordance with the present disclosure;

Figure 4 shows an example of non-overlapping clock signals in accordance with the present disclosure;

Figure 5 shows an example of a differential interleaved circuit comprising two interleaved circuits in accordance with the present disclosure.

Detailed description

Figure 1 shows a known architecture 1 based on a so called Bucket- Brigade Devices, BBD.

The architecture 1 as shown in figure 1 resembles an analogue shift register. The boxes as indicated with reference numerals 2, 3, 4 and 5 may each comprise a switch for connecting the corresponding input capacitor to the output capacitor. The capacitors are indicated with reference numerals 6, 7, 8 and 9. For example, by activating the switch as indicated with reference numeral 2, the charge present in its input capacitor, being the one with reference numeral 6, flow to its output capacitor, being the one with reference numeral 7. This process is repeated until the charge is present in capacitor 10. Each of the switches 2, 3, 4, 5 are consecutively activated.

Following the above, a particular sample taken is stored in the first capacitor 6, and is then passed on to the next capacitor 7 as the signal evolves in time, and the complementary clocks triggers the switches 2, 3, 4, 5, just like water in a bucket-brigade manner, thus allowing for a clock controllable analogue delay.

Initially used to support analogue processing of video and audio signals by substituting bulky magnetic recording devices, BBD stopped being used due to its large losses and limited bandwidth created by charge sharing.

Figure 2 shows an interleaved circuit 21 in accordance with the present disclosure.

The Interleaved Circuit 21 is arranged for providing a delayed output signal from an input signal. The input signal is provided to the input of the circuit as indicated with “IN”. The output signal is provided by the output of the circuit as indicated with“OUT”.

In this particular example, the circuit 21 comprises four branches in a sequence of“Branch 1”,“Branch 2”,“Branch 3” and“Branch 4”, wherein each branch has an input and an output, wherein each branch comprises a sampling switch S1 , S2, S3 and S4 connected to the input“IN”, and a release switch S5, S6, S7 and S8 connected to its corresponding sampling switch S1 , S2, S3 and S4, and the output “OUT”.

Capacitors C1 , C2, C3 and C4 are provided between each of the switches S1 - S5, S2 - S6, S3 - S7 and S4 - S8, respectively. The capacitors C1 , C2, C3 and C4 may be dimensioned in such a way that they are able to hold a particular sample of the input signal. In this particular case, the capacitors C 1 , C2, C3 and C4 thus form the energy-storing components in accordance with the present disclosure.

A controller is provided for providing a clock signal. The controller may be implemented as an Integrated Circuit, an Application Specific Integrated Circuit, a Field Programmable Gate Array, or anything alike. The clock signal may have a sequence formed by a repetition of each time 4 pulses subsequently numbered pulse 1 to pulse 4. Here, following a repetitive loop along each of the branches each time following the sequence of the four branches from branch 1 to branch 4,

Each one of the 4 pulses is provided to the sampling of the branch having the same sequence number as the respective one pulse, and is also provided to the release switch of a different branch of the sequence of 4 branches such that the release switches are activated in the same sequence within the loop as the sampling switches. This process is explained in a bit more detail with respect to figure 3.

From direct analysis, the maximum available delay (TD-MAX) can be derived with respect to the clock period (Tc) and number of paths (N):

Analogously, the minimum available delay (TD-MIN) can be derived as:

Consequently, the delay range can virtually have any value from TD- MIN to TD-MAX by either setting the clock frequency and/or by changing the release order. Nevertheless, it may be of importance that the input signal to be lower than Nyquist frequency. In this way, all the input signal bellow Nyquist frequency will be delayed (substantially) equally.

As for the component values, the sampling nature of the circuit may require the sampling capacitor and the switches size to have an equivalent RC constant lower than half the active period of the switches, Ts.

The general transfer function of the described circuit can be derived from a single path discrete-time switched capacitor circuit:

where w_IN is the input angular frequency, V is the discrete-time signal on the sampling capacitor, V_IN is the input signal and RC is the constant due to the source resistance plus on-resistance of the switch and the capacitance of Cs_.

Combining the previous equation with multiplexing clock signal and simplifying it for T_S/RC » 0 and T_s « f_IN, the general transfer function for the interleaved switched capacitor circuit for wideband TTD as:

Thus, each term of the above described equation provides an insight on how to design the N-TTD:

1) the capacitor value and switches size (RC) determine the circuit bandwidth;

2) the insertion loss will be modulated by the proximity of the input frequency to the effective clock (Nfc);

3) the time delay range is only dependent on clock frequency, number of paths and release order.

Figure 3 shows a flow chart 31 resulting from a method in accordance with the present disclosure.

The flow chart 31 as indicated in figure 3 corresponds to the circuit as provided in figure 2.

Here, the input signal is given by“IN”, and three different output signals are provided as given by“OUT”. The first output signal has a time delay of 1 f, the second output signal has a time delay of 21 and the third output signal has a time delay of 31.

The input signal“IN” is sampled four times, as indicated with S1 , S2, S3 and S4. S1 means that the switch S1 is activated such that the sample taken is stored in the corresponding capacitor C1. S2 means that the switch S2 is activated such that the sample taken is stored in the corresponding capacitor C2. C3 means that the switch S3 is activated such that the sample taken is stored in the corresponding capacitor C3. C4 means that the switch S4 is activated such that the sample taken is stored in the corresponding capacitor C4.

Consider the first output signal, i.e. the one having a time delay of 1 f. Here it is shown that the switch S5 is activated at the same time as the switch S2, the switch S6 is activated at the same time as the switch S3 and the switch S7 is activated at the same time as S4. This, effectively, establishes a delay of one clock signal.

The scenarios as depicted with 2t and 3t effectively establish delay of two clock signals and three clock signals, respectively.

Figure 4 shows an example of non-overlapping clock signals 41 in accordance with the present disclosure.

The clock signals are shown may be used for a four branch types circuit in accordance with the present disclosure. The first clock signal, CLK1 , may be provided to S1 and S5, the second clock signal, CLK2, may be provided to S2 and S6, the third clock signal, CLK3, may be provided to S3 and S7 and the fourth clock signal, CLK4, may be provided to S4 and S8.

A differential true time delay circuit is an effective way to reduce DC offset and clock feedthrough. In order to keep symmetry for the clock distribution and transistors, the differential circuit is built by using 2 single ended circuits for each path, positive and negative. The capacitor from each path can be now shared in a differential way, which also makes the circuit more compact. Positive and Negative paths refer to a differential signal. Differential signals are characterised by two conductors (or path) with the same signal 180 degrees phase shifted. So that when an external interference affect both conductors, the difference between them will cancel the interference signal while amplifying the desired signal.

In conclusion, the present invention will enable wideband, low-power, low-area, high-performance true time delay for applications for which such systems are currently out of reach, such as many consumer applications, for example 5G & future mobile smartphones/smartwatches, laptops/tablets, autonomous cars & trucks, small aircrafts, drones, robots, smart buildings, etc. In addition, the wider band and smaller size might also be attractive for current professional/military applications.

Claims

1. A circuit arranged for providing a delayed output signal from an input signal, wherein the circuit comprises:

n branches in a sequence of branch 1 to n, each having an input and an output, wherein each branch comprises a sampling switch connected to the input, a release switch connected to the sampling switch and the output, and having an energy-storing component connected between the sampling switch and the release switch, wherein each of the branches are connected to each other via the respective inputs as well as via the respective outputs;

2. An Interleaved Circuit in accordance with claim 1 , wherein the controller is arranged to provide n non-overlapping clock signals, wherein each of the n clock signals is provided to the sampling switch of the branch having the same sequence number as the respective one clock signal, and is also provided to the release switch of a different branch of the sequence of n branches such that the release switches are activated in the same sequence within the loop as the sampling switches.

3. An interleaved Circuit in accordance with any of the previous claims, wherein n = 4.

4. An interleaved Circuit in accordance with any of the previous claims, wherein one of: the switches and the energy-storing components are integrated in a silicon die;

5. A circuit in accordance with any of the previous claims, wherein the energy-storing components are any of:

capacitors, and/or

inductors.

6. A differential interleaved circuit comprising two interleaved circuits in accordance with any of the previous claims, wherein

7. An integrated circuit comprising an interleaved circuit in accordance with any of the claims 1- 5.

8. A method for operating an interleaved circuit in accordance with any of the claims 1 - 5, wherein the method comprises the steps of:

9. A method in accordance with claim 8, wherein the step of providing comprises: providing, by the controller, n non-overlapping clock signals, wherein each of the n clock signals is provided to the sampling switch of the branch having the same sequence number as the respective one clock signal, and is also provided to the release switch of a different branch of the sequence of n branches such that the release switches are activated in the same sequence within the loop as the sampling switches.

10. A method in accordance with any of the claims 8 - 9, wherein n = 4.

1 1. A method in accordance with any of the claims 8 - 10, wherein one of:

the switches and the energy-storing components are integrated in a silicon die;

12. A method in accordance with any of the previous claims 8 - 1 1 , wherein, wherein the energy-storing components are any of:

capacitors, and/or

inductors.

13. A computer program product comprising a computer readable medium having instructions stored thereon which, when executed by a controller, cause the controller to implement a method in accordance with any of the claims 8 -

12.