WO2020072277A1 - Selectively etching for nanowires - Google Patents

Selectively etching for nanowires

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Publication number
WO2020072277A1
WO2020072277A1 PCT/US2019/053245 US2019053245W WO2020072277A1 WO 2020072277 A1 WO2020072277 A1 WO 2020072277A1 US 2019053245 W US2019053245 W US 2019053245W WO 2020072277 A1 WO2020072277 A1 WO 2020072277A1
Authority
WO
WIPO (PCT)
Prior art keywords
layers
silicon
respect
selectively
reactant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2019/053245
Other languages
French (fr)
Inventor
Jun XUE
Samantha SiamHwa Tan
Mohand BROURI
Yuanhui Li
Daniel Peter
Alexander Kabansky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Priority to CN201980064886.7A priority Critical patent/CN112789710B/en
Priority to KR1020217013323A priority patent/KR20210055785A/en
Priority to US17/280,065 priority patent/US11521860B2/en
Priority to KR1020267009333A priority patent/KR20260046253A/en
Publication of WO2020072277A1 publication Critical patent/WO2020072277A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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    • H10P50/00—Etching of wafers, substrates or parts of devices
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    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
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    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
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    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
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    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
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    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
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    • H10D30/01—Manufacture or treatment
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    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2

Definitions

  • the disclosure relates to methods of forming semiconductor devices on a semiconductor wafer. More specifically, the disclosure relates to the selective etching of nano wires.
  • nano wires may be formed by selectively etching silicon germanium (SiGe) with respect to silicon (Si). Nanowires may also be formed by selectively etching Si with respect to SiGe.
  • a method for selectively etching layers of a first material with respect to layers of a second material in a stack, wherein layers of the first material alternate with layers of the second material is provided.
  • the layers of the first material are partially etched with respect to the layers of the second material.
  • a deposition layer is selectively deposited on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions of the deposition layer covering the layers of the first material, the selective depositing comprising providing a first reactant, wherein some of the first reactant deposits on the stack, purging some of the first reactant, wherein some undeposited first reactant is not purged, and providing a second reactant, wherein the undeposited first reactant combines with the second reactant, wherein the combined undeposited first reactant and second reactant selectively deposits on the layers of the second material with respect to the layers of the first material, and wherein some of the second reactant reacts with the deposited first reactant to form part of the deposition layer.
  • the layers of the first material are selectively etched with respect to the layers of the second material to completely remove the layers of the first material, wherein the layers of the second material are protected by the deposition layer.
  • a method for selectively etching silicon germanium with respect to silicon in a stack wherein at least one layer of silicon germanium is between two layers of silicon is provided.
  • the silicon germanium is partially etched with respect to silicon.
  • the stack is coated with a selective deposition process, wherein the selective deposition process deposits more on silicon than silicon germanium.
  • the selective deposition process comprises providing a silicon precursor, wherein some of the silicon precursor deposits on the stack, purging some of the silicon precursor, wherein some undeposited silicon precursor remains, providing an oxidizing gas, wherein the undeposited silicon precursor combines with the oxidizing gas to form undeposited silicon oxide, wherein the undeposited silicon oxide nonconformally and preferentially deposits on silicon with respect to the silicon germanium, and wherein some of the oxidizing gas oxidizes the deposited silicon precursor to transform the deposited silicon precursor into silicon oxide.
  • the silicon germanium is selectively etched with respect to the silicon oxide to completely remove the silicon germanium.
  • a method for selectively etching silicon with respect to silicon germanium in a stack wherein at least one layer of silicon is between two layers of silicon germanium is provided.
  • the silicon is partially etched with respect to the silicon germanium.
  • the stack is coated with a selective deposition process, wherein the selective deposition process deposits more on silicon germanium than silicon.
  • the selective deposition process comprises providing a silicon precursor, wherein some of the silicon precursor deposits on the stack, purging some of the silicon precursor, wherein some undeposited silicon precursor remains, providing an oxidizing gas, wherein the undeposited silicon precursor combines with the oxidizing gas to form undeposited silicon oxide, wherein the undeposited silicon oxide nonconformally and preferentially deposits on the silicon germanium with respect to the silicon, and wherein some of the oxidizing gas oxidizes the deposited silicon precursor to transform the deposited silicon precursor into silicon oxide.
  • the silicon is selectively etched with respect to the silicon oxide to completely remove the silicon.
  • FIG. 1 is a high level flow chart of an embodiment.
  • FIGS. 2A-D are schematic cross-sectional views of a stack processed according to an embodiment.
  • FIG. 3 is a more detailed flow chart of a selective etch process.
  • FIG. 4 is a more detailed flow chart of a selective deposition process.
  • FIGS. 5A-D are schematic cross-sectional views of a stack processed according to another embodiment.
  • FIG. 6 is a schematic view of a process chamber that may be used in an embodiment.
  • FIG. 7 is a schematic view of a computer system that may be used in practicing an embodiment.
  • FIG. 1 is a high level flow chart of an embodiment.
  • a stack of alternating layers of a first material and a second material is selectively etched to form recessed layers of the first material (step 104).
  • the first material is SiGe and the second material is Si.
  • FIG. 2A is a schematic cross- sectional view of part of a stack 200 on a wafer.
  • the stack 200 comprises a first Si layer 208 adjacent to a first SiGe layer 212 on a first side of the first SiGe layer 212.
  • the first SiGe layer 212 is adjacent to a second Si layer 216 on a second side of the first SiGe layer 212.
  • the first Si layer 208 and the second Si layer 216 are on opposite sides of the first SiGe layer 212.
  • a second SiGe layer 220 is adjacent to the second Si layer 216.
  • the second Si layer 216 is on a first side of the second SiGe layer 220.
  • the first SiGe layer 212 and the second SiGe layer 220 are on opposite sides of the second Si layer 216.
  • the second SiGe layer 220 is adjacent to a third Si layer 224 on a second side of the second SiGe layer 220.
  • the second Si layer 216 and the third Si layer 224 are on opposite sides of the second SiGe layer 220.
  • the Si layers 208, 216, 224 and SiGe layers 212, 220 may extend between and be connected to electrical contacts or other structures (not shown). If the SiGe layers 212, 220 are selectively etched away, then the Si layers 208, 216, 224 remain extending between the electrical contacts and may be used as nanowires. Similarly, if the Si layers 208, 216, 224 are selectively etched away, then the SiGe layers 212, 220 remain extending between the electrical contacts and may be used as nanowires. The dimensions of the Si layers 208, 216, 224 and SiGe layers 212, 220 are so small that the etch should be highly selective. The Si layers 208, 216, 224 and SiGe layers 212, 220 may be horizontal layers or vertical layers or provide layers that are at other angles.
  • the stack is partially selectively etched to form recessed layers (step 104).
  • the first SiGe layer 212 and the second SiGe layer 220 are partially selectively etched with respect to the first Si layer 208, the second Si layer 216, and the third Si layer 224.
  • the etch is an atomic layer etch (ALE) using a cyclic etch process.
  • FIG. 3 is a more detailed flow chart of the selective partial etch to form recessed layers (step 104) using an ALE.
  • the ALE is shown as at least one cycle.
  • Each cycle of the ALE process comprises an oxidation phase (step 312), a first purge (step 316), an etch phase (step 320), and a second purge (step 324).
  • the stack 200 is exposed to an oxidation gas, such as 0 2 , for about 2 seconds.
  • the oxidization causes an outer surface of the first Si layer 208, the second Si layer 216, and the third Si layer 224 to oxidize forming a silicon oxide (Si0 2 ) layer on the surfaces of the first Si layer 208, the second Si layer 216, and the third Si layer 224.
  • the oxidation gas is purged during the first purge (step 316).
  • a purge gas such as nitrogen (N 2 ) may be used to purge the oxidation gas.
  • the stack 200 is exposed to an etch gas, such as carbon tetrafluoride (CF 4 ).
  • CF 4 carbon tetrafluoride
  • the CF 4 selectively etches SiGe with respect to SiCF-
  • a second purge (step 324) provides a purge gas to purge the etch gas.
  • the purge gas is N 2 .
  • the ALE process is performed for 7-10 cycles.
  • FIG. 2B is a cross-sectional view of the stack 200 after the first SiGe layer 212 and the second SiGe layer 220 are partially selectively etched with respect to the first Si layer 208, the second Si layer 216, and the third Si layer 224. All of the layers are etched. However, the first and second SiGe layers 212, 220 are etched more than the first, second, and third Si layers 208, 216, 224. In this example, the ratio of the etching of the first and second SiGe layers 212, 220 with respect to the first, second, and third Si layers 208, 216. 224 is about 9:1. The etching of the layers is not drawn to scale. This creates a dip 228 or recess transitioning from the first Si layer 208 to the first SiGe layer 212.
  • FIG. 4 is a more detailed flow chart of the selective deposition process (step 108).
  • the selective deposition process (step 108) comprises at least one cycle of providing a first reactant (step 412), providing a partial purge (step 414), providing a second reactant (step 416), and providing a second purge (step 418).
  • the first reactant is provided to the stack 200 (step 412).
  • the first reactant is a liquid silicon containing precursor.
  • the precursor is vaporized and delivered in vapor form to the stack 200.
  • the vapor doses the stack 200 to saturation, forming a layer of precursor over the stack 200.
  • the precursor has a composition of the general type C(x)H(y)N(z)0(a)Si(b).
  • the precursor has one of the following compositions: N,N,N',N',N",N"- Hexamethylsilanetriamine (CyFLyNySi, C8H22N2S1), (3-Aminopropyl)triethoxysilane (C9H23NO3S1), and Tetra(isopropoxy)silane (Ci2H2s0 4 Si).
  • the precursor comprises Bis(tert-butylamino) silane (CxFL N SiKBTB AS).
  • the providing of the precursor is plasmaless.
  • the precursor has a silicon function group.
  • the silicon function group forms a monolayer on the stack 200, since the precursor does not attach to another precursor.
  • a partial purge step is provided (step 414) to purge out some of the undeposited precursors that linger in a process chamber.
  • N 2 may be used as the purge gas for the partial purge (step 414). Some of the undeposited precursors may remain in the process chamber.
  • a second reactant is provided (step 416).
  • the providing the second reactant comprises providing a second reactant gas comprising 1000 seem to 2000 seem oxygen (0 2 ) to the process chamber.
  • the second reactant is an oxidizing gas.
  • a power of 500 to 3000 watts is delivered at 13.56 MHz to form the second reactant gas into a plasma.
  • a pressure of 20 mTorr to 100 mTorr is provided.
  • Some of the second reactant gas combines with the undeposited first reactant.
  • the oxidizing gas and the undeposited silicon precursor form undeposited silicon oxide (Si0 2 ).
  • the undeposited silicon oxide selectively deposits on the stack 200 to provide a nonconformal deposition.
  • the oxidizing gas oxidizes the deposited silicon precursor, forming a conformal atomic layer deposition (ALD) layer on the stack 200.
  • the process chamber is purged (step 418).
  • N 2 may be used as the purge gas.
  • the cycle may then be repeated. In this example, the cycle is repeated from 3 to 15 times.
  • FIG. 2C is a cross-sectional view of the stack 200 after a selective deposition layer 232 has been deposited (step 108).
  • the selective deposition layer 232 forms a thicker layer over the first, second, and third Si layers 208, 216, 224 than over the first and second SiGe layers 212, 220.
  • the deposition layer 232 forms a coating over the stack 200. Without being bound by theory, it is believed that the selective deposition process (step 108) deposits less on recessed regions. One reason may be that the selective deposition process (step 108) deposits less on the recessed layers due to curvature created by the dip 228.
  • the thickness of the selective deposition layer 232 is not drawn to scale, but is enlarged for better clarity and illustration.
  • the recessed layers are selectively etched (step 112).
  • an atomic layer etch process is used to selectively etch the first SiGe layer 212 and the second SiGe layer 220 with respect to the first Si layer 208, the second Si layer 216, and the third Si layer 224.
  • the atomic layer etch process recipe used for partially selectively etching the stack 200 to form recessed layers (step 104) may be used for selectively etching the recessed layers (step 112).
  • FIG. 2D is a cross-sectional view of the stack 200 after the first and second SiGe layers 212, 220 are completely etched away.
  • the resulting Si layers 208, 216, 224 may be used as horizontal nanowires for n-type metal-oxide-semiconductor (NMOS) devices.
  • NMOS metal-oxide-semiconductor
  • the Si layers 208, 216, 224 may be suspended between the electrical contact structures.
  • This embodiment provides an etch selectivity greater than 20:1 for etching SiGe with respect to Si.
  • less than 5A of Si is lost due to oxidation or etching during the process.
  • This embodiment selectively etches SiGe with respect to silicon oxide (S1O 2 ) and silicon nitride (SiN) with a selectivity of greater than 100:1.
  • the etch gas comprises a fluorine containing component.
  • the fluorine containing component is a fluorocarbon, such as CF 4 , hexafluoro-2-butyne (C 4 Fe), octafluorocyclobutane (C 4 F 8 ), or hydrofluorocarbon, such as fluoroform (CHF 3 ) or difluoromethane (CH 2 F 2 ).
  • the etch gas has a total flow per etch gas molecule.
  • the fluorine containing gas comprises fluorine, wherein the fluorine has a fluorine flow per fluorine atom.
  • a ratio of the total flow of the etch gas per etch gas molecule to the fluorine flow per fluorine atom is between 1000:1 to 5:1.
  • the etch gas was 45 seem CF 4 , 1000 seem Ar, and 1000 seem He.
  • the flow rate of fluorine atoms is 180 seem.
  • the total flow rate of all molecules of the etch gas is 2045 seem.
  • the ratio of the total flow rate of the etch gas to the flow rate of fluorine atoms is 2045:180, which is about 11:1.
  • one or more inert gases such as noble gases are added to the etch gas.
  • the selective deposition layer 232 is completely removed.
  • a protection layer may be deposited around the resulting Si layers 208,
  • the protection layer may be formed by an atomic layer deposition process that deposits a silicon containing layer.
  • a silicon containing layer may be a silicon oxide or silicon nitride layer.
  • the protective layer prevents the resulting Si layers 208, 216, 224 from oxidizing. The oxidation of the resulting Si layers 208, 216, 224 would further diminish the silicon layers. As a result, the etch would be even less selective.
  • FIG. 5 A is a schematic cross-sectional view of part of a stack 500 on a wafer.
  • the stack 500 comprises a first SiGe layer 508 adjacent to a first Si layer 512 on a first side of the first Si layer 512.
  • the first Si layer 512 is adjacent to a second SiGe layer 516 on a second side of the first Si layer 512.
  • the first SiGe layer 508 and the second SiGe layer 516 are on opposite sides of the first Si layer 512.
  • a second Si layer 520 is adjacent to the second SiGe layer 516.
  • the second SiGe layer 516 is on a first side of the second Si layer 520.
  • the first Si layer 512 and the second Si layer 520 are on opposite sides of the second SiGe layer 516.
  • the second Si layer 520 is adjacent to a third SiGe layer 524 on a second side of the second Si layer 520.
  • the second SiGe layer 516 and the third SiGe layer 524 are on opposite sides of the second Si layer 520.
  • the SiGe layers 508, 516, 524 and Si layers 512, 520 may extend between and be connected to electrical contacts or other structures (not shown).
  • the stack 500 is partially selectively etched to form recessed layers (step 104).
  • the first Si layer 512 and the second Si layer 520 are partially selectively etched with respect to the first SiGe layer 508, the second SiGe layer 516, and the third SiGe layer 524.
  • An example recipe for such a selective etch comprises providing an etch gas comprising 10 seem CF 4 , 100 seem hydrogen (H 2 ), 1000 seem Ar, and 1000 seem He.
  • a small flow of sulfur hexafluoride (SF 6 ) or hydrogen sulfide (H 2 S) (0-100 seem) may be added to improve selectivity.
  • the etch gas is transformed into a plasma. The plasma selectively etches Si with respect to SiGe.
  • FIG. 5B is a cross-sectional view of the stack 500 after the first Si layer 512 and the second Si layer 520 are partially selectively etched with respect to the first SiGe layer 508, the second SiGe layer 516, and the third SiGe layer 524. All of the layers are etched. However, the first and second Si layers 512, 520 are etched more than the first, second, and third SiGe layers 508, 516, 524. This creates a dip 528 or recess transitioning from the first SiGe layer 508 to the first Si layer 512.
  • FIG. 4 is a more detailed flow chart of the selective deposition process (step 108).
  • the selective deposition process (step 108) comprises at least one cycle of providing a first reactant (step 412), providing a partial purge (step 414), providing a second reactant (step 416), and providing a second purge (step 418).
  • the first reactant is provided to the stack 500 (step 412). In this case
  • the first reactant is a liquid silicon containing precursor.
  • the liquid silicon containing precursor is vaporized and delivered in vapor form to the stack 500.
  • the liquid silicon containing precursor doses the stack 500 to saturation, forming a layer of precursor over the stack 500.
  • the precursor comprises Bis(tert-butylamino) silane (CsF ⁇ SiXBTBAS).
  • the providing of the precursor is plasmaless.
  • the first reactant is a silicon precursor.
  • the precursor has a silicon function group. The silicon function group forms a monolayer on the stack 500 since the precursor does not attach to another precursor.
  • step 4114 a partial purge step is provided (step 414) to purge out some of the undeposited precursors that linger in the process chamber. Some of the undeposited precursors may remain in the process chamber.
  • a second reactant is provided (step 416).
  • the providing the second reactant comprises providing a second reactant gas comprising 1000 seem to 2000 seem oxygen (0 2 ) to the process chamber.
  • the second reactant is an oxidizing gas.
  • a power of 500 to 3000 watts is delivered at 13.56 MHz to form the second reactant gas into a plasma.
  • a pressure of 20 mTorr to 100 mTorr is provided.
  • Some of the second reactant gas combines with the undeposited first reactant.
  • the oxidizer gas and the undeposited silicon precursor form undeposited silicon oxide.
  • the undeposited silicon oxide selectively deposits on the stack 500 to provide a nonconformal deposition.
  • the oxidizer gas oxidizes the deposited silicon precursor, forming a conformal ALD layer on the stack 500.
  • the process chamber is purged (step 418). The cycle may then be repeated. In this example, the cycle is repeated from 3 to 12 times.
  • FIG. 5C is a cross-sectional view of the stack 500 after a selective deposition layer 532 has been deposited.
  • the selective deposition layer 532 forms a thicker layer over the first, second, and third SiGe layers 508, 516, 524 than over the first and second Si layers 512, 520.
  • the thickness of the selective deposition layer 532 is not drawn to scale but is enlarged for better clarity and illustration.
  • the recessed layers are selectively etched (step 112).
  • the first Si layer 512 and the second Si layer 520 are selectively etched with respect to the first SiGe layer 508, the second SiGe layer 516, and the third SiGe layer 524.
  • An example recipe for such a selective etch comprises providing an etch gas comprising 10 seem CF 4 , 100 seem FF, 1000 seem Ar, and 1000 seem He.
  • a small flow of sulfur hexafluoride (SF 6 ) or hydrogen sulfide ( FFS) (0-100 seem) may be added to improve selectivity.
  • the etch gas is transformed into a plasma. The plasma selectively etches Si with respect to SiGe.
  • the selective deposition layer 532 covering the SiGe layers 508, 516, 524 is not thick enough so that these layers 508, 516, 524 are protected from the selective etching before the first and second Si layers 512, 520 are completely etched away.
  • another selective deposition process is provided (step 108) and then the first and second Si layers 512, 520 are completely etched away (step 112).
  • FIG. 5D is a cross-sectional view of the stack 500 after the first and second Si layers 512, 520 are completely etched away.
  • the resulting SiGe layers 508, 516, 524 may be used as horizontal nanowires for p-type metal-oxide-semiconductor (PMOS) devices.
  • PMOS metal-oxide-semiconductor
  • This embodiment provides an etch selectivity greater than 20:1 for etching Si with respect to SiGe.
  • less than 5A of SiGe is lost due to oxidation or etching during the process.
  • This embodiment selectively etches Si with respect to silicon oxide (Si0 2 ) and silicon nitride (SiN) with a selectivity of greater than 100:1.
  • an etch gas comprising SF 6 and FF may be used.
  • the fluorine from SF 6 may be tied up by the hydrogen as hydrogen fluoride (HF), and SF may be used to passivate Ge in the form of Ge-F, which can help to further passivate SiGe wire.
  • the etch gas may comprise fluorocarbons, SF 6, and 3 ⁇ 4S or sulfur- containing gases with 3 ⁇ 4.
  • a CF 4 to hF ratio is between 1:1 - 1: 500.
  • FIG. 6 is a schematic view of a process chamber 600 which may be used in an embodiment.
  • the process chamber 600 comprises a showerhead 606 providing a gas inlet and an electrostatic chuck (ESC) 608, within a reactor chamber 610, enclosed by a chamber wall 612.
  • ESC electrostatic chuck
  • a gas source 616 is connected to a remote plasma generator 620.
  • the remote plasma generator 620 is connected to the reactor chamber 610 through the showerhead 606.
  • a radio frequency (RF) source 630 provides RF power at one or more frequencies of 27 megahertz (MHz), 13.56 MHz, 60 MHz, 2 MHz, or 400 kHz to the remote plasma generator 620, an upper electrode provided by the showerhead 606, or a lower electrode, provided by the ESC 608.
  • the RF source 630 may provide power to coils.
  • the RF power is used to create an inductively coupled plasma.
  • a chuck temperature controller 640 controls a chiller 644.
  • the chiller 644 cools a coolant 648.
  • the coolant 648 is provided to a chuck cooling system 650.
  • a controller 635 is controllably connected to the RF source 630, an exhaust pump 652, the chuck temperature controller 640, and the gas source 616.
  • FIG. 7 is a high level block diagram showing a computer system 700, which is suitable for implementing a controller 635 used in embodiments.
  • the computer system 700 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer.
  • the computer system 700 includes one or more processors 702, and further can include an electronic display device 704 (for displaying graphics, text, and other data), a main memory 706 (e.g., random access memory (RAM)), storage device 708 (e.g., hard disk drive), removable storage device 710 (e.g., optical disk drive), user interface devices 712 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 714 (e.g., wireless network interface).
  • the communications interface 714 allows software and data to be transferred between the computer system 700 and external devices via a link.
  • the system may also include a communications infrastructure 716 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices/modules are connected.
  • a communications infrastructure 716 e.g., a communications bus, cross-over bar, or network
  • Information transferred via communications interface 714 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 714, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communications channels.
  • a communications interface 714 it is contemplated that the one or more processors 702 might receive information from a network, or might output information to the network in the course of performing the above-described method steps.
  • method embodiments may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.
  • non-transient computer readable medium is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals.
  • Examples of computer code include machine code, such as produced by a compiler, and files containing higher- level code that are executed by a computer using an interpreter.
  • Computer readable media may also be computer code transmitted by a computer data signal a processor.

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Abstract

A method for selectively etching layers of a first material with respect to layers of a second material in a stack is provided. The layers of the first material are partially etched with respect to the layers of the second material. A deposition layer is selectively deposited on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions covering the layers of the first material, the selective depositing comprising providing a first reactant, purging some of the first reactant, wherein some undeposited first reactant is not purged, and providing a second reactant, wherein the undeposited first reactant combines with the second reactant and selectively deposits on the layers of the second material with respect to the layers of the first material. The layers of the first material are selectively etched with respect to the layers of the second material.

Description

SELECTIVELY ETCHING FOR NANO WIRES
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of priority of U.S. Application No. 62/740,806, filed October 3, 2018, which is incorporated herein by reference for all purposes.
BACKGROUND
[0002] The disclosure relates to methods of forming semiconductor devices on a semiconductor wafer. More specifically, the disclosure relates to the selective etching of nano wires.
[0003] In forming semiconductor devices, nano wires may be formed by selectively etching silicon germanium (SiGe) with respect to silicon (Si). Nanowires may also be formed by selectively etching Si with respect to SiGe.
SUMMARY
[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method for selectively etching layers of a first material with respect to layers of a second material in a stack, wherein layers of the first material alternate with layers of the second material is provided. The layers of the first material are partially etched with respect to the layers of the second material. A deposition layer is selectively deposited on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions of the deposition layer covering the layers of the first material, the selective depositing comprising providing a first reactant, wherein some of the first reactant deposits on the stack, purging some of the first reactant, wherein some undeposited first reactant is not purged, and providing a second reactant, wherein the undeposited first reactant combines with the second reactant, wherein the combined undeposited first reactant and second reactant selectively deposits on the layers of the second material with respect to the layers of the first material, and wherein some of the second reactant reacts with the deposited first reactant to form part of the deposition layer. The layers of the first material are selectively etched with respect to the layers of the second material to completely remove the layers of the first material, wherein the layers of the second material are protected by the deposition layer. [0005] In another manifestation, a method for selectively etching silicon germanium with respect to silicon in a stack wherein at least one layer of silicon germanium is between two layers of silicon is provided. The silicon germanium is partially etched with respect to silicon. The stack is coated with a selective deposition process, wherein the selective deposition process deposits more on silicon than silicon germanium. The selective deposition process comprises providing a silicon precursor, wherein some of the silicon precursor deposits on the stack, purging some of the silicon precursor, wherein some undeposited silicon precursor remains, providing an oxidizing gas, wherein the undeposited silicon precursor combines with the oxidizing gas to form undeposited silicon oxide, wherein the undeposited silicon oxide nonconformally and preferentially deposits on silicon with respect to the silicon germanium, and wherein some of the oxidizing gas oxidizes the deposited silicon precursor to transform the deposited silicon precursor into silicon oxide. The silicon germanium is selectively etched with respect to the silicon oxide to completely remove the silicon germanium.
[0006] In another manifestation, a method for selectively etching silicon with respect to silicon germanium in a stack, wherein at least one layer of silicon is between two layers of silicon germanium is provided. The silicon is partially etched with respect to the silicon germanium. The stack is coated with a selective deposition process, wherein the selective deposition process deposits more on silicon germanium than silicon. The selective deposition process comprises providing a silicon precursor, wherein some of the silicon precursor deposits on the stack, purging some of the silicon precursor, wherein some undeposited silicon precursor remains, providing an oxidizing gas, wherein the undeposited silicon precursor combines with the oxidizing gas to form undeposited silicon oxide, wherein the undeposited silicon oxide nonconformally and preferentially deposits on the silicon germanium with respect to the silicon, and wherein some of the oxidizing gas oxidizes the deposited silicon precursor to transform the deposited silicon precursor into silicon oxide. The silicon is selectively etched with respect to the silicon oxide to completely remove the silicon.
[0007] These and other features of the present disclosure will be described in more details below in the detailed description and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
[0009] FIG. 1 is a high level flow chart of an embodiment.
[0010] FIGS. 2A-D are schematic cross-sectional views of a stack processed according to an embodiment.
[0011] FIG. 3 is a more detailed flow chart of a selective etch process.
[0012] FIG. 4 is a more detailed flow chart of a selective deposition process.
[0013] FIGS. 5A-D are schematic cross-sectional views of a stack processed according to another embodiment.
[0014] FIG. 6 is a schematic view of a process chamber that may be used in an embodiment.
[0015] FIG. 7 is a schematic view of a computer system that may be used in practicing an embodiment.
DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
[0016] The present disclosure will now be described in detail with reference to a few exemplary embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.
[0017] FIG. 1 is a high level flow chart of an embodiment. In this embodiment, a stack of alternating layers of a first material and a second material is selectively etched to form recessed layers of the first material (step 104). In this example, the first material is SiGe and the second material is Si. FIG. 2A is a schematic cross- sectional view of part of a stack 200 on a wafer. In this embodiment, the stack 200 comprises a first Si layer 208 adjacent to a first SiGe layer 212 on a first side of the first SiGe layer 212. The first SiGe layer 212 is adjacent to a second Si layer 216 on a second side of the first SiGe layer 212. The first Si layer 208 and the second Si layer 216 are on opposite sides of the first SiGe layer 212. A second SiGe layer 220 is adjacent to the second Si layer 216. The second Si layer 216 is on a first side of the second SiGe layer 220. The first SiGe layer 212 and the second SiGe layer 220 are on opposite sides of the second Si layer 216. The second SiGe layer 220 is adjacent to a third Si layer 224 on a second side of the second SiGe layer 220. The second Si layer 216 and the third Si layer 224 are on opposite sides of the second SiGe layer 220.
[0018] The Si layers 208, 216, 224 and SiGe layers 212, 220 may extend between and be connected to electrical contacts or other structures (not shown). If the SiGe layers 212, 220 are selectively etched away, then the Si layers 208, 216, 224 remain extending between the electrical contacts and may be used as nanowires. Similarly, if the Si layers 208, 216, 224 are selectively etched away, then the SiGe layers 212, 220 remain extending between the electrical contacts and may be used as nanowires. The dimensions of the Si layers 208, 216, 224 and SiGe layers 212, 220 are so small that the etch should be highly selective. The Si layers 208, 216, 224 and SiGe layers 212, 220 may be horizontal layers or vertical layers or provide layers that are at other angles.
[0019] In an exemplary embodiment, the stack is partially selectively etched to form recessed layers (step 104). In this embodiment, the first SiGe layer 212 and the second SiGe layer 220 are partially selectively etched with respect to the first Si layer 208, the second Si layer 216, and the third Si layer 224. In this example, the etch is an atomic layer etch (ALE) using a cyclic etch process. FIG. 3 is a more detailed flow chart of the selective partial etch to form recessed layers (step 104) using an ALE.
The ALE is shown as at least one cycle. Each cycle of the ALE process comprises an oxidation phase (step 312), a first purge (step 316), an etch phase (step 320), and a second purge (step 324).
[0020] In an example, during the oxidation phase (step 312), the stack 200 is exposed to an oxidation gas, such as 02, for about 2 seconds. The oxidization causes an outer surface of the first Si layer 208, the second Si layer 216, and the third Si layer 224 to oxidize forming a silicon oxide (Si02) layer on the surfaces of the first Si layer 208, the second Si layer 216, and the third Si layer 224. The oxidation gas is purged during the first purge (step 316). A purge gas, such as nitrogen (N2) may be used to purge the oxidation gas. During the etch phase (step 320), the stack 200 is exposed to an etch gas, such as carbon tetrafluoride (CF4). The CF4 selectively etches SiGe with respect to SiCF- A second purge (step 324) provides a purge gas to purge the etch gas. In this example, the purge gas is N2. In this example, the ALE process is performed for 7-10 cycles.
[0021] FIG. 2B is a cross-sectional view of the stack 200 after the first SiGe layer 212 and the second SiGe layer 220 are partially selectively etched with respect to the first Si layer 208, the second Si layer 216, and the third Si layer 224. All of the layers are etched. However, the first and second SiGe layers 212, 220 are etched more than the first, second, and third Si layers 208, 216, 224. In this example, the ratio of the etching of the first and second SiGe layers 212, 220 with respect to the first, second, and third Si layers 208, 216. 224 is about 9:1. The etching of the layers is not drawn to scale. This creates a dip 228 or recess transitioning from the first Si layer 208 to the first SiGe layer 212.
[0022] A layer is selectively deposited on nonrecessed layers of the stack 200 (step 108). FIG. 4 is a more detailed flow chart of the selective deposition process (step 108). The selective deposition process (step 108) comprises at least one cycle of providing a first reactant (step 412), providing a partial purge (step 414), providing a second reactant (step 416), and providing a second purge (step 418).
[0023] The first reactant is provided to the stack 200 (step 412). In this embodiment, the first reactant is a liquid silicon containing precursor. The precursor is vaporized and delivered in vapor form to the stack 200. The vapor doses the stack 200 to saturation, forming a layer of precursor over the stack 200. In this example, the precursor has a composition of the general type C(x)H(y)N(z)0(a)Si(b). In some embodiments, the precursor has one of the following compositions: N,N,N',N',N",N"- Hexamethylsilanetriamine (CyFLyNySi, C8H22N2S1), (3-Aminopropyl)triethoxysilane (C9H23NO3S1), and Tetra(isopropoxy)silane (Ci2H2s04Si). In this example, the precursor comprises Bis(tert-butylamino) silane (CxFL N SiKBTB AS). In this example, the providing of the precursor is plasmaless. The precursor has a silicon function group. The silicon function group forms a monolayer on the stack 200, since the precursor does not attach to another precursor.
[0024] Once the stack 200 is dosed with the precursor, the delivery of the precursor vapor is stopped. Then a partial purge step is provided (step 414) to purge out some of the undeposited precursors that linger in a process chamber. N2 may be used as the purge gas for the partial purge (step 414). Some of the undeposited precursors may remain in the process chamber.
[0025] A second reactant is provided (step 416). In this embodiment, the providing the second reactant comprises providing a second reactant gas comprising 1000 seem to 2000 seem oxygen (02) to the process chamber. In this example, the second reactant is an oxidizing gas. In this example, a power of 500 to 3000 watts is delivered at 13.56 MHz to form the second reactant gas into a plasma. A pressure of 20 mTorr to 100 mTorr is provided. Some of the second reactant gas combines with the undeposited first reactant. In this example, the oxidizing gas and the undeposited silicon precursor form undeposited silicon oxide (Si02). The undeposited silicon oxide selectively deposits on the stack 200 to provide a nonconformal deposition. In addition, the oxidizing gas oxidizes the deposited silicon precursor, forming a conformal atomic layer deposition (ALD) layer on the stack 200. After the deposition is completed, the process chamber is purged (step 418). N2 may be used as the purge gas. The cycle may then be repeated. In this example, the cycle is repeated from 3 to 15 times.
[0026] FIG. 2C is a cross-sectional view of the stack 200 after a selective deposition layer 232 has been deposited (step 108). The selective deposition layer 232 forms a thicker layer over the first, second, and third Si layers 208, 216, 224 than over the first and second SiGe layers 212, 220. The deposition layer 232 forms a coating over the stack 200. Without being bound by theory, it is believed that the selective deposition process (step 108) deposits less on recessed regions. One reason may be that the selective deposition process (step 108) deposits less on the recessed layers due to curvature created by the dip 228. The thickness of the selective deposition layer 232 is not drawn to scale, but is enlarged for better clarity and illustration.
[0027] Referring back to FIG. 1 , the recessed layers are selectively etched (step 112). In this embodiment, an atomic layer etch process is used to selectively etch the first SiGe layer 212 and the second SiGe layer 220 with respect to the first Si layer 208, the second Si layer 216, and the third Si layer 224. The atomic layer etch process recipe used for partially selectively etching the stack 200 to form recessed layers (step 104) may be used for selectively etching the recessed layers (step 112).
In this example, the selective deposition layer 232 covering the Si layers 208, 216,
224 is thick enough so that these layers 208, 216, 224 are protected from the selective etching before the first and second SiGe layers 212, 220 are completely etched away.
[0028] FIG. 2D is a cross-sectional view of the stack 200 after the first and second SiGe layers 212, 220 are completely etched away. The resulting Si layers 208, 216, 224 may be used as horizontal nanowires for n-type metal-oxide-semiconductor (NMOS) devices. In such devices, the Si layers 208, 216, 224 may be suspended between the electrical contact structures. This embodiment provides an etch selectivity greater than 20:1 for etching SiGe with respect to Si. In addition, less than 5A of Si is lost due to oxidation or etching during the process. This embodiment selectively etches SiGe with respect to silicon oxide (S1O2) and silicon nitride (SiN) with a selectivity of greater than 100:1.
[0029] In various embodiments the etch gas comprises a fluorine containing component. In various embodiments, the fluorine containing component is a fluorocarbon, such as CF4, hexafluoro-2-butyne (C4Fe), octafluorocyclobutane (C4F8), or hydrofluorocarbon, such as fluoroform (CHF3) or difluoromethane (CH2F2). In various embodiments, the etch gas has a total flow per etch gas molecule. The fluorine containing gas comprises fluorine, wherein the fluorine has a fluorine flow per fluorine atom. A ratio of the total flow of the etch gas per etch gas molecule to the fluorine flow per fluorine atom is between 1000:1 to 5:1. For example, in the above embodiment, the etch gas was 45 seem CF4, 1000 seem Ar, and 1000 seem He. In this example, since there are 4 fluorine atoms in CF4 the flow rate of fluorine atoms is 180 seem. The total flow rate of all molecules of the etch gas is 2045 seem.
Therefore, the ratio of the total flow rate of the etch gas to the flow rate of fluorine atoms is 2045:180, which is about 11:1. In order to lower the percentage of fluorine atoms compared to the total etch gas flow, one or more inert gases such as noble gases are added to the etch gas.
[0030] In some embodiments, the selective deposition layer 232 is completely removed. A protection layer may be deposited around the resulting Si layers 208,
216, 224. In an embodiment, the protection layer may be formed by an atomic layer deposition process that deposits a silicon containing layer. Examples of such a silicon containing layer may be a silicon oxide or silicon nitride layer. The protective layer prevents the resulting Si layers 208, 216, 224 from oxidizing. The oxidation of the resulting Si layers 208, 216, 224 would further diminish the silicon layers. As a result, the etch would be even less selective.
[0031] In another embodiment, a Si layer is selectively etched with respect to SiGe layers. The first material is Si and the second material is SiGe. FIG. 5 A is a schematic cross-sectional view of part of a stack 500 on a wafer. In this embodiment, the stack 500 comprises a first SiGe layer 508 adjacent to a first Si layer 512 on a first side of the first Si layer 512. The first Si layer 512 is adjacent to a second SiGe layer 516 on a second side of the first Si layer 512. The first SiGe layer 508 and the second SiGe layer 516 are on opposite sides of the first Si layer 512. A second Si layer 520 is adjacent to the second SiGe layer 516. The second SiGe layer 516 is on a first side of the second Si layer 520. The first Si layer 512 and the second Si layer 520 are on opposite sides of the second SiGe layer 516. The second Si layer 520 is adjacent to a third SiGe layer 524 on a second side of the second Si layer 520. The second SiGe layer 516 and the third SiGe layer 524 are on opposite sides of the second Si layer 520. The SiGe layers 508, 516, 524 and Si layers 512, 520 may extend between and be connected to electrical contacts or other structures (not shown).
[0032] In an exemplary embodiment, the stack 500 is partially selectively etched to form recessed layers (step 104). In this embodiment, the first Si layer 512 and the second Si layer 520 are partially selectively etched with respect to the first SiGe layer 508, the second SiGe layer 516, and the third SiGe layer 524. An example recipe for such a selective etch comprises providing an etch gas comprising 10 seem CF4, 100 seem hydrogen (H2), 1000 seem Ar, and 1000 seem He. A small flow of sulfur hexafluoride (SF6) or hydrogen sulfide (H2S) (0-100 seem) may be added to improve selectivity. The etch gas is transformed into a plasma. The plasma selectively etches Si with respect to SiGe.
[0033] FIG. 5B is a cross-sectional view of the stack 500 after the first Si layer 512 and the second Si layer 520 are partially selectively etched with respect to the first SiGe layer 508, the second SiGe layer 516, and the third SiGe layer 524. All of the layers are etched. However, the first and second Si layers 512, 520 are etched more than the first, second, and third SiGe layers 508, 516, 524. This creates a dip 528 or recess transitioning from the first SiGe layer 508 to the first Si layer 512.
[0034] A layer is selectively deposited on nonrecessed layers of the stack (step 108). FIG. 4 is a more detailed flow chart of the selective deposition process (step 108). The selective deposition process (step 108) comprises at least one cycle of providing a first reactant (step 412), providing a partial purge (step 414), providing a second reactant (step 416), and providing a second purge (step 418).
[0035] The first reactant is provided to the stack 500 (step 412). In this
embodiment, the first reactant is a liquid silicon containing precursor. The liquid silicon containing precursor is vaporized and delivered in vapor form to the stack 500. The liquid silicon containing precursor doses the stack 500 to saturation, forming a layer of precursor over the stack 500. In this example, the precursor comprises Bis(tert-butylamino) silane (CsF^^SiXBTBAS). In this example, the providing of the precursor is plasmaless. In this embodiment, the first reactant is a silicon precursor. The precursor has a silicon function group. The silicon function group forms a monolayer on the stack 500 since the precursor does not attach to another precursor.
[0036] Once the stack 500 is dosed with the precursor, the delivery of the precursor vapor is stopped. Then a partial purge step is provided (step 414) to purge out some of the undeposited precursors that linger in the process chamber. Some of the undeposited precursors may remain in the process chamber.
[0037] A second reactant is provided (step 416). In this embodiment, the providing the second reactant comprises providing a second reactant gas comprising 1000 seem to 2000 seem oxygen (02) to the process chamber. In this example, the second reactant is an oxidizing gas. In this example, a power of 500 to 3000 watts is delivered at 13.56 MHz to form the second reactant gas into a plasma. A pressure of 20 mTorr to 100 mTorr is provided. Some of the second reactant gas combines with the undeposited first reactant. In this example, the oxidizer gas and the undeposited silicon precursor form undeposited silicon oxide. The undeposited silicon oxide selectively deposits on the stack 500 to provide a nonconformal deposition. In addition, the oxidizer gas oxidizes the deposited silicon precursor, forming a conformal ALD layer on the stack 500. After the deposition process is completed, the process chamber is purged (step 418). The cycle may then be repeated. In this example, the cycle is repeated from 3 to 12 times.
[0038] FIG. 5C is a cross-sectional view of the stack 500 after a selective deposition layer 532 has been deposited. The selective deposition layer 532 forms a thicker layer over the first, second, and third SiGe layers 508, 516, 524 than over the first and second Si layers 512, 520. The thickness of the selective deposition layer 532 is not drawn to scale but is enlarged for better clarity and illustration.
[0039] Referring back to FIG. 1 , the recessed layers are selectively etched (step 112). In this embodiment, the first Si layer 512 and the second Si layer 520 are selectively etched with respect to the first SiGe layer 508, the second SiGe layer 516, and the third SiGe layer 524. An example recipe for such a selective etch comprises providing an etch gas comprising 10 seem CF4, 100 seem FF, 1000 seem Ar, and 1000 seem He. A small flow of sulfur hexafluoride (SF6) or hydrogen sulfide ( FFS) (0-100 seem) may be added to improve selectivity. The etch gas is transformed into a plasma. The plasma selectively etches Si with respect to SiGe. In this example, the selective deposition layer 532 covering the SiGe layers 508, 516, 524 is not thick enough so that these layers 508, 516, 524 are protected from the selective etching before the first and second Si layers 512, 520 are completely etched away. As a result, in this example another selective deposition process is provided (step 108) and then the first and second Si layers 512, 520 are completely etched away (step 112).
[0040] FIG. 5D is a cross-sectional view of the stack 500 after the first and second Si layers 512, 520 are completely etched away. The resulting SiGe layers 508, 516, 524 may be used as horizontal nanowires for p-type metal-oxide-semiconductor (PMOS) devices. This embodiment provides an etch selectivity greater than 20:1 for etching Si with respect to SiGe. In addition, less than 5A of SiGe is lost due to oxidation or etching during the process. This embodiment selectively etches Si with respect to silicon oxide (Si02) and silicon nitride (SiN) with a selectivity of greater than 100:1.
[0041] In another embodiment for selectively etching Si with respect to SiGe, an etch gas comprising SF6 and FF may be used. The fluorine from SF6 may be tied up by the hydrogen as hydrogen fluoride (HF), and SF may be used to passivate Ge in the form of Ge-F, which can help to further passivate SiGe wire. In other embodiments, the etch gas may comprise fluorocarbons, SF6, and ¾S or sulfur- containing gases with ¾. In some embodiments, with CF4 and hF, a CF4 to hF ratio is between 1:1 - 1: 500.
[0042] FIG. 6 is a schematic view of a process chamber 600 which may be used in an embodiment. In one or more embodiments, the process chamber 600 comprises a showerhead 606 providing a gas inlet and an electrostatic chuck (ESC) 608, within a reactor chamber 610, enclosed by a chamber wall 612. Within the reactor chamber 610, a wafer 614 is positioned over the electrostatic chuck 608. A gas source 616 is connected to a remote plasma generator 620. The remote plasma generator 620 is connected to the reactor chamber 610 through the showerhead 606. A radio frequency (RF) source 630 provides RF power at one or more frequencies of 27 megahertz (MHz), 13.56 MHz, 60 MHz, 2 MHz, or 400 kHz to the remote plasma generator 620, an upper electrode provided by the showerhead 606, or a lower electrode, provided by the ESC 608. The RF source 630 may provide power to coils. The RF power is used to create an inductively coupled plasma. A chuck temperature controller 640 controls a chiller 644. The chiller 644 cools a coolant 648. The coolant 648 is provided to a chuck cooling system 650. A controller 635 is controllably connected to the RF source 630, an exhaust pump 652, the chuck temperature controller 640, and the gas source 616.
[0043] FIG. 7 is a high level block diagram showing a computer system 700, which is suitable for implementing a controller 635 used in embodiments. The computer system 700 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 700 includes one or more processors 702, and further can include an electronic display device 704 (for displaying graphics, text, and other data), a main memory 706 (e.g., random access memory (RAM)), storage device 708 (e.g., hard disk drive), removable storage device 710 (e.g., optical disk drive), user interface devices 712 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 714 (e.g., wireless network interface). The communications interface 714 allows software and data to be transferred between the computer system 700 and external devices via a link. The system may also include a communications infrastructure 716 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices/modules are connected.
[0044] Information transferred via communications interface 714 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 714, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communications channels. With such a communications interface 714, it is contemplated that the one or more processors 702 might receive information from a network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.
[0045] The term“non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher- level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal a processor.
[0046] While this disclosure has been described in terms of several exemplary embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure.

Claims

CLAIMS What is claimed is:
1. A method for selectively etching layers of a first material with respect to layers of a second material in a stack, wherein layers of the first material alternate with layers of the second material, comprising:
partially etching the layers of the first material with respect to the layers of the second material;
selectively depositing a deposition layer on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions of the deposition layer covering the layers of the first material, the selectively depositing comprising:
providing a first reactant, wherein some of the first reactant deposits on the stack;
purging some of the first reactant, wherein some undeposited first reactant is not purged; and
providing a second reactant, wherein the undeposited first reactant combines with the second reactant, wherein the combined undeposited first reactant and second reactant selectively deposits on the layers of the second material with respect to the layers of the first material, and wherein some of the second reactant reacts with the deposited first reactant to form part of the deposition layer; and
selectively etching the layers of the first material with respect to the layers of the second material to completely remove the layers of the first material, wherein the layers of the second material are protected by the deposition layer.
2. The method, as recited in claim 1, wherein the partially etching the layers of the first material with respect to the layers of the second material comprises:
providing an etch gas; and
transforming the etch gas into a plasma, wherein the plasma selectively etches the layers of the first material with respect to the layers of the second material to create recessed layers of the first material.
3. The method, as recited in 1, wherein the undeposited first reactant combined with the second reactant selectively deposits on the layers of the second material with respect to the layers of the first material to provide the deposition layer that is nonconformal.
4. The method, as recited in claim 1, wherein the first material is SiGe and the second material is Si.
5. The method, as recited in claim 4, wherein the selectively etching the layers of the first material with respect to the layers of the second material comprises providing an atomic layer etch process.
6. The method, as recited in claim 5, wherein the atomic layer etch process comprises a plurality of cycles, wherein each cycle comprises:
an oxidation phase, wherein the oxidation phase selectively oxidizes the layers of the second material with respect to the layers of the first material; and
an etch phase with selectively etches the layers of the first material with respect to the oxidized layers of the second material.
7. The method, as recited in claim 1, wherein the partially etching the layers comprises providing an atomic layer etch process.
8. The method, as recited in claim 7 wherein the atomic layer etch process comprises a plurality of cycles, wherein each cycle comprises:
an oxidation phase, wherein the oxidation phase selectively oxidizes the layers of the second material with respect to the layers of the first material; and
an etch phase, wherein the etch phase selectively etches the layers of the first material with respect to the oxidized layers of the second material.
9. The method, as recited in claim 1, wherein the first material is Si and the second material is SiGe.
10. The method, as recited in claim 1, wherein the first reactant is a silicon containing precursor and the second reactant is an oxidizing gas, wherein the undeposited first reactant is an undeposited silicon containing precursor, wherein the undeposited silicon containing precursor reacts with the oxidizing gas to form undeposited silicon oxide, wherein the undeposited silicon oxide selectively deposits on the layers of the second material.
11. The method, as recited in claim 1, wherein the selectively etching the layers of the first material with respect to the layers of the second material to completely remove the layers of the first material, comprises:
selectively etching the layers of the first material with respect to the layers of the second material;
selectively depositing a deposition layer on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions of the deposition layer covering the layers of the first material; and
selectively etching the layers of the first material with respect to the layers of the second material.
12. The method, as recited in claim 1, wherein the selectively etching the layers of the first material with respect to the layers of the second material to completely remove the layers of the first material comprises selectively etching the layers of the first material with respect to the layers of the second material without selectively depositing a deposition layer on the stack.
13. A method for selectively etching silicon germanium with respect to silicon in a stack, wherein at least one layer of silicon germanium is between two layers of silicon, comprising:
partially etching the silicon germanium with respect to silicon;
coating the stack with a selective deposition process, wherein the selective deposition process deposits more on silicon than silicon germanium, the selective deposition process comprising:
providing a silicon precursor, wherein some of the silicon precursor deposits on the stack;
purging some of the silicon precursor, wherein some undeposited silicon precursor remains;
providing an oxidizing gas, wherein the undeposited silicon precursor combines with the oxidizing gas to form undeposited silicon oxide, wherein the undeposited silicon oxide nonconformally and preferentially deposits on silicon with respect to the silicon germanium, and wherein some of the oxidizing gas oxidizes the deposited silicon precursor to transform the deposited silicon precursor into silicon oxide; and
selectively etching silicon germanium with respect to the silicon oxide to completely remove the silicon germanium.
14. The method, as recited in claim 13, wherein the partially etching the silicon germanium with respect to the silicon, comprises: providing an etch gas; and
transforming the etch gas into a plasma, wherein the plasma selectively etches the layers of the first material with respect to the layers of the second material to create recessed layers of the first material.
15. The method, as recited in claim 13, wherein the partially etching the silicon germanium with respect to the silicon comprises providing an atomic layer etch process, the atomic layer etch process comprising:
an oxidation phase, wherein the oxidation phase selectively oxidizes the silicon forming silicon oxide with respect to the silicon germanium; and
an etch phase, wherein the etch phase selectively etches the silicon germanium with respect to the silicon oxide.
16. A method for selectively etching silicon with respect to silicon germanium in a stack, wherein at least one layer of silicon is between two layers of silicon
germanium, comprising:
partially etching the silicon with respect to the silicon germanium;
coating the stack with a selective deposition process, wherein the selective deposition process deposits more on silicon germanium than silicon, the selective deposition process comprising:
providing a silicon precursor, wherein some of the silicon precursor deposits on the stack;
purging some of the silicon precursor, wherein some undeposited silicon precursor remains;
providing an oxidizing gas, wherein the undeposited silicon precursor combines with the oxidizing gas to form undeposited silicon oxide, wherein the undeposited silicon oxide nonconformally and preferentially deposits on the silicon germanium with respect to the silicon, and wherein some of the oxidizing gas oxidizes the deposited silicon precursor to transform the deposited silicon precursor into silicon oxide; and
selectively etching the silicon with respect to the silicon oxide to completely remove the silicon.
17. The method, as recited in claim 16, wherein the partially etching the silicon with respect to the silicon germanium comprises: providing an etch gas comprising a fluorocarbon and hydrogen; and transforming the etch gas into a plasma, wherein the plasma selectively etches the silicon with respect to the silicon germanium.
18. The method, as recited in claim 17, wherein the etch gas further comprises a sulfur containing component.
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