Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/04—Apparatus for manufacture or treatment
  • H10P72/0442—Apparatus for placing on an insulating substrate, e.g. tape
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/04—Apparatus for manufacture or treatment
  • H10P72/0446—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/30—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations
  • H10P72/34—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
  • H10P72/3402—Mechanical parts of transfer devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W99/00—Subject matter not provided for in other groups of this subclass
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7408—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including alignment aids
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
  • H10P72/7414—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support the auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7432—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/0198—Manufacture or treatment batch processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/0711—Apparatus therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/0711—Apparatus therefor
  • H10W72/07141—Means for applying energy, e.g. ovens or lasers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/0711—Apparatus therefor
  • H10W72/07173—Means for moving chips, wafers or other parts, e.g. conveyor belts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/0711—Apparatus therefor
  • H10W72/07178—Means for aligning
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/0711—Apparatus therefor
  • H10W72/07183—Means for monitoring
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W80/00—Direct bonding of chips, wafers or substrates
  • H10W80/161—Aligning
  • H10W80/163—Aligning using active alignment, e.g. detecting marks and correcting position
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W80/00—Direct bonding of chips, wafers or substrates
  • H10W80/211—Direct bonding of chips, wafers or substrates using auxiliary members, e.g. aids for protecting the bonding area
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
  • H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/53—Means to assemble or disassemble
  • Y10T29/5313—Means to assemble electrical device

Definitions

• Semiconductor devices are electrical components that utilize semiconductor material, such as silicon, germanium, gallium arsenide, and the like. Semiconductor devices are typically manufactured as single discrete devices or as integrated circuits (ICs). Examples of single discrete devices include electrically-actuatable elements such as light-emitting diodes (LEDs), diodes, transistors, resistors, capacitors, fuses, and the like.
• LEDs light-emitting diodes
• the fabrication of semiconductor devices typically involves an intricate manufacturing process with a myriad of steps.
• the end-product of the fabrication is a“packaged” semiconductor device.
• the “packaged” modifier refers to the enclosure and protective features built into the final product as well as the interface that enables the device in the package to be incorporated into an ultimate circuit.
• the conventional fabrication process for semiconductor devices starts with handling a semiconductor wafer.
• the wafer is diced into a multitude of“unpackaged” semiconductor devices.
• the “unpackaged” modifier refers to an unenclosed semiconductor device without protective features.
• unpackaged semiconductor devices may be called semiconductor device die, or just“die” for simplicity.
• a single semiconductor wafer may be diced to create die of various sizes, so as to form upwards of more than 100,000 or even 1,000,000 die from the semiconductor wafer (depending on the starting size of the semiconductor), and each die has a certain quality.
• the unpackaged die are then“packaged” via a conventional fabrication process discussed briefly below.
• the actions between the wafer handling and the packaging may be referred to as“die preparation.”
• the die preparation may include sorting the die via a“pick and place process,” whereby diced die are picked up individually and sorted into bins.
• the sorting may be based on the forward voltage capacity of the die, the average power of the die, and/or the wavelength of the die.
• the packaging involves mounting a die into a plastic or ceramic package (e.g., mold or enclosure).
• the packaging also includes connecting the die contacts to pins/wires for interfacing/interconnecting with ultimate circuitry.
• the packaging of the semiconductor device is typically completed by sealing the die to protect it from the environment (e.g., dust).
• a product manufacturer then places packaged semiconductor devices in product circuitry. Due to the packaging, the devices are ready to be“plugged in” to the circuit assembly of the product being manufactured. Additionally, while the packaging of the devices protects them from elements that might degrade or destroy the devices, the packaged devices are inherently larger (e.g., in some cases, around 10 times the thickness and 10 times the area, resulting in 100 times the volume) than the die found inside the package. Thus, the resulting circuit assembly cannot be any thinner than the packaging of the semiconductor devices.
• a single semiconductor wafer may be diced to create more than 100,000 or 1,000,000 die from the semiconductor wafer. Therefore, these machines used in transferring semiconductor die require extreme precision.
• transfer mechanisms are often built with a specific design purpose in mind and are built with tight constraints to ensure precision and accuracy.
• these transfer mechanisms often lack variability and adaptability to different applications or manufacturing purposes. For example, a transfer mechanism will be used to transfer die for a specific product and then may be reconfigured or adjusted to transfer die for another product. The reconfiguration can be time consuming, inefficient, and, at times, requires tearing down and rebuilding components on a machine.
• FIG. 1 represents a schematic view of an embodiment of a direct transfer apparatus in a pre-transfer position.
• FIG. 2 illustrates a top-down schematic representation of a direct transfer apparatus in multi-pitch configuration along with circuit traces and semiconductor device die.
• FIG. 3 illustrates a top-down schematic representation of a matched-pitch transfer apparatus along with circuit traces and semiconductor device die.
• FIG. 4 illustrate a method for determining a configuration of a plurality of impact wires of a direct transfer apparatus.
• FIG. 5 illustrates a top-down schematic representation of a plurality of impact wires arranged in a multi-pitch configuration and example movements that a transfer apparatus may make to transfer semiconductor device die according to an embodiment of this application.
• FIG. 6 illustrates a top-down schematic representation of a plurality of impact wires arranged in a matched-pitch configuration and example movements that a transfer apparatus may make to transfer semiconductor device die according to an embodiment of this application.
• FIG. 7 illustrates a method for determining adjustments made by a transfer apparatus for transferring semiconductor device die according to an embodiment of this application.
• This disclosure is directed generally to a transfer mechanism that directly transfers semiconductor device die from one substrate to another substrate, such as a die substrate (e.g., blue tape, semiconductor wafer on tape, etc.), a circuit substrate (e.g., printed circuit board, flexible or rigid, metal or plastic, surface of a circuit), another die (i.e., die stacked on die, where the die to be stacked on acts as the“substrate” to receive the transferred die), etc., and to the general process for achieving the same.
• the transfer mechanism may function to transfer unpackaged die directly from a substrate, such as a“wafer tape,” to a product substrate, such as a circuit substrate.
• the direct transfer of unpackaged die may significantly reduce the thickness of an end product compared to a similar product produced by conventional means, as well as the amount of time and/or cost to manufacture the product substrate.
• the term“substrate” refers to any substance on which, or to which, a process or action occurs.
• the term“product” refers to the desired output from a process or action, regardless of the state of completion.
• a product substrate may refer to any substance on which or to which, a process or action is caused to occur for a desired output.
• the wafer tape may also be referred to herein as the semiconductor device die substrate, or simply a die substrate.
• the transfer mechanism may transfer a semiconductor device die directly from a wafer tape to a product substrate without“packaging” the die.
• the transfer mechanism may be disposed vertically above the wafer tape and may actuate impact wires so as to press down on the die via the wafer tape toward the product substrate. This process of pressing down on the die may cause the die to peel off of the wafer tape, starting at the sides of the die until the die separates from the wafer tape to be attached to the product substrate. That is, by reducing the adhesion force between the die and the wafer tape, and increasing the adhesion force between the die and the product substrate, the die may be transferred.
• a transfer machine may secure a product substrate for receiving“unpackaged” dies, such as LEDs, transferred from the wafer tape, for example.
• the dies are very small and thin, for example, a die may be about 12 microns to 50 microns in height and may range from about 100 microns to 400 microns, or more or less, in lateral dimensions.
• embodiments of the transfer machine discussed herein may accommodate the transfer of die that are greater in size than the aforementioned dimensions. Nevertheless, embodiments of the transfer machine discussed herein may be particularly well-suited for the transfer of microLEDs, ranging in size as aforementioned.
• the transfer machine includes components that function to precisely align both the wafer tape carrying the dies and the product substrate to ensure accurate placement and/or avoid product material waste.
• the components that align the product substrate and the dies on the wafer tape may include a set of frames in which the wafer tape and the product substrate are secured respectively and conveyed individually to a position of alignment such that a specific die on the wafer tape is transferred to a specific spot on the product substrate.
• the frame that conveys the product substrate may travel in various directions, including horizontal directions and/or vertical directions, or even directions that would permit transfer to a curved surface.
• the frame that conveys the wafer tape may travel in various directions also.
• a system of gears, tracks, motors, and/or other elements may be used to secure and convey the frames carrying the product substrate and the wafer tape respectively to align the product substrate with the wafer tape in order to place a die on the correct position of the product substrate.
• Each frame system may also be moved to an extraction position in order to facilitate extraction of the wafer tape and the product substrate upon completion of the transfer process.
• the transfer mechanism may include a multi-needle transfer head, similar to print heads used in dot matrix printers, which therefore may also be referred to hereinafter as a“dot matrix transfer head.”
• the dot matrix transfer head may include a plurality of impact wires (also referred to herein as“needles” or“pins”) that may be individually actuated concurrently or sequentially.
• the plurality of impact wires may be implemented to directly transfer a plurality of semiconductor device die from the first substrate, such as a wafer tape, to the second substrate, such as a product substrate.
• the dot matrix transfer head may further include a housing, the housing may include an actuating assembly configured to control actuation of the plurality of impact wires.
• the dot matrix transfer head may also include a splaying element.
• the splaying element may be configured to spread the plurality of impact wires at a specified distance from each other.
• the splaying element may be included as part of the housing.
• the splaying element may be removably attached to the housing.
• the dot matrix transfer head may also include a guide or guide head that may attach to a side of the splaying element and/or the housing.
• the guide may be configured to maintain a lateral position of the plurality of impact wires during a transfer process.
• the guide may contact a surface of the wafer tape.
• the guide may disposed proximate to a surface of the wafer tape without any or with only some intermittent direct contact.
• the plurality of impact wires may be configured in a multi-pitch dot matrix configuration (referred to herein as“multi-pitch”).
• the term“pitch,” as used herein, refers to the spacing between obj ects or points.
• the term“pitch” refers to how the plurality of impact wires may or may not align with one or more other components, e.g., die to be transferred.
• the multi-pitch configuration may arrange the plurality of impact wires at a constant distance from one another.
• the arrangement of the plurality of impact wires may be evenly spaced from one another rather than being spaced to align with circuit traces or semiconductor device die. Therefore, the term “multi-pitch” is used because the multi-pitch configuration of the plurality of impact wires may be useful when semiconductor device die on a wafer tape or circuit traces on a product substrate are spaced unevenly (i.e., having multiple distinct pitches between die or traces). For example, having the plurality of impact wires spaced evenly from one another may increase the chance that at least one impact wire of the plurality of impact wires may align with at least one of a semiconductor device die or circuit trace.
• the multi -pitch configuration may be achieved by attaching a guide head to the arrangement of the plurality of impact wires in the multi-pitch configuration.
• the plurality of impact wires may be arranged in a matched-pitch configuration.
• the plurality of impact wires may be arranged to align with the predetermined pitch of circuit traces on a product substrate or semiconductor device die on a wafer tape.
• the particular alignment may be determined by which of the circuit traces or the semiconductor device die tend to be spaced at more constant intervals. For example, if the circuit traces tend to be spaced more evenly when held in a frame than the semiconductor device die, then the plurality of impact wires may be arranged to align with the circuit traces when arranged in the matched- pitch configuration.
• FIG. 1 illustrates an embodiment of an apparatus 100 (or“direct transfer apparatus”) that may be used to directly transfer unpackaged semiconductor device die from a wafer tape 102 to a product substrate 104, or likewise, to transfer other electrical components from a carrier substrate, i.e., a substrate carrying one or more electrical components, to a product substrate.
• the wafer tape may also be referred to herein as the semiconductor device die substrate, or simply a die substrate.
• the apparatus 100 may include a product substrate conveyance mechanism 106 and a wafer tape conveyance mechanism 108.
• the product substrate conveyance mechanism 106 may include a product substrate frame 110 and the wafer tape conveyance mechanism may include a wafer tape frame 112.
• the product substrate frame 110 and the wafer tape frame 112 may stretch the product substrate and the wafer tape, respectively, such that the stretching circuit traces and the semiconductor device die are spread apart due to the stretching.
• stretching is not required, for example, where the product substrate is a material with minimal relative stretching/flexing characteristics.
• the apparatus 100 may further include a transfer mechanism 114, such as a dot matrix transfer head (referenced herein as 114), which, as shown, may be disposed vertically above the wafer tape 102. In an embodiment, the dot matrix transfer head 114 may be located so as to nearly contact the wafer substrate 102.
• the dot matrix transfer head 114 may further include a guide head 116, whereby a single impact wire 118(1) of a plurality of impact wires (118(1), 118(2), . . . 1 l8(n); which are collectively referred to herein as 118) is inserted into a single hole of the multiple holes 120 of the guide head to maintain a position of each of the plurality of impact wires 118 during a transfer operation.
• the guide head 116 may configure the plurality of impact wires H8 in a m x n matrix configuration.
• the plurality of impact wires 118 may be inserted into the multiple holes 120 in the guide head 116 thereby guiding the plurality of impact wires 118 to actuate in an m x n matrix configuration (e.g., 12 x 2 matrix configuration, where there are twelve rows of holes and two columns of holes).
• the guide head 116 is configured to be easily replaced by another guide head having the same or a different configuration of multiple holes.
• a first guide head may be attached to the dot matrix transfer head 114 having a 12 x 2 matrix configuration for use on a first circuit design.
• a second guide head having a 8 x 3 matrix or other configuration, may be attached to the dot matrix transfer head 100, thereby replacing the first guide head.
• the guide head 106 includes a base side and attachment side that opposes the base side, the guide head 116 being removably attached to the dot matrix transfer head 114 via the attachment side.
• the plurality of impact wires 118 may be connected to an actuator(s) 122.
• the actuator 122 may include a motor (not shown) connected to the plurality of impact wires 118 to drive the plurality of impact wires 118 toward the wafer tape 102 at predetermined/programmed times.
• the actuator 122 and/or the apparatus 100 may be communicatively coupled to a controller (not shown) that is configured to activate/control the actuator 122 and/or the other features described herein.
• the plurality of impact wires 118 may be used to directly transfer unpackaged semiconductor device die 124 from the wafer tape 102 to the product substrate 104, such that at least one of the semiconductor device die 124 contacts and bonds to at least one circuit trace 126.
• the dot matrix transfer head 114 may be configured and programmed to transfer multiple semiconductor device die 124 concurrently. Additionally, and/or alternatively, the dot matrix transfer head 114 may implement the plurality of impact wires 118 to transfer multiple semiconductor device die 124 sequentially. Though depicting three impact wires 118 in FIG. 1, in an embodiment, a dot matrix transfer head 114 may include two or more impact wires 118. For example, the plurality of impact wires 118 may include impact wires in quantities of 2, 3, 6, 12, 24, etc., and anywhere in between or greater than the example quantities.
• individual impact wires of the plurality of impact wires may be independently-actuatable, enabling individual impact wires of the plurality of impact wires 118 to be actuated solitarily and/or in one or more groups. That is, for example, the dot matrix transfer head 114 may actuate a single impact wire 118(1) at a time, two or more impact wires (e.g., 118(1) and 1 l8(n)) at a time, and/or all of the plurality of impact wires 118.
• the implementation of a head or a cluster of a plurality of impact wires 118 allows the transfer mechanism to transfer die in a manner that may be more efficient than a mechanism implementing a single impact wire.
• a transfer mechanism implementing a plurality of impact wires 118 may be able to transfer more than one die at a time. Transferring multiple die via a head containing a plurality of impact wires 118 or a cluster of a plurality of needles 118 may significantly reduce total transfer time, as well as reducing the travel distance that the transfer mechanism would otherwise need to move.
• the plurality of impact wires 118 may actuate concurrently or sequentially. However, in another embodiment, one or more than one, but fewer than all, of the plurality of impact wires may be actuated at a same time or substantially the same time, as mentioned above.
• FIG. 2 illustrates a top-down schematic representation of an embodiment of the direct transfer apparatus 100 having a plurality of impact wires 202 arranged in a multi-pitch configuration along with semiconductor device die 204 and circuit traces 206.
• each of the plurality of impact wires 202 in a row may be spaced apart from one another evenly.
• the plurality of impact wires 202 may be spaced apart at uneven intervals in a multi-pitch configuration.
• the plurality of impact wires 202 may be spaced proximate to each other. This multi-pitch configuration arranges the plurality of impact wires 202 such that one impact wire is disposed immediately adjacent to another impact wire.
• the multi-pitch configuration is deemed thus because of the ability of the plurality of impact wires to accommodate semiconductor device die and/or circuit traces disposed at a plurality of different pitches (or“spacing”). Since there is essentially one impact wire disposed next to another continuously along a row, the multi-pitch configuration may be implemented when a semiconductor device die or circuit traces are used in the transfer process that have less than uniform spacing when held in their respective frames. As previously discussed, the multi-pitch configuration may be achieved by attaching a guide head having multiple holes that force the plurality of impact wires 202 into the configuration shown in FIG. 2.
• the plurality of impact wires 202 may be attached to the transfer mechanism such that the plurality of impact wires 202 are arranged in the multi-pitch configuration.
• the plurality of impact wires 202 may be spaced apart, for example, between O. lmm and 2 mm, between 0.25 mm and 1 mm, between 0.35 mm and 0.75 mm, between 0.4 mm and 0.6 mm.
• a semiconductor device die 204 may be transferred at a location where an impact wire 202, a semiconductor device die 204, and a circuit trace 206 all align so that the impact wire 202 may be actuated towards the semiconductor device die 204 such that the impact wire presses the semiconductor device die 204 so that it contacts the circuit trace 206 and bonds thereto.
• a location is shown at location A.
• the three components impact wire, semiconductor device die, and circuit trace
• the semiconductor device die 204 may be transferred if the components align within a threshold tolerance.
• Locations B and C depict possible locations where the three components are not aligned through a central axis, but may still be capable of transferring the semiconductor device die 204. Such a tolerance may be predetermined based on constraints of quality of a resulting product.
• FIG. 3 illustrates a top-down schematic representation of an embodiment of the direct transfer apparatus 100 having a plurality of impact wires 302 arranged in a matched-pitch configuration along with semiconductor device die 304 and circuit traces 306.
• each of the plurality of impact wires 302 are arranged to align with one other type of component.
• the plurality of impact wires 302 are arranged to align with the circuit traces 306 in the matched-pitch configuration.
• the plurality of impact wires 302 may be arranged to align with the semiconductor device die 304.
• the plurality of impact wires 302 may be aligned to whichever other component may be the more consistently spaced. For example, if the circuit traces 306 have a more constant spacing between each of the circuit traces 306, then the plurality of impact wires 302 will be arranged to align with the circuit traces 306 in the matched-pitch configuration. However, if the semiconductor device die 304 have a more consistent spacing, then the plurality of impact wires 302 will be arranged to align with the semiconductor device die 304 in the matched-pitch configuration.
• the matched-pitch configuration allows two of the components to remain fairly stationary between transfer operations, while the third component may be adjusted as needed.
• the semiconductor device die 302 may be the only components that may need to be adjusted for a transfer to be able to occur.
• only one component e.g., wafer tape having the semiconductor device die disposed thereon
• the matched-pitch configuration may be achieved by attaching a guide head having multiple holes that force the plurality of impact wires 302 into the matched- pitch configuration shown in FIG. 3.
• a guide head may be used that can be adjusted between a matched-pitch and multi-pitch configuration without having to replace the guide head.
• the plurality of impact wires 302 may be attached to the transfer mechanism such that the plurality of impact wires 302 are arranged in a matched- pitch configuration.
• the multi-pitch or matched pitch configuration may be selected based at least in part on the pitch of the circuit traces on the product substrate and/or the pitch of the semiconductor device die on the wafer tape.
• the plurality of impact wires may be grouped such that a first portion of the plurality of impact wires are arranged in a multi- pitch configuration and a second portion of the plurality of impact wires are arranged in a matched-pitch configuration.
• the direct transfer apparatus may automatically switch guide heads to configure the plurality of impact wires in a multi or matched-pitch configuration. Additionally, and/or alternatively, a human operator may change the guide head on the dot matrix transfer head to arrange the needles in the desired configuration.
• the process 400 is described as being performed, at least in part, by the direct transfer apparatus 100.
• the process 400 may be performed by another apparatus and/or an outside controller, computing resource, or human operator.
• any one and/or all of the steps may be performed by a human operator, due to the nature of the application along with the size of the product components and desired speeds of work, the steps are best left to the processing capabilities of an electronic device.
• any one and/or all of the steps may be fully automated and carried out by the direct transfer apparatus 100.
• the pitch of a component of interest is determined, such as the semiconductor device die and/or the circuit traces. That is, the spacing in between individual ones of the semiconductor device die and/or the circuit traces is determined.
• the plurality of impact wires are configured in either the matched-pitch configuration or the multi-pitch configuration.
• the impact wires may be configured in a different configuration entirely (e.g., circular type pattern, mixed pattern, etc.).
• the plurality of impact wires may be arranged in a specific configuration via attaching a guide head the arranges the plurality of impact wires in the specific configuration.
• FIG. 5 illustrates a top-down schematic representation of a plurality of impact wires 502 arranged in a multi -pitch configuration and example movements that the direct transfer apparatus 100 may make to transfer semiconductor device die 504 according to an embodiment.
• FIG. 5 illustrates a possible advantage of using a multi-pitch dot matrix transfer head over using a single impact wire transfer mechanism or a multiple impact wire mechanism having fixed impact wires.
• FIG. 5 depicts how the plurality of impact wires 502 arranged in the multi -pitch configuration benefit a scenario in which the semiconductor device die 504 and the circuit traces 506 may be unevenly spaced.
• positions A and B represent locations that transfer operations may occur without any adjustment of any of the components.
• the transfer mechanism may transfer multiple semiconductor device die 504 simultaneously.
• Position C may represent a location that an adjustment of the transfer head, and/or another component may be necessary.
• the transfer mechanism may need to make a slight adjustment to the dot matrix transfer head and to the wafer tape to be able to perform a transfer operation at position C.
• the transfer mechanism may prioritize transfers requiring only small adjustments before making large adjustments to make other transfers occur.
• the transfer mechanism may transfer semiconductor device die 504 at locations A, B, and C before making a bigger adjustment (or“jump”) to the next row and adjusting components to complete a transfer at position D. This process is described further herein below with respect to FIG. 7.
• FIG. 6 illustrates a top-down schematic representation of a plurality of impact wires 602 arranged in a matched-pitch configuration and example movements that the direct transfer apparatus 100 may make to transfer semiconductor device die 604 according to an embodiment.
• FIG. 6 depicts how the plurality of impact wires 602 arranged in the matched-pitch configuration may benefit a scenario in which either the semiconductor device die 604 or the circuit traces 606 may be substantially evenly spaced.
• the circuit traces 606 are shown as being relatively evenly spaced and the plurality of impact wires 602 are arranged to align thereto.
• the plurality of impact wires 602 may be arranged to align with the semiconductor device die 604. As shown in FIG.
• positions A and C in FIG 6 depict locations where a transfer can immediately be completed without any adjustment.
• Position B depicts a location where a slight adjustment of one of the semiconductor device die 604 may be the only necessary adjustment required to complete a transfer of the semiconductor device die 604.
• the transfer mechanism may prioritize transfers requiring only small adjustments before making large adjustments to make other transfers occur.
• the transfer mechanism may make the small adjustments on a slow axis of movement, while making the large adjustments on a fast axis of movement, such as to“jump” to position D.
• FIG. 7 illustrates a method 700 for determining adjustments made by the direct transfer apparatus 100 for transferring semiconductor device die according to an embodiment of this application.
• the process 700 is described as being performed at least in part by the direct transfer apparatus 100.
• the process 700 may be performed by other apparatus and/or an outside controller or computing resource.
• any one and/or all of the steps may be performed by a human operator, due to the nature of the application along with the size of the product components and desired speeds of work, the steps are best left to the processing capabilities of an electronic device.
• any one and/or all of the steps may be fully automated and carried out by the direct transfer apparatus 100.
• the method 700 (as well as each process described herein) is illustrated as a logical flow graph, each operation of which represents a sequence of operations that can be implemented by hardware, software, or a combination thereof.
• the operations represent computer- executable instruction stored on one or more computer-readable media that, when executed by one or more processors, perform the recited operations.
• computer-executable instructions include routines, programs, objects, components, data structures, and the like that perform particular functions or implement particular abstract data types.
• the computer-readable media may include non-transitory computer readable storage media, which may include hard drives, floppy diskettes, optical disks, CD-ROMs, DVDs, read-only memories (ROMs), random access memories (RAMs), EPROMS, EEPROMS, flash memory, magnetic or optical cards, solid- state memory devices, or other types of storage media suitable for storing electronic instructions.
• the computer-readable media may include a transitory computer-readable signal (in compressed or uncompressed form). Examples of computer-readable signals, whether modulated using a carrier or not, include, but are not limited to, signals that a computer system hosting or running a computer program can be configured to access, including signals downloaded through the Internet or other networks.
• an apparatus may determine a position of one or more components.
• the apparatus may determine the location of each of the components.
• the term components includes, but may not be limited to, a transfer head (e.g., dot matrix transfer head), a wafer tape and individual semiconductor device die disposed thereon, and a product substrate and individual circuit traces or desired transfer locations thereon. Therefore, at step 702, the apparatus may determine the location of each of these components. More specifically, at step 702, the apparatus may focus on a location that the transfer head is directly above, as illustrated by FIGS. 2-5. The apparatus may determine the location of each of a plurality of impact wires and may determine where multiple circuit traces and semiconductor device die may be disposed nearby.
• Step 702 may be accomplished prior to any transfers being completed such that the transfer apparatus locates and maps the location of each of the circuit traces and semiconductor device die.
• the apparatus knows the location of each of the circuit traces and semiconductor device die and merely has to determine the location of the transfer head relative to the known position of the other components.
• the apparatus may determine the locations of the components in real time. That is, as the transfer head moves along over the substrates, one or more sensors may“look ahead” and determine the locations of the components as the transfer process is being completed.
• the apparatus may determine if there are any positions where a transfer is possible without any adjustment. That is, once the transfer head has moved to a specific location, it may determine if there are any locations where an impact wire, a semiconductor device die, and a transfer location (such as a circuit trace, used as an example transfer location herein) are sufficiently aligned to complete a transfer of the semiconductor device die. As mentioned previously, an impact wire, semiconductor device die, and a circuit trace do not have to be perfectly aligned about a central axis. However, in an embodiment, the apparatus may determine if they are aligned within a specific tolerance threshold. Such a threshold tolerance may be predetermined based on constraints of quality of a resulting product. If the apparatus determines that the three components are sufficiently aligned within the threshold, the process will continue to step 706.
• a specific tolerance threshold may be predetermined based on constraints of quality of a resulting product.
• the apparatus may actuate at least one and/or all of the impact wires that are sufficiently aligned with a semiconductor device die and a circuit trace. For example, if the apparatus determines that the first, third, and fourth impact wires are sufficiently aligned with the other components, the transfer head may concurrently or sequentially actuate the first, third, and fourth impact wires.
• the apparatus may determine if there are more semiconductor device die that can be transferred in the current location at step 708. If there are no more semiconductor device die that can be transferred by only small adjustments the transfer head may move to the next location or if the entire wafer tape of semiconductor device die has been transferred the process will end at step 710. However, if there are more semiconductor device die that need to be transferred, the process may begin again at step 702, as shown by the optional arrow from step 710 to step 702.
• the apparatus may skip steps 702 and 704 and may follow the“No” path in response to step 704 since there may be no more possible transfer locations available without some adjustment.
• the“Yes” path from step 708 may optionally follow to step 712, as shown in FIG. 6.
• the apparatus may determine a location to transfer a semiconductor device that requires the least amount of adjustment, thus the apparatus will determine the next transfer that can be completed in the least amount of time with the least amount of movement necessary. However, in an embodiment, at step 712, the apparatus may determine a sequence of movements that will optimize the adjustments necessary to complete the rest of the transfers in a given location (i.e., section of the wafer tape).
• the apparatus may adjust one or more components so that the three components are sufficiently aligned to complete a transfer.
• the apparatus may adjust up to all three of the components.
• the apparatus may adjust all three components concurrently in the multi-pitch configuration to limit the distance that any one component would have to move to align the three components, thus reducing time between transfers.
• the apparatus may leave one or more components stationary and move one or more other components relative to the first component, similar to the example described in FIG. 4.
• the apparatus may leave two of the components stationary while only adjusting one other component while making small adjustments, similar to the example described in FIG. 5.
• the apparatus may determine if there are other possible semiconductor device die that could be transferred after making the adjustment(s).
• the apparatus may actuate at least one and/or all of the impact wires that are sufficiently aligned with a semiconductor device die and a circuit trace.
• the process may then return to step 708 and determine whether there are more semiconductor device die to be transferred in a location proximate to the transfer head.
• the apparatus may prioritize large and small adjustments on different axes of movement.
• the small adjustments (or adjustments requiring an adjustment distance that is below a predetermined distance threshold) made at step 714 may be made on a slow axis of movement of the apparatus and the larger adjustments (or adjustments requiring an adjustment distance that is above a predetermined distance threshold (e.g., switching rows or moving the transfer head to the next location of step 710) may be made on a fast axis of movement.
• a predetermined distance threshold e.g., switching rows or moving the transfer head to the next location of step 710
• the process may be completed in the opposite, with small movements being made on the fast axis of movement and large movements being made on the slow axis of movement.
• the“small” and“large” movement may be made on the order of microns and the“fast” and“slow” movement may be made on the order of milliseconds.
• the small adjustments may be around or less than 0.45 mm +/- 50 microns and the large adjustments being around 2 mm.
• the“fast” movements may be between 0.1 and 10 milliseconds, while the slow movement may be between 10 and 30 milliseconds.
• the given quantities are merely examples and are not necessarily limiting the features or acts described.
• Example Clauses A An apparatus for performing a direct transfer of a semiconductor device die of a plurality of semiconductor device die from a first substrate to a second substrate, the first substrate having a first side and a second side, and the semiconductor device die being disposed on the first side of the first substrate, the apparatus comprising: a first frame to hold the first substrate; a second frame to hold the second substrate adjacent to the first side of the first substrate; and a transfer mechanism including a plurality of impact wires disposed adjacent to the first frame and extending in a direction toward the second side of the first substrate, wherein the plurality of impact wires are arranged in a multi-pitch configuration, the multi-pitch configuration spacing the plurality of impact wires evenly from one another.
• a direct transfer apparatus for transferring semiconductor device die from a first substrate to circuit traces disposed on a second substrate, the first substrate having a first side and a second side, and the semiconductor device die being disposed on the first side of the first substrate
• the direct transfer apparatus comprising: a dot matrix transfer head including: an impact wire housing, and a plurality of impact wires disposed within the impact wire housing and extending out of the impact wire housing, the plurality of impact wires being disposed such that the plurality of impact wires are arranged in a matrix configuration, the matrix configuration being a matched-pitch configuration.
• J The direct transfer apparatus according to paragraph I, wherein the matched-pitch configuration includes an arrangement such that the plurality of impact wires are aligned with a layout of one of the semiconductor device die or the circuit traces.
• N The direct transfer apparatus according to any one of paragraphs I-M, wherein the direct transfer apparatus is configured to adjust a position of the semiconductor device die relative to the plurality of impact wires and the circuit traces while the plurality of impact wires are aligned with the circuit traces in the matched-pitch configuration.
• An apparatus for executing a direct transfer of semiconductor device die from a wafer tape to circuit traces on a product substrate comprising: a first frame to hold the wafer tape, the wafer tape having a first side and a second side, and the semiconductor device die being disposed on the first side of the wafer tape; a second frame to hold the product substrate adjacent to the first side of the wafer tape; and multiple impact wires secured within a dot matrix transfer head at a first end of the multiple impact wires, the multiple impact wires being secured within the dot matrix transfer head such that the multiple impact wires are arranged in a matched-pitch configuration.

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• Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
• Engineering & Computer Science (AREA)
• Robotics (AREA)
• Die Bonding (AREA)

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• 2018
  • 2018-09-28 US US16/147,055 patent/US11232968B2/en active Active
• 2019
  • 2019-09-26 CN CN201980027553.7A patent/CN112020767B/zh active Active
  • 2019-09-26 WO PCT/US2019/053199 patent/WO2020069159A1/en not_active Ceased
  • 2019-09-26 EP EP19866179.5A patent/EP3857594A4/en active Pending
  • 2019-09-26 KR KR1020217011411A patent/KR102551661B1/ko active Active
  • 2019-09-26 JP JP2021517283A patent/JP7254170B2/ja active Active
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