WO2020040393A1 - Compound semiconductor solar cell and method for manufacturing same - Google Patents

Compound semiconductor solar cell and method for manufacturing same Download PDF

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Publication number
WO2020040393A1
WO2020040393A1 PCT/KR2019/003133 KR2019003133W WO2020040393A1 WO 2020040393 A1 WO2020040393 A1 WO 2020040393A1 KR 2019003133 W KR2019003133 W KR 2019003133W WO 2020040393 A1 WO2020040393 A1 WO 2020040393A1
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Prior art keywords
compound semiconductor
solar cell
cells
semiconductor layer
forming
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PCT/KR2019/003133
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French (fr)
Korean (ko)
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김건호
김수현
이홍철
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엘지전자 주식회사
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Publication of WO2020040393A1 publication Critical patent/WO2020040393A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264Inorganic materials
    • H01L31/032Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042PV modules or arrays of single PV cells
    • H01L31/048Encapsulation of modules
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a compound semiconductor solar cell and a method for manufacturing the same, and more particularly, a compound semiconductor solar cell having improved contact resistance and improved efficiency, and a compound semiconductor solar cell capable of increasing productivity and reducing costs of the solar cell. It relates to a method for producing.
  • the present invention relates to a compound semiconductor solar cell and a method for manufacturing the same, and more particularly, a compound semiconductor solar cell having improved contact resistance and improved efficiency, and a compound semiconductor solar cell capable of increasing productivity and reducing costs of the solar cell. It relates to a method for producing.
  • An object of the present invention is to provide a compound semiconductor solar cell having improved contact resistance and an improved efficiency, and a method of manufacturing a compound semiconductor solar cell which can increase productivity and reduce cost of the solar cell.
  • Method of manufacturing a compound semiconductor solar cell forming a sacrificial layer on one side of the mother substrate; Forming a compound semiconductor layer on the sacrificial layer by using a regular growth method; Forming a plurality of grid-shaped front electrodes on a front surface of the compound semiconductor layer and then annealing; Performing a mesa etching to form a plurality of cells having the front electrode; Attaching a support film to the front surface side of the compound semiconductor layer provided in each of the plurality of cells using an adhesive material; Performing an epitaxial lift off (ELO) process to separate the plurality of cells from the mother substrate; Forming a back electrode on a back surface of the compound semiconductor layer provided in each of the plurality of cells; Cutting the support film in the region between the plurality of cells; And modularizing the plurality of cells using the cut support film as the front substrate.
  • ELO epitaxial lift off
  • an anti-reflection film may be formed on the front surface of the compound semiconductor layer, and then the supporting film may be attached.
  • the support film may be formed of a material having a refractive index of 1.0 to 2.0 and a light transmittance of 80% or more in the wavelength range of 450 nm to 950 nm, and the adhesive material may have a refractive index of 1.0 to 2.0 and 80% at a wavelength range of 450 nm to 950 nm. It has the above light transmissivity can be formed of a material having a bond strength of 100kgf / cm 2 to 500kgf / cm 2.
  • the support film may be formed of polyethylene terephthalate (PET) or polyimide (PI), and the adhesive material may be formed of epoxy, ethylene-vinyl acetate, or UV curing agent.
  • PET polyethylene terephthalate
  • PI polyimide
  • the adhesive material may be formed of epoxy, ethylene-vinyl acetate, or UV curing agent.
  • the annealing may be performed at a temperature of 400 ° C. to 500 ° C. for 5 minutes to 15 minutes.
  • a rear substrate may be installed below the rear electrode, and a sealing material may be disposed between the front substrate and the rear substrate, and the sealing material may be formed of the same material as the adhesive material or different materials.
  • the compound semiconductor solar cell manufactured by the manufacturing method of such a structure is a compound semiconductor layer; And a grid-shaped front electrode positioned on a front surface of the compound semiconductor layer, and the contact resistance of the front electrode may be formed to be 1 m ⁇ / cm 2 or less.
  • the front electrode may be formed of palladium (Pd) / germanium (Ge) / gold (Au), the palladium / germanium / gold may be formed to a thickness of 5nm / 20nm / 250nm.
  • the contact resistance of the front electrode can be reduced.
  • the ELO process can be used as a front substrate of the module without removing the support film for supporting the compound semiconductor layer, thereby improving productivity and reducing manufacturing costs.
  • FIG. 1 is a process chart showing a method of manufacturing a compound semiconductor solar cell according to an embodiment of the present invention.
  • FIG. 2 is a perspective view showing a schematic configuration of the compound semiconductor solar cell shown in FIG. 1.
  • FIG. 3 is a photograph of the front electrode illustrated in FIG. 2.
  • FIG. 4 is a graph showing a change in contact resistance according to the process conditions of the annealing step shown in FIG.
  • FIG. 5 is a table illustrating efficiency of a compound semiconductor solar cell according to whether or not annealing step illustrated in FIG. 1 is performed.
  • first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component.
  • the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
  • the term "and / or” may include a combination of a plurality of related items or any of a plurality of related items.
  • a component When a component is said to be “connected” or “coupled” to another component, it may be directly connected to or coupled to the other component, but other components may be present in the middle. Can be understood.
  • FIG. 1 is a process chart showing a method of manufacturing a compound semiconductor solar cell according to an embodiment of the present invention.
  • FIG. 2 is a perspective view showing a schematic configuration of the compound semiconductor solar cell shown in FIG. 1.
  • FIG. 3 is a photograph of the front electrode illustrated in FIG. 2.
  • FIG. 4 is a graph showing a change in contact resistance according to the process conditions of the annealing step shown in FIG.
  • FIG. 5 is a table illustrating efficiency of a compound semiconductor solar cell according to whether or not annealing step illustrated in FIG. 1 is performed.
  • the compound semiconductor solar cell includes a light absorbing layer PV, a window layer 10 positioned on the front surface of the light absorbing layer PV, a grid-shaped front electrode 20 positioned on the front surface of the window layer 10, The front contact layer 30 positioned between the window layer 10 and the front electrode 20, the antireflection film 40 positioned on the window layer 10, and the rear contact layer positioned on the rear surface of the light absorbing layer PV ( 50 and a rear electrode 60 positioned on the rear surface of the rear contact layer 50.
  • At least one of the anti-reflection film 40, the window layer 10, the front contact layer 30, and the rear contact layer 50 may be omitted.
  • the light absorbing layer (PV) is a group III-VI semiconductor compound, for example, a GaInP compound containing gallium (Ga), indium (In) and phosphorus (P), or a GaAs compound containing gallium (Ga) and arsenic (As). It may be formed to include.
  • the light absorption layer PV is a p-type semiconductor layer PV-p doped with an impurity of a first conductivity type, for example, a p-type impurity, and an n-type semiconductor doped with an impurity of a second conductivity type, for example, an n-type impurity.
  • Layer (PV-n) is a p-type semiconductor layer PV-p doped with an impurity of a first conductivity type, for example, a p-type impurity, and an n-type semiconductor doped with an impurity of a second conductivity type, for example, an n-type impurity.
  • the light absorbing layer PV may further include a rear electric field layer disposed at the rear of the p-type semiconductor layer PV-p.
  • the light absorbing layer (PV) of this configuration can be prepared from a mother substrate by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method or any other suitable method for forming an epitaxial layer. Can be.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the window layer 10 may be formed between the light absorbing layer PV and the front electrode 20, and may be formed by doping a III-VI group semiconductor compound with a second conductivity type, that is, an n-type impurity.
  • the window layer 10 functions to passivate the front surface of the light absorbing layer PV, and may have an energy band gap higher than that of the light absorbing layer PV.
  • the anti-reflection film 40 may be located on the remaining area of the window layer 10 except for the area where the front electrode 20 and / or the front contact layer 30 is located.
  • the anti-reflection film 40 may be disposed on the front contact layer 30 and the front electrode 20 as well as the exposed window layer 10.
  • the compound semiconductor solar cell may further include a busbar electrode for physically connecting the plurality of front electrodes 20, and the busbar electrode is not covered by the anti-reflection film 40 and exposed to the outside. Can be.
  • the front electrode 20 may be formed to extend in the first direction X-X ', and the plurality of front electrodes 20 may be spaced apart at regular intervals along the second direction Y-Y' perpendicular to the first direction. .
  • the front electrode 20 having such a configuration may be formed by including an electrically conductive material.
  • the front electrode 20 may include at least one of gold (Au), germanium (Ge), and nickel (Ni).
  • the front electrode 20 may be formed of palladium (Pd) / germanium (Ge) / gold (Au), and the palladium / germanium / gold may be formed to a thickness of 5 nm / 20 nm / 250 nm.
  • the front contact layer 30 positioned between the window layer 10 and the front electrode 20 is formed by doping the group III-VI semiconductor compound with a second impurity at a doping concentration higher than the impurity doping concentration of the window layer 10. can do.
  • the rear contact layer 50 located on the rear surface of the p-type semiconductor layer PV-p of the light absorption layer PV is generally located on the rear surface of the light absorption layer PV, and has a first conductivity type in the group III-VI semiconductor compound. May be formed by doping at a higher doping concentration than the p-type semiconductor layer PV-p.
  • the rear electrode 60 positioned on the rear surface of the rear contact layer 50 may be formed of a sheet-shaped conductor positioned entirely on the rear surface of the rear contact layer 50. . That is, the rear electrode 60 may also be referred to as a sheet electrode positioned on the entire rear surface of the rear contact layer 50.
  • the rear electrode 60 may be formed in the same plane as the light absorbing layer PV, and may include gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), and nickel (Ni). ), Magnesium (Mg), palladium (Pd), copper (Cu), and germanium (Ge) may be formed as a single film or a multi-layer including at least one material selected from, and the material forming the rear electrode is It may be appropriately selected depending on the conductivity type of the contact layer.
  • the sacrificial layer 120 is formed on one side of the mother substrate 110, and then the compound semiconductor layer CS is formed on the sacrificial layer 120 by using a regular growth method.
  • ELO epitaxial lift off
  • the sacrificial layer 120 is formed on one side of a mother substrate 110 serving as a base for providing an appropriate lattice structure in which the light absorbing layer PV is formed, and is regular.
  • the compound semiconductor layer CS is formed on the sacrificial layer 120 by using a regular growth method.
  • the regular growth method refers to a method of sequentially forming the back contact layer 50, the light absorbing layer PV, the window layer 10, and the front contact layer 30 on the sacrificial layer 120.
  • inverse is a method of forming each layer in the reverse order of the regular growth method.
  • a plurality of grid-shaped front electrodes 20 are formed on the front surface of the compound semiconductor layer CS.
  • the plurality of front electrodes 20 are formed to form a plurality of cells C by mesa etching the compound semiconductor layer CS formed on the sacrificial layer 120.
  • an annealing process is performed.
  • the annealing process is to reduce the contact resistance of the front electrode by heat treatment of the front electrode 20, it is carried out for 5 to 15 minutes at a temperature of 400 °C to 500 °C.
  • FIG. 4 is a graph showing a change in contact resistance of the front electrode according to the process conditions of the annealing step illustrated in FIG. 1, and FIG. 5 illustrates the efficiency of a compound semiconductor solar cell according to whether or not the annealing step illustrated in FIG.
  • FIG. 4 and FIG. 5 show the measurement results when the front electrode 20 is formed of 5 nm thick palladium (Pd) / 20 nm thick germanium (Ge) / 250 nm thick gold (Au).
  • the front electrode may be formed by any one of an evaporation method, a sputtering method, a plating method, and a screen printing method.
  • the contact resistance of the front electrode 20 is about 10 mPa / cm 2 regardless of the increase or decrease of the annealing time. Can be.
  • the contact resistance of the front electrode 20 is lowered to about 1 mPa / cm 2 or less.
  • the annealing process of the front electrode 20 is preferably carried out for 5 to 15 minutes at a temperature of 400 °C to 500 °C.
  • the efficiency of the solar cell before (annealed) and after the annealing (invention) will be described with reference to FIG. 5. Compared with the solar cell, it is lower, respectively, and the short-circuit current density Jsc and the fill factor FF show that the solar cell after annealing is increased compared with the solar cell before annealing.
  • the efficiency Eff is increased as compared with the conventional case where the annealing is not performed.
  • the reason why the annealing process can be performed after the front electrode 20 is formed in the present invention is that the front electrode forming step and the annealing step are performed before the ELO process.
  • wax was used to attach the lamination film to the metal protective layer.
  • the manufacturing cost of the compound semiconductor solar cell is increased due to a problem such as a high deposition time required for forming the metal protective layer or a cost increase due to the use of expensive metal, and also the metal protective layer and Since the lamination film needs to be removed, there is a problem in that the number of processes increases, and damage to the compound semiconductor layer occurs during the removal of the metal protective layer and the lamination film.
  • the carrier substrate for supporting the compound semiconductor layer in the front electrode formation step Should be attached to the compound semiconductor layer.
  • the front electrode 20 is formed and the annealing process is performed before the EOL process, so that the mother substrate 110 is formed of the compound semiconductor layer CS in the process of forming the front electrode 20. I can definitely support it.
  • the effect of reducing misalignment of the front electrode can be obtained as compared with the conventional case in which the front electrode is formed after the ELO process (photo shown on the left side of FIG. 3).
  • the antireflection film 40 is formed.
  • the anti-reflection film 40 forming process may be omitted.
  • mesa etching refers to an etching process for manufacturing a plurality of cells (C), that is, a plurality of compound semiconductor solar cells in one compound semiconductor layer (CS) by separating one compound semiconductor layer (CS) into several. do.
  • the supporting film 140 is attached to the front surface side of the compound semiconductor layer CS provided in each of the plurality of cells C.
  • the support film 140 may be attached using the adhesive material 130.
  • the support film 140 is not removed and is used as a front substrate in the modularization process of a compound semiconductor solar cell.
  • the support film 140 is formed of a material having a refractive index of 1.0 to 2.0 and a light transmittance of 80% or more in the wavelength range of 450 nm to 950 nm, and an adhesive material. 130 is preferably from 1.0 to have a refractive index and, 450nm to the light transmittance of 80% or more in the wavelength range of 950nm of 2.0 to form a material having a bond strength of 100kgf / cm 2 to 500kgf / cm 2.
  • an epitaxial lift off (ELO) process is performed to separate the plurality of cells C from the mother substrate 110.
  • the carrier substrate 150 is attached to the support film 140 by an adhesive, and the compound semiconductor layer provided in each of the plurality of cells C in the state in which the carrier substrate 150 is attached to the support film 140 ( After forming the back electrode 60 on the back surface of the CS, the carrier substrate 150 is removed.
  • the process of attaching and removing the carrier substrate 150 may be omitted if the supporting film 140 has a strength sufficient to support the compound semiconductor layer CS.
  • the material forming the back electrode may be filled in the region between the cells C.
  • the back electrode forming material filled in the region between the cells C may be formed in the support film 140 to be described later. Can be removed in the cutting process.
  • the support film 140 is cut by irradiating a laser to a region between the plurality of cells C, and the back electrode forming material filled in the region between the cells C is removed.
  • the plurality of cells C are modularized using the cut support film 140 as the front substrate.
  • the rear substrate 160 may be installed below the rear electrode 60, and the sealing material 170 may be disposed between the front substrate 140 and the rear substrate 160, in which case the sealing material 170 may be disposed. May be formed of the same material as the adhesive material 130 or may be formed of different materials.

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Abstract

The present invention relates to a compound semiconductor solar cell and a method for manufacturing same. A method for manufacturing a compound semiconductor solar cell, according to one aspect of the present invention, comprises the steps of: forming a sacrificial layer on one surface of a mother substrate; forming a compound semiconductor layer on the sacrificial layer by using a regular growth method; forming a plurality of front electrodes in the shape of a grid on the front surface of the compound semiconductor layer and then annealing the plurality of front electrodes; performing mesa etching so as to form a plurality of cells comprising the front electrodes; using an adhesive material so as to attach a support film to the front surface of the compound semiconductor layer provided in each of the plurality of cells; performing an epitaxial lift off (ELO) process so as to separate the plurality of cells from the mother substrate; forming a back electrode on the back surface of the compound semiconductor layer provided in each of the plurality of cells; cutting the support film at a region between the plurality of cells; and modularizing each of the plurality of cells by using the cut support film as a front substrate.

Description

화합물 반도체 태양전지 및 이의 제조 방법Compound semiconductor solar cell and method for manufacturing same
본 발명은 화합물 반도체 태양전지 및 이의 제조 방법에 관한 것으로, 보다 상세하게는 접촉 저항이 개선되어 효율이 향상된 화합물 반도체 태양전지 및 상기 태양전지의 생산성을 증가시키고 원가를 절감할 수 있는 화합물 반도체 태양전지의 제조 방법에 관한 것이다.The present invention relates to a compound semiconductor solar cell and a method for manufacturing the same, and more particularly, a compound semiconductor solar cell having improved contact resistance and improved efficiency, and a compound semiconductor solar cell capable of increasing productivity and reducing costs of the solar cell. It relates to a method for producing.
본 발명은 화합물 반도체 태양전지 및 이의 제조 방법에 관한 것으로, 보다 상세하게는 접촉 저항이 개선되어 효율이 향상된 화합물 반도체 태양전지 및 상기 태양전지의 생산성을 증가시키고 원가를 절감할 수 있는 화합물 반도체 태양전지의 제조 방법에 관한 것이다.The present invention relates to a compound semiconductor solar cell and a method for manufacturing the same, and more particularly, a compound semiconductor solar cell having improved contact resistance and improved efficiency, and a compound semiconductor solar cell capable of increasing productivity and reducing costs of the solar cell. It relates to a method for producing.
본 발명은 접촉 저항이 개선되어 효율이 향상된 화합물 반도체 태양전지 및 상기 태양전지의 생산성을 증가시키고 원가를 절감할 수 있는 화합물 반도체 태양전지의 제조 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a compound semiconductor solar cell having improved contact resistance and an improved efficiency, and a method of manufacturing a compound semiconductor solar cell which can increase productivity and reduce cost of the solar cell.
본 발명의 한 측면에 따른 화합물 반도체 태양전지의 제조 방법은, 모기판의 한쪽 면 위에 희생층을 형성하는 단계; 레귤러(regular) 성장법을 이용하여 상기 희생층 위에 화합물 반도체층을 형성하는 단계; 상기 화합물 반도체층의 전면(front surface)에 그리드 형상의 전면 전극을 복수 개 형성한 후, 어닐링하는 단계; 메사 에칭(mesa etching)을 실시하여, 상기 전면 전극을 구비하는 셀을 복수 개 형성하는 단계; 접착 물질을 이용하여, 상기 복수의 셀 각각에 구비된 화합물 반도체층의 전면(front surface) 쪽에 지지 필름을 부착하는 단계; ELO(Epitaxial lift off) 공정을 실시하여, 상기 복수의 셀을 상기 모기판으로부터 분리하는 단계; 상기 복수의 셀 각각에 구비된 화합물 반도체층의 후면(back surface)에 후면 전극을 형성하는 단계; 상기 복수의 셀 사이 영역에서 상기 지지 필름을 절단하는 단계; 및 절단한 지지 필름을 전면 기판으로 사용하여 복수의 셀을 각각 모듈화 하는 단계를 포함할 수 있다.Method of manufacturing a compound semiconductor solar cell according to an aspect of the present invention, forming a sacrificial layer on one side of the mother substrate; Forming a compound semiconductor layer on the sacrificial layer by using a regular growth method; Forming a plurality of grid-shaped front electrodes on a front surface of the compound semiconductor layer and then annealing; Performing a mesa etching to form a plurality of cells having the front electrode; Attaching a support film to the front surface side of the compound semiconductor layer provided in each of the plurality of cells using an adhesive material; Performing an epitaxial lift off (ELO) process to separate the plurality of cells from the mother substrate; Forming a back electrode on a back surface of the compound semiconductor layer provided in each of the plurality of cells; Cutting the support film in the region between the plurality of cells; And modularizing the plurality of cells using the cut support film as the front substrate.
본 발명의 실시예에 있어서, 상기 메사 에칭을 실시한 후, 상기 화합물 반도체층의 전면(front surface)에 반사 방지막을 형성하고, 이후, 상기 지지 필름을 부착하는 단계를 실시할 수 있다.In an embodiment of the present invention, after the mesa etching, an anti-reflection film may be formed on the front surface of the compound semiconductor layer, and then the supporting film may be attached.
상기 지지 필름은 1.0 내지 2.0의 굴절률과, 450nm 내지 950nm의 파장대에서 80% 이상의 광 투과율을 갖는 물질로 형성할 수 있고, 상기 접착 물질은 1.0 내지 2.0의 굴절률과, 450nm 내지 950nm의 파장대에서 80% 이상의 광 투과율을 가지며 100kgf/cm 2 내지 500kgf/cm 2의 접착 강도를 갖는 물질로 형성할 수 있다.The support film may be formed of a material having a refractive index of 1.0 to 2.0 and a light transmittance of 80% or more in the wavelength range of 450 nm to 950 nm, and the adhesive material may have a refractive index of 1.0 to 2.0 and 80% at a wavelength range of 450 nm to 950 nm. It has the above light transmissivity can be formed of a material having a bond strength of 100kgf / cm 2 to 500kgf / cm 2.
한 예로, 상기 지지 필름은 PET(polyethylene terephthalate) 또는 PI(polyimide)로 형성할 수 있고, 상기 접착 물질은 에폭시(epoxy), 에바(ethylene-vinyl acetate), 또는 UV 경화제로 형성할 수 있다.For example, the support film may be formed of polyethylene terephthalate (PET) or polyimide (PI), and the adhesive material may be formed of epoxy, ethylene-vinyl acetate, or UV curing agent.
상기 어닐링하는 단계는 400℃ 내지 500℃의 온도에서 5분 내지 15분 동안 실시할 수 있다.The annealing may be performed at a temperature of 400 ° C. to 500 ° C. for 5 minutes to 15 minutes.
상기 모듈화 단계에서, 상기 후면 전극의 하부에 후면 기판을 설치하고, 상기 전면 기판과 후면 기판 사이에 밀봉재를 배치하되, 상기 밀봉재를 상기 접착 물질과 동일한 물질, 또는 서로 다른 물질로 형성할 수 있다.In the modularization step, a rear substrate may be installed below the rear electrode, and a sealing material may be disposed between the front substrate and the rear substrate, and the sealing material may be formed of the same material as the adhesive material or different materials.
이러한 구성의 제조 방법에 의해 제조한 화합물 반도체 태양전지는 화합물 반도체층; 및 상기 화합물 반도체층의 전면(front surface) 위에 위치하는 그리드 형상의 전면 전극을 포함하며, 상기 전면 전극의 접촉 저항은 1mΩ/㎝ 2 이하로 형성될 수 있다.The compound semiconductor solar cell manufactured by the manufacturing method of such a structure is a compound semiconductor layer; And a grid-shaped front electrode positioned on a front surface of the compound semiconductor layer, and the contact resistance of the front electrode may be formed to be 1 mΩ / cm 2 or less.
상기 전면 전극은 팔라듐(Pd)/게르마늄(Ge)/금(Au)으로 형성될 수 있으며, 상기 팔라듐/게르마늄/금은 5nm/20nm/250nm의 두께로 형성될 수 있다.The front electrode may be formed of palladium (Pd) / germanium (Ge) / gold (Au), the palladium / germanium / gold may be formed to a thickness of 5nm / 20nm / 250nm.
본 발명에 따른 화합물 반도체 태양전지의 제조 방법에 따르면, 전면 전극을 형성하고 어닐링을 실시한 후에 화합물 반도체층을 모기판으로부터 분리하므로, 전면 전극의 접촉 저항을 감소시킬 수 있다.According to the method for manufacturing a compound semiconductor solar cell according to the present invention, since the compound semiconductor layer is separated from the mother substrate after forming the front electrode and performing annealing, the contact resistance of the front electrode can be reduced.
그리고 ELO 공정을 실시하는 동안 화합물 반도체층을 지지하는 지지 필름을 제거하지 않고 모듈의 전면 기판으로 사용할 수 있으므로, 생산성 향상 및 제조 원가의 절감이 가능하다.In addition, the ELO process can be used as a front substrate of the module without removing the support film for supporting the compound semiconductor layer, thereby improving productivity and reducing manufacturing costs.
도 1은 본 발명의 실시예에 따른 화합물 반도체 태양전지의 제조 방법을 나타내는 공정도이다.1 is a process chart showing a method of manufacturing a compound semiconductor solar cell according to an embodiment of the present invention.
도 2는 도 1에 도시한 화합물 반도체 태양전지의 개략적인 구성을 나타내는 사시도이다.FIG. 2 is a perspective view showing a schematic configuration of the compound semiconductor solar cell shown in FIG. 1.
도 3은 도 2에 도시한 전면 전극을 촬영한 사진이다.3 is a photograph of the front electrode illustrated in FIG. 2.
도 4는 도 1에 도시한 어닐링 단계의 공정 조건에 따른 접촉 저항의 변화를 나타내는 그래프이다.4 is a graph showing a change in contact resistance according to the process conditions of the annealing step shown in FIG.
도 5는 도 1에 도시한 어닐링 단계의 실시 여부에 따른 화합물 반도체 태양전지의 효율을 나타내는 표이다.FIG. 5 is a table illustrating efficiency of a compound semiconductor solar cell according to whether or not annealing step illustrated in FIG. 1 is performed.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해될 수 있다.As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. It is not intended to limit the invention to the specific embodiments, it can be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.
본 발명을 설명함에 있어서 제1, 제2 등의 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되지 않을 수 있다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용될 수 있다. In describing the present invention, terms such as first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component.
예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성요소는 제2 구성요소로 명명될 수 있고, 유사하게 제2 구성요소도 제1 구성요소로 명명될 수 있다.For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
"및/또는" 이라는 용어는 복수의 관련된 기재된 항목들의 조합 또는 복수의 관련된 기재된 항목들 중의 어느 항목을 포함할 수 있다.The term "and / or" may include a combination of a plurality of related items or any of a plurality of related items.
어떤 구성요소가 다른 구성요소에 "연결되어" 있다거나 "결합되어" 있다고 언급되는 경우는, 그 다른 구성요소에 직접적으로 연결되어 있거나 또는 결합되어 있을 수도 있지만, 중간에 다른 구성요소가 존재할 수도 있다고 이해될 수 있다.When a component is said to be "connected" or "coupled" to another component, it may be directly connected to or coupled to the other component, but other components may be present in the middle. Can be understood.
반면에, 어떤 구성요소가 다른 구성요소에 "직접 연결되어" 있다거나 "직접 결합되어" 있다고 언급된 때에는, 중간에 다른 구성요소가 존재하지 않는 것으로 이해될 수 있다.On the other hand, when a component is referred to as being "directly connected" or "directly coupled" to another component, it may be understood that there is no other component in between.
본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함할 수 있다.The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions may include plural expressions unless the context clearly indicates otherwise.
본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것으로서, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해될 수 있다.In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It may be understood that the present invention does not exclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or a combination thereof.
도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 층, 막, 영역, 판 등의 부분이 다른 부분 "위에" 있다고 할 때, 이는 다른 부분 "바로 위에" 있는 경우뿐 아니라 그 중간에 다른 부분이 있는 경우도 포함한다. 반대로 어떤 부분이 다른 부분 "바로 위에" 있다고 할 때에는 중간에 다른 부분이 없는 것을 뜻한다.In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가질 수 있다. Unless defined otherwise, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art.
일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미를 가지는 것으로 해석될 수 있으며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않을 수 있다.Terms such as those defined in the commonly used dictionaries may be interpreted as having meanings consistent with the meanings in the context of the related art, and shall be interpreted in ideal or excessively formal meanings unless expressly defined in the present application. It may not be.
아울러, 이하의 실시예는 당 업계에서 평균적인 지식을 가진 자에게 보다 완전하게 설명하기 위해서 제공되는 것으로서, 도면에서의 요소들의 형상 및 크기 등은 보다 명확한 설명을 위해 과장될 수 있다.In addition, the following embodiments are provided to more fully describe those skilled in the art, and the shape and size of the elements in the drawings may be exaggerated for clarity.
이하, 첨부도면을 참조하여 본 발명에 대해 설명한다.Hereinafter, the present invention will be described with reference to the accompanying drawings.
도 1은 본 발명의 실시예에 따른 화합물 반도체 태양전지의 제조 방법을 나타내는 공정도이다.1 is a process chart showing a method of manufacturing a compound semiconductor solar cell according to an embodiment of the present invention.
도 2는 도 1에 도시한 화합물 반도체 태양전지의 개략적인 구성을 나타내는 사시도이다.FIG. 2 is a perspective view showing a schematic configuration of the compound semiconductor solar cell shown in FIG. 1.
도 3은 도 2에 도시한 전면 전극을 촬영한 사진이다.3 is a photograph of the front electrode illustrated in FIG. 2.
도 4는 도 1에 도시한 어닐링 단계의 공정 조건에 따른 접촉 저항의 변화를 나타내는 그래프이다.4 is a graph showing a change in contact resistance according to the process conditions of the annealing step shown in FIG.
도 5는 도 1에 도시한 어닐링 단계의 실시 여부에 따른 화합물 반도체 태양전지의 효율을 나타내는 표이다.FIG. 5 is a table illustrating efficiency of a compound semiconductor solar cell according to whether or not annealing step illustrated in FIG. 1 is performed.
먼저, 본 발명의 제조 방법에 의해 제조한 화합물 반도체 태양전지에 대해 도 2 및 도 3을 참조하여 설명한다.First, the compound semiconductor solar cell manufactured by the manufacturing method of this invention is demonstrated with reference to FIG.
화합물 반도체 태양전지는 광 흡수층(PV), 광 흡수층(PV)의 전면(front surface) 위에 위치하는 윈도우층(10), 윈도우층(10)의 전면 위에 위치하는 그리드 형상의 전면 전극(20), 윈도우층(10)과 전면 전극(20) 사이에 위치하는 전면 콘택층(30), 윈도우층(10) 위에 위치하는 반사 방지막(40), 광 흡수층(PV)의 후면 위에 위치하는 후면 콘택층(50) 및 후면 콘택층(50)의 후면 위에 위치하는 후면 전극(60)을 포함할 수 있다. The compound semiconductor solar cell includes a light absorbing layer PV, a window layer 10 positioned on the front surface of the light absorbing layer PV, a grid-shaped front electrode 20 positioned on the front surface of the window layer 10, The front contact layer 30 positioned between the window layer 10 and the front electrode 20, the antireflection film 40 positioned on the window layer 10, and the rear contact layer positioned on the rear surface of the light absorbing layer PV ( 50 and a rear electrode 60 positioned on the rear surface of the rear contact layer 50.
여기서, 반사 방지막(40), 윈도우층(10), 전면 콘택층(30) 및 후면 콘택층(50) 중 적어도 하나는 생략될 수도 있지만, 도 2에 도시된 바와 같이 상기 층들이 구비된 경우를 일례로 설명한다.Here, at least one of the anti-reflection film 40, the window layer 10, the front contact layer 30, and the rear contact layer 50 may be omitted. However, as shown in FIG. It demonstrates as an example.
광 흡수층(PV)은 III-VI족 반도체 화합물, 일례로, 갈륨(Ga), 인듐(In) 및 인(P)이 함유된 GaInP 화합물 또는 갈륨(Ga)과 비소(As)가 함유된 GaAs 화합물을 포함하여 형성될 수 있다.The light absorbing layer (PV) is a group III-VI semiconductor compound, for example, a GaInP compound containing gallium (Ga), indium (In) and phosphorus (P), or a GaAs compound containing gallium (Ga) and arsenic (As). It may be formed to include.
광 흡수층(PV)은 제1 도전성 타입의 불순물, 한 예로 p형 불순물이 도핑되는 p형 반도체층(PV-p)과, 제2 도전성 타입의 불순물, 한 예로 n형 불순물이 도핑되는 n형 반도체층(PV-n)을 포함할 수 있다.The light absorption layer PV is a p-type semiconductor layer PV-p doped with an impurity of a first conductivity type, for example, a p-type impurity, and an n-type semiconductor doped with an impurity of a second conductivity type, for example, an n-type impurity. Layer (PV-n).
그리고 도시하지는 않았지만, 광 흡수층(PV)은 p형 반도체층(PV-p)의 후면에 위치하는 후면 전계층을 더 포함할 수 있다.Although not shown, the light absorbing layer PV may further include a rear electric field layer disposed at the rear of the p-type semiconductor layer PV-p.
이러한 구성의 광 흡수층(PV)은 MOCVD(Metal Organic Chemical Vapor Deposition) 방법, MBE(Molecular Beam Epitaxy) 방법 또는 에피택셜층을 형성하기 위한 임의의 다른 적절한 방법에 의해 모기판(mother substrate)으로부터 제조할 수 있다.The light absorbing layer (PV) of this configuration can be prepared from a mother substrate by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method or any other suitable method for forming an epitaxial layer. Can be.
윈도우층(10)은 광 흡수층(PV)과 전면 전극(20) 사이에 형성될 수 있으며, III-VI족 반도체 화합물에 제2 도전성 타입, 즉 n형의 불순물을 도핑하여 형성할 수 있다.The window layer 10 may be formed between the light absorbing layer PV and the front electrode 20, and may be formed by doping a III-VI group semiconductor compound with a second conductivity type, that is, an n-type impurity.
윈도우층(10)은 광 흡수층(PV)의 전면(front surface)을 패시베이션(passivation)하는 기능을 하며, 광 흡수층(PV)의 에너지 밴드갭보다 높은 에너지 밴드갭을 가질 수 있다.The window layer 10 functions to passivate the front surface of the light absorbing layer PV, and may have an energy band gap higher than that of the light absorbing layer PV.
반사 방지막(40)은 윈도우층(10)의 전면 위 중에서 전면 전극(20) 및/또는 전면 콘택층(30)이 위치하는 영역을 제외한 나머지 영역에 위치할 수 있다.The anti-reflection film 40 may be located on the remaining area of the window layer 10 except for the area where the front electrode 20 and / or the front contact layer 30 is located.
이와 달리, 반사 방지막(40)은 노출된 윈도우층(10) 뿐만 아니라, 전면 콘택층(30) 및 전면 전극(20) 위에 배치될 수도 있다.Alternatively, the anti-reflection film 40 may be disposed on the front contact layer 30 and the front electrode 20 as well as the exposed window layer 10.
이 경우, 도시하지는 않았지만 화합물 반도체 태양전지는 복수의 전면 전극(20)을 물리적으로 연결하는 버스바 전극을 더 구비할 수 있으며, 버스바 전극은 반사 방지막(40)에 의해 덮여지지 않고 외부로 노출될 수 있다.In this case, although not shown, the compound semiconductor solar cell may further include a busbar electrode for physically connecting the plurality of front electrodes 20, and the busbar electrode is not covered by the anti-reflection film 40 and exposed to the outside. Can be.
전면 전극(20)은 제1 방향(X-X')으로 길게 연장되어 형성될 수 있으며, 제1 방향과 직교하는 제2 방향(Y-Y')을 따라 복수개가 일정한 간격으로 이격될 수 있다.The front electrode 20 may be formed to extend in the first direction X-X ', and the plurality of front electrodes 20 may be spaced apart at regular intervals along the second direction Y-Y' perpendicular to the first direction. .
이러한 구성의 전면 전극(20)은 전기 전도성 물질을 포함하여 형성될 수 있으며, 일례로 금속인 금(Au), 게르마늄(Ge), 니켈(Ni) 중 적어도 하나를 포함하여 형성될 수 있다.The front electrode 20 having such a configuration may be formed by including an electrically conductive material. For example, the front electrode 20 may include at least one of gold (Au), germanium (Ge), and nickel (Ni).
한 예로, 전면 전극(20)은 팔라듐(Pd)/게르마늄(Ge)/금(Au)으로 형성될 수 있으며, 팔라듐/게르마늄/금은 5nm/20nm/250nm의 두께로 형성될 수 있다.For example, the front electrode 20 may be formed of palladium (Pd) / germanium (Ge) / gold (Au), and the palladium / germanium / gold may be formed to a thickness of 5 nm / 20 nm / 250 nm.
윈도우층(10)과 전면 전극(20) 사이에 위치하는 전면 콘택층(30)은 III-VI족 반도체 화합물에 윈도우층(10)의 불순물 도핑농도보다 높은 도핑농도로 제2 불순물을 도핑하여 형성할 수 있다.The front contact layer 30 positioned between the window layer 10 and the front electrode 20 is formed by doping the group III-VI semiconductor compound with a second impurity at a doping concentration higher than the impurity doping concentration of the window layer 10. can do.
광 흡수층(PV)의 p형 반도체층(PV-p)의 후면 위에 위치하는 후면 콘택층(50)은 광 흡수층(PV)의 후면에 전체적으로 위치하며, III-VI족 반도체 화합물에 제1 도전성 타입의 불순물을 p형 반도체층(PV-p)보다 높은 도핑농도로 도핑하여 형성할 수 있다.The rear contact layer 50 located on the rear surface of the p-type semiconductor layer PV-p of the light absorption layer PV is generally located on the rear surface of the light absorption layer PV, and has a first conductivity type in the group III-VI semiconductor compound. May be formed by doping at a higher doping concentration than the p-type semiconductor layer PV-p.
그리고 후면 콘택층(50)의 후면 위에 위치하는 후면 전극(60)은 전면 전극(20)과는 다르게 후면 콘택층(50)의 후면에 전체적으로 위치하는 시트(Sheet) 형상의 도전체로 형성될 수 있다. 즉, 후면 전극(60)은 후면 콘택층(50)의 후면 전체에 위치하는 면 전극(sheet electrode)이라고도 말할 수 있다.In addition, unlike the front electrode 20, the rear electrode 60 positioned on the rear surface of the rear contact layer 50 may be formed of a sheet-shaped conductor positioned entirely on the rear surface of the rear contact layer 50. . That is, the rear electrode 60 may also be referred to as a sheet electrode positioned on the entire rear surface of the rear contact layer 50.
이때, 후면 전극(60)은 광 흡수층(PV)과 동일한 평면적으로 형성될 수 있으며, 금(Au), 백금(Pt), 티타늄(Ti), 텅스텐(W), 규소(Si), 니켈(Ni), 마그네슘(Mg), 팔라듐(Pd), 구리(Cu), 및 게르마늄(Ge) 중에서 선택된 적어도 어느 한 물질을 포함하는 단일막 또는 다중막으로 형성될 수 있고, 후면 전극을 형성하는 물질은 후면 콘택층의 도전성 타입에 따라 적절하게 선택될 수 있다.In this case, the rear electrode 60 may be formed in the same plane as the light absorbing layer PV, and may include gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), and nickel (Ni). ), Magnesium (Mg), palladium (Pd), copper (Cu), and germanium (Ge) may be formed as a single film or a multi-layer including at least one material selected from, and the material forming the rear electrode is It may be appropriately selected depending on the conductivity type of the contact layer.
이하, 상기한 화합물 반도체 태양전지의 제조 방법에 대해 설명한다.Hereinafter, the manufacturing method of said compound semiconductor solar cell is demonstrated.
본 발명의 제조 방법은 크게, 모기판(110)의 한쪽 면 위에 희생층(120)을 형성한 후 레귤러(regular) 성장법을 이용하여 상기 희생층(120) 위에 화합물 반도체층(CS)을 형성하는 단계; 상기 화합물 반도체층(CS)의 전면(front surface)에 그리드 형상의 전면 전극(20)을 복수 개 형성한 후, 어닐링하는 단계; 메사 에칭(mesa etching)을 실시하여, 상기 전면 전극(20)을 구비하는 셀(C)을 복수 개 형성하는 단계; 접착 물질(130)을 이용하여, 상기 복수의 셀(C) 각각에 구비된 화합물 반도체층(CS)의 전면(front surface) 쪽에 지지 필름(140)을 부착하는 단계; ELO(Epitaxial lift off) 공정을 실시하여, 상기 복수의 셀(C)을 상기 모기판(110)으로부터 분리하는 단계; 상기 복수의 셀(C) 각각에 구비된 화합물 반도체층(CS)의 후면(back surface)에 후면 전극(60)을 형성하는 단계; 상기 복수의 셀(C) 사이 영역에서 상기 지지 필름(140)을 절단하는 단계; 및 절단한 지지 필름(140)을 전면 기판으로 사용하여 복수의 셀(C)을 각각 모듈화 하는 단계를 포함한다.In the manufacturing method of the present invention, the sacrificial layer 120 is formed on one side of the mother substrate 110, and then the compound semiconductor layer CS is formed on the sacrificial layer 120 by using a regular growth method. Making; Forming a plurality of grid-shaped front electrodes 20 on the front surface of the compound semiconductor layer CS and then annealing; Performing mesa etching to form a plurality of cells C including the front electrode 20; Attaching the support film 140 to the front surface side of the compound semiconductor layer CS provided in each of the plurality of cells C using the adhesive material 130; Performing an epitaxial lift off (ELO) process to separate the plurality of cells (C) from the mother substrate (110); Forming a rear electrode (60) on a back surface of the compound semiconductor layer (CS) provided in each of the plurality of cells (C); Cutting the support film 140 in an area between the plurality of cells C; And modularizing the plurality of cells C using the cut support film 140 as a front substrate.
이에 대해 보다 상세히 설명하면, 먼저, 광 흡수층(PV)이 형성되는 적절한 격자 구조를 제공하기 위한 베이스로 작용하는 모기판(110, mother substrate)의 한쪽 면에 희생층(120)을 형성하고, 레귤러(regular) 성장법을 이용하여 희생층(120) 위에 화합물 반도체층(CS)을 형성한다.In more detail, first, the sacrificial layer 120 is formed on one side of a mother substrate 110 serving as a base for providing an appropriate lattice structure in which the light absorbing layer PV is formed, and is regular. The compound semiconductor layer CS is formed on the sacrificial layer 120 by using a regular growth method.
여기에서, 레귤러 성장법은 희생층(120) 위에, 후면 콘택층(50), 광 흡수층(PV), 윈도우층(10) 및 전면 콘택층(30)을 순차적으로 형성하는 방법을 말하며, 인버스(inverse) 성장법은 레귤러 성장법의 반대되는 순서로 각 층을 형성하는 방법을 말한다.Here, the regular growth method refers to a method of sequentially forming the back contact layer 50, the light absorbing layer PV, the window layer 10, and the front contact layer 30 on the sacrificial layer 120. inverse) is a method of forming each layer in the reverse order of the regular growth method.
이어서, 상기 화합물 반도체층(CS)의 전면(front surface)에 그리드 형상의 전면 전극(20)을 복수 개 형성한다.Subsequently, a plurality of grid-shaped front electrodes 20 are formed on the front surface of the compound semiconductor layer CS.
여기에서, 전면 전극(20)을 복수 개 형성하는 것은 희생층(120) 위에 형성된 화합물 반도체층(CS)을 메사 에칭하여 복수의 셀(C)을 형성하기 위함이다.Here, the plurality of front electrodes 20 are formed to form a plurality of cells C by mesa etching the compound semiconductor layer CS formed on the sacrificial layer 120.
복수의 전면 전극(20)을 형성한 후, 어닐링 공정을 실시한다.After the plurality of front electrodes 20 are formed, an annealing process is performed.
어닐링 공정은 전면 전극(20)을 열처리하여 전면 전극의 접촉 저항을 감소시키기 위한 것으로, 400℃ 내지 500℃의 온도에서 5분 내지 15분 동안 실시한다.The annealing process is to reduce the contact resistance of the front electrode by heat treatment of the front electrode 20, it is carried out for 5 to 15 minutes at a temperature of 400 ℃ to 500 ℃.
도 4는 도 1에 도시한 어닐링 단계의 공정 조건에 따른 전면 전극의 접촉 저항의 변화를 나타내는 그래프이고, 도 5는 도 1에 도시한 어닐링 단계의 실시 여부에 따른 화합물 반도체 태양전지의 효율을 나타내는 표로서, 도 4 및 도 5는 5nm 두께의 팔라듐(Pd)/20nm 두께의 게르마늄(Ge)/250nm 두께의 금(Au)으로 전면 전극(20)을 형성한 경우에 측정한 결과를 나타낸다.FIG. 4 is a graph showing a change in contact resistance of the front electrode according to the process conditions of the annealing step illustrated in FIG. 1, and FIG. 5 illustrates the efficiency of a compound semiconductor solar cell according to whether or not the annealing step illustrated in FIG. As a table, FIG. 4 and FIG. 5 show the measurement results when the front electrode 20 is formed of 5 nm thick palladium (Pd) / 20 nm thick germanium (Ge) / 250 nm thick gold (Au).
전면 전극은 진공(evaporation)법, 스퍼터링(sputtering)법, 도금(plating)법 및 스크린 인쇄(screen printing)법 중에서 어느 한 방법으로 형성할 수 있다.The front electrode may be formed by any one of an evaporation method, a sputtering method, a plating method, and a screen printing method.
도 4를 참조하면, 200℃의 온도 및 300℃의 온도로 전면 전극(20)을 어닐링하는 경우에는 어닐링 시간의 증감에 관계없이 전면 전극(20)의 접촉 저항이 대략 10mΩ/㎝ 2인 것을 알 수 있다.Referring to FIG. 4, when annealing the front electrode 20 at a temperature of 200 ° C. and a temperature of 300 ° C., the contact resistance of the front electrode 20 is about 10 mPa / cm 2 regardless of the increase or decrease of the annealing time. Can be.
하지만, 본원 발명에 개시된 바와 같이 400℃의 온도에서 5분 이상 어닐링을 실시하면, 전면 전극(20)의 접촉 저항이 대략 1mΩ/㎝ 2 이하로 낮아지는 것을 알 수 있다.However, when annealing is performed for 5 minutes or more at a temperature of 400 ° C as disclosed in the present invention, it can be seen that the contact resistance of the front electrode 20 is lowered to about 1 mPa / cm 2 or less.
따라서, 전면 전극(20)의 어닐링 공정은 400℃ 내지 500℃의 온도에서 5분 내지 15분 동안 실시하는 것이 바람직하다.Therefore, the annealing process of the front electrode 20 is preferably carried out for 5 to 15 minutes at a temperature of 400 ℃ to 500 ℃.
그리고 도 5를 참조하여 어닐링 실시 전(종래)과 어닐링 실시 후(본 발명)의 태양전지의 효율에 대해 살펴 보면, 개방전압(Voc)과 면저항(Rs)은 어닐링 실시 후의 태양전지가 어닐링 실시 전의 태양전지에 비해 각각 낮아지고, 단락전류밀도(Jsc)와 필팩터(FF)는 어닐링 실시 후의 태양전지가 어닐링 실시 전의 태양전지에 비해 각각 증가하는 것을 알 수 있다.Referring to FIG. 5, the efficiency of the solar cell before (annealed) and after the annealing (invention) will be described with reference to FIG. 5. Compared with the solar cell, it is lower, respectively, and the short-circuit current density Jsc and the fill factor FF show that the solar cell after annealing is increased compared with the solar cell before annealing.
따라서, 본원 발명에서와 같이 전면 전극(20)을 형성한 후에 어닐링을 실시하면, 어닐링을 실시하지 않은 종래의 경우에 비해 효율(Eff)가 증가하는 것을 알 수 있다.Therefore, when the annealing is performed after the front electrode 20 is formed as in the present invention, it can be seen that the efficiency Eff is increased as compared with the conventional case where the annealing is not performed.
이와 같이, 본 발명에 있어서 전면 전극(20)을 형성한 후에 어닐링 공정을 실시할 수 있는 이유는 ELO 공정을 실시하기 전에 전면 전극 형성 공정 및 어닐링 공정을 실시하기 때문이다.As described above, the reason why the annealing process can be performed after the front electrode 20 is formed in the present invention is that the front electrode forming step and the annealing step are performed before the ELO process.
즉, 종래의 제조 방법과 비교해 보면, 종래에는 ELO 공정에서 화합물 반도체층을 지지함과 아울러 ELO 공정에서 사용되는 식각 용액으로부터 화합물 반도체층을 보호할 수 있도록 하기 위해 금속 보호층을 형성한 후, 왁스(wax)를 사용하여 라미네이션 필름을 금속 보호층에 부착하였다.That is, compared with the conventional manufacturing method, conventionally, after forming a metal protective layer to support the compound semiconductor layer in the ELO process and to protect the compound semiconductor layer from the etching solution used in the ELO process, wax (wax) was used to attach the lamination film to the metal protective layer.
따라서, 종래 방법에 따르면, 금속 보호층을 형성하기 위한 증착 시간이 많이 요구되거나 고가의 금속 사용으로 인한 비용 상승 등의 문제로 인해 화합물 반도체 태양전지의 제조 원가가 상승하고, 또한 상기 금속 보호층과 라미네이션 필름을 제거해야 하기 때문에 공정수가 증가하고, 금속 보호층과 라미네이션 필름의 제거 과정에서 화합물 반도체층의 손상이 발생하는 등의 문제점이 있다.Therefore, according to the conventional method, the manufacturing cost of the compound semiconductor solar cell is increased due to a problem such as a high deposition time required for forming the metal protective layer or a cost increase due to the use of expensive metal, and also the metal protective layer and Since the lamination film needs to be removed, there is a problem in that the number of processes increases, and damage to the compound semiconductor layer occurs during the removal of the metal protective layer and the lamination film.
또한, 종래 방법에 따르면, ELO 공정에 의해 화합물 반도체층을 모기판으로부터 분리한 후 화합물 반도체층에 금속 전극(전면 전극)을 형성하고 있으므로, 전면 전극 형성 공정에서 화합물 반도체층을 지지하기 위한 캐리어 기판을 화합물 반도체층에 부착해야 한다.In addition, according to the conventional method, since the metal compound (front electrode) is formed in the compound semiconductor layer after the compound semiconductor layer is separated from the mother substrate by the ELO process, the carrier substrate for supporting the compound semiconductor layer in the front electrode formation step Should be attached to the compound semiconductor layer.
그런데, 캐리어 기판을 화합물 반도체층에 부착하기 위한 접착제는 열에 매우 취약하므로, 전극 형성 후에 접촉 저항을 감소시키기 위한 열처리를 진행하기 어려우며, 이로 인해 화합물 반도체 태양전지의 효율 개선에 제한이 있는 문제점이 있다.However, since the adhesive for attaching the carrier substrate to the compound semiconductor layer is very vulnerable to heat, it is difficult to proceed the heat treatment to reduce the contact resistance after electrode formation, which has a problem in that the efficiency of the compound semiconductor solar cell is limited. .
하지만, 본 발명의 제조 방법에 따르면, 전면 전극(20)을 형성한 후에 어닐링 공정을 실시하고, 이후 ELO 공정을 실시하므로, 종래의 제조 방법에서 발생하는 문제점을 제거할 수 있다.However, according to the manufacturing method of the present invention, since the annealing process is performed after the front electrode 20 is formed, and then the ELO process is performed, problems occurring in the conventional manufacturing method can be eliminated.
한편, 본원 발명의 제조 방법에서는 EOL 공정을 실시하기 전에 전면 전극(20)을 형성하고 및 어닐링 공정을 실시하므로, 전면 전극(20)의 형성 공정에서 모기판(110)이 화합물 반도체층(CS)을 확실히 지지할 수 있다.Meanwhile, in the manufacturing method of the present invention, the front electrode 20 is formed and the annealing process is performed before the EOL process, so that the mother substrate 110 is formed of the compound semiconductor layer CS in the process of forming the front electrode 20. I can definitely support it.
따라서, 도 3에 도시한 바와 같이, ELO 공정 후에 전면 전극을 형성한 종래의 경우(도 3의 좌측에 도시한 사진)에 비해 전면 전극의 오정렬을 줄일 수 있는 효과도 얻을 수 있다.Therefore, as shown in FIG. 3, the effect of reducing misalignment of the front electrode can be obtained as compared with the conventional case in which the front electrode is formed after the ELO process (photo shown on the left side of FIG. 3).
어닐링 공정을 실시한 후에는 반사 방지막(40)을 형성한다.After the annealing process is performed, the antireflection film 40 is formed.
반사 방지막(40) 형성 공정은 생략될 수 있다.The anti-reflection film 40 forming process may be omitted.
반사 방지막(40)을 형성한 후에는 메사 에칭(mesa etching)을 실시한다.After the anti-reflection film 40 is formed, mesa etching is performed.
여기에서, 메사 에칭은 1개의 화합물 반도체층(CS)을 여러 개로 분리하여 1개의 화합물 반도체층(CS)에서 복수의 셀(C), 즉 여러 개의 화합물 반도체 태양전지를 제조하기 위한 에칭 공정을 의미한다.Here, mesa etching refers to an etching process for manufacturing a plurality of cells (C), that is, a plurality of compound semiconductor solar cells in one compound semiconductor layer (CS) by separating one compound semiconductor layer (CS) into several. do.
메사 에칭을 실시하여 복수의 셀(C)을 형성한 후에는 복수의 셀(C) 각각에 구비된 화합물 반도체층(CS)의 전면(front surface) 쪽에 지지 필름(140)을 부착한다.After the mesa etching is performed to form the plurality of cells C, the supporting film 140 is attached to the front surface side of the compound semiconductor layer CS provided in each of the plurality of cells C.
이때, 지지 필름(140)은 접착 물질(130)을 이용하여 부착할 수 있다.In this case, the support film 140 may be attached using the adhesive material 130.
그런데, 본 발명의 제조 방법에 있어서, 지지 필름(140)은 제거되지 않고 화합물 반도체 태양전지의 모듈화 공정에서 전면 기판으로 사용된다.By the way, in the manufacturing method of this invention, the support film 140 is not removed and is used as a front substrate in the modularization process of a compound semiconductor solar cell.
따라서, 화합물 반도체층(CS)으로 빛이 효과적으로 입사되도록 하기 위해, 지지 필름(140)은 1.0 내지 2.0의 굴절률과, 450nm 내지 950nm의 파장대에서 80% 이상의 광 투과율을 갖는 물질로 형성하고, 접착 물질(130)은 1.0 내지 2.0의 굴절률과, 450nm 내지 950nm의 파장대에서 80% 이상의 광 투과율을 가지며 100kgf/cm 2 내지 500kgf/cm 2의 접착 강도를 갖는 물질로 형성하는 것이 바람직하다.Therefore, in order to allow light to effectively enter the compound semiconductor layer CS, the support film 140 is formed of a material having a refractive index of 1.0 to 2.0 and a light transmittance of 80% or more in the wavelength range of 450 nm to 950 nm, and an adhesive material. 130 is preferably from 1.0 to have a refractive index and, 450nm to the light transmittance of 80% or more in the wavelength range of 950nm of 2.0 to form a material having a bond strength of 100kgf / cm 2 to 500kgf / cm 2.
지지 필름(140)을 부착한 후, ELO(Epitaxial lift off) 공정을 실시하여, 상기 복수의 셀(C)을 모기판(110)으로부터 분리한다.After attaching the supporting film 140, an epitaxial lift off (ELO) process is performed to separate the plurality of cells C from the mother substrate 110.
이어서, 지지 필름(140)에 캐리어 기판(150)을 접착제에 의해 부착하고, 캐리어 기판(150)을 지지 필름(140)에 부착한 상태에서 복수의 셀(C) 각각에 구비된 화합물 반도체층(CS)의 후면(back surface)에 후면 전극(60)을 형성한 후, 캐리어 기판(150)을 제거한다.Subsequently, the carrier substrate 150 is attached to the support film 140 by an adhesive, and the compound semiconductor layer provided in each of the plurality of cells C in the state in which the carrier substrate 150 is attached to the support film 140 ( After forming the back electrode 60 on the back surface of the CS, the carrier substrate 150 is removed.
본 발명의 제조 방법에 있어서, 지지 필름(140)이 화합물 반도체층(CS)을 지지할 수 있을 정도의 강도를 갖는다면 캐리어 기판(150)의 부착 및 제거 공정은 삭제할 수 있다.In the manufacturing method of the present invention, the process of attaching and removing the carrier substrate 150 may be omitted if the supporting film 140 has a strength sufficient to support the compound semiconductor layer CS.
그리고 후면 전극(60)을 형성할 때에는 후면 전극을 형성하는 물질이 셀(C)간 영역에 채워질 수 있는데, 셀(C)간 영역에 채워진 후면 전극 형성 물질은 이후 설명할 지지 필름(140)의 절단 공정에서 제거할 수 있다.When the back electrode 60 is formed, the material forming the back electrode may be filled in the region between the cells C. The back electrode forming material filled in the region between the cells C may be formed in the support film 140 to be described later. Can be removed in the cutting process.
후면 전극(60)을 형성한 후, 복수의 셀(C) 사이 영역에 레이저를 조사하여 지지 필름(140)을 절단함과 아울러 셀(C)간 영역에 채워진 후면 전극 형성 물질을 제거한다.After the back electrode 60 is formed, the support film 140 is cut by irradiating a laser to a region between the plurality of cells C, and the back electrode forming material filled in the region between the cells C is removed.
이후, 절단한 지지 필름(140)을 전면 기판으로 사용하여 복수의 셀(C)을 각각 모듈화 한다.Thereafter, the plurality of cells C are modularized using the cut support film 140 as the front substrate.
상기 모듈화 단계에서는 후면 전극(60)의 하부에 후면 기판(160)을 설치하고, 전면 기판(140)과 후면 기판(160) 사이에 밀봉재(170)를 배치할 수 있는데, 이때, 밀봉재(170)는 접착 물질(130)과 동일한 물질로 형성하거나, 서로 다른 물질로 형성할 수 있다.In the modularization step, the rear substrate 160 may be installed below the rear electrode 60, and the sealing material 170 may be disposed between the front substrate 140 and the rear substrate 160, in which case the sealing material 170 may be disposed. May be formed of the same material as the adhesive material 130 or may be formed of different materials.
이상에서 본 발명의 바람직한 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (10)

  1. 모기판의 한쪽 면 위에 희생층을 형성하는 단계;Forming a sacrificial layer on one side of the mother substrate;
    레귤러(regular) 성장법을 이용하여 상기 희생층 위에 화합물 반도체층을 형성하는 단계;Forming a compound semiconductor layer on the sacrificial layer by using a regular growth method;
    상기 화합물 반도체층의 전면(front surface)에 그리드 형상의 전면 전극을 복수 개 형성한 후, 어닐링하는 단계;Forming a plurality of grid-shaped front electrodes on a front surface of the compound semiconductor layer and then annealing;
    메사 에칭(mesa etching)을 실시하여, 상기 전면 전극을 구비하는 셀을 복수 개 형성하는 단계;Performing a mesa etching to form a plurality of cells having the front electrode;
    접착 물질을 이용하여, 상기 복수의 셀 각각에 구비된 화합물 반도체층의 전면(front surface) 쪽에 지지 필름을 부착하는 단계;Attaching a support film to the front surface side of the compound semiconductor layer provided in each of the plurality of cells using an adhesive material;
    ELO(Epitaxial lift off) 공정을 실시하여, 상기 복수의 셀을 상기 모기판으로부터 분리하는 단계;Performing an epitaxial lift off (ELO) process to separate the plurality of cells from the mother substrate;
    상기 복수의 셀 각각에 구비된 화합물 반도체층의 후면(back surface)에 후면 전극을 형성하는 단계; Forming a back electrode on a back surface of the compound semiconductor layer provided in each of the plurality of cells;
    상기 복수의 셀 사이 영역에서 상기 지지 필름을 절단하는 단계; 및Cutting the support film in the region between the plurality of cells; And
    절단한 지지 필름을 전면 기판으로 사용하여 복수의 셀을 각각 모듈화 하는 단계Modularizing a plurality of cells, respectively, using the cut support film as the front substrate.
    를 포함하는 화합물 반도체 태양전지의 제조 방법.Method for producing a compound semiconductor solar cell comprising a.
  2. 제1항에서,In claim 1,
    상기 메사 에칭을 실시한 후, 상기 화합물 반도체층의 전면(front surface)에 반사 방지막을 형성하고, 이후, 상기 지지 필름을 부착하는 단계를 실시하는 화합물 반도체 태양전지의 제조 방법.After the mesa etching, forming an anti-reflection film on the front surface of the compound semiconductor layer, and then attaching the support film.
  3. 제1항 또는 제2항에서,The method of claim 1 or 2,
    상기 지지 필름은 1.0 내지 2.0의 굴절률과, 450nm 내지 950nm의 파장대에서 80% 이상의 광 투과율을 갖는 물질로 형성하고,The support film is formed of a material having a refractive index of 1.0 to 2.0 and a light transmittance of 80% or more in the wavelength range of 450 nm to 950 nm,
    상기 접착 물질은 1.0 내지 2.0의 굴절률과, 450nm 내지 950nm의 파장대에서 80% 이상의 광 투과율을 가지며 100kgf/cm 2 내지 500kgf/cm 2의 접착 강도를 갖는 물질로 형성하는 화합물 반도체 태양전지의 제조 방법.The adhesive material of 1.0 to have a refractive index and, 450nm to the light transmittance of 80% or more in the wavelength range of 950nm of 2.0 100kgf / cm 2 to compound A method for fabricating a semiconductor solar cell formed of a material having an adhesive strength of 500kgf / cm 2.
  4. 제3항에서,In claim 3,
    상기 지지 필름은 PET(polyethylene terephthalate) 또는 PI(polyimide)로 형성하고, 상기 접착 물질은 에폭시(epoxy), 에바(ethylene-vinyl acetate), 또는 UV 경화제로 형성하는 화합물 반도체 태양전지의 제조 방법.The support film is formed of polyethylene terephthalate (PET) or polyimide (PI), and the adhesive material is formed of epoxy (epoxy), EVA (ethylene-vinyl acetate), or a UV curing agent manufacturing method of a compound semiconductor solar cell.
  5. 제3항에서,In claim 3,
    상기 어닐링하는 단계는 400℃ 내지 500℃의 온도에서 5분 내지 15분 동안 실시하는 화합물 반도체 태양전지의 제조 방법.The annealing is carried out for 5 minutes to 15 minutes at a temperature of 400 ℃ to 500 ℃ manufacturing method of a compound semiconductor solar cell.
  6. 제5항에서,In claim 5,
    상기 모듈화 단계에서, 상기 후면 전극의 하부에 후면 기판을 설치하고, 상기 전면 기판과 후면 기판 사이에 밀봉재를 배치하되, 상기 밀봉재를 상기 접착 물질과 동일한 물질로 형성하는 화합물 반도체 태양전지의 제조 방법.In the modularizing step, a rear substrate is provided below the rear electrode and a sealing material is disposed between the front substrate and the rear substrate, wherein the sealing material is a manufacturing method of a compound semiconductor solar cell.
  7. 제5항에서,In claim 5,
    상기 모듈화 단계에서, 상기 후면 전극의 하부에 후면 기판을 설치하고, 상기 전면 기판과 후면 기판 사이에 밀봉재를 배치하되, 상기 밀봉재를 상기 접착 물질과 서로 다른 물질로 형성하는 화합물 반도체 태양전지의 제조 방법.In the modularization step, a rear substrate is installed below the rear electrode, and a sealing material is disposed between the front substrate and the rear substrate, wherein the sealing material is formed of a material different from the adhesive material. .
  8. 화합물 반도체층; 및Compound semiconductor layers; And
    상기 화합물 반도체층의 전면(front surface) 위에 위치하는 그리드 형상의 전면 전극Grid-shaped front electrode positioned on the front surface of the compound semiconductor layer
    을 포함하며,Including;
    상기 전면 전극의 접촉 저항은 1mΩ/㎝ 2 이하인 화합물 반도체 태양전지.The contact resistance of the front electrode is 1 mPa / cm 2 or less compound semiconductor solar cell.
  9. 제8항에서,In claim 8,
    상기 전면 전극은 팔라듐(Pd)/게르마늄(Ge)/금(Au)으로 형성되는 화합물 반도체 태양전지.The front electrode is a compound semiconductor solar cell formed of palladium (Pd) / germanium (Ge) / gold (Au).
  10. 제9항에서,In claim 9,
    상기 팔라듐은 5nm의 두께로 형성되고, 상기 게르마늄은 20nm의 두께로 형성되며, 상기 금은 250nm의 두께로 형성되는 화합물 반도체 태양전지.The palladium is formed to a thickness of 5nm, the germanium is formed to a thickness of 20nm, the gold compound semiconductor solar cell is formed to a thickness of 250nm.
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