WO2020023907A1 - Alternative integration for redistribution layer process - Google Patents

Alternative integration for redistribution layer process Download PDF

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Publication number
WO2020023907A1
WO2020023907A1 PCT/US2019/043729 US2019043729W WO2020023907A1 WO 2020023907 A1 WO2020023907 A1 WO 2020023907A1 US 2019043729 W US2019043729 W US 2019043729W WO 2020023907 A1 WO2020023907 A1 WO 2020023907A1
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Prior art keywords
layer
dielectric layer
patterned
substrate
copper
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PCT/US2019/043729
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French (fr)
Inventor
Justin Oberst
Bryan L. Buckalew
Stephen J. Banik
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Lam Research Corp
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Lam Research Corp
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Priority to CN201980049818.3A priority Critical patent/CN112514050B/en
Priority to CN202510296192.3A priority patent/CN120413522A/en
Priority to US17/263,503 priority patent/US11450631B2/en
Priority to KR1020217005955A priority patent/KR102920130B1/en
Publication of WO2020023907A1 publication Critical patent/WO2020023907A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01904—Manufacture or treatment of bond pads using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01953—Changing the shapes of bond pads by etching

Definitions

  • the present disclosure relates generally to a redistribution layer (RDL) process, and in particular to systems and methods for alternative integration for RDL.
  • RDL redistribution layer
  • both a thin barrier and copper seed layer are deposited onto an incoming substrate (most often silicon).
  • a photoresist layer is applied, via spin coating or lamination.
  • the photoresist is exposed, developed, and descummed to expose the copper seed in an RDL pattern.
  • This patterned area is then filled with copper via an electroplating process.
  • the photoresist is then removed.
  • the copper seed and barrier layer are removed last.
  • the etchant attacks the copper seed at the pattern/seed interface producing undercut beneath the RDL pattern. Undercut can reduce the mechanical integrity of the RDL pattern and produce poor signal integrity.
  • undercut There are two types of undercut that can occur: (1) seed underneath the RDL pattern is etched and (2) both seed and base of electroplated RDL are etched. As RDL dimensions continue to shrink, this issue is becoming more prominent as the undercut occurs under a larger area of the RDL.
  • FIG. 1A is a picture of a cross section of a substrate before a conventional redistribution layer (RDL) process.
  • RDL redistribution layer
  • FIG. IB is a picture of a cross section of a substrate after a conventional RDL process.
  • FIG. 2 is a block diagram of a cross section of a substrate after a conventional RDL process.
  • FIGS. 3A-33 are block diagrams illustrating a partially embedded alternative integration RDL process, according to a first example embodiment.
  • FIGS. 4A-4J are block diagrams illustrating a partially embedded alternative integration RDL process, according to a second example embodiment.
  • FIGS. 5A-5G are block diagrams illustrating a fully embedded alternative integration RDL process, according to an example embodiment.
  • FIG. 6A is cross-sectional depiction of a substrate illustrating an example of engineered copper RDL post-seed etch.
  • FIG. 6B is cross-sectional depiction of a substrate illustrating a conventional copper RDL post-seed etch.
  • FIG. 7 is flow diagram illustrating a method for a partially embedded RDL process, according to an example embodiment.
  • FIG. 8 is flow diagram illustrating a method for a fully embedded RDL process, according to an example embodiment. DESCRIPTION
  • RDL redistribution layer
  • FIG. 1 A is a picture of a cross section of a substrate before a convention RDL process.
  • FIG. IB is a picture of a cross section of a substrate after a convention RDL process. The after picture illustrates the undercut problem.
  • FIG. 2 is a block diagram of a cross section of a substrate after an RDL process.
  • the substrate 202 is deposited with a barrier 204, a copper seed 206, and BCD copper 208.
  • the copper seed 206 underneath the ECD copper 208 is etched resulting in an undercut.
  • both the copper seed 206 and the base of electroplated RDL are etched.
  • FIGS. 3A-3J are block diagrams illustrating a partially embedded alternative integration RDL process, according to a first example embodiment.
  • a substrate 322 is provided at operation 302 in FIG. 3A.
  • a dielectric (polyimide, nitride, etc.) layer 324 is applied to the incoming substrate 322.
  • the dielectric layer 324 is patterned. For photosensitive polymeric material (polyimide), this would require exposure, develop, and descum steps.
  • a barrier layer 326 and a copper seed layer 328 are applied on top of this layer dielectric layer 324.
  • a photoresist layer 330 may be applied to the substrate 322 at operation 310 in FIG, 3E. Depending on the photoresist material (spin on vs.
  • the photoresist layer 330 could fill the underlying features or just lay atop.
  • the photoresist layer 330 is then exposed, developed, and descummed at operation 312 in FIG. 3E.
  • the patterned feature size matches that in the underlying dielectric as illustrated in operation 312 in FIG. 3F.
  • a copper layer 322 is electroplated in the patterned regions.
  • the photoresist layer 330 is removed.
  • the copper seed layer 328 and the barrier layer 326 is etched and removed.
  • the dielectric layer 324 can be removed as well.
  • the seed etch does not create an undercut.
  • a seed etch may only remove a small amount of material m the electroplated RDL side. It may remove the seed between the RDL structure and the barrier.
  • Electroplated RDL thickness can range from 2pm to IOmih.
  • the dielectric layer has at least about 0.5mih minimum thickness.
  • the thickness range may be between 5-50% depending on the RDL final thickness.
  • FIGS. 4A-4J are block diagrams illustrating a partially embedded alternative integration RDL process, according to a second example
  • FIGS. 4A-4J differs from the flow of FIGS. 3A-3J for RDL dimensions in the photoresist layer.
  • a substrate 422 is provided.
  • a dielectric layer 424 is deposited onto the substrate 422.
  • the dielectric layer 424 is patterned (for polymers: expose, develop, descum).
  • both a barrier layer 426 and a seed layer 428 are deposited on the dielectric layer 424 and the substrate 422.
  • a photoresist layer 430 is applied to the substrate 422.
  • the photoresist layer 430 is patterned similarly to the dielectric layer 424.
  • the features in the photoresist layer 430 have larger critical dimensions (CDs) or widths than the corresponding ones in the dielectric layer 424.
  • copper 432 is electrodeposited.
  • the photoresist 430 is removed.
  • the copper seed 426 and the barrier layer 424 are etched.
  • the dielectric layer 424 is optionally removed.
  • This flow process results in RDL patterns with thicker dimensions near the top. This can be beneficial to maintain RDL dimensions post-copper seed etch. This flow may also minimize side-wall cut in after seed etch resulting in RDL structures of excellent mechanical integrity.
  • FIGS. 5A-5G are block diagrams illustrating a fully embedded alternative integration RDL process, according to an example embodiment.
  • a substrate 516 is provided at operation 502 of FIG. 5A.
  • a dielectric (polyimide, nitride, etc.) layer 518 is applied to the incoming substrate 516.
  • the dielectric layer 518 is patterned.
  • this process includes exposure, develop, and descum steps.
  • a barrier layer 520 and a copper seed layer 522 are applied on top of the patterned dielectric layer 518 and exposed surface of the substrate 516.
  • copper 524 is electroplated in the patterned regions.
  • the copper 524 is planarized. The plating evolution is illustrated by operation 514 in FIG. 5G.
  • FIG. 6A is a cross-sectional depiction of a substrate illustrating an example of grain engineering.
  • Cross-section 604 illustrates a substrate 610, a hairier 608, and a copper layer 606.
  • a stronger, more robust electroplated copper may be required. Tills can be engineered using various process parameters including waveform, convection, and chemistry.
  • Some copper grain structures that can be engineered to exhibit etch resistance include large grains, columnar grains, and nanotwinned grains.
  • nanotwinned copper has pre viously been shown to have high tensile strength, excellent electrical conductivity, and high electromigration resistance. If formed early in the electroplating process, the engineered grain structure (including nanotwins) could reduce the attack on the electroplated copper although not reducing the undercut to the copper seed layer beneath the RDL structure. In the above alternative process schemes detailed above, grain engineered copper could minimize etch into the side of the electroplated RDL structure. This would maintain the pattern dimensions and mechanical integrity of the RDL
  • FIG. 6B is a cross-sectional depiction of a substrate illustrating an example of a conventional copper RDL post-seed etch.
  • Cross-section 604 illustrates an undercut 612 in the copper 606 in a conventional copper RDL post seed etch.
  • FIG. 7 is flow diagram illustrating a method for a partially embedded RDL process, according to an example embodiment.
  • a substrate is provided.
  • a dielectric polyimide, nitride, etc.
  • the dielectric layer is patterned. For photosensitive polymeric material (polyimide), this would require exposure, develop, and descum steps.
  • a barrier and copper seed layer is applied on top of the layer dielectric layer.
  • a photoresist process is applied to the substrate. The photoresist is exposed, developed, and descummed at operation 710. In this process flow, the patterned feature size would match that in the underlying dielectric.
  • the photoresist is removed.
  • the copper seed and barrier etch is removed.
  • the dielectric layer can be removed as well. In this integration scheme, the seed etch does not create an undercut.
  • FIG. 8 is flow' diagram illustrating a method for a fully embedded RDL process, according to an example embodiment.
  • a substrate is provided.
  • a dielectric polyimide, nitride, etc.
  • the dielectric layer is patterned. For photosensitive polymeric material (po!yimide), this would require exposure, develop, and descum steps.
  • a harrier and copper seed layer is deposited on top of this layer dielectric layer.
  • copper is electroplated in the patterned regions.
  • the copper (or copper/dielectric layer) is planarized.
  • Example 1 is a method for redistribution layer (RDL) process, the method comprising: depositing a dielectric layer on a surface of a substrate; patterning the dielectric layer, the patterned dielectric layer exposing a region of the surface of the substrate; depositing a protective layer on the patterned dielectric layer and the exposed region of the surface of the substrate; depositing a photoresist layer on the protective layer; paterning the photoresist layer, the patterned photoresist layer exposing a first region of the protective layer;
  • RDL redistribution layer
  • Example 2 includes the method of example 1, further comprising:
  • Example 3 includes the method of example 2, wherein a size of a feature in the patterned photoresist layer is larger than a size of a feature in the patterned dielectric layer.
  • Example 4 includes the method of example 1, wherein a size of a feature in the patterned photoresist layer is smaller than a size of a feature in the paterned dielectric layer.
  • Example 5 includes the method of example 1, wherein the protective layer comprises a barrier layer and a copper seed layer, the copper seed layer being on top of the barrier layer.
  • Example 6 includes the method of example 1, wherein the dielectric layer comprises a photosensitive polymide layer or a nitride layer.
  • Example 7 includes the method of example 6, wherein patterning the dielectric layer further comprises: forming the patterned dielectric layer using expose, develop, and descum processes.
  • Example 8 includes the method of example 1, wherein a feature size of the patterned photoresist layer matches a feature size of the underlying paterned dielectric layer.
  • Example 9 includes the method of example 1, wherein depositing the photoresist layer on top of the protective layer further comprises: filling features of the patterned dielectric layer with the photoresist layer.
  • Example 10 includes the method of example 1 , wherein the photoresist layer lays on top of the features of the patterned dielectric layer and does not fill the features of the paterned dielectric layer.

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Abstract

In one example, a method for redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier and copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier and copper seed layer. The photoresist layer is patterned to correspond with the dielectric layer pattern. Copper is electrodepositing in the patterned regions exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier are etched.

Description

Figure imgf000002_0001
RELATED APPLICATION
[0001] The present application claims priority from United States Provisional Patent Application No. 62/703,762, filed July 26, 2018, which is herein incorporated by reference in its entirety.
FIELD
[0002] The present disclosure relates generally to a redistribution layer (RDL) process, and in particular to systems and methods for alternative integration for RDL.
BACKGROUND
[0003] In a conventional RDL process flow, both a thin barrier and copper seed layer are deposited onto an incoming substrate (most often silicon). A photoresist layer is applied, via spin coating or lamination. The photoresist is exposed, developed, and descummed to expose the copper seed in an RDL pattern. This patterned area is then filled with copper via an electroplating process. After electroplating, the photoresist is then removed. To electrically isolate the electroplated RDL patterns, the copper seed and barrier layer are removed last. During the seed removal step (via wet chemical etch), the etchant attacks the copper seed at the pattern/seed interface producing undercut beneath the RDL pattern. Undercut can reduce the mechanical integrity of the RDL pattern and produce poor signal integrity. There are two types of undercut that can occur: (1) seed underneath the RDL pattern is etched and (2) both seed and base of electroplated RDL are etched. As RDL dimensions continue to shrink, this issue is becoming more prominent as the undercut occurs under a larger area of the RDL.
[0004J The present disclosure seeks to address these drawbacks. It should be noted that the information described in this section is provided to provide the skilled artisan some context for the following disclosed subject matter and should not be considered as admitted prior art.
DESCRIPTION OF THE DRAWINGS
[0005] Some embodiments are illustrated by way of example and not limitation in the view's of the accompanying drawings.
[0006] FIG. 1A is a picture of a cross section of a substrate before a conventional redistribution layer (RDL) process.
[0007] FIG. IB is a picture of a cross section of a substrate after a conventional RDL process.
[0008] FIG. 2 is a block diagram of a cross section of a substrate after a conventional RDL process.
[0009] FIGS. 3A-33 are block diagrams illustrating a partially embedded alternative integration RDL process, according to a first example embodiment.
[0010] FIGS. 4A-4J are block diagrams illustrating a partially embedded alternative integration RDL process, according to a second example embodiment.
[0011] FIGS. 5A-5G are block diagrams illustrating a fully embedded alternative integration RDL process, according to an example embodiment.
[0012] FIG. 6A is cross-sectional depiction of a substrate illustrating an example of engineered copper RDL post-seed etch.
[0013] FIG. 6B is cross-sectional depiction of a substrate illustrating a conventional copper RDL post-seed etch.
[0014] FIG. 7 is flow diagram illustrating a method for a partially embedded RDL process, according to an example embodiment.
[0015] FIG. 8 is flow diagram illustrating a method for a fully embedded RDL process, according to an example embodiment. DESCRIPTION
[0016] The description that follows includes systems, methods, techniques, instruction sequences, and computing machine program products that embody illustrative embodiments of the present inventive subject matter. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of example embodiments. It will be evident, however, to one skilled in the art, that the present embodiments may be practiced without these specific details.
[0017] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Tire following notice applies to any data as described below and in the drawings that form a part of this document: Copyright LAM Research Corporation, 2018, All Rights Reserved.
[0018J In the present disclosure, various terms are used to describe a semiconductor processing surface:“wafer” and“substrate” may be used interchangeably. The process of depositing, or plating, metal onto a conductive surface of the w'afer via an electrochemical reaction may be referred to generally as“electrodeposition” or“electroplating.”
[0019] The present document describes several alternatives to the conventional redistribution layer (RDL) process: three integration schemes and one electroplating process that result in minimized undercut during seed etch. FIG.
1 A is a picture of a cross section of a substrate before a convention RDL process. FIG. IB is a picture of a cross section of a substrate after a convention RDL process. The after picture illustrates the undercut problem.
[0020] FIG. 2 is a block diagram of a cross section of a substrate after an RDL process. The substrate 202 is deposited with a barrier 204, a copper seed 206, and BCD copper 208. In the first issue type, the copper seed 206 underneath the ECD copper 208 is etched resulting in an undercut. In the second issue type, both the copper seed 206 and the base of electroplated RDL (BCD copper 208) are etched.
[0021] FIGS. 3A-3J are block diagrams illustrating a partially embedded alternative integration RDL process, according to a first example embodiment.
In this process flow, a substrate 322 is provided at operation 302 in FIG. 3A. At operation 304 in FIG. 3B, a dielectric (polyimide, nitride, etc.) layer 324 is applied to the incoming substrate 322. At operation 306 in FIG. 3C, the dielectric layer 324 is patterned. For photosensitive polymeric material (polyimide), this would require exposure, develop, and descum steps. At operation 308 in FIG. 3D, a barrier layer 326 and a copper seed layer 328 are applied on top of this layer dielectric layer 324. A photoresist layer 330 may be applied to the substrate 322 at operation 310 in FIG, 3E. Depending on the photoresist material (spin on vs. laminate), the photoresist layer 330 could fill the underlying features or just lay atop. The photoresist layer 330 is then exposed, developed, and descummed at operation 312 in FIG. 3E. In this process flow, the patterned feature size matches that in the underlying dielectric as illustrated in operation 312 in FIG. 3F. At operation 314 in FIG. 3G, a copper layer 322 is electroplated in the patterned regions. At operation 316 in FIG. 3H, the photoresist layer 330 is removed. At operation 318 in FIG. 31, the copper seed layer 328 and the barrier layer 326 is etched and removed. At operation 320 in FIG. 3J, optionally, the dielectric layer 324 can be removed as well. In this integration scheme, the seed etch does not create an undercut. A seed etch may only remove a small amount of material m the electroplated RDL side. It may remove the seed between the RDL structure and the barrier.
[0022] Electroplated RDL thickness can range from 2pm to IOmih. For partially embedded, the dielectric layer has at least about 0.5mih minimum thickness. The thickness range may be between 5-50% depending on the RDL final thickness.
[0023] FIGS. 4A-4J are block diagrams illustrating a partially embedded alternative integration RDL process, according to a second example
embodiment. The flow of FIGS. 4A-4J differs from the flow of FIGS. 3A-3J for RDL dimensions in the photoresist layer. At operation 402 of FIG. 4A, a substrate 422 is provided. At operation 404 of FIG. 4B, a dielectric layer 424 is deposited onto the substrate 422. At operation 406 of FIG. 4C, the dielectric layer 424 is patterned (for polymers: expose, develop, descum). At operation 408 of FIG, 4D, both a barrier layer 426 and a seed layer 428 are deposited on the dielectric layer 424 and the substrate 422.
[QQ24] At operation 410 of FIG. 4E, a photoresist layer 430 is applied to the substrate 422. At operation 412 of FIG. 4F, the photoresist layer 430 is patterned similarly to the dielectric layer 424. However, the features in the photoresist layer 430 have larger critical dimensions (CDs) or widths than the corresponding ones in the dielectric layer 424. At operation 414 of FIG. 4G, copper 432 is electrodeposited. At operation 416 of FIG. 4H, the photoresist 430 is removed. At operation 418 of FIG. 41, the copper seed 426 and the barrier layer 424 are etched. At operation 420 of FIG. 4J, the dielectric layer 424 is optionally removed.
[0025] This flow process results in RDL patterns with thicker dimensions near the top. This can be beneficial to maintain RDL dimensions post-copper seed etch. This flow may also minimize side-wall cut in after seed etch resulting in RDL structures of excellent mechanical integrity.
[0026] FIGS. 5A-5G are block diagrams illustrating a fully embedded alternative integration RDL process, according to an example embodiment. In this process flow, a substrate 516 is provided at operation 502 of FIG. 5A. At operation 504 of FIG, SB, a dielectric (polyimide, nitride, etc.) layer 518 is applied to the incoming substrate 516. At operation 506 of FIG. 5C, the dielectric layer 518 is patterned. For photosensitive polymeric material (polyimide), this process includes exposure, develop, and descum steps. At operation 508 of FIG. 5D, a barrier layer 520 and a copper seed layer 522 are applied on top of the patterned dielectric layer 518 and exposed surface of the substrate 516. At operation 510 of FIG. 5E, copper 524 is electroplated in the patterned regions. At operation 512 of FIG. 5F, the copper 524 is planarized. The plating evolution is illustrated by operation 514 in FIG. 5G.
[0027] FIG. 6A is a cross-sectional depiction of a substrate illustrating an example of grain engineering. Cross-section 604 illustrates a substrate 610, a hairier 608, and a copper layer 606. To minimize seed etch effect, a stronger, more robust electroplated copper may be required. Tills can be engineered using various process parameters including waveform, convection, and chemistry.
.7 [0028] Some copper grain structures that can be engineered to exhibit etch resistance include large grains, columnar grains, and nanotwinned grains. As an example, nanotwinned copper has pre viously been shown to have high tensile strength, excellent electrical conductivity, and high electromigration resistance. If formed early in the electroplating process, the engineered grain structure (including nanotwins) could reduce the attack on the electroplated copper although not reducing the undercut to the copper seed layer beneath the RDL structure. In the above alternative process schemes detailed above, grain engineered copper could minimize etch into the side of the electroplated RDL structure. This would maintain the pattern dimensions and mechanical integrity of the RDL
[0029] FIG. 6B is a cross-sectional depiction of a substrate illustrating an example of a conventional copper RDL post-seed etch. Cross-section 604 illustrates an undercut 612 in the copper 606 in a conventional copper RDL post seed etch.
[0030] FIG. 7 is flow diagram illustrating a method for a partially embedded RDL process, according to an example embodiment. At operation 702, a substrate is provided. At operation 704, a dielectric (polyimide, nitride, etc.) is applied to the substrate. At operation 706, the dielectric layer is patterned. For photosensitive polymeric material (polyimide), this would require exposure, develop, and descum steps. At operation 708, a barrier and copper seed layer is applied on top of the layer dielectric layer. At operation 710, a photoresist process is applied to the substrate. The photoresist is exposed, developed, and descummed at operation 710. In this process flow, the patterned feature size would match that in the underlying dielectric. At operation 712, copper is electroplated in the patterned regions. At operation 714, the photoresist is removed. At operation 716, the copper seed and barrier etch is removed. At operation 718, optionally, the dielectric layer can be removed as well. In this integration scheme, the seed etch does not create an undercut.
[0031] FIG. 8 is flow' diagram illustrating a method for a fully embedded RDL process, according to an example embodiment. At operation 802, a substrate is provided. At operation 804, a dielectric (polyimide, nitride, etc.) is applied to the substrate. At operation 806, the dielectric layer is patterned. For photosensitive polymeric material (po!yimide), this would require exposure, develop, and descum steps. At operation 808, a harrier and copper seed layer is deposited on top of this layer dielectric layer. At operation 810, copper is electroplated in the patterned regions. At operation 812, the copper (or copper/dielectric layer) is planarized.
[0032] Although an embodiment has been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the scope of the disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of tins disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term“invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover all adaptations or variations of various embodim nts. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.
[QQ33] Examples:
[QQ34] Example 1 is a method for redistribution layer (RDL) process, the method comprising: depositing a dielectric layer on a surface of a substrate; patterning the dielectric layer, the patterned dielectric layer exposing a region of the surface of the substrate; depositing a protective layer on the patterned dielectric layer and the exposed region of the surface of the substrate; depositing a photoresist layer on the protective layer; paterning the photoresist layer, the patterned photoresist layer exposing a first region of the protective layer;
electrodepositing a copper layer on top of the exposed first region of the protective layer; removing the patterned photoresist layer to expose a second region of the protective layer; and rem oving the exposed second region of the protective layer to expose the patterned dielectric layer.
[0035] Example 2 includes the method of example 1, further comprising:
removing the exposed patterned dielectric layer to expose a region of the surface of the substrate.
[0036] Example 3 includes the method of example 2, wherein a size of a feature in the patterned photoresist layer is larger than a size of a feature in the patterned dielectric layer.
[0037] Example 4 includes the method of example 1, wherein a size of a feature in the patterned photoresist layer is smaller than a size of a feature in the paterned dielectric layer.
[0038] Example 5 includes the method of example 1, wherein the protective layer comprises a barrier layer and a copper seed layer, the copper seed layer being on top of the barrier layer.
[0039] Example 6 includes the method of example 1, wherein the dielectric layer comprises a photosensitive polymide layer or a nitride layer.
[0040] Example 7 includes the method of example 6, wherein patterning the dielectric layer further comprises: forming the patterned dielectric layer using expose, develop, and descum processes.
[0041] Example 8 includes the method of example 1, wherein a feature size of the patterned photoresist layer matches a feature size of the underlying paterned dielectric layer.
[0042] Example 9 includes the method of example 1, wherein depositing the photoresist layer on top of the protective layer further comprises: filling features of the patterned dielectric layer with the photoresist layer. [0043] Example 10 includes the method of example 1 , wherein the photoresist layer lays on top of the features of the patterned dielectric layer and does not fill the features of the paterned dielectric layer.

Claims

CLAIMS What is claimed is:
1. A method for redistribution layer (RDL) process, the method comprising: depositing a dielectric layer on a surface of a substrate;
patterning the dielectric layer, the patterned dielectric layer exposing a regi on of the surface of the substrate;
depositing a protective layer on the patterned dielectric layer and the exposed region of the surface of the substrate;
depositing a photoresist layer on the protective layer;
patterning the photoresist layer, the patterned photoresist layer exposing a first region of the protective layer;
electrodepositing a copper layer on top of the exposed first region of the protective layer;
remo v ing the patterned photoresist layer to expose a second region of the protective layer; and
removing the exposed second region of the protective layer to expose the patterned dielectric layer.
2. The method of claim 1 , further comprising:
removing the exposed patterned dielectric layer to expose a region of the surface of the substrate.
3. The method of claim 1 , wherein a size of a feature in the patterned photoresist layer is larger than a size of a feature in the patterned dielectric layer.
4. The method of claim l, wherein a size of a feature in the patterned photoresist layer is smaller than a size of a feature in the paterned dielectric layer.
5. The method of claim 1, wherein the protective layer comprises a barrier layer and a copper seed layer, the copper seed layer being on top of the barrier layer.
6. The method of claim 1, wherein the dielectric layer comprises a photosensitive polyimide layer or a nitride layer.
7. The method of claim 6, wherein patterning the dielectric layer further comprises:
forming the patterned dielectric layer using expose, develop, and descum processes.
8. The method of claim 1 , wherein a feature size of the patterned photoresist layer matches a feature size of the underlying patterned dielectric layer.
9. The method of claim 1 , wherein depositing the photoresist layer on top of the protective layer further comprises: filling features of the patterned dielectric layer with the photoresist layer.
10. The method of claim 1 , wherein the photoresist layer lays on top of the features of the patterned dielectric layer and does not fill the features of the patterned dielectric layer.
PCT/US2019/043729 2018-07-26 2019-07-26 Alternative integration for redistribution layer process Ceased WO2020023907A1 (en)

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