WO2019223233A1

WO2019223233A1 - Blade server architecture based on redundant and extended configuration

Info

Publication number: WO2019223233A1
Application number: PCT/CN2018/112049
Authority: WO
Inventors: 张斌
Original assignee: 郑州云海信息技术有限公司
Priority date: 2018-05-24
Filing date: 2018-10-26
Publication date: 2019-11-28
Also published as: CN108733613A

Abstract

Provided in the present application is a blade server architecture based on redundant and extended configuration, comprising: at least two PCIe switch board components, at least one configuration management board, and a backplane. The PCIe switch board components comprise: a switch board, a PCIe switch chipset being provided on the switch board. The PCIe switch chipset is connected to the PCIe switch chipset on a neighboring PCIe switch board component by means of the configuration management board, the configuration management board configures the connection and disconnection of data communication between the PCIe switch chipsets. Two extensible PCIe switches are arranged in a unit height space. Data switching is performed directly, without the need for bus conversion, improving data transmission efficiency. Two switches are connected to each other by means of a configuration management board, which configures and manages PCIe switch chips, allowing the two extensible PCIe switches to change between redundant and extension modes, satisfying the requirements for varying emphases on high reliability or high performance in different application scenarios.

Description

Blade server architecture based on redundant expansion configuration

This application claims priority from a Chinese patent application filed with the Chinese Patent Office on May 24, 2018, with application number 201810507642.9, and with the application name "A Blade Server Architecture Based on Redundant Extended Configuration", the entire contents of which are incorporated by reference In this application.

Technical field

The present application relates to the field of server technology, and in particular, to a blade server architecture based on a redundant expansion configuration.

Background technique

In recent years, as the construction of high-power, high-density computer rooms continues to climb, the demand for high-density servers continues to rise. As a typical representative of high-density servers, blade servers continue to be a hot market. Traditional blade servers mostly use 10 Gigabit, Fibre Channel (English: Fibre Channel, FC), wireless bandwidth (English: InfiniBand, IB) switches to implement data exchange. The processor's PCIE bus must be converted first. After converting to 10 Gigabit, FC, and IB buses, data is transmitted through the switch. This has a certain degree of overhead in the bus conversion and affects the data transmission efficiency. At the same time, the multi-switch configuration of the blade cannot achieve the multi-switch redundant configuration and Flexible configuration switching on performance extension configuration.

Summary of the Invention

In order to overcome the deficiencies in the prior art mentioned above, this application provides a blade server architecture based on a redundant expansion configuration, including: at least two PCIE switch board components, at least one configuration management board, and a backplane;

Each PCIE switch board component is connected to the backplane separately;

The PCIE switch board components include: a switch board, which is provided with a PCIE switch chipset;

The PCIE switch chipset is connected to the PCIE switch chipset on an adjacent PCIE switchboard component through a configuration management board. The configuration management board is used to configure the on-off of data communication between the PCIE switch chipset.

Preferably, the PCIE switch chipset includes: at least one PCIE switch chip;

When at least two PCIE switching chips are used, the PCIE switching chip and the PCIE switching chip are interconnected with each other through a PCIE data bus to form a PCIE switching chipset;

The configuration interface of each PCIE switch chip is connected to the configuration management board.

Preferably, the switch board is further provided with a plurality of externally connected PCIE interfaces.

Preferably, the switch board is further provided with a backplane connector, a first PCIE data harness, and a second PCIE

Data wiring harness and third PCIE data wiring harness;

The PCIE switching chipset is connected to the backplane through the first PCIE data harness and the backplane connector in order;

The PCIE switching chipset is connected to the configuration management board through a second PCIE data harness;

The PCIE switching chipset is connected to an external PCIE interface through a third PCIE data harness.

Preferably, the switching board is further provided with a power connector;

The switch board is connected to the backplane through a power connector to provide power to the switch board.

Preferably, the configuration management board includes: an Intel Avoton processor chip and a Flash chip;

The Intel Avoton processor chip is used to configure the PCIE switch chipset for redundancy and extended configuration switching; the Flash chipset is used to store the configuration file configured for the PCIE switch chipset, and supports different topological configurations between the chips in the PCIE switch chipset.

Preferably, the PCIE switch chip is a PLX9797PCIE switch chip;

The PLX9797PCIE switch chip and the PLX9797PCIE switch chip are interconnected with each other through the PCIEx16 data bus to form a PCIE switch chipset;

Each PLX9797PCIE switch chip is connected to the configuration management board through the PCIEx1 configuration interface.

Preferably, the first PCIE data harness uses a 16 * PCIEx8PCIE data line;

The PCIE switch chipset is connected to the backplane through the 16 * PCIEx8PCIE data cable and the backplane connector in turn;

The second PCIE data harness uses 3 * PCIEx16PCIE data lines;

The PCIE switch chipset is connected to the configuration management board through a 3 * PCIEx16PCIE data cable;

The third PCIE data harness uses 16 * PCIEx4PCIE data lines;

The PCIE switch chipset is connected to an external PCIE interface through a 16 * PCIEx4PCIE data cable.

Preferably, the externally connected PCIE interface uses an SFP interface for external interconnection of the PCIE signal line and the sideband signal line.

As can be seen from the above technical solutions, this application has the following advantages:

In the blade server architecture based on the redundant expansion configuration, the PCIE switch chipset is connected to the PCIE switch chipset on the adjacent PCIE switch board component through the configuration management board, and the configuration management board configures the on-off of the data communication between the PCIE switch chipset. Configure two expandable PCIE switches in a unit height space. Data is exchanged directly without bus conversion, which reduces overhead and improves data transmission efficiency. The two switches are interconnected through the configuration management board to configure and manage the PCIE switch chip, so that the two expandable PCIE switches can switch between redundant and extended modes to meet the requirements of high reliability and high performance in different application scenarios. Different focus needs.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solution of the present application more clearly, the drawings used in the description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. In terms of personnel, other drawings can be obtained based on these drawings without paying creative labor.

FIG. 1 is a schematic diagram of an embodiment of a blade server architecture based on a redundant expansion configuration according to an embodiment of the present application; FIG.

2 is a schematic diagram of a redundant configuration mode of an embodiment of a blade server architecture according to an embodiment of the present application;

3 is a schematic diagram of an extended configuration mode of an embodiment of a blade server architecture according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a fifth embodiment of a blade server architecture according to an embodiment of the present application.

Detailed ways

In order to make the object, features, and advantages of the present application more obvious and easier to understand, specific embodiments and drawings will be used below to clearly and completely describe the technical solution protected by the present application. Obviously, the implementation described below The examples are only some of the embodiments of this application, but not all of them. Based on the embodiments in this patent, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of this patent.

Embodiment 1 provides a blade server architecture based on a redundant expansion configuration, including: at least two PCIE switch board components, at least one configuration management board, and a backplane; each PCIE switch board component is respectively connected to the backplane; and a PCIE switch The board components include: a switch board, which is provided with a PCIE switch chipset; the PCIE switch chipset is connected to a PCIE switch chipset on an adjacent PCIE switch board component through a configuration management board, and the configuration management board is used to configure the PCIE switch chipset On and off of data communication.

The PCIE switch chipset includes: at least one PCIE switch chip; when at least two PCIE switch chips are used, the PCIE switch chip and the PCIE switch chip are interconnected with each other through the PCIE data bus to form a PCIE switch chipset; each PCIE switch The configuration interface of the chip is connected to the configuration management board.

The switch board is also provided with a backplane connector, a first PCIE data harness, a second PCIE data harness, and a third PCIE data harness; the PCIE switch chipset connects the backplane through the first PCIE data harness and the backplane connector in sequence; PCIE The switching chipset is connected to the configuration management board through a second PCIE data harness; the PCIE switching chipset is connected to an external PCIE interface through a third PCIE data harness.

The switch board is also provided with a power connector; the switch board is connected to the backplane through the power connector to realize the power supply to the switch board. The switch board is also provided with several external PCIE interfaces.

The second embodiment, as shown in FIGS. 1 to 3, includes: a first PCIE switch board assembly, a second PCIE switch board assembly, a configuration management board 4, and a backplane 2.

The first PCIE switch board component and the second PCIE switch board component are connected to the backplane 2 respectively; the first PCIE switch board component includes: a first switch board 1, and a first PCIE switch chipset 16 is provided on the first switch board 1.

The second PCIE switch board assembly includes: a second switch board 3, and a second PCIE switch chipset 36 is provided on the second switch board 3; the first PCIE switch chipset 16 and the second PCIE switch chipset 36 are configured through the configuration management board 4 The connection and configuration management board 4 is configured to configure on-off of data communication between the first PCIE switch chipset 16 and the second PCIE switch chipset 36.

The first switch board is further provided with a backplane connector 14, a first PCIE data harness 11, a second PCIE data harness 12, and a third PCIE data harness 13.

The first PCIE switch chipset 16 is connected to the backplane 2 through the first PCIE data harness 11 and the backplane connector 14 in order; the first PCIE switch chipset 16 is connected to the configuration management board 4 through the second PCIE data harness 12; the first PCIE switch The chipset 16 is connected to the external PCIE interface 17 through a third PCIE data harness 13.

The second switch board 3 is also provided with a second backplane connector 34, a first PCIE data harness 31, a second PCIE data harness 32, and a third PCIE data harness 33; the second PCIE switch chipset 36 passes the first PCIE in sequence The data harness 31 and the backplane connector 34 are connected to the backplane 2; the second PCIE exchange chipset 36 is connected to the configuration management board 4 through the second PCIE data harness 32; the second PCIE exchange chipset 36 is connected to the outside through the third PCIE data harness 33 Connected to PCIE interface 37.

The first switching board 1 is connected to the backplane 2 through a power connector 15 to implement power supply to the first switching board 1.

The second switching board 3 is connected to the backplane 2 through a power connector 35 to implement power supply to the second switching board 3.

The third embodiment is different from the first and second embodiments in that the PCIE switch chipset includes: at least one PCIE switch chip; when at least two PCIE switch chips are used, the PCIE switch chip and the PCIE switch chip are mutually The PCIE data bus interconnects to form a PCIE switch chipset; the configuration interface of each PCIE switch chip is connected to the configuration management board.

Wherein, as in the second embodiment, the first PCIE switch chipset 16 may use at least one PCIE switch chip. The second PCIE switch chipset 36 may use at least one PCIE switch chip.

Specifically, the PCIE switch chip uses a PLX9797PCIE switch chip; the PLX9797PCIE switch chip and the PLX9797PCIE switch chip are interconnected with each other through a PCIEx16 data bus to form a PCIE switch chipset; each PLX9797PCIE switch chip is connected to the configuration management board through a PCIEx1 configuration interface.

In this embodiment, the first PCIE data harness uses 16 * PCIEx8PCIE data lines; the PCIE switch chipset connects to the backplane through the 16 * PCIEx8PCIE data line and the backplane connector in turn; the second PCIE data harness uses 3 * PCIEx16PCIE data lines; The PCIE switch chipset is connected to the configuration management board through a 3 * PCIEx16PCIE data line; the third PCIE data harness uses a 16 * PCIEx4PCIE data line; the PCIE switch chipset is connected to an external PCIE interface through a 16 * PCIEx4PCIE data line. The external PCIE interface uses SFP interface for external interconnection of PCIE signal lines and sideband signal lines.

In this embodiment, the configuration management board includes: an Intel Avoton processor chip and a Flash chip; the Intel Avoton processor chip is used to configure the PCIE switch chipset to implement redundancy and extended configuration switching; the Flash chipset is used to store and configure the PCIE switch chipset Configuration file, and supports different topology configurations between chips in the PCIE switch chipset.

The integrated management chip is used to configure the PCIE switch chipset to achieve redundancy and extended configuration switching; the integrated flash chip is used to store the configuration file of the PCIE switch chip, and supports different topological configurations between the chips in the chipset. When configured in redundant mode, the PCIE signal between the two expandable PCIE switch boards is disconnected, and the two switch boards are separated to work independently as two switches to achieve redundant configuration.

Embodiment 4

The PCIE switch chipset includes: three PLX9797 PCIE switch chips, which are interconnected through a set of PCIEx16 data buses to form a PCIE switch chipset. The chipset as a whole provides the PCIE bus switching function. The PCIEx1 configuration interface of each 9977 chip in the chipset is connected to the configuration management board. The chipset's PCIE data cable is divided into three groups: a group of 16 * PCIEx8 connected to the system backplane, and connected to the blade server nodes in the system through the system backplane; the second group of 16 * PCIEx4 data cables are connected to the external PCIE interface, To connect with the PCIE switch outside the blade server system; the third group of 3 * PCIEx16 data cables is connected to the configuration management board, which can be connected or disconnected with another expandable PCIE switch board through configuration. Integrated IntelAvoton processor chip is used to configure the PCIE switch chipset to achieve redundancy and extended configuration switching; integrated 12 Flash chips are used to store the two configuration files required by the 6 PCIE switch chips on 2 PCIE switch boards, supporting Different topology configurations between chips within a chipset. The two expandable PCIE switch boards are interconnected through the configuration management board, and the Avoton processor of the configuration management board is used to select the Flash chip, and then select the configuration file to achieve the current redundant or extended configuration.

The fifth embodiment is the same as the second embodiment, as shown in FIG. 4, except that it includes: a first PCIE switch board component, a second PCIE switch board component, a third PCIE switch board component, a configuration management board 4, and configuration management Board 6 and back plate 2.

A third PCIE switch board component, the first PCIE switch board component and the second PCIE switch board component are connected to the backplane 2 respectively;

The first PCIE switch board assembly includes a first switch board 1, and a first PCIE switch chipset 16 is provided on the first switch board 1.

The third PCIE switch board assembly includes a third switch board 5, and a third PCIE switch chipset 56 is provided on the first switch board 5.

The second PCIE switch chipset 36 is connected to the third PCIE switch chipset 56 through the configuration management board 6. The configuration management board 6 is configured to configure on / off of data communication between the third PCIE switch chipset 56 and the second PCIE switch chipset 36.

The third switch board 5 is further provided with a second backplane connector 54, a first PCIE data harness 51, a second PCIE data 52, and a third PCIE data harness 53; the third PCIE switch chipset 56 passes the first PCIE data in order. The wiring harness 52 and the third PCIE data harness 53; the third PCIE switching chipset 56 is connected to the backplane 2 through the first PCIE data wiring harness 51 and the backplane connector 54 in sequence; the third PCIE switching chipset 56 is connected through the second PCIE data wiring harness 52 is connected to the configuration management board 6; the third PCIE switch chipset 56 is connected to the external PCIE interface 57 through the third PCIE data harness 33. The third switching board 5 is connected to the backplane 2 through a power connector 55 to implement power supply to the first switching board 3.

Configure three expandable PCIE switches in a unit height space. Data is exchanged directly without bus conversion, which reduces overhead and improves data transmission efficiency. The three switches are interconnected through the configuration management board to configure and manage the PCIE switch chip, so that the three expandable PCIE switches can switch between redundant and extended modes to meet the requirements of high reliability and high performance in different application scenarios. Different focus needs. Thereby increasing the competitiveness of the blade server system.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

The terms "first", "second", "third", "fourth", etc. (if present) in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used for Describe a specific order or sequence. It should be understood that the data used in this way are interchangeable under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. Furthermore, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusion.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, this application will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

A blade server architecture based on a redundant expansion configuration, comprising: at least two PCIE switch board components, at least one configuration management board, and a backplane;

Each of the PCIE switch board components is connected to a backplane, respectively;

The PCIE switch board component includes a switch board, and the switch board is provided with a PCIE switch chipset;

The PCIE switching chipset is connected to a PCIE switching chipset on an adjacent PCIE switching board component through the configuration management board, and the configuration management board is configured to configure on-off of data communication between the PCIE switching chipset.
The blade server architecture according to claim 1, wherein:

The PCIE switch chipset includes: at least one PCIE switch chip;

When at least two PCIE switching chips are used, the PCIE switching chip and the PCIE switching chip are interconnected with each other through a PCIE data bus to form a PCIE switching chipset;

A configuration interface of each PCIE switch chip is connected to the configuration management board.
The blade server architecture according to claim 1 or 2, wherein:

The switch board is also provided with a plurality of externally connected PCIE interfaces.
The blade server architecture according to claim 3, wherein:

The exchange board is further provided with a backplane connector, a first PCIE data harness, a second PCIE data harness, and a third PCIE data harness;

The PCIE switch chipset is connected to the backplane through the first PCIE data harness and the backplane connector in sequence;

The PCIE switching chipset is connected to the configuration management board through the second PCIE data harness;

The PCIE switching chipset is connected to the external PCIE interface through the third PCIE data harness.
The blade server architecture according to claim 1 or 2, wherein:

A power connector is also provided on the exchange board;

The switching board is connected to the backplane through the power connector to implement power supply to the switching board.
The blade server architecture according to claim 1 or 2, wherein:

The configuration management board includes: an Intel Avoton processor chip and a Flash chip;

The IntelAvoton processor chip is configured to implement redundancy and extended configuration switching between the PCIE switch chipset; the Flash chipset is used to store a configuration file configured by the PCIE switch chipset, and supports the PCIE switch Different topology configurations between chips within a chipset.
The blade server architecture according to claim 2, wherein:

The PCIE switch chip is a PLX9797PCIE switch chip;

The PLX9797PCIE switch chip and the PLX9797PCIE switch chip are interconnected with each other through a PCIEx16 data bus to form a PCIE switch chipset;

Each PLX9797PCIE switching chip is connected to the configuration management board through a PCIEx1 configuration interface.
The blade server architecture according to claim 4, wherein:

The first PCIE data harness uses 16 * PCIEx8PCIE data lines;

The PCIE switching chipset is connected to the backplane through the 16 * PCIEx8PCIE data line and the backplane connector in order;

The second PCIE data harness uses a 3 * PCIEx16PCIE data line;

The PCIE switching chipset is connected to the configuration management board through the 3 * PCIEx16PCIE data line;

The third PCIE data harness uses 16 * PCIEx4PCIE data lines;

The PCIE switch chipset is connected to the external PCIE interface through the 16 * PCIEx4PCIE data line.
The blade server architecture according to claim 3, wherein:

The externally connected PCIE interface uses an SFP interface for external interconnection of PCIE signal lines and sideband signal lines.