WO2019119176A1 - 一种电流采样保持电路及传感器 - Google Patents

一种电流采样保持电路及传感器 Download PDF

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Publication number
WO2019119176A1
WO2019119176A1 PCT/CN2017/116831 CN2017116831W WO2019119176A1 WO 2019119176 A1 WO2019119176 A1 WO 2019119176A1 CN 2017116831 W CN2017116831 W CN 2017116831W WO 2019119176 A1 WO2019119176 A1 WO 2019119176A1
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Prior art keywords
photodiode
electronic switch
pmos transistor
current
transconductance amplifier
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PCT/CN2017/116831
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English (en)
French (fr)
Inventor
李经珊
张孟文
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深圳市汇顶科技股份有限公司
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Priority to CN201790000305.XU priority Critical patent/CN209911984U/zh
Priority to EP17905908.4A priority patent/EP3527126B1/en
Priority to PCT/CN2017/116831 priority patent/WO2019119176A1/zh
Priority to US16/166,699 priority patent/US10607711B2/en
Publication of WO2019119176A1 publication Critical patent/WO2019119176A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/028—Current mode circuits, e.g. switched current memories
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0046—Arrangements for measuring currents or voltages or for indicating presence or sign thereof characterised by a specific application or detail not covered by any other subgroup of G01R19/00
    • G01R19/0061—Measuring currents of particle-beams, currents from electron multipliers, photocurrents, ion currents; Measuring in plasmas
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H03F1/086—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers with FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/129—Indexing scheme relating to amplifiers there being a feedback over the complete amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/156—One or more switches are realised in the feedback circuit of the amplifier stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/375—Circuitry to compensate the offset being present in an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/45—Indexing scheme relating to amplifiers the load of the amplifier being a capacitive element, e.g. CRT

Definitions

  • the gate-source voltage of the PMOS transistor M also becomes large, and the voltage of the capacitor CSH is equal to the gate-source voltage of the PMOS transistor M, and becomes larger.
  • the voltage of the capacitor CSH becomes large, the reverse bias voltage of the photodiode PD becomes small.
  • the efficiency of the photodiode PD is greatly reduced. Therefore, in the prior art, in order to ensure the efficiency of the photodiode PD, the voltage of the capacitor CSH is prevented from becoming large, that is, the background light current of the photodiode PD is prevented from being large. That is to say, the conventional current sample-and-hold circuit can only be used to offset a small background photocurrent.
  • the embodiment of the present application further provides a sensor, the sensor is integrated with a photodiode and a current sample and hold circuit as described above, and the other end of the first transconductance amplifier in the current sample and hold circuit is connected to the photodiode .
  • the second transconductance amplifier includes a second sampling switch, an amplifying circuit, a first current source, a third electronic switch, and a fourth electronic switch; a first end of the third electronic switch is connected to the second electronic switch a second end of the third electronic switch; the control end of the third electronic switch is connected between the second end of the first current source and the first end of the fourth electronic switch a connection point, and a control end of the fourth electronic switch; a first end of the first current source is connected to the power supply VDD end; and a first end of the fourth electronic switch is further passed through the second sampling switch One end of the amplifying circuit is connected; the second end of the fourth electronic switch is grounded; and the other end of the amplifying circuit is used to connect the photodiode.
  • An implementation of a second transconductance amplifier is provided.
  • the amplifying circuit includes a second current source and a fifth electronic switch; the first end of the fifth electronic switch serves as one end of the amplifying circuit, and the second current source and the second sampling switch are respectively connected The second end of the fifth electronic switch is grounded; the control end of the fifth electronic switch serves as the other end of the amplifying circuit for connecting the photodiode.
  • the amplifying circuit can be an amplifying circuit in the integrator, which facilitates multiplexing of the amplifying circuit.
  • the first electronic switch is a PMOS transistor; a plurality of the PMOS transistors are sequentially arranged in a direction toward the photodiode; and a first one of the plurality of PMOS transistors is closest to the photodiode a PMOS transistor, the last PMOS transistor being the PMOS transistor farthest from the photodiode; the width and length ratio of the first PMOS transistor being equal to the width to length ratio of the second PMOS transistor, and the width to length ratio of the ith PMOS transistor It is twice the width to length ratio of the i-1th PMOS tube, and the i is greater than or equal to 3.
  • An implementation of a first electronic switch is provided.
  • the current sample and hold circuit further includes a third sampling switch; the third sampling switch is connected in parallel across the capacitor. The charge on the capacitor can be released by closing the third sampling switch before sampling begins to ensure the accuracy of the sampling.
  • FIG. 1 is a schematic structural view of a current sample and hold circuit according to prior art
  • the first embodiment of the present application relates to a current sample and hold circuit.
  • the current sample-and-hold circuit is used to cancel the background photocurrent in the photodiode, and includes a capacitor CSH and a first transconductance amplifier OTA1 that outputs a sampling current to the photodiode to cancel the background photocurrent in the photodiode.
  • One end of the capacitor CSH is connected to the power supply VDD terminal, and the other end is connected to one end of the first transconductance amplifier OTA1; the other end of the first transconductance amplifier OTA1 is used to connect the photodiode PD.
  • the current in the variable current source IBG in FIG. 2 is the background photocurrent in the photodiode PD; the parasitic capacitance C PD is the parasitic capacitance inside the photodiode PD.
  • the transconductance of the first transconductance amplifier OTA1 is adjustable.
  • the working process of the current sample-and-hold circuit will be specifically described below.
  • the working process of the current sample and hold circuit includes a sampling phase and an integration phase.
  • the current flowing from the first transconductance amplifier OTA1 to the photodiode PD is equal to the current in the variable current source IBG (ie, the background photocurrent in the photodiode PD), and the capacitance CSH is equivalent to sampling the background photocurrent, and Convert it to its own voltage.
  • the capacitor CSH can be specifically a holding capacitor, but in practical applications, it is not limited thereto.
  • the current sample-and-hold circuit can sample a larger range of background photocurrents, and the voltage U of the capacitor can be prevented from changing over a wide range.
  • the transconductance g m1 of the first transconductance amplifier can be varied in equal proportion to the background photocurrent I in the photodiode, so that the voltage U of the capacitor can be kept constant.
  • the voltage on the capacitor CSH is converted into a current (the magnitude of the current is equal to the magnitude of the previously sampled background photocurrent), and is output to the photodiode PD through the first transconductance amplifier OTA1, thereby canceling the background in the photodiode PD.
  • Photocurrent This is equivalent to canceling the background photocurrent in the photodiode PD with the previous sampling current.
  • I the background photocurrent I in the photodiode increases
  • the transconductance g m1 of the first transconductance amplifier by increasing the transconductance g m1 of the first transconductance amplifier, the voltage U of the capacitor can be avoided as the background photocurrent I increases.
  • a wide range of variations and the current sample-and-hold circuit can cancel a wider range of background photocurrents.
  • a second embodiment of the present application relates to a current sample and hold circuit.
  • the second embodiment is a further improvement based on the first embodiment, the main improvement being that the second embodiment provides a bias circuit for supplying a bias voltage to the first transconductance amplifier OTA1.
  • the current sample and hold circuit in this embodiment further includes a first sampling switch SW1 and a bias circuit 31 for supplying a bias voltage to the first transconductance amplifier OTA1.
  • the first end of the bias circuit 31 is connected to the first sampling switch SW1, and is connected to one end of the first transconductance amplifier OTA1 and the other end of the capacitor CSH through the first sampling switch SW1.
  • the second end of the bias circuit 31 is connected to the power supply VDD terminal, and the third end of the bias circuit 31 is used to connect the photodiode PD.
  • the bias circuit 31 can include a second electronic switch M3 and a second transconductance amplifier OTA2.
  • the second electronic switch M3 may be formed by a field effect transistor or other electron tube, and the field effect transistor may be a PMOS transistor or an NMOS transistor.
  • FIG. 3 is an example in which the second electronic switch is a PMOS transistor.
  • the NMOS transistor can be selected as the second electronic switch as needed, which is not limited in this embodiment.
  • the first end of the second electronic switch M3 ie, the source of the PMOS tube in FIG. 3) serves as the second end of the bias circuit 31 and is connected to the power supply VDD terminal.
  • the second end of the second electronic switch M3 ie, the drain of the PMOS transistor in FIG.
  • a control end of the second electronic switch M3 (ie, a gate of the PMOS transistor in FIG. 3) as a first end of the bias circuit 31, connected to the first sampling switch SW1, and a second end of the second electronic switch M3
  • the other end of the second transconductance amplifier OTA2 serves as the third end of the bias circuit 31 for connecting the photodiode PD.
  • the third sampling switch SW3 may be connected in parallel across the capacitor CSH, and the third sampling switch SW3 is closed before the sampling phase begins. At this time, both ends of the capacitor CSH are turned on, and the capacitor CSH enters a discharge state. The purpose of this is to eliminate the charge on the capacitor CSH and ensure the accuracy of the sampling.
  • the third sampling switch SW3 can be turned off and the first sampling switch SW1 can be closed.
  • the entire current sample-and-hold circuit forms a closed-loop negative feedback.
  • the first end of the second transconductance amplifier OTA2 ie, the end for connecting the photodiode PD
  • the second end of the second transconductance amplifier OTA2 ie, for connecting the second electronic switch
  • One end of M3 outputs current to the second electronic switch M3 (ie, provides a bias current to the second electronic switch M3).
  • the first transconductance amplifier OTA1 When a current flows through the second electronic switch M3, a voltage is generated to supply a bias voltage to the first transconductance amplifier OTA1, which triggers the first transconductance amplifier OTA1 to enter an active state.
  • the current flowing from the first transconductance amplifier OTA1 to the photodiode PD is equal to the current in the variable current source IBG (ie, the background photocurrent in the photodiode PD), and the capacitance CSH is equivalent to sampling the background photo current, and It is converted to its own voltage.
  • the transconductance of the first transconductance amplifier OTA1 can be adjusted to avoid the voltage U of the capacitor being Change over a wide range.
  • the transconductance g m1 of the first transconductance amplifier can be increased to prevent the voltage U of the capacitor from changing over a large range as the background photocurrent I increases. .
  • the current sample-and-hold circuit can be sampled to sample a larger range of background photocurrents, and the voltage U of the capacitor can be prevented from changing over a wide range.
  • the current sampling and holding circuit is configured to include two poles in the loop, and one is a main pole P1 (corresponding to a node between the first transconductance amplifier OTA1 and the photodiode PD) The other is the non-primary pole P2 (corresponding to the node between the control end of the second electronic switch M3, the second end, and the second transconductance amplifier OTA2).
  • the pole position P 2 is independent of the photodiode PD, so that when the area of the photodiode PD changes, the position of the non-primary pole remains unchanged.
  • the C PD When the area of the photodiode PD changes, the C PD also changes synchronously (for example, the area of the photodiode PD increases by A times, and the C PD also increases by A times), by adjusting the transconductance of the first transconductance amplifier.
  • g m1 which makes g m1 change in equal proportions (even if g m1 is increased by A times), the gain bandwidth product GBW can be kept unchanged.
  • the gain bandwidth product GBW remains unchanged, and the position of the non-main pole P2 remains unchanged, so that the stability of the entire loop is not affected by the change in the area of the photodiode PD.
  • the background photocurrent I in the photodiode PD is increased (caused by a change in light intensity or caused by a change in the area of the photodiode), by increasing the first transconductance amplifier By transconducting g m1 , the voltage U of the capacitor can be prevented from changing over a wide range as the background photocurrent I increases, and the current sample-and-hold circuit can cancel a larger range of background photocurrent.
  • the first transconductance amplifier transconductance g m1 photodiode PD area equal proportions change, to make The stability of the entire circuit is not affected by changes in the area of the photodiode PD.
  • a third embodiment of the present application relates to a current sample and hold circuit.
  • Third Embodiment On the basis of the second embodiment, an implementation of a first transconductance amplifier and a second transconductance amplifier is provided.
  • the first transconductance amplifier OTA1 may include a plurality of first electronic switches and a plurality of control switches for controlling the first electronic switches.
  • the first electronic switches are connected between the power supply VDD terminal and the photodiode PD, and a plurality of first electronic switches are connected in series with each other, and the control terminals of the plurality of electronic switches are connected to the other end of the capacitor CSH.
  • the connection point of any two adjacent first electronic switches corresponds to one control switch, one end of each control switch is connected to the power supply VDD end, and the other end is connected to the corresponding connection point.
  • the first electronic switch may be composed of a field effect transistor or other electron tube, and the field effect transistor may be a PMOS transistor or an NMOS transistor.
  • 4 is an illustration in which the first electronic switch is a PMOS transistor and the number of first electronic switches is equal to four.
  • the four first electronic switches in FIG. 4 are respectively connected PMOS tube M4, PMOS tube M5, PMOS tube M6, and PMOS tube M7.
  • the source of the PMOS transistor M4 serves as one end of the first transconductance amplifier OTA1, and is connected to the capacitor CSH;
  • the drain of the PMOS transistor M4 is connected to the source of the PMOS transistor M5, the drain of the PMOS transistor M5 is connected to the source of the PMOS transistor M6, the drain of the PMOS transistor M6 is connected to the source of the PMOS transistor M7, and the drain of the PMOS transistor M7 is used as the drain.
  • the other end of a transconductance amplifier OTA1 is used to connect the photodiode PD.
  • the gates of the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 are connected to the other end of the capacitor CSH.
  • the control switch can be an electronic switch or a conventional mechanical switch, which can be a field effect transistor such as a PMOS or NMOS transistor.
  • the control switch is a PMOS transistor, and the number of control switches is equal to three.
  • the three control switches in Figure 4 are M8 (ie CN1), M9 (ie CN2) and M10 (ie CN3).
  • the connection point corresponding to the control switch M8 is a connection point between the PMOS tube M6 and the PMOS tube M7
  • the connection point corresponding to the control switch M9 is a connection point between the PMOS tube M5 and the PMOS tube M6, and the corresponding connection of the control switch M10
  • the point is the connection point between the PMOS transistor M4 and the PMOS transistor M5.
  • the number of the first electronic switches is four, and the number of the control switches is three.
  • the number of the first electronic switches can be flexibly selected according to the actual situation, and the number of the control switches can be adaptively adjusted according to the number of the first electronic switches, which is not limited in this embodiment.
  • the second transconductance amplifier OTA2 may include a second sampling switch SW2, an amplifying circuit 41, a first current source IB1, a third electronic switch M2, and a fourth electronic switch M1.
  • Third electronic switch M2 and fourth electric Sub-switch M1 may be formed by a field effect transistor or other electron tube, which may be a PMOS transistor or an NMOS transistor.
  • the third electronic switch M2 and the fourth electronic switch M1 are both NMOS tubes as an example.
  • the first end of the third electronic switch M2 ie, the drain of the NMOS transistor M2 in FIG. 4) is connected to the second end of the second electronic switch M3; the second end of the third electronic switch M2 (ie, the NMOS tube in FIG.
  • the source of the M2 is grounded; the control end of the third electronic switch M2 (ie, the gate of the NMOS transistor M2 in FIG. 4) is connected to the second end of the first current source IB1 and the first end of the fourth electronic switch M1 (ie, a connection point between the drains of the NMOS transistors M1 in 4, and a control terminal of the fourth electronic switch M1 (ie, the gate of the NMOS transistor M1 in FIG. 4), and a second end of the fourth electronic switch M4 (ie, FIG. 4)
  • the source of the middle NMOS transistor M1 is grounded.
  • the first end of the first current source IB1 is connected to the power supply VDD terminal.
  • the first end of the fourth electronic switch M4 is further connected to one end of the amplifying circuit 41 through the second sampling switch SW2; the other end of the amplifying circuit 41 is used to connect the photodiode PD.
  • the amplifying circuit 41 may be an amplifying circuit in the integrator, which is advantageous for realizing multiplexing of the amplifying circuit.
  • the amplifying circuit 41 may include a second current source IB2 and a fifth electronic switch MA.
  • the fifth electronic switch MA may be constituted by a field effect transistor or other electron tube, and the field effect transistor may be a PMOS transistor or an NMOS transistor.
  • the fifth electronic switch MA is an NMOS transistor as an example.
  • the first end of the fifth electronic switch MA ie, the drain of the NMOS transistor MA in FIG.
  • the amplifying circuit 41 serves as one end of the amplifying circuit 41, and is respectively connected to the second current source IB2 and the second sampling switch SW2; and the fifth electronic switch MA
  • the second end ie, the source of the NMOS transistor MA in FIG. 4 is grounded;
  • the control end of the fifth electronic switch MA ie, the gate of the NMOS transistor MA in FIG. 4 serves as the other end of the amplifying circuit 41 for connecting the photodiode PD.
  • the conduction field effect crystal can be adjusted by controlling the number of conduction of the plurality of field effect transistors.
  • the equivalent width-to-length ratio of the tube and the equivalent output impedance of the turned-on field effect transistor thereby achieving the purpose of adjusting the transconductance of the first transconductance amplifier OTA1, so that the current sampling and holding circuit avoids the voltage U of the capacitor in a large range.
  • more background photocurrent can be cancelled, and the stability of the current sample-and-hold circuit is not affected by the change of the photodiode PD area.
  • the width to length ratio of the plurality of PMOS transistors should satisfy the following relationship: when the plurality of PMOS transistors are sequentially arranged in a direction toward the photodiode PD, The first PMOS transistor of the plurality of PMOS transistors is the PMOS transistor closest to the photodiode PD, and the last PMOS transistor is the PMOS transistor farthest from the photodiode PD.
  • the width to length ratio of the first PMOS transistor is equal to the width to length ratio of the second PMOS transistor, and the width to length ratio of the ith PMOS transistor is twice the width to length ratio of the i-1th PMOS transistor, where i is greater than or Equal to 3.
  • the width ratio of the second electronic switch M3 may be equal to the width to length ratio of the first PMOS transistor.
  • a series connection between the PMOS transistor M4 and the power supply VDD terminal can also be used. Or multiple PMOS tubes (the number of series may depend on the actual situation). For example, if a PMOS transistor is connected in series, the width to length ratio of the PMOS transistor should be twice the width to length ratio of the PMOS transistor M4.
  • the third sampling switch SW3 is turned off, and the first sampling switch SW1 and the second are closed. Sampling switch SW2. At this time, the current sample-and-hold circuit constitutes a closed-loop negative feedback.
  • the first current source IB1 and the second current source IB2 supply current to the fourth electronic switch M1, and a voltage is generated on the fourth electronic switch M1 to supply a bias voltage to the third electronic switch M2.
  • the third electronic switch M2 generates a current after receiving the bias voltage, thereby supplying a bias current to the second electronic switch M3.
  • the second electronic switch M3 generates a voltage after receiving the bias current, thereby providing a bias voltage to the gates of the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 (ie, providing bias to the plurality of first electronic switches) Voltage), triggering the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 to enter an active state.
  • the current flowing into the photodiode PD through the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 is equal to the current in the variable current source IBG (ie, the background photocurrent), and the capacitance CSH is equivalent to the sampled background. Photocurrent and convert it to its own voltage.
  • the control switches M8, M9, and M10 can be turned off, and the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 are all turned on.
  • the equivalent width to length ratio of the PMOS transistor M4, the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 is W/(8L)
  • the width and length ratio of the second electronic switch M3 is W/L, that is, the second electron.
  • I BG the background photo current
  • the control switches M8 and M9 can be turned off, and the control switch M10 can be turned on to short-circuit the PMOS transistor M4.
  • the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 are turned on, and the equivalent width to length ratio of the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 is W/(4L), and the aspect ratio of the second electronic switch M3.
  • the control switches M8 and M10 can be turned off, and the control switch M9 can be turned on to make the PMOS tube M4 and PMOS transistor M5 are short-circuited.
  • the PMOS transistor M6 and the PMOS transistor M7 are turned on, and the equivalent width to length ratio of the PMOS transistor M6 and the PMOS transistor M7 is W/(2L).
  • the width to length ratio of the second electronic switch M3 is twice the equivalent width to length ratio of the turned-on PMOS transistor M6 and the PMOS transistor M7, and the current I M3 flowing through the second electronic switch M3 is the current variable current source IBG.
  • the current I M3 flowing through the second electronic switch M3 is always constant.
  • the formula I (1/2) * uc ox * (W / L) * (V GS - V TH ), where I is the background photocurrent in the photodiode PD, that is, the current in the variable current source IBG I BG ; uc ox is the parameter does not change; here (W / L) represents the equivalent width to length ratio of the turned-on PMOS tube; V GS is the gate-source voltage of the several PMOS transistors, the size of which is equal to the capacitance CSH The voltage U; V TH is the turn-on voltage of several PMOS transistors, and is not affected by the change of the area of the photodiode PD.
  • the current I M3 flowing through the second electronic switch M3 is always constant, which causes non-master in the circuit.
  • the position of the pole P2 remains unchanged.
  • the current flowing through the fourth electronic switch M1 in the circuit is provided by the first current source IB1 and the second current source IB2. Since both are constant current sources, the current I M1 flowing through the fourth electronic switch M1 is also Will not change, I M1 does not change, the position of the non-main pole P3 in the circuit (corresponding to the second end of the first current source IB1, the node between the first end of the fourth electronic switch M1 and the control end) will not change.
  • the ratio of the length ratio; g mA is the transconductance of the amplifier MA, which is not affected by the change of the photodiode PD.
  • the C PD is also doubled.
  • the PMOS transistor M4 is short-circuited, and the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 are turned on, and the equivalent channel length of the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M7 is doubled, which makes the conduction.
  • the ratio K of the equivalent width to length ratio of the PMOS tube to the width to length ratio of the second electronic switch M3 is also doubled, and the GBW remains unchanged.
  • the ratio K of the equivalent width-to-length ratio of the pass-through PMOS tube to the width-to-length ratio of the second electronic switch M3 is also four times that of the original, and the GBW remains unchanged.
  • the equivalent channel length of the turned-on PMOS transistor and the area of the photodiode PD are changed in opposite proportions by changing the number of turned-on PMOS transistors (equivalent
  • the output impedance is proportional to the equivalent channel length, so the equivalent output impedance of the turned-on PMOS transistor can be changed in the opposite ratio to the area of the photodiode PD, so that the loop gain bandwidth product is constant.
  • the positions of the two non-main poles P2 and P3 in the loop remain unchanged, and the loop gain bandwidth product is also constant, so that the stability of the loop is not affected by the change of the photodiode PD area.
  • the minimum aspect ratio (such as the width to length ratio of the PMOS transistor M7) can be designed according to the area of the smallest photodiode PD. And the design generally leaves a certain margin. For example, when the area of the photodiode PD changes between 0.5 and 1.5, the gear of 1x area can be selected to support (ie, the area of the photodiode PD is considered to be increased). 1 times); if the area of the photodiode PD is changed between 1.5 times and 2.5 times, the gear of 2 times the area can be supported (ie, the area of the photodiode PD is increased by 2 times).
  • the first sampling switch SW1 and the second sampling switch SW2 can be disconnected, and the circuit enters the integration phase.
  • the voltage on the capacitor CSH is converted to a current (the magnitude of the current is equal to the magnitude of the previously sampled background photocurrent), and is output to the photodiode PD through the turned-on PMOS transistor to cancel the background photocurrent in the photodiode PD.
  • the embodiment provides an implementation manner of the first transconductance amplifier OTA1 and the second transconductance amplifier OTA2.
  • a conventional operational transconductance amplifier can be directly selected as the first transconductance amplifier OTA1 and the second transconductance amplifier OTA2, which is not limited in this embodiment.
  • a fourth embodiment of the present application relates to a sensor.
  • the sensor may be a sensing path for detecting the heart rate.
  • the current sampling and holding circuit and the photodiode of the first embodiment, the second embodiment or the third embodiment may be integrated on the sensor.
  • the other end of the first transconductance amplifier OTA1 in the current sample and hold circuit can be connected to the cathode of the photodiode, and the anode of the photodiode can be grounded.
  • an integrator may be integrated on the sensor, and the amplifying circuit in the integrator is used as an amplifying circuit in the bias circuit in Embodiment 2.
  • the first sampling switch SW1 is closed, and the amplifying circuit in the integrator is used as a part of the current sampling and holding circuit, and the current The other parts of the sample and hold circuit form a loop.
  • the amplifying circuit operates as part of the integrator. This facilitates multiplexing of the amplifying circuit of the integrator.

Abstract

一种电流采样保持电路及传感器。该电流采样保持电路用于抵消光电二极管（PD）中的背景光电流，包括电容（CSH）及一个向所述光电二极管（PD）输出采样电流以抵消光电二极管（PD）中的背景光电流的跨导可调节的第一跨导放大器（OTA1）；所述电容（CSH）的一端连接电源VDD端，所述电容（CSH）的另一端连接所述第一跨导放大器（OTA1）的一端；所述第一跨导放大器（OTA1）的另一端用于连接光电二极管（PD），以向所述光电二极管（PD）输出采样电流，抵消所述光电二极管（PD）中的背景光电流。在电流采样保持电路中设置了跨导可调节的第一跨导放大器（OTA1），当光电二极管（PD）中的背景光电流增大时，通过增大第一跨导放大器（OTA1）的跨导，就可避免电容（CSH）的电压在较大范围内变化，以使电流采样保持电路能够抵消更大的背景光电流。

Description

一种电流采样保持电路及传感器 技术领域
本申请涉及电流采样保持技术领域，特别涉及一种电流采样保持电路及传感器。
背景技术
现有的心率检测电路中，通常都会用到光电二极管来接收人体反射光，再利用积分器把光电二极管的感应电流转换成电压信号，以供后续处理。但环境光的存在，常常会使积分器饱和，从而影响电路的正常工作。为此，需要引入电流采样保持电路，来抵消光电二极管中的背景光电流(即光电二极管因接收环境光而产生的感应电流)，防止积分器饱和。
传统的电流采样保持电路如图1所示。图1中，电流采样保持电路中的电流输出电路由一个尺寸固定的PMOS管M构成。PMOS管M在采样阶段用于采样光电二极管PD中的背景光电流(即光电二极管PD的感应电流，也就是图1中可变电流源IBG的电流)，并将采样电流转换为电容CSH的电压。在积分阶段，PMOS管M用于将之前的采样电流输送给光电二极管PD，从而抵消光电二极管中的背景光电流。
在光电二极管PD的面积保持不变的情况下，光电二极管PD的背景光电流随光强的增大而增大。而在光强保持不变的情况下，光电二极管PD的背景光电流又与光电二极管PD的面积成正比。因此，当光电二极管PD的面积保持不变而光强在一个较大范围内变化时，或光强保持不变而光电二极管PD的面 积在一个较大范围内变化时，都会使得光电二极管PD中的背景光电流在一个较大范围内变化。当光电二极管PD的背景光电流很大时，PMOS管M的栅源电压也会变得很大，电容CSH的电压与PMOS管M的栅源电压相等，也会随之变大。而电容CSH的电压变大，会使光电二极管PD的反偏电压变小。当反偏电压小到一定程度时，会使光电二极管PD的效率大大降低。因此现有技术中为保障光电二极管PD的效率，就会避免电容CSH的电压变得很大，即避免光电二极管PD的背景光电流很大。也就是说，传统的电流采样保持电路只能用于抵消较小的背景光电流。
发明内容
本申请部分实施例的目的在于提供一种电流采样保持电路及传感器，能在避免电容的电压在较大范围内变化的前提下，使得电流采样保持电路可以抵消更宽范围的背景光电流。
本申请的一个实施例提供了一种电流采样保持电路，用于抵消光电二极管中的背景光电流，包括：电容及向所述光电二极管输出采样电流以抵消光电二极管中的背景光电流的一个跨导可调节的第一跨导放大器；所述电容的一端连接电源VDD端，所述电容的另一端连接所述第一跨导放大器的一端；所述第一跨导放大器的另一端用于连接光电二极管，以向所述光电二极管输出所述采样电流，抵消所述光电二极管中的背景光电流。
本申请实施例还提供了一种传感器，所述传感器上集成有光电二极管及如上所述的电流采样保持电路，所述电流采样保持电路中的第一跨导放大器的另一端连接所述光电二极管。
本申请实施例相对于现有技术而言，在电流采样保持电路中设置了跨导可调节的第一跨导放大器，根据公式I＝gm1*U可知，当光电二极管中的背景光电流I增大(由光强变化引起或由光电二极管的面积变化引起)时，通过增大第一跨导放大器的跨导gm1，就可避免电容的电压U在较大范围内变化，这使得电流采样保持电路能够抵消更大的背景光电流。
另外，所述第一跨导放大器包括若干个第一电子开关及若干个用于控制所述第一电子开关的控制开关；所述若干个第一电子开关连接在所述电源VDD端及所述光电二极管之间，且所述若干个第一电子开关之间相互串联，所述若干个电子开关的控制端均连接所述电容的另一端；任意两个相邻的所述第一电子开关的连接点对应一个所述控制开关，每个所述控制开关的一端连接所述电源VDD端，每个所述控制开关的另一端连接对应的所述连接点。提供一种第一跨导放大器的实现方式。
另外，所述电流采样保持电路还包括第一采样开关及用于向所述第一跨导放大器提供偏置电压的偏置电路；所述偏置电路的一端通过所述第一采样开关同时连接所述第一跨导放大器的一端及所述电容的另一端；所述偏置电路的另一端用于连接所述光电二极管。在闭合第一采样开关时，可使电流采样保持电路构成闭环负反馈。
另外，所述偏置电路包括第二电子开关及第二跨导放大器；所述第二电子开关的第一端连接所述电源VDD端；所述第二电子开关的第二端连接所述第二跨导放大器的一端；所述第二电子开关的控制端作为所述偏置电路的一端连接所述第一采样开关，以及所述第二电子开关的第二端与所述第二跨导放大器的一端之间的连接点；所述第二跨导放大器的另一端作为所述偏置电路的另 一端用于连接所述光电二极管。提供一种偏置电路的结构。
另外，所述第二跨导放大器包括第二采样开关、放大电路、第一电流源、第三电子开关及第四电子开关；所述第三电子开关的第一端连接所述第二电子开关的第二端；所述第三电子开关的第二端接地；所述第三电子开关的控制端连接所述第一电流源的第二端与所述第四电子开关的第一端之间的连接点，以及所述第四电子开关的控制端；所述第一电流源的第一端连接所述电源VDD端；所述第四电子开关的第一端还通过所述第二采样开关连接所述放大电路的一端；所述第四电子开关的第二端接地；所述放大电路的另一端用于连接所述光电二极管。提供一种第二跨导放大器的实现方式。
另外，所述放大电路包括第二电流源及第五电子开关；所述第五电子开关的第一端作为所述放大电路的一端，分别连接所述第二电流源及所述第二采样开关；所述第五电子开关的第二端接地；所述第五电子开关的控制端作为所述放大电路的另一端，用于连接所述光电二极管。该放大电路可以是积分器中的放大电路，这有利于实现对该放大电路的复用。
另外，所述第一电子开关为PMOS管；若干个所述PMOS管沿朝向所述光电二极管的方向依次排列；若干个所述PMOS管中的第一个PMOS管为最靠近所述光电二极管的PMOS管，最后一个PMOS管为最远离所述光电二极管的PMOS管；所述第一个PMOS管的宽长比与第二个PMOS管的宽长比相等，第i个PMOS管的宽长比为第i-1个PMOS管的宽长比的两倍，所述i大于或等于3。提供一种第一电子开关的实现方式。
另外，所述第二电子开关为PMOS管，且所述第二电子开关的宽长比与所述第一个PMOS管的宽长比相等。提供一种第一电子开关与第二电子开关的 关系。
另外，所述电流采样保持电路还包括第三采样开关；所述第三采样开关并联在所述电容的两端。在采样开始前，可通过闭合第三采样开关来释放电容上的电荷，以确保采样的准确性。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据现有技术的电流采样保持电路的结构示意图；
图2是根据本申请第一实施例的电流采样保持电路的结构示意图；
图3是根据本申请第二实施例的电流采样保持电路的结构示意图；
图4是根据本申请第三实施例的电流采样保持电路的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种电流采样保持电路。如图2所示，该电流采样保持电路用于抵消光电二极管中的背景光电流，包括电容CSH及向所述光电二极管输出采样电流以抵消光电二极管中的背景光电流的第一跨导放大器OTA1。电容CSH的一端连接电源VDD端，另一端连接第一跨导放大器OTA1 的一端；第一跨导放大器OTA1的另一端用于连接光电二极管PD。图2中可变电流源IBG中的电流即是光电二极管PD中的背景光电流；寄生电容CPD为光电二极管PD内部的寄生电容。
本实施例中，设置第一跨导放大器OTA1的跨导是可调的。下面将具体介绍电流采样保持电路的工作过程。
具体而言，电流采样保持电路的工作过程包括采样阶段及积分阶段。在采样阶段，第一跨导放大器OTA1向光电二极管PD流入的电流与可变电流源IBG中的电流(即光电二极管PD中的背景光电流)相等，电容CSH相当于采样了背景光电流，并将其转换为自身的电压。其中，电容CSH可以具体为保持电容，但在实际应用中，并不以此为限。
当光电二极管PD中的背景光电流发生变化(由光强变化引起或由光电二极管的面积变化引起)时，即可变电流源IBG中的电流发生变化时，可调节第一跨导放大器OTA1的跨导，以避免电容的电压U在较大范围内变化。根据公式I＝gm1*U可知，当光电二极管中的背景光电流I增大时，通过增大第一跨导放大器的跨导gm1，就可以避免电容的电压U随背景光电流I的增大而在较大范围内变化。这样，即可使电流采样保持电路采样更大范围的背景光电流，也可避免电容的电压U在较大范围内变化。特别地，可使第一跨导放大器的跨导gm1，与光电二极管中的背景光电流I按相等比例变化，这样，就可使电容的电压U保持不变。
采样阶段结束后，即可进入积分阶段。此时，电容CSH上的电压转为电流(该电流的大小即等于之前采样的背景光电流的大小)，并通过第一跨导放大器OTA1输出至光电二极管PD，从而抵消光电二极管PD中的背景光电流。 这相当于用之前的采样电流，抵消光电二极管PD中的背景光电流。
本实施例相对于现有技术而言，在电流采样保持电路中设置了跨导可调节的第一跨导放大器，根据公式I＝gm1*U可知，当光电二极管中的背景光电流I增大(由光强变化引起或由光电二极管的面积变化引起)时，通过增大第一跨导放大器的跨导gm1，就可避免电容的电压U随背景光电流I的增大而在较大范围内变化，并使电流采样保持电路能抵消更大范围的背景光电流。
本申请的第二实施例涉及一种电流采样保持电路。第二实施例是在第一实施例的基础上做的进一步改进，主要改进之处在于，第二实施例提供了一种用于向第一跨导放大器OTA1提供偏置电压的偏置电路。
如图3所示，本实施例中的电流采样保持电路还包括第一采样开关SW1及用于向第一跨导放大器OTA1提供偏置电压的偏置电路31。偏置电路31的第一端连接第一采样开关SW1，并通过第一采样开关SW1同时连接第一跨导放大器OTA1的一端及电容CSH的另一端。偏置电路31的第二端连接电源VDD端，偏置电路31的第三端则用于连接光电二极管PD。
在实际应用中该偏置电路31可包括第二电子开关M3及第二跨导放大器OTA2。其中，第二电子开关M3可由场效应晶体管或其它电子管构成，该场效应晶体管可以是PMOS管或NMOS管。图3是以第二电子开关是PMOS管为例进行示意的，但在实际应用中，也可根据需要选择NMOS管作为第二电子开关，本实施例对此不做限制。第二电子开关M3的第一端(即图3中PMOS管的源极)作为所述偏置电路31的第二端，连接电源VDD端。第二电子开关M3的第二端(即图3中PMOS管的漏极)连接第二跨导放大器OTA2的一端。 第二电子开关M3的控制端(即图3中PMOS管的栅极)作为所述偏置电路31的第一端，连接第一采样开关SW1，以及第二电子开关M3的第二端与第二跨导放大器OTA2的一端之间的连接点。第二跨导放大器OTA2的另一端则作为所述偏置电路31的第三端，用于连接光电二极管PD。
本实施方式还可在电容CSH的两端并联第三采样开关SW3，并在采样阶段开始前，闭合第三采样开关SW3。此时，电容CSH的两端接通，电容CSH进入放电状态。这样做的目的是消除电容CSH上的电荷，确保采样的准确性。
在采样阶段，可断开第三采样开关SW3，并闭合第一采样开关SW1。此时，整个电流采样保持电路构成闭环负反馈。其中，第二跨导放大器OTA2的第一端(即用于连接光电二极管PD的一端)输入光电二极管PD的阴极电压，第二跨导放大器OTA2的第二端(即用于连接第二电子开关M3的一端)输出电流至第二电子开关M3(即向第二电子开关M3提供偏置电流)。第二电子开关M3中有电流经过时，会产生电压，从而向第一跨导放大器OTA1提供偏置电压，触发第一跨导放大器OTA1进入工作状态。此时，第一跨导放大器OTA1向光电二极管PD流入的电流与可变电流源IBG中的电流(即光电二极管PD中的背景光电流)相等，电容CSH相当于采样了背景光电流，并将其转换为自身的电压。
同样的，当光电二极管PD中的背景光电流发生变化(由光强变化引起或由光电二极管的面积变化引起)时，可调节第一跨导放大器OTA1的跨导，以避免电容的电压U在较大范围内变化。比如，光电二极管中的背景光电流I增大时，可通过增大第一跨导放大器的跨导gm1，来避免电容的电压U随背景光电流I的增大而在较大范围内变化。这样，即可使电流采样保持电路采样更大 范围的背景光电流，也可避免电容的电压U在较大范围内变化。
当采样阶段结束后，即可断开第一采样开关SW1，此时电路进入积分阶段。如上文所述，在采样阶段，第一跨导放大器OTA1向光电二极管PD流入的电流与可变电流源IBG中的电流(即光电二极管PD中的背景光电流)相等，电容CSH相当于采样了背景光电流，并将其转换为自身的电压。而在积分阶段，电容CSH上的电压转为电流(该电流的大小即等于之前采样的背景光电流的大小)，并通过第一跨导放大器OTA1输出至光电二极管PD，从而抵消光电二极管PD中的背景光电流。这相当于用之前的采样电流，抵消光电二极管PD中的背景光电流。
此外，值得一提的是，本实施例中，电流采样保持电路构在的环路中包括两个极点，一个是主极点P1(对应第一跨导放大器OTA1与光电二极管PD之间的节点)，另一个是非主极点P2(对应第二电子开关M3的控制端、第二端及第二跨导放大器OTA2三者之间的节点)。非主极点P2的位置公式为：P2＝1/(r2*C2)，其中，r2表示对应的节点的等效阻抗，C2表示对应的节点的等效电容。可以看出，该极点位置P2与光电二极管PD无关，因此当光电二极管PD的面积发生变化时，该非主极点的位置保持不变。环路的增益带宽积GBW＝gm1*gm2*r2/CPD，其中，gm2表示第二跨导放大器OTA2的跨导，CPD表示光电二极管PD的寄生电容。当光电二极管PD的面积变化时，CPD也会同步发生变化(比如光电二极管PD的面积增大A倍，CPD也会增大A倍)，此时通过调节第一跨导放大器的跨导gm1，使gm1按相等比例变化(即使gm1也增大A倍)，就可使增益带宽积GBW保持不变。增益带宽积GBW保持不变，且非主极点P2的位置也保持不变，就可使整个环路的稳定性不受光电二极管PD面积变化 的影响。
本实施例相对于第一实施方式而言，在光电二极管PD中的背景光电流I增大(由光强变化引起或由光电二极管的面积变化引起)时，通过增大第一跨导放大器的跨导gm1，就可避免电容的电压U随背景光电流I的增大而在较大范围内变化，并使电流采样保持电路能抵消更大范围的背景光电流。同时，在光电二极管PD的面积发生变化时，通过调节第一跨导放大器的跨导gm1，使第一跨导放大器的跨导gm1与光电二极管PD的面积按相等比例变化，即可使整个电路的稳定性不受光电二极管PD面积变化的影响。
本申请的第三实施例涉及一种电流采样保持电路。第三实施例在第二实施例的基础上，提供一种第一跨导放大器及第二跨导放大器的实现方式。
如图4所示，第一跨导放大器OTA1可包括若干个第一电子开关及若干个用于控制所述第一电子开关的控制开关。该若干个第一电子开关连接在电源VDD端及光电二极管PD之间，且若干个第一电子开关之间相互串联，该若干个电子开关的控制端均连接电容CSH的另一端。并且，任意两个相邻的第一电子开关的连接点对应一个控制开关，每个控制开关的一端连接电源VDD端，另一端则连接对应的连接点。
具体地，第一电子开关可由场效应晶体管或其它电子管构成，该场效应晶体管可以是PMOS管或NMOS管。图4是以第一电子开关是PMOS管，且第一电子开关的数量等于4为例进行示意的。图4中的4个第一电子开关分别为依次连接的PMOS管M4、PMOS管M5、PMOS管M6、PMOS管M7。其中，PMOS管M4的源极作为第一跨导放大器OTA1的一端，连接至电容CSH； PMOS管M4的漏极连接PMOS管M5的源极，PMOS管M5的漏极连接PMOS管M6的源极，PMOS管M6的漏极连接PMOS管M7的源极，PMOS管M7的漏极作为第一跨导放大器OTA1的另一端用于连接光电二极管PD。PMOS管M4、PMOS管M5、PMOS管M6及PMOS管M7的栅极(即第一电子开关的控制端)均连接电容CSH的另一端。
控制开关可以是电子开关或普通的机械开关，该电子开关可以是场效应晶体管，如PMOS管或NMOS管。图4中是以控制开关是PMOS管，且控制开关的数量等于3为例进行示意的。图4中的3个控制开关分别为M8(即CN1)、M9(即CN2)及M10(即CN3)。其中，控制开关M8对应的连接点是PMOS管M6与PMOS管M7之间的连接点，控制开关M9对应的连接点是PMOS管M5与PMOS管M6之间的连接点，控制开关M10对应的连接点则是PMOS管M4与PMOS管M5之间的连接点。值得一提的是，选择PMOS管或NMOS管作为控制开关时，可使PMOS管或NMOS管的栅极悬空，并将源极及漏极作为控制开关的两个连接端。在PMOS管与NMOS管之间，本实施例优选PMOS管作为控制开关，因为PMOS管的衬底与源极短接，不存在衬偏效应，导通特性更佳。
需要说明的是，本实施例仅是以第一电子开关的数量是4个、控制开关的数量是3个进行举例说明。在实际应用中，也可根据实际情况，灵活选择第一电子开关的数量，并根据第一电子开关的数量适应性地调整控制开关的数量，本实施方式对此不做限制。
第二跨导放大器OTA2可包括第二采样开关SW2、放大电路41、第一电流源IB1、第三电子开关M2及第四电子开关M1。第三电子开关M2及第四电 子开关M1可由场效应晶体管或其它电子管构成，该场效应晶体管可以是PMOS管或NMOS管。图4中是以第三电子开关M2及第四电子开关M1均是NMOS管为例进行示意的。其中，第三电子开关M2的第一端(即图4中NMOS管M2的漏极)连接第二电子开关M3的第二端；第三电子开关M2的第二端(即图4中NMOS管M2的源极)接地；第三电子开关M2的控制端(即图4中NMOS管M2的栅极)连接第一电流源IB1的第二端与第四电子开关M1的第一端(即图4中NMOS管M1的漏极)之间的连接点，以及第四电子开关M1的控制端(即图4中NMOS管M1的栅极)，第四电子开关M4的第二端(即图4中NMOS管M1的源极)接地。第一电流源IB1的第一端连接电源VDD端。第四电子开关M4的第一端还通过第二采样开关SW2连接放大电路41的一端；放大电路41的另一端用于连接光电二极管PD。
本实施例中，放大电路41可以是积分器中的放大电路，这有利于实现对该放大电路的复用。放大电路41可包括第二电流源IB2及第五电子开关MA。第五电子开关MA可由场效应晶体管或其它电子管构成，该场效应晶体管可以是PMOS管或NMOS管。图4中是以第五电子开关MA是NMOS管为例进行示意的。其中，第五电子开关MA的第一端(即图4中NMOS管MA的漏极)作为放大电路41的一端，分别连接第二电流源IB2及第二采样开关SW2；第五电子开关MA的第二端(即图4中NMOS管MA的源极)接地；第五电子开关MA的控制端(即图4中NMOS管MA的栅极)作为放大电路41的另一端，用于连接光电二极管PD。
当第一跨导放大器OTA1包括的若干个第一电子开关均为场效应晶体管时，可通过控制该若干个场效应晶体管的导通数量，来调节导通的场效应晶体 管的等效宽长比以及导通的场效应晶体管的等效输出阻抗，从而达到调节第一跨导放大器OTA1的跨导的目的，使电流采样保持电路在避免电容的电压U在较大范围内变化的前提下，可抵消更多的背景光电流，且使电流采样保持电路的稳定性不受光电二极管PD面积变化的影响。
下面将以该若干个第一电子开关均为PMOS管为例进行说明。具体地说，当该若干个第一电子开关均为PMOS管时，若干个PMOS管的宽长比应满足以下关系：当该若干个PMOS管沿朝向光电二极管PD的方向依次排列时，以该若干个PMOS管中的第一个PMOS管为最靠近光电二极管PD的PMOS管，最后一个PMOS管为最远离光电二极管PD的PMOS管。第一个PMOS管的宽长比与第二个PMOS管的宽长比相等，第i个PMOS管的宽长比为第i-1个PMOS管的宽长比的两倍，其中i大于或等于3。当第二电子开关M3也为PMOS管时，第二电子开关M3的宽长比可与第一个PMOS管的宽长比相等。即：PMOS管M7与PMOS管M6的宽长比相等：(W/L)M7＝(W/L)M6；PMOS管M5的宽长比是PMOS管M6的宽长比的2倍：(W/L)M5＝2(W/L)M6；PMOS管M4的宽长比是PMOS管M5的宽长比的2倍：(W/L)M4＝2(W/L)M5；第二电子开关M3与PMOS管M7的宽长比相等：(W/L)M3＝(W/L)M7。
值得一提的是，在实际应用中，为了覆盖更大的背景电流的覆盖范围(即覆盖更大的光电二极管的面积变化范围)，也可以在PMOS管M4与电源VDD端之间再串联一个或多个PMOS管(串联的数量可视实际情况而定)。例如，再串联一个PMOS管，则该PMOS管的宽长比应是PMOS管M4的宽长比的2倍。
在采样阶段，断开第三采样开关SW3，并闭合第一采样开关SW1及第二 采样开关SW2。此时，电流采样保持电路构成闭环负反馈。第一电流源IB1及第二电流源IB2向第四电子开关M1提供电流，第四电子开关M1上产生电压，从而向第三电子开关M2提供偏置电压。第三电子开关M2接收到偏置电压后产生电流，从而为第二电子开关M3提供偏置电流。第二电子开关M3接收到偏置电流后产生电压，从而向PMOS管M4、PMOS管M5、PMOS管M6及PMOS管M7的栅极提供偏置电压(即向若干个第一电子开关提供偏置电压)，触发PMOS管M4、PMOS管M5、PMOS管M6及PMOS管M7进入工作状态。此时，经PMOS管M4、PMOS管M5、PMOS管M6及PMOS管M7向光电二极管PD流入的电流与可变电流源IBG中的电流(即背景光电流)相等，电容CSH相当于采样了背景光电流，并将其转换为自身的电压。
在光强不变的情况下，当光电二极管PD的面积最小时，背景光电流也最小。此时可断开控制开关M8、M9及M10，使PMOS管M4、PMOS管M5、PMOS管M6、PMOS管M7都导通。此时，PMOS管M4、PMOS管M5、PMOS管M6、PMOS管M7的等效宽长比为W/(8L)，而第二电子开关M3的宽长比为W/L，即第二电子开关M3的宽长比为导通的PMOS管M4、PMOS管M5、PMOS管M6、PMOS管M7的等效宽长比的8倍。那么流过第二电子开关M3的电流IM3即为当前可变电流源IBG中的电流IBG(即背景光电流)的8倍，即IM3＝8IBG。当光电二极管PD的面积增加一倍时，可变电流源IBG中的电流也变为2IBG。此时，可断开控制开关M8、M9，并导通控制开关M10，使PMOS管M4被短路。此时，PMOS管M5、PMOS管M6、PMOS管M7导通，PMOS管M5、PMOS管M6、PMOS管M7的等效宽长比为W/(4L)，第二电子开关M3的宽长比则是导通的PMOS管M5、PMOS管M6、PMOS管M7的等效 宽长比的4倍，流过第二电子开关M3的电流IM3即为当前可变电流源IBG中的电流2IBG的4倍，即IM3＝8IBG。同理，当光电二极管PD的面积变为原来的4倍时，可变电流源IBG中的电流也变为4IBG，可断开控制开关M8、M10，并导通控制开关M9，使PMOS管M4、PMOS管M5被短路。此时，PMOS管M6、PMOS管M7导通，PMOS管M6、PMOS管M7的等效宽长比为W/(2L)。第二电子开关M3的宽长比是导通的PMOS管M6、PMOS管M7的等效宽长比的2倍，流过第二电子开关M3的电流IM3即为当前可变电流源IBG中的电流4IBG的2倍，即IM3＝8IBG。由此可见，不管光电二极管PD的面积如何变化，都可通过控制该若干个控制开关的导通与断开来改变导通的PMOS管的数量，从而调节导通的PMOS管等效宽长比，使得流过第二电子开关M3的电流IM3始终不变。
一方面，公式I＝(1/2)*ucox*(W/L)*(VGS-VTH)，其中I为光电二极管PD中的背景光电流，即可变电流源IBG中的电流IBG；ucox为参数不会改变；这里的(W/L)表示导通的PMOS管的等效宽长比；VGS为该若干个PMOS管的栅源电压，其大小等于电容CSH的电压U；VTH为若干个PMOS管的开启电压，不受光电二极管PD面积变化的影响。由以上公式可知，当光电二极管PD的面积发生变化时，I会随之发生变化，此时，通过改变导通的PMOS管的数量，使导通的PMOS管的等效宽长比(W/L)也发生变化，就可避免电容CSH的电压在较大范围内变化。特别地，若使等效宽长比(W/L)与电流I发生相同比例的变化，就可保持VGS不变，即使电容CSH的电压保持不变。
另一方面，在光电二极管的面积发生变化时，通过调节导通的PMOS管的等效宽长比，使得流过第二电子开关M3的电流IM3始终不变，会使电路中的 非主极点P2的位置保持不变。而电路中流过第四电子开关M1的电流是由第一电流源IB1及第二电流源IB2提供的，由于两者都是恒定电流源，因此，流过第四电子开关M1的电流IM1也不会改变，IM1不变，电路中的非主极点P3(对应第一电流源IB1的第二端、第四电子开关M1的第一端与控制端三者之间的节点)的位置就不会改变。也就是说电路中两个非主极点P2、P3的位置都不会变化。电路的增益带宽积的公式GBW＝gmA*K/CPD，其中，CPD即为光电二极管的寄生电容，K为导通的PMOS管的等效宽长比与第二电子开关M3的宽长比的比例；gmA为放大器MA的跨导，其不受光电二极管PD变化的影响。如上所述，当光电二极管PD的面积增大一倍时，CPD也会增大一倍。此时使PMOS管M4短路，并使PMOS管M5、PMOS管M6、PMOS管M7导通，PMOS管M5、PMOS管M6、PMOS管M7的等效沟道长度缩小一倍，这使导通的PMOS管的等效宽长比与第二电子开关M3的宽长比的比例K也变为原来的2倍，GBW保持不变。同样的，当光电二极管PD的面积增大4倍时，即CPD也会增大4倍，而此时使PMOS管M4被短路，PMOS管M5、PMOS管M6、PMOS管M7导通，导通的PMOS管的等效宽长比与第二电子开关M3的宽长比的比例K也变为原来的4倍，GBW仍保持不变。由此可见，在光电二极管PD的面积发生变化时，通过改变导通的PMOS管的数量，使导通的PMOS管的等效沟道长度与光电二极管PD的面积按相反的比例变化(等效输出阻抗与等效沟道长度成正比，所以这里也可以是使导通的PMOS管的等效输出阻抗与光电二极管PD的面积按相反的比例变化)，可使环路增益带宽积恒定不变。环路中的两个非主极点P2、P3的位置保持不变，环路增益带宽积也恒定不变，就可使环路的稳定性不受光电二极管PD面积变化的影响。
需要说明的是，在实际设计时，可根据最小的光电二极管PD的面积，设计最小的宽长比(如PMOS管M7的宽长比)。且设计时一般会留有一定的余量，比如，光电二极管PD的面积在0.5倍～1.5之间变化时，可选择1倍面积的档位便能支持(即认为光电二极管PD的面积增大1倍)；若光电二极管PD面积在1.5倍～2.5倍之间变化时，选择2倍面积的档位便能支持(即认为光电二极管PD的面积增大2倍)。
当采样阶段结束后，即可断开第一采样开关SW1及第二采样开关SW2，此时电路进入积分阶段。电容CSH上的电压转为电流(该电流的大小即等于之前采样的背景光电流的大小)，并通过导通的PMOS管输出给光电二极管PD，以抵消光电二极管PD中的背景光电流。
值得一提的是，本实施例提供了一种第一跨导放大器OTA1及第二跨导放大器OTA2的实现方式。但在实际应用中，也可直接选择常规的运算跨导放大器作为第一跨导放大器OTA1及第二跨导放大器OTA2，本实施方式对此不做限制。
本申请的第四实施例涉及一种传感器。该传感器可以为检测心率的传感顺路，具体地，该传感器上可集成有第一实施例、第二实施例或第三实施例所述的电流采样保持电路及光电二极管。其中，电流采样保持电路中的第一跨导放大器OTA1的另一端可连接光电二极管的阴极，光电二极管的阳极可接地。
另外，可选地，该传感器上还可集成有积分器，并将积分器中的放大电路作为实施例2中的偏置电路中的放大电路。这样，在采样阶段，闭合第一采样开关SW1，积分器中的放大电路作为电流采样保持电路中的一部分，与电流 采样保持电路的其他部分构成环路。在积分阶段，断开第一采样开关SW1后，该放大电路则作为积分器的一部分进行工作。这有利于实现对积分器的放大电路的复用。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (10)

  1. 一种电流采样保持电路，用于抵消光电二极管中的背景光电流，其特征在于，包括：电容及向所述光电二极管输出采样电流以抵消光电二极管中的背景光电流的跨导可调节的第一跨导放大器；
    所述电容的一端连接电源VDD端，所述电容的另一端连接所述第一跨导放大器的一端；所述第一跨导放大器的另一端用于连接光电二极管，以向所述光电二极管输出所述采样电流。
  2. 根据权利要求1所述的电流采样保持电路，其特征在于，所述第一跨导放大器包括若干个第一电子开关及若干个用于控制所述第一电子开关的控制开关；
    所述若干个第一电子开关连接在所述电源VDD端及所述光电二极管之间，且所述若干个第一电子开关之间相互串联，所述若干个第一电子开关的控制端均连接所述电容的另一端；
    任意两个相邻的所述第一电子开关的连接点对应一个所述控制开关，每个所述控制开关的一端连接所述电源VDD端，每个所述控制开关的另一端连接对应的所述连接点。
  3. 根据权利要求1或2所述的电流采样保持电路，其特征在于，所述电流采样保持电路还包括第一采样开关及用于向所述第一跨导放大器提供偏置电压的偏置电路；
    所述偏置电路的第一端通过所述第一采样开关同时连接所述第一跨导放大器的一端及所述电容的另一端；所述偏置电路的第二端连接所述电源VDD端；所述偏置电路的第三端用于连接所述光电二极管。
  4. 根据权利要求3所述的电流采样保持电路，其特征在于，所述偏置电路包括第二电子开关及第二跨导放大器；
    所述第二电子开关的第一端作为所述偏置电路的第二端连接所述电源VDD端；所述第二电子开关的第二端连接所述第二跨导放大器的一端；所述第二电子开关的控制端作为所述偏置电路的第一端连接所述第一采样开关，以及所述第二电子开关的第二端与所述第二跨导放大器的一端之间的连接点；所述第二跨导放大器的另一端作为所述偏置电路的第三端用于连接所述光电二极管。
  5. 根据权利要求4所述的电流采样保持电路，其特征在于，所述第二跨导放大器包括第二采样开关、放大电路、第一电流源、第三电子开关及第四电子开关；
    所述第三电子开关的第一端连接所述第二电子开关的第二端；所述第三电子开关的第二端接地；所述第三电子开关的控制端连接所述第一电流源的第二端与所述第四电子开关的第一端之间的连接点，以及所述第四电子开关的控制端；所述第一电流源的第一端连接所述电源VDD端；
    所述第四电子开关的第一端还通过所述第二采样开关连接所述放大电路的一端；所述第四电子开关的第二端接地；所述放大电路的另一端用于连接所述 光电二极管。
  6. 根据权利要求5所述的电流采样保持电路，其特征在于，所述放大电路包括第二电流源及第五电子开关；
    所述第五电子开关的第一端作为所述放大电路的一端，分别连接所述第二二电流源及所述第二采样开关；所述第五电子开关的第二端接地；所述第五电子开关的控制端作为所述放大电路的另一端，用于连接所述光电二极管。
  7. 根据权利要求4所述的电流采样保持电路，其特征在于，所述第一电子开关为PMOS管；若干个所述PMOS管沿朝向所述光电二极管的方向依次排列；
    若干个所述PMOS管中的第一个PMOS管为最靠近所述光电二极管的PMOS管，最后一个PMOS管为最远离所述光电二极管的PMOS管；所述第一个PMOS管的宽长比与第二个PMOS管的宽长比相等，第i个PMOS管的宽长比为第i-1个PMOS管的宽长比的两倍，所述i大于或等于3。
  8. 根据权利要求7所述的电流采样保持电路，其特征在于，所述第二电子开关为PMOS管，且所述第二电子开关的宽长比与所述第一个PMOS管的宽长比相等。
  9. 根据权利要求1所述的电流采样保持电路，其特征在于，所述电流采样保持电路还包括第三采样开关；所述第三采样开关并联在所述电容的两端。
  10. 一种传感器，其特征在于，所述传感器包括光电二极管及如权利要求1至9任意一项所述的电流采样保持电路；
    所述电流采样保持电路中的第一跨导放大器的另一端连接所述光电二极管。
PCT/CN2017/116831 2017-12-18 2017-12-18 一种电流采样保持电路及传感器 WO2019119176A1 (zh)

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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0046396A1 (en) * 1980-08-20 1982-02-24 Hitachi, Ltd. Solid state image pickup device
CN201215954Y (zh) * 2008-07-14 2009-04-01 深圳新飞通光电子技术有限公司 一种数字光接收器的光功率检测监控电路
CN102353395A (zh) * 2011-06-26 2012-02-15 西安电子科技大学 抑制环境噪声的红外接近传感器
CN104359455A (zh) * 2014-12-03 2015-02-18 张石 基于背景噪声消除的光电二极管电路及激光测距系统
CN106535753A (zh) * 2014-07-23 2017-03-22 深圳市汇顶科技股份有限公司 光学心率传感器
CN106599754A (zh) * 2017-01-16 2017-04-26 深圳市傲科微创有限公司 一种lid读写器及其跨阻放大电路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5852374A (en) * 1997-05-16 1998-12-22 Texas Instruments Incorporated Resettable latched voltage comparator
US6445321B2 (en) * 1999-04-05 2002-09-03 Sonic Innovations, Inc. Hybrid low-pass sigma-delta modulator
US7970811B2 (en) * 2003-04-04 2011-06-28 Shen David H Continuous-time multi-gigahertz filter using transmission line delay elements
EP2075909A3 (en) * 2007-12-26 2016-10-12 TPO Displays Corp. Current sampling method and circuit
CN103359445A (zh) 2012-04-05 2013-10-23 软控股份有限公司 一种顺料筒及其制造方法
US8907669B2 (en) * 2012-07-24 2014-12-09 Allegro Microsystems, Llc Circuits and techniques for adjusting a sensitivity of a closed-loop current sensor
US9880266B2 (en) * 2015-07-31 2018-01-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Measurement system incorporating ambient light component nullification
CN106788276B (zh) * 2015-12-29 2020-03-13 深圳市汇顶科技股份有限公司 转换电路及检测电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0046396A1 (en) * 1980-08-20 1982-02-24 Hitachi, Ltd. Solid state image pickup device
CN201215954Y (zh) * 2008-07-14 2009-04-01 深圳新飞通光电子技术有限公司 一种数字光接收器的光功率检测监控电路
CN102353395A (zh) * 2011-06-26 2012-02-15 西安电子科技大学 抑制环境噪声的红外接近传感器
CN106535753A (zh) * 2014-07-23 2017-03-22 深圳市汇顶科技股份有限公司 光学心率传感器
CN104359455A (zh) * 2014-12-03 2015-02-18 张石 基于背景噪声消除的光电二极管电路及激光测距系统
CN106599754A (zh) * 2017-01-16 2017-04-26 深圳市傲科微创有限公司 一种lid读写器及其跨阻放大电路

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