WO2019101044A1 - 一种降低读延时的方法及装置 - Google Patents

一种降低读延时的方法及装置 Download PDF

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Publication number
WO2019101044A1
WO2019101044A1 PCT/CN2018/116257 CN2018116257W WO2019101044A1 WO 2019101044 A1 WO2019101044 A1 WO 2019101044A1 CN 2018116257 W CN2018116257 W CN 2018116257W WO 2019101044 A1 WO2019101044 A1 WO 2019101044A1
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Prior art keywords
read voltage
storage area
read
controller
management information
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PCT/CN2018/116257
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English (en)
French (fr)
Inventor
贾学超
玄在雄
夏天
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华为技术有限公司
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Priority to KR1020207017575A priority Critical patent/KR102374239B1/ko
Priority to EP18880718.4A priority patent/EP3702897A4/en
Publication of WO2019101044A1 publication Critical patent/WO2019101044A1/zh
Priority to US16/884,158 priority patent/US11210210B2/en

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Definitions

  • the embodiments of the present invention relate to the field of data storage technologies, and in particular, to a method and an apparatus for reducing a read delay. .
  • SSD Solid State Drive
  • the quality of service (QoS) of the SSD is that the SSD product provides stable and consistent to the host.
  • QoS quality of service
  • the ability to predictively respond to a service is one of the key factors shaping the competitiveness of SSD products.
  • SSD can be applied to scenarios such as data centers and servers.
  • Read Latency is a key performance indicator of QoS, mainly depending on the number of read operations occurring in the Flash media in response to host IO requests. Flash is the main storage medium of SSD. Its characteristics are affected by many factors such as Program/Erase Cycles (PE) and Retention Time. The voltage signal carrying data will be transmitted and drifted.
  • PE Program/Erase Cycles
  • the secondary read operation can successfully respond to the host IO request, thus causing a long read latency in QoS.
  • the read delay can be reduced by the read voltage pre-tabulation technique, that is, by analyzing the relationship between the factors affecting the read voltage and the voltage offset, the influencing factors and the read voltage compensation table are produced or the specific method is summarized by the fitting method.
  • the formula is used to compensate the read voltage according to the influence factor value table or calculation, thereby improving the first reading success rate and thus reducing the read delay.
  • the read voltage pre-tabulation technique is related to the sampled samples, and different read voltage prefabrication tables are required for different storage media, and the workload is large.
  • the storage medium will change during use, the reliability of using the read voltage pre-tabulation technology is low, and the improvement of the first read success rate is limited, so the effect of reducing the read delay is not good.
  • Embodiments of the present application provide a method and apparatus for reducing read latency, which solves the problem of long read delay in the prior art.
  • the first aspect provides a method for reducing read latency, which is applied to a controller, where a front end of the controller is connected to the host, and a back end is connected to the flash array.
  • the method includes: the controller receives a read request sent by the host, and the read request is in the read request. And including, by the first physical location indicated by the location indication information, a read voltage corresponding to the first storage area where the first physical location is located, where the first physical location is obtained by the controller;
  • the location is the physical location of the request data in the Flash array, and the Flash array includes a plurality of storage areas, and the physical characteristics of the plurality of physical locations included in the same storage area are the same or similar, and the read voltage management information includes the storage area and the read voltage.
  • the correspondence between the read voltage management information is dynamically updated; the controller acquires the request data according to the read voltage corresponding to the first storage area, and sends the request data to the host.
  • the read voltage acquired by the controller can be ensured.
  • the accuracy, based on the read voltage to obtain the request data can improve the first read success rate, reduce the number of read operations, and thus reduce the read latency.
  • the read voltage characteristics of the physical locations included in the same storage area are the same or similar; and/or the physical characteristics of the physical locations included in the different storage areas are different; and/or different The read voltage characteristics of the physical locations contained in the memory area are different.
  • the memory in the controller can be saved. s expenses.
  • the method further includes: when the preset update condition is met, the controller updates the storage area corresponding to the read voltage management information Read voltage.
  • the controller updates the storage area corresponding to the read voltage management information Read voltage.
  • the read voltage in the read voltage management information is dynamically updated, including: when the preset update condition is met, the controller updates the read voltage corresponding to the storage region in the read voltage management information
  • the controller includes: when the system idle time window or the preset update period is met, the controller determines a first error parameter under the read voltage corresponding to the storage area; when the first error parameter is greater than or equal to the first threshold, the controller updates the read The read voltage corresponding to the storage area in the voltage management information.
  • the controller can ensure that the read voltage is valid in real time by actively updating the read voltage in the read voltage management information, so that the success rate when the read data is acquired by the read voltage is higher, thereby reducing the success rate. Read delay.
  • the preset update period is related to the usage state of the storage area; or the preset update period is related to an average service life of the plurality of storage areas included in the Flash array.
  • the controller when the preset update condition is met, updates the read voltage corresponding to the storage area in the read voltage management information, including: when the read voltage corresponding to the storage area is read for the first time When the second error parameter of the fetched request data is greater than or equal to the first threshold, the controller updates the read voltage corresponding to the storage region in the read voltage management information.
  • the controller reads the read voltage in the voltage management information through passive dynamic update, and can quickly and effectively update the read voltage after the first read data failure of the read voltage, thereby reducing the number of read operations, thereby reducing the read delay. Time.
  • the controller when the controller updates the read voltage corresponding to the storage area in the read voltage management in the first time period, at the second time When the read voltage corresponding to the storage area is obtained from the read voltage management in the segment, there is no overlap between the first time period and the second time period; and/or, for any two of the plurality of storage areas, when the controller is The first time period and the second time period exist when the read voltage corresponding to one storage area in the read voltage management is updated in the third time period, and the read voltage corresponding to another storage area is acquired from the read voltage management in the fourth time period Overlap, or the first time period does not overlap with the second time period.
  • the controller can perform different operations on the read voltage management information in different time periods, thereby saving time for managing the read voltage management information and improving system performance.
  • a storage area includes at least one storage unit, and the storage unit includes at least one of the following: a granular device, a logical unit Die, a face Plane, a block block, a super block super block, Layer Layer, Sub-Block, Word Line WL, and Page Page.
  • the controller can reduce the data amount of the read voltage management information by reasonably dividing the storage area, thereby saving the memory overhead in the controller.
  • a controller configured to be connected to the host, and the back end is connected to the Flash array.
  • the controller includes: a receiving unit, configured to receive a read request sent by the host, where the read request includes a location indication of the requested data.
  • a processing unit configured to acquire, according to the first physical location indicated by the location indication information, a read voltage corresponding to the first storage region where the first physical location is located, where the first physical location is the Requesting the physical location of the data stored in the Flash array.
  • the Flash array includes a plurality of storage areas. The physical characteristics of the plurality of physical locations included in the same storage area are the same or similar, and the read voltage management information includes the storage area and the read voltage. Corresponding relationship, the read voltage in the read voltage management information is dynamically updated; the processing unit is further configured to acquire the request data according to the read voltage corresponding to the first storage area; and the sending unit is configured to send the request data to the host.
  • the read voltage characteristics of the physical locations included in the same storage area are the same or similar; and/or the physical characteristics of the physical locations included in the different storage areas are different; and/or different The read voltage characteristics of the physical locations contained in the memory area are different.
  • the processing unit is configured to, for any one of the plurality of storage areas, update the storage area corresponding to the read voltage management information when the preset update condition is met.
  • the voltage is read so that the read voltage in the read voltage management information is dynamically updated.
  • the processing unit is further configured to determine, when the system idle time window or the preset update period is satisfied, the first error parameter under the read voltage corresponding to the storage area; When an error parameter is greater than or equal to the first threshold, the read voltage corresponding to the storage region in the read voltage management information is updated.
  • the preset update period is related to the usage state of the storage area; or the preset update period is related to an average service life of the plurality of storage areas included in the Flash array.
  • the processing unit is further configured to: when the second error parameter of the first read request data is greater than or equal to the first threshold, when the read voltage corresponding to the storage area is The read voltage corresponding to the storage area in the voltage management information is read.
  • the second aspect for any one of the plurality of storage areas, when the read voltage corresponding to the storage area in the read voltage management is updated in the first time period, in the second time period When the read voltage corresponding to the storage area is obtained from the read voltage management, there is no overlap between the first time period and the second time period; and/or, for any two of the plurality of storage areas, when in the third time period When the read voltage corresponding to one storage area in the read voltage management is updated, and the read voltage corresponding to another storage area is acquired from the read voltage management in the fourth time period, the first time period overlaps with the second time period, or A period of time does not overlap with the second period of time.
  • a storage area includes at least one storage unit, and the storage unit includes at least one of the following: a granular device, a logical unit Die, a face Plane, a block block, a super block super block, Layer Layer, Sub-Block, Word Line WL, and Page Page.
  • a system in a third aspect, includes a host, a controller, and a flash array.
  • the flash array includes multiple storage areas, and physical attributes of multiple physical locations included in the same storage area are the same or similar; And configured to send a read request to the controller, and receive request data returned by the controller, the read request includes location indication information of the request data, a controller for managing read voltage management information, and the read voltage management information includes a storage area and a read voltage Corresponding relationship, the read voltage in the read voltage management information is dynamically updated; the controller is further configured to: when receiving the read request, according to the first physical location indicated by the location indication information, the read voltage management Obtaining, in the information, a read voltage corresponding to the first storage area where the first physical location is located, where the first physical location is a physical location of the request data stored in the Flash array; and the controller is further configured to use the read voltage corresponding to the first storage area , get the request data, and send the request data to the host.
  • the read voltage characteristics of the physical locations included in the same storage area are the same or similar; and/or the physical characteristics of the physical locations included in the different storage areas are different; and/or different The read voltage characteristics of the physical locations contained in the memory area are different.
  • the controller is specifically configured to, for any one of the plurality of storage areas, update the storage area corresponding to the read voltage management information when the preset update condition is met.
  • the voltage is read so that the read voltage in the read voltage management information is dynamically updated.
  • the controller is configured to determine, when the system idle time window or the preset update period is met, the first error parameter under the read voltage corresponding to the storage area; When an error parameter is greater than or equal to the first threshold, the read voltage corresponding to the storage region in the read voltage management information is updated.
  • the preset update period is related to the usage state of the storage area; or the preset update period is related to an average service life of the plurality of storage areas in the Flash array.
  • the controller is configured to: when the second error parameter of the first read request data is greater than or equal to the first threshold, when the read voltage corresponding to the storage area is greater than or equal to the first threshold The read voltage corresponding to the storage area in the voltage management information is read.
  • the controller updates the read voltage corresponding to the storage area in the read voltage management in the first time period, at the second time
  • the controller updates the read voltage corresponding to the storage area in the read voltage management in the first time period, at the second time
  • the controller is The first time period and the second time period exist when the read voltage corresponding to one storage area in the read voltage management is updated in the third time period, and the read voltage corresponding to another storage area is acquired from the read voltage management in the fourth time period Overlap, or the first time period does not overlap with the second time period.
  • a storage area includes at least one storage unit, and the storage unit includes at least one of the following: a granular device, a logical unit Die, a face Plane, a block block, a super block super block, Layer Layer, Sub-Block, Word Line WL, and Page page.
  • a still further aspect of the present application provides a computer readable storage medium having stored therein instructions that, when executed on a computer, cause the computer to perform the first aspect or the first aspect described above
  • a method of reducing read latency provided by any of the possible implementations.
  • a computer program product comprising instructions which, when run on a computer, cause the computer to perform the reduction provided by any of the above first aspect or any of the possible implementations of the first aspect The method of reading the delay.
  • any of the above-mentioned methods, computer storage media or computer program products for reducing the read delay method are used to perform the corresponding methods provided above, and therefore, the beneficial effects that can be achieved can be referred to.
  • the beneficial effects in the corresponding methods provided above are not described herein again.
  • FIG. 1 is a schematic structural diagram of a storage particle according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a communication system according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another communication system according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic flowchart of a method for reducing a read delay according to an embodiment of the present application
  • FIG. 5 is a schematic flowchart of another method for reducing read latency according to an embodiment of the present disclosure
  • FIG. 6 is a schematic flowchart of updating read voltage management information according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart of another method for updating read voltage management information according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart of processing a read request according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of operation of reading voltage management information according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a controller according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another controller according to an embodiment of the present application.
  • SSD Solid State Drive
  • QoS Quality of Service
  • HDR Quality of Service
  • Flash media is the main storage medium of SSD, and its characteristics are affected by various factors such as Program/Erase Cycles (PE), Retention Time, and Read Counts.
  • PE Program/Erase Cycles
  • the voltage signal will transmit drift, so the back end needs multiple read operations (trial and error) to successfully respond to the host IO request, thus affecting the QoS read latency indicator, resulting in a longer read latency.
  • FIG. 1 it is a hierarchical structure diagram of an internal particle provided by an embodiment of the present application.
  • the smallest unit of the write operation is the page, and the page can be divided into three types, namely, the Upper Page, the Middle Page, and the Lower Page.
  • a top page, a middle page, and a lower page can form a word line (Word Line, WL), and several WLs form a layer or a sub-block in different directions.
  • WL word line
  • Multiple WLs form a Layer, and multiple WLs in the vertical form a Sub-Block.
  • the minimum erase operation unit composed of Page is called a block.
  • Multiple blocks form a plane, and multiple planes can form a logical unit (Die).
  • Multiple Dies make up a Device, and each Device corresponds to a Channel.
  • the controller will make some blocks into a Super Block.
  • the feature of Super Block in the application is that the internal block will be erased at the same time or programmed at the same time.
  • the state of the use condition of the Block inside the Super Block is consistent or close, for example, the number of times of erasing (Program/Erase Cycles, PE) ), and data retention time (Retention Time).
  • the 3D TLC increases the logic state in each cell from 4 (2bits) to 8 (3bits).
  • the voltage signal window that distinguishes different logic states becomes smaller, so the accuracy of the read voltage is required. Upgrade.
  • the number of pages in the Block and the number of blocks in the Die gradually increase, and the physical inconsistency of each level in the Flash increases, and it becomes more and more difficult to set a uniform effective read voltage for all Pages.
  • the embodiment of the present application provides a method and apparatus for reducing read latency, which is used to improve read latency indicators in QoS.
  • the system includes a host, an SSD controller, and a Flash array.
  • the host can store/take data in the Flash array through the SSD controller.
  • the host can be connected to the front end of the SSD controller through various interfaces such as NVMe/SAS/PCIe.
  • the back end of the SSD controller can be connected to the Flash array through the NFI, and the host reads and writes data in the Flash array through the SSD controller. Or erase and other operations.
  • FIG. 3 it is a hardware architecture diagram of another communication system applied in the embodiment of the present application.
  • the controller in this system is similar to the SSD controller in the system shown in Figure 2.
  • the controller in the system is packaged into a separate chip from the Flash array, and the host is connected to the controller through an interface such as UFS/eMMC, and accesses data through the interface.
  • the chip packaged by the controller and the flash array can be applied to mobile terminals such as mobile phones, tablets, wearable devices, and the like.
  • FIG. 4 is a schematic flowchart of a method for reducing read latency according to an embodiment of the present disclosure. The method can be applied to the communication system shown in FIG. 2 or FIG. 3, and FIG. 4 includes the following steps. .
  • Step 401 The controller receives a read request sent by the host, where the read request includes location indication information of the request data.
  • the host may send a read request to the controller, and the data requested by the read request may be referred to as request data, and the location may be carried in the read request.
  • the location indication information may be used to indicate a logical address, that is, a logical address used by the host to access the requested data, and the logical address has a mapping relationship with the physical address, and the request data may be determined in the Flash array according to the logical address of the request data. Physical location.
  • the location indication information may also be other information that has a corresponding relationship with the physical location.
  • the location indication information may be a key value, and the corresponding relationship between the key value and the Value value is obtained.
  • the Value value which may be the physical location of the data, is not limited in this embodiment of the present application.
  • the controller may acquire the physical address of the request data stored in the flash array according to the location indication information, where the physical address of the request data is referred to as the first physical location.
  • Step 402 The controller acquires, from the read voltage management information, a read voltage corresponding to the first storage area where the first physical location is located.
  • the flash array includes a plurality of storage areas, and the physical characteristics of the plurality of physical locations included in the same storage area are the same or similar, and the read voltage management information includes a correspondence between the storage area and the read voltage, where the read voltage management information is The read voltage is dynamically updated.
  • Each of the plurality of storage areas may include at least one storage unit, each storage unit may be represented by a corresponding physical location, and the plurality of physical locations included in one storage area may be at least one storage unit included therein Corresponding physical location.
  • the physical characteristics of the plurality of physical locations included in the same storage area are the same or similar, that is, the physical characteristics of the storage units included in the same storage area are the same or similar.
  • the physical characteristics of multiple physical locations included in different storage areas are different, that is, the physical characteristics of the storage units included in different storage areas are different.
  • the physical characteristics of the memory cell herein may include aspects such as nano-scale geometry, electrical properties of the material, structure of the memory cell combination, and internal control circuitry and the like.
  • the physical characteristics of the two storage units being the same or similar means that the physical characteristics of the two storage units are small, for example, a corresponding parameter of the physical characteristics is less than a set threshold, or a physical characteristic thereof. If the corresponding multiple parameters are smaller than the corresponding set thresholds, it is determined that the difference in physical characteristics is small.
  • the physical characteristics of the two storage units are different.
  • the physical characteristics of the two storage units are different. For example, the corresponding parameter of the physical characteristic is greater than the set threshold, or multiple parameters corresponding to the physical characteristics are greater than the corresponding parameters. Set the threshold to determine that the difference in physical properties is small.
  • the physical characteristics of the memory cell are related to the read voltage characteristics corresponding to the memory cell, and the read voltage refers to the corresponding conversion voltage when converting from the analog signal to the data signal, and the read voltage characteristic may refer to different conditions (eg, different temperatures, different Time, different PE, different data retention time, different read counts (Read Counts), when using different devices to read the read voltage, the corresponding error parameters change.
  • the difference between the read voltage characteristics corresponding to the plurality of memory cells having the same or similar physical characteristics is small, and the difference between the read voltage characteristics corresponding to the plurality of memory cells having different physical properties is large.
  • the difference in read voltage characteristics corresponding to the memory cells included in the same memory region is small, so that one memory region can correspond to one read voltage.
  • the physical characteristics of the memory cells included in different memory regions are different, and the difference in read voltage characteristics corresponding to the memory cells included in the different memory regions is large, so that different memory regions may correspond to different read voltages.
  • the read voltage characteristics of the memory cells included in the same storage area are the same or similar, and the read voltage characteristics of the memory cells included in the different memory areas are different.
  • the plurality of memory cells may belong in the same memory region; when the read voltage characteristics of the plurality of memory cells are different That is, when the difference in read voltage characteristics of the plurality of memory cells is large, the plurality of memory cells may belong to different memory regions.
  • the method of determining that the difference in read voltage characteristics is small and large can be similar to the method of determining that the difference in physical characteristics is small or large. In the embodiment of the present application, by dividing a plurality of physical locations having the same or similar physical characteristics and the same or similar read voltage characteristics in the same storage area, corresponding to one read voltage, system overhead can be saved.
  • the read voltage management information may include a correspondence between each of the memory regions and the read voltage.
  • the read voltage included in the read voltage management information is dynamically updated, that is, the read voltage corresponding to each storage area in the read voltage management information is refreshed in time to ensure the accuracy of the read voltage corresponding to each storage area.
  • the controller may determine, according to the first physical location included in the read request, a storage area where the first physical location is located in the multiple storage areas, where the physical location is located It is called the first storage area.
  • the controller acquires a read voltage corresponding to the first storage area from a correspondence relationship between the storage area and the read voltage included in the dynamically updated read voltage management information according to the first storage area, and the acquired read voltage has good accuracy. Thereby, the success rate when reading data from the first storage area with the read voltage is high.
  • the controller selects whether to acquire the read voltage by reading the voltage management information according to a specific read request policy.
  • the read voltage is selected by reading the voltage management information according to the specific read request policy (ie, YES is selected)
  • the corresponding read voltage is acquired according to the above step 402.
  • the specific read request policy may be set in advance. For different read requests, different read request policies may be set, and the same read request policy may be set, which is not specifically limited in this embodiment of the present application.
  • the Flash array may include multiple Devices, and the internal structure of each Device may be as shown in FIG. 1.
  • the storage unit can include at least one of the following: a device, a logical unit (Die), a plane (Plane), a block (Block), Super Block, Layer, Sub-Block, Word Line (WL), and Page. That is, the partition granularity when the Flash array is divided into a plurality of storage areas may include at least one of the above.
  • the partitioning granularity when the partitioning granularity includes a Device, at least one Device may be included in one storage area.
  • the partitioning granularity includes Die at least one Die may be included in one storage area.
  • the partitioning granularity includes Plane at least one Plane may be included in one storage area.
  • the partitioning granularity includes a block at least one block may be included in one storage area.
  • the partitioning granularity includes a Super Block
  • at least one Super Block may be included in one storage area.
  • the partitioning granularity includes a Layer at least one Layer may be included in one storage area.
  • the partitioning granularity includes a Sub-Block at least one Sub-Block may be included in one storage area.
  • the partitioning granularity includes WL at least one WL may be included in one storage area.
  • the partitioning granularity includes Page at least one Page may be included in one storage area.
  • the usage conditions of each block in the Flash array are generally different, so that different blocks can be located in different storage areas.
  • the read voltage characteristic of the internal page of the block is related to the physical position of the page in the block. Therefore, the pages having the same or similar read voltage characteristics can be divided into the same storage area, which is not specifically limited in the embodiment of the present application.
  • Step 403 The controller acquires the request data according to the read voltage corresponding to the first storage area, and sends the request data to the host.
  • the controller may acquire the request data stored at the first physical location from the first storage area according to the read voltage corresponding to the first storage area when the controller acquires the read voltage corresponding to the first storage area. Thereafter, the controller can send the request data to the host so that the host can receive the request data.
  • the controller when the controller receives the read request sent by the host, the controller may select the storage area and the read voltage included in the read voltage management information according to the first physical location indicated by the location indication information included in the read request.
  • the read voltage corresponding to the first storage area where the first physical location is located is obtained, and the physical characteristics and the read voltage characteristics of the plurality of physical locations included in the first storage area are the same or similar, and the read voltage management information is The read voltage is dynamically updated, so that the accuracy of the read voltage can be ensured.
  • the request data is acquired based on the read voltage, the first read success rate can be improved, the number of read operations can be reduced, and the read delay can be reduced.
  • the read voltage in the read voltage management information is dynamically updated, and may include step 404: for any one of the plurality of storage areas, when the preset condition is met, the controller updates the read voltage management.
  • Step 404 and step 401 - step 403 may be in no particular order.
  • the controller can determine the effective read voltage corresponding to the storage area by using a specific online read voltage optimization algorithm, and update the read corresponding to the storage area in the read voltage management information according to the valid read voltage. Voltage.
  • the controller dynamically updates the read voltage corresponding to the storage area in the read voltage management information
  • the controller may actively update the read voltage corresponding to the storage area, or may passively update the read voltage corresponding to the storage area. Actively updating the read voltage in the read voltage management information, or the updated read voltage in the passive read voltage management information, ensures that the read voltage in the read voltage management information is dynamically updated. The two methods are described in detail below.
  • the first type the controller actively updates the read voltage corresponding to the storage area, and specifically includes: when the controller is in the system idle time window or meets the preset update period, the controller determines the read voltage corresponding to the storage area. An error parameter; when the first error parameter is greater than or equal to the first threshold, the controller updates the read voltage corresponding to the storage region in the read voltage management information.
  • the controller in the system idle time window may mean that the controller is in an idle state, and the idle state may be understood as the controller's read/write IO load is lower than a certain value, so that the controller is relatively idle.
  • the preset update period may be set in advance, and the preset update period may include one period or may include a plurality of different periods.
  • the setting of the preset update period corresponding to one storage area may be related to the usage status of the storage area (for example, the number of PE times and the number of read operations), or related to the average service life of the plurality of storage areas included in the Flash array. For example, the average lifetime of multiple storage areas can be represented by the average PE. When the average PE is large (for example, early life), a larger preset update period can be used, when the average PE is smaller (for example, the end of life). A smaller preset update period can be used.
  • the first error parameter may be used to indicate the degree of error in the read data, and the first error parameter may be the number of error bits or the bit error rate RBER.
  • the first threshold may be a fault tolerance threshold set in advance. If the first error parameter is smaller than the first threshold, it indicates that it is within the fault tolerance range. If the first error parameter is greater than or equal to the first threshold, it indicates that it is not within the fault tolerance range.
  • the controller when the controller is in the system idle time window or meets the preset update period, the controller reads the read voltage corresponding to the storage area currently stored in the read voltage management information as the detected read voltage, according to the detected read voltage. And sampling the physical location included in the storage area, and acquiring the error parameter under the detected read voltage as the first error parameter. If the first error parameter is less than the first threshold, the controller may determine that the read voltage corresponding to the storage area is valid so as not to update it. If the first error parameter is greater than or equal to the first threshold, the controller may determine that the read voltage corresponding to the storage area is invalid and needs to be updated.
  • the controller may determine the current effective read voltage by an attempted method. For example, the controller may test the error parameters of the multiple voltages according to the stepwise increasing or decreasing voltage. The read voltage with the smallest error parameter is determined as the current valid read voltage, so that the read voltage corresponding to the storage region in the read voltage management information is replaced with the current effective read voltage to implement the update of the read voltage corresponding to the storage region. .
  • the controller actively updates the read voltage in the read voltage management information in each system idle time window, or actively in each preset update period.
  • the read voltage in the read voltage management information is updated, so that the read voltage in the read voltage management information is updated once every once. Therefore, actively updating the read voltage in the read voltage management information can cause the read voltage in the read voltage management information to be in a dynamically updated state, thereby ensuring that the read voltage in the read voltage management information is real-time valid.
  • the trigger when the controller is actively triggered to update the read voltage corresponding to the storage area by the preset update period, the trigger may be triggered by a timer interrupt.
  • the controller can also be used to trigger the controller to actively update the read voltage corresponding to the storage area.
  • the specific forced signal can be set in advance, which is not limited in this embodiment of the present application.
  • the second type the controller passively updates the read voltage corresponding to the storage area, and specifically includes: when the second error parameter of the first read request data is greater than or equal to the first threshold when the read voltage corresponding to the storage area is The controller updates the read voltage corresponding to the storage area in the read voltage management information.
  • the request data read for the first time refers to the request data read by the controller from the storage area for the first time according to the read voltage corresponding to the storage area in the read voltage management, and the request data is based on the read request sent by the host.
  • the acquired data is not the data that the controller actively takes to sample.
  • the controller reads the request data from the storage area for the first time under the read voltage corresponding to the storage area, and the error parameter of the read request data is the second error parameter. If the second error parameter is less than the first threshold, the controller may determine that the read voltage corresponding to the storage area is valid so as not to update it. If the second error parameter is greater than or equal to the first threshold, the controller may determine that the read voltage corresponding to the storage area is invalid and needs to be updated.
  • the controller when the controller updates the read voltage corresponding to the storage area (that is, obtains the current effective read voltage), the controller may also update according to the voltage gradually increasing or decreasing, and the specific implementation process and the first manner The descriptions are consistent, and the embodiments of the present application are not described herein again.
  • the controller may first determine the storage area in which the read voltage is invalid, and then the controller may only invalidate the read voltage in the read voltage management information.
  • the read voltage of the storage area is updated.
  • the controller when updating the read voltage corresponding to the storage area in the read voltage management information, the controller first determines whether the read voltage corresponding to the storage area stored in the read voltage management information is valid, and determines that it is invalid. Updates are made to avoid unnecessary operations, which saves system bandwidth and load overhead.
  • the controller updates the read voltage in the read voltage management information to the current effective read voltage, thereby reading the voltage during each period of time.
  • the controller updates the one or more read voltages. Therefore, passively updating the read voltage in the read voltage management information can cause the read voltage in the read voltage management information to be in a dynamically updated state, thereby ensuring that the read voltage in the read voltage management information is real-time valid.
  • FIG. 6 is a flow chart of a controller actively updating read voltage management information, taking the controller in a system idle time window as an example. Specifically, if all the read voltages in the read voltage management information need to be updated, when the controller is in the system idle time window, the controller may determine the corresponding error parameter under each read voltage in the read voltage management information, and determine the read voltage.
  • the read voltage that needs to be updated in the management information (for example, when the corresponding error parameter is less than the first threshold, it is determined that the update is not required, and when the corresponding error parameter is greater than or equal to the first threshold, it is determined that the update is required), thereby obtaining
  • the read voltage record information i.e., the read record in which the read voltage is invalid in the read voltage management information
  • the controller updates the read voltage record information by a method of reading the voltage update (for example, the method provided in the above step 404).
  • Figure 7 is a flow diagram of a controller passively updating read voltage management information. Specifically, the controller receives the read request sent by the host, and obtains a corresponding read voltage from the read voltage management information according to the physical location information included in the read request (ie, responds to the read request by reading the voltage management information), and acquires the first time based on the read voltage.
  • the request data data fails (ie, the first read data fails)
  • the read voltage in the read voltage management information is marked as an invalid read voltage; thereafter, the error recovery process (ie, updating the invalid read voltage) or the end is entered.
  • the step of the controller determining the read voltage that is invalid in the read voltage management information and the step of updating the read voltage that is invalid in the read voltage management information may be performed synchronously or asynchronously. That is, the controller may first determine all invalid read voltages in the read voltage management information, and then update all invalid read voltages one by one; or, after each undetermined read voltage in the read voltage management information is determined by the controller, That is, the invalid read voltage is updated, then the next invalid read voltage is determined to be updated, and so on; or, the controller determines the invalid read voltage in the read voltage management information while reading the determined invalid read.
  • the voltage is updated, which is not specifically limited in this embodiment of the present application.
  • the controller when the controller updates the read voltage management information, if the read voltage management information resides in a fast storage medium such as a memory, it needs to be backed up in a non-volatile storage medium, and when the system is initialized, The read voltage management information is initialized from the non-volatile storage medium into the fast storage medium.
  • the controller stores the read voltage management information directly in a storage medium having both fast access and non-volatile characteristics.
  • the controller may not only acquire the read voltage from the read voltage management information, but also acquire the request data according to the read voltage, and may also update the read voltage in the read voltage management information.
  • the operation of acquiring the read voltage from the read voltage management information and acquiring the request data by the controller is referred to as an acquisition operation, and the state of the read voltage management information may be referred to as an operation phase; the controller is updated with the read voltage.
  • the operation of the read voltage in the management information is referred to as an update operation, and the state of the read voltage management information at this time may be referred to as a maintenance phase.
  • the relationship between the get operation and the update operation is as follows.
  • the controller when the controller updates the read voltage corresponding to the storage area in the read voltage management in the first time period, the storage area is obtained from the read voltage management in the second time period.
  • the voltage is read, there is no overlap between the first time period and the second time period. That is, for the read voltage corresponding to the same storage area in the read voltage management information, the controller cannot perform the acquisition operation and the update operation at the same time; or the same storage area in the read voltage management information cannot be simultaneously in the operation phase and the maintenance side .
  • the controller updates the read voltage corresponding to one storage area in the read voltage management in the third time period, and acquires another storage from the read voltage management in the fourth time period
  • the first time period overlaps with the second time period, or the first time period does not overlap with the second time period. That is, the controller cannot simultaneously perform the acquisition operation and the update operation on the same storage area corresponding to the read voltage in the read voltage management information at the same time period. That is, for the read voltage corresponding to different storage areas in the read voltage management information, the controller may perform the acquisition operation and the update operation at the same time, or may perform the acquisition operation and the update operation at different times; or read different storage areas in the voltage management information. It can be in the operation phase and maintenance phase at the same time, or it can be in the operation phase and maintenance phase at the same time.
  • the controller when the controller receives the read request sent by the host, it may determine whether to acquire the corresponding read voltage by reading the voltage management information according to a specific read response policy. If not, processing is performed by other response methods in the prior art. If yes, obtaining a corresponding read voltage from the read voltage management information according to the physical location information included in the read request; acquiring the request data according to the corresponding read voltage; determining whether the read request response is successful; if yes (ie, the response is successful), ending If no (ie unsuccessful) then enter the error recovery process.
  • the Flash array includes particles 0 to n, and each block includes a block. 0 to block n are described as an example.
  • the controller determines, according to the read request sent by the host, that the physical location included in the request is block 0 in the granularity n, the controller obtains the read voltage corresponding to the block 0 from the read voltage management information.
  • the request data is obtained from the Flash array according to the read voltage corresponding to the block 0, and then the request data is returned to the host.
  • the controller determines that the current corresponding to the block n is valid by the read voltage update method (for example, the method provided in the above step 404).
  • the read voltage is then updated to the read voltage management information by the currently active read voltage.
  • the embodiment of the present application may divide the function module into the controller according to the foregoing method example.
  • each function module may be divided according to each function, or two or more functions may be integrated into one processing module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present application is schematic, and is only a logical function division, and the actual implementation may have another division manner.
  • the controller includes a receiving unit 1001, a processing unit 1002, and a transmitting unit 1003.
  • the receiving unit 1001 is configured to support the controller to perform step 401 in the method for reducing the read delay provided by FIG. 4 or FIG. 5;
  • the processing unit 1002 is configured to support the controller to perform the reduced read delay provided in FIG. 4 or FIG. 5.
  • the transmitting unit 1003 is configured to support the controller to perform FIG. Or the process of reducing the read latency provided in FIG. 5, in which the step 403 sends the request data to the host.
  • the controller includes a processor 1102, a communication interface 1103, a memory 1101, and a bus 1104.
  • the processor 1102, the communication interface 1103, and the memory 1101 are connected to each other through a bus 1104.
  • the processor 1102 is configured to perform control management on the action of the controller, for example, the processor 1102 is configured to support the controller to perform the steps in the method for reducing the read delay provided by FIG. 4 or FIG. 5.
  • the communication interface 1103 is used to support the controller for communication.
  • the memory 1101 is configured to store program code and data of the controller.
  • the processor 1102 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof, which can Various exemplary logical blocks, modules, and circuits are described in conjunction with the present disclosure.
  • Processor 1102 can also be a combination of computing functions, for example, including one or more microprocessor combinations, a combination of digital signal processors and microprocessors, and the like.
  • the bus 1104 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus or the like.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus 1104 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 11, but it does not mean that there is only one bus or one type of bus.
  • the embodiment of the present application further provides a system, where the system includes a host, a controller, and a Flash array.
  • the Flash array includes a plurality of storage areas, and the physical characteristics of the plurality of physical locations included in the same storage area are the same or similar to the system.
  • the system can be the system shown in Figure 2 or Figure 3.
  • the host may be used in the Flash array, and send a read request to the controller, and receive request data sent by the controller; the controller may be used to manage the reduction that can be used to perform the FIG. 4 or FIG.
  • the steps of the controller in the method of reading the delay The controller is operative to perform steps 401-403 of Figure 4, or to perform steps 401-404 of Figure 5, and/or other processes of the techniques described herein. For details, refer to the description in the embodiment shown in FIG. 4 or FIG. 5, and details are not described herein again.
  • a computer readable storage medium having stored therein computer executable instructions that, when executed by at least one processor of a device, cause the device to execute The method of reducing the read latency provided by Figure 4 or Figure 5.
  • a computer program product comprising computer executable instructions stored in a computer readable storage medium; at least one processor of the device
  • the readable storage medium reads the computer to execute instructions, and the at least one processor executes the computer to execute the instructions such that the apparatus implements the method of performing the reduced read delay provided by FIG. 4 or FIG.
  • the controller when the controller receives the read request sent by the host, the controller may select the storage area and the read voltage included in the read voltage management information according to the first physical location indicated by the location indication information included in the read request.
  • the read voltage corresponding to the first storage area where the first physical location is located is obtained, and the physical characteristics and the read voltage characteristics of the plurality of physical locations included in the first storage area are the same or similar, and the read voltage management information is The read voltage is dynamically updated, so that the accuracy of the read voltage can be ensured.
  • the request data is acquired based on the read voltage, the first read success rate can be improved, the number of read operations can be reduced, and the read delay can be reduced.

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Abstract

一种降低读延迟的方法及装置，涉及数据存储技术领域，用于降低读延时。该方法应用于控制器中，控制器的前端连接主机，后端连接Flash阵列，包括：接收主机发送的读请求，该读请求中包括请求数据的位置指示信息；根据位置指示信息所指示的第一物理位置，从读电压管理信息中获取第一物理位置所在的第一存储区域对应的读电压，第一物理位置为所述请求数据在Flash阵列中的物理位置，Flash阵列中包括多个存储区域，同一存储区域中包含的多个物理位置的物理特性相同或相似，读电压管理信息包括存储区域与读电压之间的对应关系，读电压管理信息中的读电压是动态更新的；根据第一存储区域对应的读电压，获取请求数据，并将请求数据发送给主机。

Description

一种降低读延时的方法及装置
本申请要求于2017年11月27日提交中国专利局、申请号为201711208323.X、申请名称为“一种降低读延时的方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及数据存储技术领域，尤其涉及一种降低读延时的方法及装置。.
背景技术
固态存储驱动(Solid State Drive，SSD)是指用固态电子存储芯片阵列制成的硬盘或者存储卡等存储介质，SSD的服务质量(Quality of Service，QoS)是SSD产品向主机提供稳定、一致和可预测性的请求应答服务的能力，它是塑造SSD产品竞争力的关键因素之一。SSD可应用于数据中心以及服务器等场景中，读响应时间(Read Latency)是QoS的关键性能指标，主要取决于响应主机IO请求的Flash介质中发生的读操作次数。Flash作为SSD的主要存储介质，它的特性受擦写次数(Program/Erase Cycles，PE)、数据保留时间(Retention Time)等多种因素的影响，承载数据的电压信号会发送漂移，从而需要多次读操作才能成功响应主机IO请求，因此造成QoS中读延时较长。
目前，现有技术中可以通过读电压预制表技术降低读延时，即通过分析影响读电压的因素与电压偏移量的关系，制作影响因素与读电压补偿表或者通过拟合的方法归纳特定的公式，使用时按照影响因素值查表或计算后对读电压进行补偿，从而提高首次读成功率，进而减小读延时。但是，读电压预制表技术与采样的样本有关，对于不同的存储介质需要制作不同的读电压预制表，工作量较大。另外，存储介质在使用过程中会发生变化，使用读电压预制表技术的可靠性较低，首次读成功率的提升幅度有限，因此降低读延时的效果不佳。
发明内容
本申请的实施例提供一种降低读延时的方法及装置，解决了现有技术中读延时较长的问题。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种降低读延时的方法，应用于控制器中，控制器的前端连接主机，后端连接Flash阵列，该方法包括：控制器接收主机发送的读请求，该读请求中包括请求数据的位置指示信息；控制器根据该位置指示信息所指示的第一物理位置，从读电压管理信息中获取第一物理位置所在的第一存储区域对应的读电压；其中，第一物理位置为该请求数据在Flash阵列中的物理位置，Flash阵列中包括多个存储区域，同一存储区域中包含的多个物理位置的物理特性相同或相似，读电压管理信息包括存储区域与读电压之间的对应关系，读电压管理信息中的读电压是动态更新的；控制器根据第一存储区域对应的读电压，获取请求数据，并将请求数据发送给主机。上述技术方案中，由于第一存储区域包括的多个物理位置的物理特性和读电压特性相同或相 似，且读电压管理信息中的读电压是动态更新的，从而可以保证控制器获取的读电压的准确性，基于该读电压获取请求数据时，可以提高首次读成功率，减少读操作次数，进而降低读延时。
在第一方面的一种可能的实现方式中，同一存储区域中包含的物理位置的读电压特性相同或相似；和/或，不同存储区域包含的物理位置的物理特性不同；和/或，不同存储区域包含的物理位置的读电压特性不同。上述可能的实现方式中，通过将物理特性相同或相似和/或读电压特性相同或相似的多个物理位置划分在同一存储区域，在读电压管理信息中对应一个读电压，可以节省控制器中内存的开销。
在第一方面的一种可能的实现方式中，对于多个存储区域中的任一存储区域，该方法还包括：当满足预设更新条件时，控制器更新读电压管理信息中存储区域对应的读电压。上述可能的实现方式中，通过动态更新读电压管理信息中的读电压，可以保证读电压的实时有效，从而以该读电压获取读取数据时的成功率较高，进而降低了读延时。
在第一方面的一种可能的实现方式中，读电压管理信息中的读电压是动态更新的，包括：当满足预设更新条件时，控制器更新读电压管理信息中存储区域对应的读电压，包括：当处于系统空闲时间窗或者满足预设更新周期时，控制器确定存储区域对应的读电压下的第一出错参数；当第一出错参数大于或等于第一阈值时，控制器更新读电压管理信息中存储区域对应的读电压。上述可能的实现方式中，控制器通过主动的动态更新读电压管理信息中的读电压，可以保证读电压的实时有效，从而以该读电压获取读取数据时的成功率较高，进而降低了读延时。
在第一方面的一种可能的实现方式中，预设更新周期与存储区域的使用状态相关；或者，预设更新周期与Flash阵列包括的多个存储区域的平均使用寿命相关。上述可能的实现方式中，通过设置合适的预设更新周期，按照预设更新周期动态更新读电压管理信息中的读电压，可以在保证读电压的实时有效的同时，避免不必要的更新操作，节省了控制器的能耗。
在第一方面的一种可能的实现方式中，当满足预设更新条件时，控制器更新读电压管理信息中存储区域对应的读电压，包括：当在存储区域对应的读电压下，首次读取的请求数据的第二出错参数大于或等于第一阈值时，控制器更新读电压管理信息中存储区域对应的读电压。上述可能的实现方式中，控制器通过被动的动态更新读电压管理信息中的读电压，可以在读电压出现首次读数据失败后快速有效的更新读电压，减小读操作次数，进而降低了读延时。
在第一方面的一种可能的实现方式中，对于多个存储区域中的任一个存储区域，当控制器在第一时间段内更新读电压管理中存储区域对应的读电压、在第二时间段内从读电压管理中获取存储区域对应的读电压时，第一时间段与第二时间段不存在重叠；和/或，对于多个存储区域中的任意两个存储区域，当控制器在第三时间段内更新读电压管理中一个存储区域对应的读电压、在第四时间段内从读电压管理中获取另一个存储区域对应的读电压时，第一时间段与第二时间段存在重叠、或者第一时间段与第二时间段不重叠。上述可能的实现方式中，控制器可以在不同的时间段内对读电压管理信息进行不同的操作，从而节省管理读电压管理信息的时间，提高系统性能。
在第一方面的一种可能的实现方式中，一个存储区域包括至少一个存储单元，存储单元包括以下中的至少一项：颗粒Device、逻辑单元Die、面Plane、块Block、超级块Super Block、层Layer、子块Sub-Block、字线WL和页面Page。上述可能的实现方式中，控制器通过合理的划分存储区域，可以减小读电压管理信息的数据量，进而节省控制器中内存的开销。
第二方面，提供一种控制器，控制器的前端连接主机，后端连接Flash阵列，该控制器包括：接收单元，用于接收主机发送的读请求，该读请求中包括请求数据的位置指示信息；处理单元，用于根据该位置指示信息所指示的第一物理位置，从读电压管理信息中获取第一物理位置所在的第一存储区域对应的读电压；其中，第一物理位置为该请求数据在Flash阵列中存储的物理位置，Flash阵列中包括多个存储区域，同一存储区域中包含的多个物理位置的物理特性相同或相似，读电压管理信息包括存储区域与读电压之间的对应关系，读电压管理信息中的读电压是动态更新的；处理单元，还用于根据第一存储区域对应的读电压，获取请求数据；发送单元，用于将请求数据发送给主机。
在第二方面的一种可能的实现方式中，同一存储区域中包含的物理位置的读电压特性相同或相似；和/或，不同存储区域包含的物理位置的物理特性不同；和/或，不同存储区域包含的物理位置的读电压特性不同。
在第二方面的一种可能的实现方式中，处理单元，具体用于：对于多个存储区域中的任一存储区域，当满足预设更新条件时，更新读电压管理信息中存储区域对应的读电压，以使读电压管理信息中的读电压是动态更新的。
在第二方面的一种可能的实现方式中，处理单元，还用于：当处于系统空闲时间窗或者满足预设更新周期时，确定存储区域对应的读电压下的第一出错参数；当第一出错参数大于或等于第一阈值时，更新读电压管理信息中存储区域对应的读电压。
在第二方面的一种可能的实现方式中，预设更新周期与存储区域的使用状态相关；或者，预设更新周期与Flash阵列包括的多个存储区域的平均使用寿命相关。
在第二方面的一种可能的实现方式中，处理单元，还用于：当在存储区域对应的读电压下，首次读取的请求数据的第二出错参数大于或等于第一阈值时，更新读电压管理信息中存储区域对应的读电压。
在第二方面的一种可能的实现方式中，对于多个存储区域中的任一个存储区域，当在第一时间段内更新读电压管理中存储区域对应的读电压、在第二时间段内从读电压管理中获取存储区域对应的读电压时，第一时间段与第二时间段不存在重叠；和/或，对于多个存储区域中的任意两个存储区域，当在第三时间段内更新读电压管理中一个存储区域对应的读电压、在第四时间段内从读电压管理中获取另一个存储区域对应的读电压时，第一时间段与第二时间段存在重叠、或者第一时间段与第二时间段不重叠。
在第二方面的一种可能的实现方式中，一个存储区域包括至少一个存储单元，存储单元包括以下中的至少一项：颗粒Device、逻辑单元Die、面Plane、块Block、超级块Super Block、层Layer、子块Sub-Block、字线WL和页面Page。
第三方面，提供一种系统，该系统包括主机、控制器和Flash阵列，Flash阵列中 包括多个存储区域，同一存储区域中包含的多个物理位置的物理特性相同或相似；其中，主机，用于向控制器发送读请求，以及接收控制器返回的请求数据，该读请求包括请求数据的位置指示信息；控制器，用于管理读电压管理信息，读电压管理信息包括存储区域与读电压之间的对应关系，读电压管理信息中的读电压是动态更新的；控制器，还用于当接收到该读请求时，根据该位置指示信息所指示的第一物理位置，从读电压管理信息中获取第一物理位置所在的第一存储区域对应的读电压，第一物理位置为该请求数据在Flash阵列中存储的物理位置；控制器，还用于根据第一存储区域对应的读电压，获取请求数据，并将请求数据发送给主机。
在第三方面的一种可能的实现方式中，同一存储区域中包含的物理位置的读电压特性相同或相似；和/或，不同存储区域包含的物理位置的物理特性不同；和/或，不同存储区域包含的物理位置的读电压特性不同。
在第三方面的一种可能的实现方式中，控制器，具体用于：对于多个存储区域中的任一存储区域，当满足预设更新条件时，更新读电压管理信息中存储区域对应的读电压，以使读电压管理信息中的读电压是动态更新的。
在第三方面的一种可能的实现方式中，控制器，具体用于：当处于系统空闲时间窗或者满足预设更新周期时，确定存储区域对应的读电压下的第一出错参数；当第一出错参数大于或等于第一阈值时，更新读电压管理信息中存储区域对应的读电压。
在第三方面的一种可能的实现方式中，预设更新周期与存储区域的使用状态相关；或者，预设更新周期与Flash阵列中多个存储区域的平均使用寿命相关。
在第三方面的一种可能的实现方式中，控制器，具体用于：当在存储区域对应的读电压下，首次读取的请求数据的第二出错参数大于或等于第一阈值时，更新读电压管理信息中存储区域对应的读电压。
在第三方面的一种可能的实现方式中，对于多个存储区域中的任一个存储区域，当控制器在第一时间段内更新读电压管理中存储区域对应的读电压、在第二时间段内从读电压管理中获取存储区域对应的读电压时，第一时间段与第二时间段不存在重叠；和/或，对于多个存储区域中的任意两个存储区域，当控制器在第三时间段内更新读电压管理中一个存储区域对应的读电压、在第四时间段内从读电压管理中获取另一个存储区域对应的读电压时，第一时间段与第二时间段存在重叠、或者第一时间段与第二时间段不重叠。
在第三方面的一种可能的实现方式中，一个存储区域包括至少一个存储单元，存储单元包括以下中的至少一项：颗粒Device、逻辑单元Die、面Plane、块Block、超级块Super Block、层Layer、子块Sub-Block、字线WL和页面page。
本申请的又一方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得该计算机执行上述第一方面或第一方面的任一种可能的实现方式所提供的降低读延时的方法。
本申请的又一方面，提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得该计算机执行上述第一方面或第一方面的任一种可能的实现方式所提供的降低读延时的方法。
可以理解地，上述提供的任一种降低读延时的方法的装置、计算机存储介质或者 计算机程序产品均用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种存储颗粒的结构示意图；
图2为本申请实施例提供的一种通信系统的结构示意图；
图3为本申请实施例提供的另一种通信系统的结构示意图；
图4为本申请实施例提供的一种降低读延时的方法的流程示意图；
图5为本申请实施例提供的另一种降低读延时的方法的流程示意图；
图6为本申请实施例提供的一种更新读电压管理信息的流程示意图；
图7为本申请实施例提供的另一种更新读电压管理信息的流程示意图；
图8为本申请实施例提供的一种处理读请求的流程示意图；
图9为本申请实施例提供的一种对读电压管理信息的操作示意图；
图10为本申请实施例提供的一种控制器的结构示意图；
图11为本申请实施例提供的另一种控制器的结构示意图。
具体实施方式
目前，大多数存储设备均使用固态存储驱动(Solid State Drive，SSD)进行数据存储，比如硬盘或存储卡等。SSD的服务质量(Quality of Service，QoS)是存储设备向主机提供稳定、一致和可预测性的请求应答服务的能力，它是影响存储设备的市场竞争力的关键因素之一。QoS可以包括多个性能指标，其中读响应时间(Read Latency)是QoS的关键性能指标，主要取决于响应主机IO请求的Flash介质中发生的读操作次数。而Flash介质作为SSD的主要存储介质，它的特性受擦写次数(Program/Erase Cycles，PE)、数据保留时间(Retention Time)、读操作次数(Read Counts)等多种因素的影响，承载数据的电压信号会发送漂移，从而后端需要多次读操作(试错)才能成功响应主机IO请求，因此影响了QoS的读延时指标，造成读延时较长。
随着更高存储密度的单元(Cell)由3D TLC(Triple-Level Cell)逐渐替代2D MLC(Multi-Level Cell)成为主流存储介质，QoS的读延时指标正面临着越来越多的挑战。如图1所示，为本申请实施例提供的一种颗粒的内部的层次结构图。其中，写操作的最小单位为页面(Page)，页面可以划分为三种类型，即上页(Upper Page)、中页(Middle Page)和下页(Lower page’)。一个上页、一个中页和一个下页可以组成一个字线(Word Line，WL)，若干个WL按不同的方向组成层(Layer)或子块(Sub-Block)，比如，图1中横向的多个WL组成Layer，纵向的多个WL组成Sub-Block。Page组成的最小擦除操作单元称为块(Block)。多个Block组成面(Plane)，多个Plane可以组成逻辑单元(Die)。多个Die组成颗粒(Device)，每个Device对应一个Channel。
此外，在许多应用中控制器会将一些Block组成Super Block。Super Block在应用中的特征是内部的Block会被同时擦除、或同时被编程，Super Block内部的Block的使用条件的状态是一致或接近的，比如，擦写次数(Program/Erase Cycles，PE)、以及数据保留时间(Retention Time)等。
3D TLC与2D MLC相比，每个单元(Cell)中的逻辑状态从4个(2bit)增加到 8个(3bit)，区分不同逻辑状态的电压信号窗口变小，从而读电压的准确度要求提升。另外，Block中的Page数、以及Die中的Block数逐步增加，Flash内部各层次的物理不一致性增加，对所有Page设置统一的有效读电压变得越来越困难。
因此，为了有效提升读延时必须同时解决两个问题：读电压随着使用条件变化而变化，Flash内部存在个层次的物理差异。基于此，本申请实施例提供一种降低读延时的方法及装置，用于提升QoS中的读延时指标。
图2为本申请实施例所应用的一种通信系统的硬件架构图，参见图2，该系统包括主机、SSD控制器和Flash阵列，主机可以通过SSD控制器存/取Flash阵列中的数据。其中，主机可以通过NVMe/SAS/PCIe等多种接口与SSD控制器的前端相连，SSD控制器的后端可以通过NFI与Flash阵列相连，主机通过SSD控制器对Flash阵列中的数据进行读写或擦除等操作。
可选的，如图3所示，为本申请实施例所应用的另一种通信系统的硬件架构图。该系统中的控制器与图2所示的系统中的SSD控制器类似。不同的是，该系统中的控制器与Flash阵列封装成独立的芯片，主机通过UFS/eMMC等接口与控制器相连，并通过该接口存取数据。示例性的，控制器与Flash阵列封装成的芯片可应用于诸如手机、平板电脑、可穿戴设备等移动终端中。
图4为本申请实施例提供的一种降低读延时的方法的流程示意图，该方法可应用于上述图2或图3所示的通信系统中，参见图4，该方法包括以下几个步骤。
步骤401：控制器接收主机发送的读请求，该读请求中包括请求数据的位置指示信息。
其中，当主机需要从控制器管理的Flash阵列中读取某一数据时，主机可以向控制器发送读请求，该读请求所请求的数据可以称为请求数据，在该读请求中可以携带位置指示信息。该位置指示信息可以用于指示逻辑地址，即主机用于访问该请求数据时的逻辑地址，逻辑地址与物理地址存在映射关系，根据该请求数据的逻辑地址可以确定该请求数据在Flash阵列中的物理位置。在实际应用中，该位置指示信息也可以是与物理位置存在对应关系的其他信息，比如，该位置指示信息可以是key值，通过预设的key值与Value值之间的对应关系，获取对应的Value值，该Value值可以是数据的物理位置，本申请实施例对此不作限定。
具体的，当控制器接收到主机发送的读请求时，控制器可以根据该位置指示信息获取请求数据在Flash阵列中存储的物理地址，这里将该请求数据的物理地址称为第一物理位置。
步骤402：控制器从读电压管理信息中获取第一物理位置所在的第一存储区域对应的读电压。其中，Flash阵列包括多个存储区域，同一存储区域包括的多个物理位置的物理特性相同或者相似，该读电压管理信息包括存储区域与读电压之间的对应关系，该读电压管理信息中的读电压是动态更新的。
其中，多个存储区域中的每个存储区域可以包括至少一个存储单元，每个存储单元可以通过对应的物理位置进行表示，一个存储区域包括的多个物理位置可以是其包括的至少一个存储单元对应的物理位置。同一存储区域包括的多个物理位置的物理特性相同或相似，即同一存储区域中包括的存储单元的物理特性相同或相似。不同存储 区域包括的多个物理位置的物理特性不同，即不同存储区域中包括的存储单元的物理特性不同。这里存储单元的物理特性可以包括多个方面，比如，纳米级的几何尺寸、材质的电学特性、存储单元组合的结构、以及内部的控制电路等等。在本申请实施例中，两个存储单元的物理特性相同或相似是指两个存储单元的物理特性差异较小，比如，其物理特性的对应的某一参数小于设定门限、或者其物理特性对应的多个参数均小于各自对应的设定门限，则确定其物理特性差异较小。两个存储单元的物理特性不同是指两个存储单元的物理特性差异较大，比如，其物理特性的对应的某一参数大于设定门限、或者其物理特性对应的多个参数均大于各自对应的设定门限，则确定其物理特性差异较小。
另外，存储单元的物理特性与存储单元对应的读电压特性有关，读电压是指从模拟信号向数据信号转换时对应的转换电压，读电压特性可以是指在不同条件(比如，不同温度、不同时间、不同PE、不同数据保留时间、不同读操作次数(Read Counts))下，使用不同的设备读取读电压时，对应的出错参数的变化规律。具体的，物理特性相同或者相似的多个存储单元对应的读电压特性之间的差异较小，物理特性不同的多个存储单元对应的读电压特性之间的差异较大。因此，同一存储区域中包括的存储单元的物理特性相同或相似，则同一存储区域包括的存储单元对应的读电压特性的差异较小，从而一个存储区域可以对应一个读电压。不同存储区域中包括的存储单元的物理特性不同，则不同存储区域包括的存储单元对应的读电压特性的差异较大，从而不同的存储区域可以对应不同的读电压。
再者，对于Flash阵列包括的多个存储区域，同一存储区域包括的存储单元的读电压特性相同或相似，不同存储区域包括的存储单元的读电压特性不同。当多个存储单元的读电压特性相同或相似，即该多个存储单元的读电压特性差异较小时，则该多个存储单元可以属于同一存储区域中；当多个存储单元的读电压特性不同，即该多个存储单元的读电压特性差异较大时，则该多个存储单元可以属于不同存储区域中。确定读电压特性差异较小和较大的方法，可以与确定物理特性差异较小或较大的方法类似。本申请实施例中，通过将物理特性相同或相似、以及读电压特性相同或相似的多个物理位置划分在同一存储区域，对应一个读电压，可以节省系统开销。
对于多个存储区域中的每个存储区域，读电压管理信息中可以包括每个存储区域与读电压之间的对应关系。读电压管理信息中包括的读电压是动态更新的，即读电压管理信息中每个存储区域对应的读电压是及时刷新的，以保证每个存储区域对应的读电压的准确性。
具体的，当控制器接收到读请求时，控制器可以根据读请求中包括的第一物理位置，确定第一物理位置在多个存储区域中所在的存储区域，这里将物理位置所在的存储区域称为第一存储区域。控制器根据第一存储区域，从动态更新的读电压管理信息包括的存储区域与读电压之间的对应关系中，获取第一存储区域对应的读电压，获取的读电压的准确性较好，从而以该读电压从第一存储区域中读取数据时的成功率较高。
可选的，当控制器接收到读请求时，控制器根据还可以特定的读请求策略，选择是否通过读电压管理信息获取读电压。当根据特定的读请求策略，选择通过读电压管理信息获取读电压(即选择是)时，则根据上述步骤402获取对应的读电压。特定的 读请求策略可以事先进行设置，对于不同的读请求，可以设置不同的读请求策略，也可以设置相同的读请求策略，本申请实施例对此不作具体限定。
进一步的，Flash阵列可以包括多个Device，每个Device的内部结构可以如图1所示。当Flash阵列中的每个存储区域可以包括至少一个存储单元时，该存储单元可以包括以下中的至少一项：颗粒(Device)、逻辑单元(Die)、面(Plane)、块(Block)、超级块(Super Block)、层(Layer)、子块(Sub-Block)、字线(WL)和页面(Page)。也即是，Flash阵列划分为多个存储区域时的划分粒度可以包括上述中的至少一项。
比如，当划分粒度包括Device时，则一个存储区域中可以包括至少一个Device。当划分粒度包括Die时，则一个存储区域中可以包括至少一个Die。当划分粒度包括Plane时，则一个存储区域中可以包括至少一个Plane。当划分粒度包括Block时，则一个存储区域中可以包括至少一个Block。当划分粒度包括Super Block时，则一个存储区域中可以包括至少一个Super Block。当划分粒度包括Layer时，则一个存储区域中可以包括至少一个Layer。当划分粒度包括Sub-Block时，则一个存储区域中可以包括至少一个Sub-Block。当划分粒度包括WL时，则一个存储区域中可以包括至少一个WL。当划分粒度包括Page时，则一个存储区域中可以包括至少一个Page。
可选的，通常由于Flash阵列中各Block的使用条件(比如，PE/Retention Time等)一般不同，从而不同的Block可以位于不同的存储区域中。此外，Block内部Page的读电压特性与Page在Block中的物理位置相关，因此可以将读电压特性相同或相似的Page划分在同一存储区域中，本申请实施例对此不作具体限定。
步骤403：控制器根据第一存储区域对应的读电压获取请求数据，并将请求数据发送给主机。
其中，当控制器获取到第一存储区域对应的读电压时，控制器可以根据第一存储区域对应的读电压，从第一存储区域中获取第一物理位置处所存储的请求数据。之后，控制器可以将该请求数据发送给主机，从而主机可以接收到该请求数据。
在本申请实施例中，当控制器接收到主机发送的读请求时，控制器可以根据读请求包含的位置指示信息所指示的第一物理位置，从读电压管理信息包括的存储区域与读电压之间的对应关系中，获取第一物理位置所在的第一存储区域对应的读电压，由于第一存储区域包括的多个物理位置的物理特性和读电压特性相同或相似，且读电压管理信息中的读电压是动态更新的，从而可以保证获取的读电压的准确性，基于该读电压获取请求数据时，可以提高首次读成功率，减少读操作次数，进而降低了读延时。
进一步的，参见图5，读电压管理信息中的读电压是动态更新的，可以包括步骤404：对于多个存储区域中的任一存储区域，当满足预设条件时，控制器更新读电压管理信息中该存储区域对应的读电压。步骤404与步骤401-步骤403可以不分先后顺序。
其中，当满足预设条件时，控制器可以通过特定的在线读电压的优化算法，确定该存储区域对应的有效读电压，并根据该有效读电压更新读电压管理信息中该存储区域对应的读电压。其中，控制器动态更新读电压管理信息中该存储区域对应的读电压时，控制器可以主动的更新该存储区域对应的读电压，也可以被动的更新该存储区域对应的读电压。主动的更新读电压管理信息中的读电压，或者被动的读电压管理信息中的更新读电压，都可以保证读电压管理信息中的读电压是动态更新的。下面分别对 这两种方式进行详细说明。
第一种、控制器主动的更新该存储区域对应的读电压，具体可以包括：当控制器处于系统空闲时间窗或者满足预设更新周期时，控制器确定该存储区域对应的读电压下的第一出错参数；当第一出错参数大于或等于第一阈值时，控制器更新读电压管理信息中该存储区域对应的读电压。
其中，控制器处于系统空闲时间窗可以是指控制器处于空闲状态，该空闲状态可以理解为控制器的读写IO的负载低于某一特定值，从而控制器相对比较空闲。预设更新周期可以事先进行设置，且预设更新周期可以包括一个周期，也可以包括多个不同的周期。一个存储区域对应的预设更新周期的设置可以与该存储区域的使用状态相关(比如，PE次数和读操作次数)，或者与Flash阵列中包括的多个存储区域的平均使用寿命相关。比如，多个存储区域的平均使用寿命可以通过平均PE来表示，当平均PE较大(比如，生命早期)时可以使用较大的预设更新周期，当平均PE较小(比如，生命末期)时可以使用较小的预设更新周期。
另外，第一出错参数可以用于指示读取数据中的出错程度，第一出错参数可以是出错比特数或者比特误码率RBER。第一阈值可以是事先设置的容错门限，若第一出错参数小于第一阈值，则表示在容错范围之内，若第一出错参数大于或等于第一阈值，则表示不在容错范围之内。
具体的，当控制器处于系统空闲时间窗或者满足预设更新周期时，控制器将读电压管理信息中当前存储的该存储区域对应的读电压作为被检测的读电压，根据被检测的读电压，对该存储区域中包括的物理位置进行采样，获取被检测的读电压下的出错参数为第一出错参数。如果第一出错参数小于第一阈值，则控制器可以确定该存储区域对应的读电压有效，从而不对其进行更新。如果第一出错参数大于或等于第一阈值，则控制器可以确定该存储区域对应的读电压无效，需要对其进行更新。
当控制器对该存储区域对应的读电压进行更新时，控制器可以通过尝试的方法确定当前的有效读电压，比如，控制器可以按照电压逐步递增或递减的方式测试多个电压下的出错参数，将出错参数最小的读电压确定为当前的有效读电压，从而将读电压管理信息中该存储区域对应的读电压替换为当前的有效读电压，以实现对该存储区域对应的读电压的更新。
上述主动的更新读电压管理信息中的读电压的方法中，控制器会在每个系统空闲时间窗内主动的更新读电压管理信息中的读电压，或者在每个预设更新周期内主动的更新读电压管理信息中的读电压，从而实现了每隔一段时间即对读电压管理信息中的读电压更新一次。因此，主动的更新读电压管理信息中的读电压，可以使得读电压管理信息中的读电压处于动态更新的状态，从而保证读电压管理信息中的读电压是实时有效性的。
此外，当通过预设更新周期触发控制器主动地更新该存储区域对应的读电压时，可以通过定时器中断的方式进行触发。还可以通过其他强制信号触发控制器主动地更新该存储区域对应的读电压，具体的强制信号可以事先进行设置，本申请实施例对此不作限定。
第二种、控制器被动的更新该存储区域对应的读电压，具体可以包括：当在该存 储区域对应的读电压下，首次读取的请求数据的第二出错参数大于或等于第一阈值时，控制器更新读电压管理信息中该存储区域对应的读电压。
其中，首次读取的请求数据是指控制器根据读电压管理中该存储区域对应的读电压，第一次从该存储区域中读取的请求数据，该请求数据是基于主机发送的读请求所获取的数据，并不是控制器主动的进行采样获取的数据。
具体的，控制器在该存储区域对应的读电压下，首次从该存储区域中读取请求数据，读取的请求数据的出错参数为第二出错参数。如果第二出错参数小于第一阈值，则控制器可以确定该存储区域对应的读电压有效，从而不对其进行更新。如果第二出错参数大于或等于第一阈值，则控制器可以确定该存储区域对应的读电压无效，需要对其进行更新。
需要说明的是，控制器对该存储区域对应的读电压进行更新(即获取当前的有效读电压)时，也可以按照电压逐步递增或递减的方式进行更新，具体实现过程与第一种方式中的描述一致，本申请实施例在此不再赘述。
当控制器对读电压管理信息中多个存储区域对应的读电压进行更新时，控制器可以先确定出读电压无效的存储区域，之后，控制器可以仅对读电压管理信息中读电压无效的存储区域的读电压进行更新。在本申请实施例中，控制器在更新读电压管理信息中该存储区域对应的读电压时，通过先确定读电压管理信息中存储的该存储区域对应的读电压是否有效，并在确定其无效时进行更新，从而可以避免不必要的操作，进而节省了系统带宽和负载开销。
上述被动的更新读电压管理信息中的读电压的方法中，控制器会在读电压管理信息中的读电压无效时，将其更新为当前的有效读电压，从而在每段时间内，当读电压管理信息中出现一个或者多个无效的读电压时，控制器都会对该一个或者多个读电压进行更新。因此，被动的更新读电压管理信息中的读电压，可以使得读电压管理信息中的读电压处于动态更新的状态，从而保证读电压管理信息中的读电压是实时有效性的。
为便于理解，通过图6和图7所示的处理流程，对控制器主动地更新读电压管理信息和被动地更新读电压管理信息的过程分别进行举例说明。
图6为一种控制器主动地更新读电压管理信息的流程图，以控制器处于系统空闲时间窗为例。具体的，假设读电压管理信息中所有的读电压都需要更新，则当控制器处于系统空闲时间窗时，控制器可以确定读电压管理信息中每个读电压下对应的出错参数，确定读电压管理信息中需要更新的读电压(比如，当其对应的出错参数小于第一阈值时则确定不需要更新，当其对应的出错参数大于或等于第一阈值时则确定需要更新)，从而得到待更新读电压记录信息(即读电压管理信息中读电压无效的存储记录)；控制器通过读电压更新的方法(比如，上述步骤404中提供的方法)对待更新读电压记录信息进行更新。当全部的待更新读电压记录信息更新完成后结束，或者系统空闲时间窗结束。
图7为一种控制器被动地更新读电压管理信息的流程图。具体的，控制器接收到主机发送的读请求，根据读请求包括的物理位置信息从读电压管理信息中获取对应的读电压(即通过读电压管理信息响应读请求)，基于该读电压首次获取的请求数据数 据失败(即首次读数据失败)时，将读电压管理信息中该读电压标记为无效的读电压；之后，进入错误恢复流程(即更新无效的读电压)或结束。
需要说明的是，控制器确定读电压管理信息中无效的读电压的步骤，以及更新读电压管理信息中无效的读电压的步骤可以同步执行，也可以异步执行。也即是，控制器可以先确定读电压管理信息中所有无效的读电压，然后对所有无效的读电压逐一进行更新；或者，控制器每确定读电压管理信息中的一个无效的读电压后，即对该无效的读电压进行更新，然后再确定下一个无效的读电压进行更新，以此类推；或者，控制器一边确定读电压管理信息中无效的读电压，一边对已确定的无效的读电压进行更新，本申请实施例对此不作具体限定。
在实际应用中，当控制器更新读电压管理信息时，若该读电压管理信息驻留在内存等快速存储介质中，则需要在非易失性存储介质中作备份，当系统初始化时，将该读电压管理信息从非易失性存储介质导入快速存储介质已完成初始化。或者，控制器将读电压管理信息直接存储在同时具备快速存取和非易失特性的存储介质中。
进一步的，控制器不仅可以从读电压管理信息中获取读电压以及根据该读电压获取请求数据，也可以更新读电压管理信息中的读电压。其中，为便于理解，将控制器从读电压管理信息中获取读电压以及获取请求数据的操作称为获取操作，此时读电压管理信息的状态可以称为操作相面；将控制器更新读电压管理信息中的读电压的操作称为更新操作，此时读电压管理信息的状态可以称为维护相面。获取操作与更新操作之间的关系具体如下所述。
对于多个存储区域中的任一个存储区域，当控制器在第一时间段内更新读电压管理中该存储区域对应的读电压，在第二时间段内从读电压管理中获取该存储区域对应的读电压时，第一时间段与第二时间段不存在重叠。也即是，对于读电压管理信息中同一存储区域对应读电压，控制器不能同时进行获取操作和更新操作；或者，读电压管理信息中的同一存储区域，不能同时处于操作相面和维护相面。
对于多个存储区域中的任意两个存储区域，当控制器在第三时间段内更新读电压管理中一个存储区域对应的读电压、在第四时间段内从读电压管理中获取另一个存储区域对应的读电压时，第一时间段与第二时间段存在重叠、或者第一时间段与第二时间段不重叠。即控制器不能在同一时间段对读电压管理信息中同一存储区域对应读电压同时进行获取操作和更新操作。也即是，对于读电压管理信息中不同存储区域对应读电压，控制器可以同时进行获取操作和更新操作，也可以不同时进行获取操作和更新操作；或者，读电压管理信息中的不同存储区域，可以同时处于操作相面和维护相面，也可以不同时处于操作相面和维护相面。
为便于理解，通过图8所示的读请求处理流程图，对本申请实施例的方案进行举例说明。如图8所示，当控制器接收到主机发送的读请求时，可以根据特定的读响应策略，确定是否通过读电压管理信息获取对应的读电压。如果否，则通过现有技术中其他的应答方式进行处理。如果是，则根据读请求中包括的物理位置信息从读电压管理信息中获取对应的读电压；根据对应的读电压获取请求数据；判断读请求应答是否成功；若是(即应答成功)则结束，若否(即不成功)则进入错误恢复流程。
示例性的，如图9所示，为读电压管理信息在操作相面和维护相面下对应的不同 操作的示意图，图9中以Flash阵列包括颗粒0～颗粒n，每个颗粒中包括块0～块n为例进行说明。具体的，在操作相面，控制器根据主机发送的读请求，假设该请求中包括的物理位置为颗粒n中的块0，则控制器从读电压管理信息中获取块0对应的读电压，并根据块0对应的读电压从Flash阵列中获取请求数据，之后将请求数据返回给主机。在维护相面，在确定读电压管理信息中块n对应的读电压为无效的读电压时，控制器通过读电压更新方法(比如，上述步骤404中提供的方法)确定块n对应的当前有效的读电压，之后将当前有效的读电压更新至读电压管理信息中。
上述主要从各个设备之间交互的角度对本申请实施例提供的方案进行了介绍。可以理解的是，各个设备，例如主机和控制器为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的设备及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对控制器进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，本申请实施例提供了上述实施例中所涉及的控制器的一种可能的结构示意图。参见图10，该控制器包括：接收单元1001、处理单元1002和发送单元1003。其中，接收单元1001用于支持控制器执行图4或图5所提供的降低读延时的方法中的步骤401；处理单元1002用于支持控制器执行图4或图5所提供的降低读延时的方法中的步骤402和步骤403中获取请求数据的过程、以及图5中的步骤404，和/或用于本文所描述的技术的其他过程；发送单元1003用于支持控制器执行图4或图5所提供的降低读延时的方法中步骤403将请求数据发送给主机的过程。具体描述参见上述实施例中的相关阐述，本申请实施例在此不再赘述。
在硬件实现上，上述处理单元1002可以为处理器；接收单元1001可以为接收器，发送单元1003可以为发送器，接收器和发送器可以构成通信接口。
本申请实施例提供了上述实施例中所涉及的控制器一种可能的逻辑结构示意图。参见图11，该控制器包括：处理器1102、通信接口1103、存储器1101以及总线1104，处理器1102、通信接口1103以及存储器1101通过总线1104相互连接。在本申请的实施例中，处理器1102用于对控制器的动作进行控制管理，例如，处理器1102用于支持控制器执行图4或图5所提供的降低读延时的方法中的步骤402和步骤403中获取请求数据的过程，和/或用于本文所描述的技术的其他过程。通信接口1103用于支持控制器进行通信。存储器1101，用于存储控制器的程序代码和数据。
其中，处理器1102可以是中央处理器单元，通用处理器，数字信号处理器，专用集成电路，现场可编程门阵列或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件 或者其任意组合，其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。处理器1102也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，数字信号处理器和微处理器的组合等等。总线1104可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。总线1104可以分为地址总线、数据总线、控制总线等。为便于表示，图11中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
本申请实施例还提供一种系统，该系统包括主机、控制器和Flash阵列，Flash阵列中包括多个存储区域，同一存储区域中包含的多个物理位置的物理特性相同或相似该系统。该系统可以为图2或者图3所示的系统。在本申请实施例中，主机可以用于Flash阵列，以及向控制器发送读请求，以及接收控制器发送的请求数据；控制器可以用于管理可以用于执行图4或图5所提供的降低读延时的方法中控制器的步骤。控制器用于执行图4中的步骤401-步骤403，或者用于执行图5中的步骤401-步骤404，和/或本文所描述的技术的其他过程。具体过程参见上述图4或图5所示的实施例中的描述，本申请实施例在此不再赘述。
在本申请的另一实施例中，还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当设备的至少一个处理器执行该计算机执行指令时，使得该设备执行图4或图5所提供的降低读延时的方法。
在本申请发明的另一实施例中，还提供一种计算机程序产品，该计算机程序产品包括计算机执行指令，该计算机执行指令存储在计算机可读存储介质中；设备的至少一个处理器可以从计算机可读存储介质读取该计算机执行指令，至少一个处理器执行该计算机执行指令使得设备实施执行图4或图5所提供的降低读延时的方法。
在本申请实施例中，当控制器接收到主机发送的读请求时，控制器可以根据读请求包含的位置指示信息所指示的第一物理位置，从读电压管理信息包括的存储区域与读电压之间的对应关系中，获取第一物理位置所在的第一存储区域对应的读电压，由于第一存储区域包括的多个物理位置的物理特性和读电压特性相同或相似，且读电压管理信息中的读电压是动态更新的，从而可以保证获取的读电压的准确性，基于该读电压获取请求数据时，可以提高首次读成功率，减少读操作次数，进而降低了读延时。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种降低读延时的方法，其特征在于，应用于控制器中，所述控制器的前端连接主机，后端连接Flash阵列，所述方法包括：
    所述控制器接收主机发送的读请求，所述读请求中包括请求数据的位置指示信息；
    所述控制器根据所述位置指示信息所指示的第一物理位置，从读电压管理信息中获取所述第一物理位置所在的第一存储区域对应的读电压；其中，所述第一物理位置为所述请求数据在所述Flash阵列中的物理位置，所述Flash阵列中包括多个存储区域，同一存储区域中包含的多个物理位置的物理特性相同或相似，所述读电压管理信息包括存储区域与读电压之间的对应关系，所述读电压管理信息中的读电压是动态更新的；
    所述控制器根据所述第一存储区域对应的读电压，获取所述请求数据，并将所述请求数据发送给所述主机。
  2. 根据权利要求1所述的方法，其特征在于，同一存储区域中包含的物理位置的读电压特性相同或相似；和/或，不同存储区域包含的物理位置的物理特性不同；和/或，不同存储区域包含的物理位置的读电压特性不同。
  3. 根据权利要求1或2所述的方法，其特征在于，所述读电压管理信息中的读电压是动态更新的，包括：
    对于所述多个存储区域中的任一存储区域，当满足预设更新条件时，所述控制器更新所述读电压管理信息中所述存储区域对应的读电压。
  4. 根据权利要求3所述的方法，其特征在于，所述当满足预设更新条件时，所述控制器更新所述读电压管理信息中所述存储区域对应的读电压，包括：
    当处于系统空闲时间窗或者满足预设更新周期时，所述控制器确定所述存储区域对应的读电压下的第一出错参数；
    当所述第一出错参数大于或等于第一阈值时，所述控制器更新所述读电压管理信息中所述存储区域对应的读电压。
  5. 根据权利要求4所述的方法，其特征在于，所述预设更新周期与所述存储区域的使用状态相关；或者，所述预设更新周期与所述Flash阵列包括的多个存储区域的平均使用寿命相关。
  6. 根据权利要求3-5任一项所述的方法，其特征在于，所述当满足预设更新条件时，所述控制器更新所述读电压管理信息中所述存储区域对应的读电压，包括：
    当在所述存储区域对应的读电压下，首次读取的请求数据的第二出错参数大于或等于第一阈值时，所述控制器更新所述读电压管理信息中所述存储区域对应的读电压。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，
    对于所述多个存储区域中的任一个存储区域，当所述控制器在第一时间段内更新所述读电压管理中所述存储区域对应的读电压、在第二时间段内从所述读电压管理中获取所述存储区域对应的读电压时，所述第一时间段与所述第二时间段不存在重叠；和/或，
    对于所述多个存储区域中的任意两个存储区域，当所述控制器在第三时间段内更新所述读电压管理中一个存储区域对应的读电压、在第四时间段内从所述读电压管理 中获取另一个存储区域对应的读电压时，所述第一时间段与所述第二时间段存在重叠、或者所述第一时间段与所述第二时间段不重叠。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，一个存储区域包括至少一个存储单元，所述存储单元包括以下中的至少一项：颗粒Device、逻辑单元Die、面Plane、块Block、超级块Super Block、层Layer、子块Sub-Block、字线WL和页面Page。
  9. 一种系统，其特征在于，所述系统包括主机、控制器和Flash阵列，所述Flash阵列中包括多个存储区域，同一存储区域中包含的多个物理位置的物理特性相同或相似；
    所述主机，用于向所述控制器发送读请求，以及接收所述控制器返回的请求数据，所述读请求包括所述请求数据的位置指示信息；
    所述控制器，用于管理读电压管理信息，所述读电压管理信息包括存储区域与读电压之间的对应关系，所述读电压管理信息中的读电压是动态更新的；
    所述控制器，还用于当接收到所述读请求时，根据所述位置指示信息所指示的第一物理位置，从所述读电压管理信息中获取所述第一物理位置所在的第一存储区域对应的读电压，所述第一物理位置为所述请求数据在所述Flash阵列中的物理位置；
    所述控制器，还用于根据所述第一存储区域对应的读电压，获取所述请求数据，并将所述请求数据发送给所述主机。
  10. 根据权利要求9所述的系统，其特征在于，同一存储区域中包含的物理位置的读电压特性相同或相似；和/或，不同存储区域包含的物理位置的物理特性不同；和/或，不同存储区域包含的物理位置的读电压特性不同。
  11. 根据权利要求9或10所述的系统，其特征在于，所述控制器，具体用于：
    对于所述多个存储区域中的任一存储区域，当满足预设更新条件时，更新所述读电压管理信息中所述存储区域对应的读电压，以使所述读电压管理信息中的读电压是动态更新的。
  12. 根据权利要求11所述的系统，其特征在于，所述控制器，具体用于：
    当处于系统空闲时间窗或者满足预设更新周期时，确定所述存储区域对应的读电压下的第一出错参数；
    当所述第一出错参数大于或等于第一阈值时，更新所述读电压管理信息中所述存储区域对应的读电压。
  13. 根据权利要求12所述的系统，其特征在于，所述预设更新周期与所述存储区域的使用状态相关；或者，所述预设更新周期与所述Flash阵列中多个存储区域的平均使用寿命相关。
  14. 根据权利要求11-13任一项所述的系统，其特征在于，所述控制器，具体用于：
    当在所述存储区域对应的读电压下，首次读取的请求数据的第二出错参数大于或等于第一阈值时，更新所述读电压管理信息中所述存储区域对应的读电压。
  15. 根据权利要求9-14任一项所述的系统，其特征在于，
    对于所述多个存储区域中的任一个存储区域，当所述控制器在第一时间段内更新所述读电压管理中所述存储区域对应的读电压、在第二时间段内从所述读电压管理中 获取所述存储区域对应的读电压时，所述第一时间段与所述第二时间段不存在重叠；和/或，
    对于所述多个存储区域中的任意两个存储区域，当所述控制器在第三时间段内更新所述读电压管理中一个存储区域对应的读电压、在第四时间段内从所述读电压管理中获取另一个存储区域对应的读电压时，所述第一时间段与所述第二时间段存在重叠、或者所述第一时间段与所述第二时间段不重叠。
  16. 根据权利要求9-15任一项所述的系统，其特征在于，一个存储区域包括至少一个存储单元，所述存储单元包括以下中的至少一项：颗粒Device、逻辑单元Die、面Plane、块Block、超级块Super Block、层Layer、子块Sub-Block、字线WL和页面page。
  17. 一种可读存储介质，其特征在于，所述可读存储介质中存储有指令，当所述可读存储介质在设备上运行时，使得所述设备执行权利要求1-8任一项所述的降低读延时的方法。
  18. 一种计算机程序产品，其特征在于，当所述计算机程序产品在计算机上运行时，使得所述计算机执行权利要求1-8任一项所述的降低读延时的方法。
PCT/CN2018/116257 2017-11-27 2018-11-19 一种降低读延时的方法及装置 WO2019101044A1 (zh)

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