WO2019095546A1 - Thin film transistor and manufacturing method therefor, and tft substrate - Google Patents

Thin film transistor and manufacturing method therefor, and tft substrate Download PDF

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Publication number
WO2019095546A1
WO2019095546A1 PCT/CN2018/072645 CN2018072645W WO2019095546A1 WO 2019095546 A1 WO2019095546 A1 WO 2019095546A1 CN 2018072645 W CN2018072645 W CN 2018072645W WO 2019095546 A1 WO2019095546 A1 WO 2019095546A1
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gate
insulating layer
region
contact hole
active region
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PCT/CN2018/072645
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French (fr)
Chinese (zh)
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李子然
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深圳市华星光电技术有限公司
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Priority to CN201711161346.XA priority patent/CN108010850A/en
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2019095546A1 publication Critical patent/WO2019095546A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Abstract

A method for manufacturing a thin film transistor, comprising: on a substrate, sequentially forming a first gate and a first insulating layer that covers the first gate; forming an active region on the first insulating layer, the active region directly facing the first gate in a direction perpendicular to the substrate, and a projection of two opposite ends of the first gate on the first insulating layer being located outside of the active region; depositing a second insulating layer that covers the active region; opening a first contact hole and a second contact hole on the second insulating layer, the first contact hole and the second contact hole penetrating the first insulating layer; on the second insulating layer, forming a second gate that directly faces the first gate, two ends of the second gate being electrically connected to two ends of the first gate by means of the first contact hole and the second contact hole. Further provided by the present application are a thin film transistor and a thin film transistor (TFT) substrate.

Description

Thin film transistor and manufacturing method thereof, TFT substrate

This application claims the priority of the Chinese Patent Application entitled "Thin Film Transistor and Its Fabrication Method, TFT Substrate" filed on November 20, 2017 by the Chinese Patent Office, Application No. 201711161346.X, the content of the above-mentioned prior application is The manner of introduction is incorporated into this text.

Technical field

The present application relates to the field of display technologies, and in particular, to a thin film transistor, a method for fabricating the same, and a TFT substrate.

Background technique

With the development of the display screen, the size of the pixel electrode in the display screen is designed to be smaller and smaller, and the performance requirements of the display screen are getting higher and higher. The carrier transport characteristics of a TFT substrate with a single gate structure change after a long period of operation, and the threshold voltage of the TFT substrate may be forward-shifted or negatively shifted with the extension of the working time, affecting the TFT. The switching characteristics make the performance stability of the display.

Summary of the invention

The present application provides a thin film transistor, a method for fabricating the same, and a TFT substrate, which can reduce the driving voltage of the device, effectively prevent variations in the threshold voltage of the TFT, and improve the switching characteristics of the TFT.

The application provides a method for fabricating a thin film transistor, comprising:

Forming a first gate and a first insulating layer covering the first gate on the substrate;

Forming an active region on the first insulating layer, in a direction perpendicular to the substrate, the active region is opposite to the first gate, and opposite ends of the first gate are at a projection on the first insulating layer is located outside the active region;

Depositing a second insulating layer covering the active region;

Opening a first contact hole and a second contact hole on the second insulating layer, the first contact hole and the second contact hole penetrating the first insulating layer;

Forming a second gate facing the first gate on the second insulating layer, and both ends of the second gate pass through the first contact hole and the second contact hole The opposite ends of the first gate are electrically connected.

Wherein in the step of molding the active region on the first insulating layer, the extending direction of the active region intersects with the extending direction of the first gate, and the active region includes the first facing a channel region of the gate, the first contact hole and the second contact hole being located on opposite sides of the channel region.

In the step of molding the second gate on the second insulating layer, a projection area of the second gate on the substrate coincides with a projection area of the first gate on the substrate .

Wherein, in the step of molding the first gate on the substrate, a source is formed on the substrate, and the source is spaced apart from the second gate.

Wherein, in the step of molding the active region on the first insulating layer, the active region is made of an oxide semiconductor, and the active region further includes a first region at opposite ends of the channel region and a second area, the first area being adjacent to the source;

After the step of forming a second gate on the second insulating layer, the second gate is aligned with the active region by a self-aligning method, and the first region and the first The two regions are doped to conduct the first region and the second region.

Wherein, after the step of conducting the non-channel region, the method comprises:

Depositing a dielectric layer on the second gate;

Forming a first via and a second via on the dielectric layer, the first via communicating with a first region of the active region and the source, the second via communicating with the active The second area of the district;

Forming a first pixel electrode and a second pixel electrode on the dielectric layer, the first pixel electrode electrically connecting the first region and the source through the first via, and the second pixel electrode The second region is electrically connected through the second via.

The present application provides a thin film transistor including a substrate, a first gate disposed on the substrate, a first insulating layer, an active region, a second insulating layer, and a second gate, the first insulating layer covering The first gate, the active region is opposite to the first gate, and a projection of opposite ends of the first gate on the first insulating layer is located outside the active region The second insulating layer covers the active region and the first insulating layer, and the second insulating layer is provided with a first contact hole and a second contact hole, the first contact hole and the first Two contact holes penetrating the first insulating layer, the second gate is opposite to the first gate, and both ends of the second gate pass through the first contact hole and the second contact hole And electrically connected to opposite ends of the first gate.

Wherein the thin film transistor further includes a source, the source is located in a same layer of the first gate, the active region includes a channel region facing the first gate, and connecting the trench A first area and a second area at both ends of the track zone, the first area being adjacent to the source.

The thin film transistor further includes a dielectric layer disposed on the second gate, the dielectric layer is provided with a first via and a second via, and the first via communicates with the first region And the source, the second via is connected to the second region; the thin film transistor further includes a first pixel electrode and a second pixel electrode on the dielectric layer, wherein the first pixel electrode passes through The first via is electrically connected to the first region and the source, and the second pixel is electrically connected to the second region through the second via.

The present application provides a TFT substrate including the thin film transistor.

The present invention provides a thin film transistor by forming opposite first and second gates on upper and lower sides of an active region, and forming first contact holes and second holes on left and right sides of the active region a contact hole, the first contact hole and the second contact hole electrically connecting the first gate and the second gate, thereby forming a ring gate structure on a circumference side of the active layer such that an effective area of the gate The increase, improve the conductivity of the conductive channel of the active region, reduce the device driving voltage, effectively prevent the threshold voltage variation of the TFT, and improve the switching characteristics of the TFT.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present application.

Figure 2 is a schematic view of the structure of Figure 1 along the AA' direction.

3 is a flow chart of a method for fabricating a thin film transistor according to an embodiment of the present application.

4 is a schematic diagram of step S102 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 5 is a schematic diagram of step S102 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 6 is a schematic diagram of step S104 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 7 is a schematic diagram of step S104 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 8 is a schematic diagram of step S106 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 9 is a schematic diagram of step S106 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 10 is a schematic diagram of step S107 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 11 is a schematic diagram of step S107 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 12 is a schematic diagram of step S110 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 13 is a schematic diagram of step S110 in the method of fabricating a thin film transistor according to an embodiment of the present application.

FIG. 14 is a schematic diagram of step S111 in the method of fabricating a thin film transistor according to an embodiment of the present application.

Detailed ways

The above described objects, features and advantages of the present application will be more clearly understood from the following description in conjunction with the appended claims. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments of the present application may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without departing from the inventive scope are the scope of the present application.

In addition, the description of the following embodiments is provided with reference to the accompanying drawings. Directional terms mentioned in this application, for example, "top", "bottom", "upper", "lower", "front", "back", "left", "right", "inside", "outside" """"""""""""""""""" The specific orientation, construction and operation in a particular orientation are not to be construed as limiting the invention.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a schematic structural diagram of a thin film transistor 100 according to an embodiment of the present application. Figure 2 is a cross-sectional view of Figure 1 taken along the line AA'. The thin film transistor 100 includes a substrate 110, a first gate 120 disposed on the substrate 110, a source 130, a first insulating layer 140, an active region 150, a second insulating layer 160, and a second gate 170. Dielectric layer 180 and pixel electrode layer.

In this embodiment, the substrate 110 may be a glass substrate or a flexible substrate. In some applications, a silicon dioxide substrate, or a polyvinyl chloride (PV) or a fusible polytetrafluoroethylene (Polytetrafluoroethylene) may also be used. , PFA), polyethylene terephthalate (PET) substrate, and the like.

Referring to FIG. 1 and FIG. 2 , the first gate 120 and the source 130 are located on the substrate 110 . The source 130 and the first gate 120 extend along a first direction x1, and the source 130 is spaced apart from the first gate 120.

In this embodiment, the first gate 120 and the source 130 may be formed in the same process. Optionally, the materials of the first gate 120 and the source 130 may be the same. They may be made of a single metal layer or a composite metal layer such as Cr, Mo, Mo/Al, MoTi, Cu, or the like.

Referring to FIG. 1 , the first insulating layer 140 covers the first gate 120 and the source 130 . The material of the first insulating layer 140 may be SiOx or SiNx or a laminated structure of SiOx and SiNx or other insulating materials. When the first insulating layer 140 is a laminated structure of SiOx and SiNx, SiOx is disposed on a side close to the active region 150.

Referring to FIG. 1 , the active region 150 faces the first gate 120 , and a projection of opposite ends of the first gate 120 on the first insulating layer 140 is located in the active region. 150 outside. The active region 150 extends along a second direction x2, and the second direction x2 is perpendicular to the first direction x1.

In one embodiment, the material of the active region 150 is an oxide semiconductor. Specifically, it may be an oxide semiconductor film layer such as IZO or IGZO, in which the film thickness of the IGZO oxide semiconductor film layer is 500A.

In this embodiment, referring to FIG. 1, the active region 150 includes a channel region 151 and a first region 152 and a second region 153 connected to both ends of the channel region 151. The channel region 151 is a region where the active region 150 overlaps with the first gate 120. The first region 152 is adjacent to the source 130. The first region 152 and the second region 153 are respectively disposed on opposite sides of the first gate 120 along the second direction x2. The material of the channel region 151 is an oxide semiconductor. Specifically, it may be an oxide semiconductor film layer such as IZO (indium zinc oxide) or IGZO (indium gallium zinc oxide).

Among them, a-IGZO (amorphous indium gallium zinc oxide) material is a channel layer material used in a new generation of thin film transistor technology for manufacturing a metal oxide display panel. a-IGZO TFT (amorphous indium gallium zinc oxide thin film transistor) has high carrier mobility, high switching ratio, low threshold voltage, high transmittance, and a simple fabrication process similar to a-Si, which can be applied to An AMOLED (Active Matrix Organic Light Emitting Diode) / High Order AMLCD (Active Matrix Liquid Crystal Display) circuit is fabricated.

The material of the first region 152 and the second region 153 is a doped oxide semiconductor, and the first region 152 and the second region 153 are doped and then conductorized.

Referring to FIG. 1, the second insulating layer 160 covers the active region 150 and the first insulating layer 140. The material of the second insulating layer 160 may be SiOx or SiNx or a laminated structure of SiOx and SiNx or other insulating materials. When the second insulating layer 160 is a laminated structure of SiOx and SiNx, SiOx is disposed on a side close to the active region 150.

Referring to FIG. 2, the second insulating layer 160 is provided with a first contact hole 161 and a second contact hole 162. The first contact hole 161 and the second contact hole 162 are distributed in a direction in which the first direction x1 extends, on opposite sides of the channel region 151. The first contact hole 161 and the second contact hole 162 penetrate the second insulating layer 160 and the first insulating layer 140 and communicate with the first end 121 and the second end of the first gate 120 122.

Referring to FIG. 1 and FIG. 2 , the second gate 170 is located on the second insulating layer 160 and is patterned to face the first gate 120 .

Optionally, the second gate 170 may be the same shape, size, and material as the first gate 120.

Optionally, a metal material is deposited on the second insulating layer 160, and the metal material fills the first contact hole 161 and the second contact hole 162. The metal material forms a second gate 170 on the second insulating layer 160.

Referring to FIG. 1 and FIG. 2 , the second gate 170 covers the first contact hole 161 and the second contact hole 162 , and both ends of the second gate 170 pass through the first contact hole 161 . And the second contact hole 162 is electrically connected to the first end 121 and the second end 122 of the first gate 120.

In this embodiment, referring to FIG. 1 and FIG. 2, the first gate 120 and the second gate 170 are formed on the upper and lower sides of the active region 150 (in the vertical direction in FIG. 2), and A first contact hole 161 and a second contact hole 162 are formed on the left and right sides of the source region 150 (in the first direction x1 in FIG. 2), and the first contact hole 161 and the second contact hole 162 are electrically connected to the first gate 120 and the second gate 170, thereby forming a ring gate structure on a circumference side of the active layer, so that an effective area of the gate is increased, the conductivity of the conductive channel of the active region 150 is improved, and device driving is reduced. The voltage effectively prevents variations in the threshold voltage of the TFT and improves the switching characteristics of the TFT.

Further, referring to FIG. 1 , the thin film transistor 100 further includes a dielectric layer 180 disposed on the second gate 170 . The dielectric layer 180 is provided with a first via 181 and a second via 182. The first via 181 and the second via 182 extend through the dielectric layer 180. The first via 181 communicates with the first region 152 and the source 130. The second via 182 communicates with the second region 153. The thin film transistor 100 further includes a first pixel electrode 191 and a second pixel electrode 192 on the dielectric layer 180. The first pixel electrode 191 and the second pixel electrode 192 are spaced apart. The first pixel electrode 191 is filled in the first via hole 181 and electrically connects the first region 152 and the source 130. The second pixel electrode 192 partially fills the second via 182, another portion is formed with the surface of the dielectric layer 180, and the second pixel electrode 192 is connected to the second region through the second via 182 153.

Optionally, the material of the first pixel electrode 191 and the second pixel electrode 192 is an ITO film. The first pixel electrode 191 and the second pixel electrode 192 may be formed in the same process.

Since the first region 152 and the second region 153 are electrically connected, the first region 152 is electrically connected to the source 130, and may serve as the source 130 of the thin film transistor 100, and the second region 153 may serve as a The drain of the thin film transistor 100 is described.

The embodiment of the present application provides a TFT substrate 100 including the thin film transistor 100.

In the TFT substrate 100, the first gate electrode 120 and the second gate electrode 170 are formed on the upper and lower sides (in the vertical direction in the drawing) of the active region 150, and on the left and right sides of the active region 150 ( A first contact hole 161 and a second contact hole 162 are formed in the first direction x1 in the drawing, and the first contact hole 161 and the second contact hole 162 are electrically connected to the first gate 120 and the second gate 170 Therefore, the ring gate structure is formed on the circumferential side of the active layer, so that the effective area of the gate is increased, the conductivity of the conductive channel of the active region 150 is improved, the driving voltage of the device is lowered, and the threshold voltage of the TFT is effectively prevented from being changed. Improve the switching characteristics of the TFT.

Referring to FIG. 3 , the embodiment of the present application further provides a method for fabricating a TFT substrate 100 , which can be used to prepare the TFT substrate 100 according to any of the above embodiments. Specifically, the following step S100 is included.

Step S101, providing a substrate 110. The substrate 110 may be a transparent material, and may specifically be a water-proof and oxygen-proof transparent organic material or glass. Commonly used are glass substrate 110, silicon dioxide substrate 110, and some applications may use polyvinyl chloride (PV), fusible polytetrafluoroethylene (PFA), polyethylene terephthalate. (Polyethylene terephthalate, PET) substrate 110 and the like.

Step S102, referring to FIG. 4 and FIG. 5, the first gate 120 is formed on the substrate 110.

Specifically, the method includes: depositing a metal material on the substrate 110, and the metal material may be a single metal layer or a composite metal layer, such as Cr, Mo, Mo/Al, MoTi, Cu, or the like. A process such as photoresist coating, exposure, development, etching, and photoresist stripping is performed to form a first gate electrode 120 and a source electrode 130 having a predetermined pattern. The source 130 is spaced apart from the second gate 170. The first gate 120 can be formed in a process of forming the source 130 without additional steps, saving time and cost.

Step S103, referring to FIG. 6, depositing a first insulating layer 140 covering the first gate 120 on the substrate 110.

A single layer of a silicon oxide (SiO2) film layer or a silicon nitride (SiNx) film layer, or a stack of silicon oxide (SiO2) and silicon nitride (SiNx), is deposited by chemical vapor deposition (CVD) and a yellow photolithography process. A layer is formed to form a first insulating layer 140 overlying the substrate 110, the first gate 120, and the source 130.

Step S104, referring to FIG. 6 and FIG. 7, an active region 150 is formed on the first insulating layer 140. In the direction perpendicular to the substrate 100, the active region 150 faces the first gate 120, and the opposite ends of the first gate 120 are projected on the first insulating layer 140 Located outside of the active area 150.

Specifically, the active region 150 is opposite to the first gate 120, and a central region of the first gate 120 may coincide with a central region of the active region 150, the first gate 120 and the active regions 150 may partially overlap. The first gate 120 includes a first end 121 and a second end 122, and a projection of the first end 121 and the second end 122 on the first insulating layer 140 is outside the active region 150.

A semiconductor material is deposited on the first insulating layer 140, and the semiconductor material is an oxide semiconductor, for example, IZO, IGZO, or the like. The semiconductor material is patterned to form an active region 150 having a predetermined pattern.

In some possible implementations, the extending direction of the active region 150 intersects with the extending direction of the first gate 120. Specifically, the extending direction of the first gate 120 is perpendicular to the extending direction of the active region 150.

In some possible implementations, referring to FIG. 8 and FIG. 9, the active region 150 includes a channel region 151 facing the first gate 120, and a first portion at opposite ends of the channel region 151. Region 152 and second region 153. The first region 152 and the second region 153 are respectively located at two sides of the first gate 120, and the first region 152 is adjacent to the source 130.

Step S105, referring to FIG. 8 and FIG. 9, a second insulating layer 160 is deposited on the active region 150.

A single layer of a silicon oxide (SiO2) film layer or a silicon nitride (SiNx) film layer, or a stack of silicon oxide (SiO2) and silicon nitride (SiNx), is deposited by chemical vapor deposition (CVD) and a yellow photolithography process. A layer is formed to form a second insulating layer 160 overlying the active region 150 and the first insulating layer 140.

Step S106, referring to FIG. 8 and FIG. 9, etching the second insulating layer 160, and forming a first contact hole 161 and a second contact hole 162 on the second insulating layer 160. The first contact hole 161 and the second contact hole 162 penetrate the first insulating layer 140 and the second insulating layer 160 and communicate with the first end 121 and the second end 122 of the first gate 120. The first contact hole 161 and the second contact hole 162 are located on opposite sides of the channel region 151.

Step S107, referring to FIG. 10 and FIG. 11, a metal material is deposited on the second insulating layer 160, and the metal material is patterned to form the second gate 170. The second gate 170 is opposite to the first gate 120, and both ends of the second gate 170 pass through the first contact hole 161 and the second contact hole 162 and the first gate The first end 121 and the second end 122 of the pole 120 are electrically connected.

Optionally, the second gate 170 may be the same shape, size, and material as the first gate 120.

Optionally, a metal material is deposited on the second insulating layer 160, and the metal material fills the first contact hole 161 and the second contact hole 162. The metal material forms a second gate 170 on the second insulating layer 160.

The first gate electrode 120 and the second gate electrode 170 are formed on the upper and lower sides of the active region 150 (in the vertical direction in the drawing), and are on the left and right sides of the active region 150 (in the first direction in the drawing) Forming a first contact hole 161 and a second contact hole 162, the first contact hole 161 and the second contact hole 162 electrically connecting the first gate electrode 120 and the second gate electrode 170, thereby having The circumferential side of the source layer forms a ring gate structure such that the effective area of the gate increases, increasing the conductivity of the conductive channel of the active region 150.

In some possible implementations, a projection area of the second gate 170 on the substrate 110 coincides with a projection area of the first gate 120 on the substrate 110 to make the ring gate The structure does not affect the aperture ratio.

In some possible implementations, the width of the channel region 151 is consistent with the width of the first gate 120 and the second gate 170 in the x2 direction.

In some possible implementation manners, referring to FIG. 9 and FIG. 11 , when the second gate 170 is formed, the scan signal line 163 is formed on the substrate 110 , and the second contact hole 162 is electrically connected to the scan signal line 163 to The ring gate structure is electrically connected to the scan signal line 163.

In this embodiment, after the step of forming the second gate 170 on the second insulating layer 160, in step S108, referring to FIG. 12 and FIG. 13, the second gate 170 is paired by a self-alignment method. The active region 150 is quasi-doped to do the first region 152 and the second region 153 to electrically conduct the first region 152 and the second region 153.

After the step of conducting the non-channel region 151, the method includes:

Step S109, referring to FIG. 12 and FIG. 13, a dielectric layer 180 is deposited on the second gate 170.

Specifically, a single layer of a silicon oxide (SiO2) film layer or a silicon nitride (SiNx) film layer is deposited by chemical vapor deposition (CVD) and a yellow light etching process, or is silicon oxide (SiO2) and silicon nitride (SiNx). The laminate is formed to form a dielectric layer 180.

Step S110, referring to FIG. 12 and FIG. 13, etching the dielectric layer 180, and forming a first via 181 and a second via 182 on the dielectric layer 180. The first via 181 communicates with the first region 152 of the active region 150 and the source 130 , and the second via 182 communicates with the second region 153 of the active region 150 .

Step S111, referring to FIG. 1 and FIG. 14, depositing a pixel electrode layer 190 on the dielectric layer 180, and patterning the pixel electrode layer 190, forming a first pixel electrode 191 and a second on the dielectric layer 180. Pixel electrode 192. A portion of the pixel electrode layer is filled in the first via hole 181, and the first pixel electrode 191 is formed to electrically connect the first region 152 and the source electrode 130. A portion of the pixel electrode layer is filled in the second via hole 182, and a second pixel electrode 192 is formed on the dielectric layer 180, and the second pixel electrode 192 is electrically connected to the second region 153 through the second via hole 182.

It should be noted that the above embodiments are only used to explain the technical solutions of the present application, and are not limited thereto. Although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technology of the present application can be applied. Modifications or equivalents of the embodiments are not to be construed as a departure from the spirit and scope of the invention.

Claims (12)

  1. A method of fabricating a thin film transistor, comprising:
    Forming a first gate and a first insulating layer covering the first gate on the substrate;
    Forming an active region on the first insulating layer, in a direction perpendicular to the substrate, the active region is opposite to the first gate, and opposite ends of the first gate are at a projection on the first insulating layer is located outside the active region;
    Depositing a second insulating layer covering the active region;
    Opening a first contact hole and a second contact hole on the second insulating layer, the first contact hole and the second contact hole penetrating the first insulating layer;
    Forming a second gate facing the first gate on the second insulating layer, and both ends of the second gate pass through the first contact hole and the second contact hole The opposite ends of the first gate are electrically connected.
  2. The thin film transistor manufacturing method according to claim 1, wherein in the step of molding the active region on the first insulating layer, an extending direction of the active region intersects with an extending direction of the first gate, The active region includes a channel region facing the first gate, and the first contact hole and the second contact hole are located on opposite sides of the channel region.
  3. The thin film transistor manufacturing method according to claim 1, wherein in the step of forming a second gate on the second insulating layer, a projection area of the second gate on the substrate and the first The projected areas of the gates on the substrate coincide.
  4. The thin film transistor manufacturing method according to claim 1, wherein in the step of molding the first gate on the substrate, a source is formed on the substrate, and the source is spaced apart from the second gate .
  5. The thin film transistor manufacturing method according to claim 2, wherein in the step of molding the active region on the first insulating layer, the active region is made of an oxide semiconductor, and the active region further includes a first region and a second region at opposite ends of the channel region, the first region being adjacent to the source;
    After the step of forming a second gate on the second insulating layer, the second gate is aligned with the active region by a self-aligning method, and the first region and the first The two regions are doped to conduct the first region and the second region.
  6. The method of fabricating a thin film transistor according to claim 5, wherein after the step of conducting the conductor of the non-channel region, the method comprises:
    Depositing a dielectric layer on the second gate;
    Forming a first via and a second via on the dielectric layer;
    Forming a first pixel electrode and a second pixel electrode on the dielectric layer, the first pixel electrode electrically connecting the first region and the source through the first via, and the second pixel electrode The second region is electrically connected through the second via.
  7. A thin film transistor, comprising: a substrate, a first gate disposed on the substrate, a first insulating layer, an active region, a second insulating layer, and a second gate, wherein the first insulating layer covers the a first gate, the active region is opposite to the first gate, and a projection of opposite ends of the first gate on the first insulating layer is located outside the active region, a second insulating layer covering the active region and the first insulating layer, wherein the second insulating layer is provided with a first contact hole and a second contact hole, the first contact hole and the second contact a hole penetrating the first insulating layer, the second gate is opposite to the first gate, and both ends of the second gate pass through the first contact hole and the second contact hole The opposite ends of the first gate are electrically connected.
  8. The thin film transistor of claim 7, wherein the thin film transistor further comprises a source, the source is located in a same layer of the first gate, and the active region includes a first gate opposite a channel region, and a first region and a second region connecting the two ends of the channel region, the first region being adjacent to the source.
  9. The thin film transistor of claim 8, wherein the thin film transistor further comprises a dielectric layer disposed on the second gate, wherein the dielectric layer is provided with a first via and a second via, The thin film transistor further includes a first pixel electrode and a second pixel electrode on the dielectric layer, the first pixel electrode electrically connecting the first region and the source through the first via, and the The second pixel electrode is electrically connected to the second region through the second via.
  10. A TFT substrate, comprising a thin film transistor, the thin film transistor comprising a substrate, a first gate disposed on the substrate, a first insulating layer, an active region, a second insulating layer and a second gate a first insulating layer covering the first gate, the active region is opposite to the first gate, and a projection of opposite ends of the first gate on the first insulating layer is located An outer surface of the active region, the second insulating layer covers the active region and the first insulating layer, and the second insulating layer is provided with a first contact hole and a second contact hole, the first The contact hole and the second contact hole penetrate through the first insulating layer, the second gate faces the first gate, and both ends of the second gate pass through the first contact hole and The second contact hole is electrically connected to opposite ends of the first gate.
  11. The TFT substrate of claim 10, wherein the thin film transistor further comprises a source, the source is located in a same layer of the first gate, and the active region includes a first gate opposite a channel region, and a first region and a second region connecting the two ends of the channel region, the first region being adjacent to the source.
  12. The TFT substrate according to claim 11, wherein the thin film transistor further comprises a dielectric layer disposed on the second gate, wherein the dielectric layer is provided with a first via and a second via, The thin film transistor further includes a first pixel electrode and a second pixel electrode on the dielectric layer, the first pixel electrode electrically connecting the first region and the source through the first via, and the The second pixel electrode is electrically connected to the second region through the second via.
PCT/CN2018/072645 2017-11-20 2018-01-15 Thin film transistor and manufacturing method therefor, and tft substrate WO2019095546A1 (en)

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KR20020048487A (en) * 2000-12-18 2002-06-24 김순택 Flat display device and method for fabricating thereof
CN106684155A (en) * 2017-01-05 2017-05-17 京东方科技集团股份有限公司 Dual-gate thin film transistor and preparation method therefor, array substrate and display apparatus
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