WO2019084085A1

WO2019084085A1 - Method and apparatus for enabling wide input common-mode range in sar adcs with no additional active circuitry

Info

Publication number: WO2019084085A1
Application number: PCT/US2018/057212
Authority: WO
Inventors: Anders VINJE; Ivar LØKKEN
Original assignee: Microchip Technology Inc
Current assignee: Microchip Technology Inc
Priority date: 2017-10-24
Filing date: 2018-10-24
Publication date: 2019-05-02
Anticipated expiration: 2020-04-24
Also published as: DE112018004698B4; KR102656345B1; TW201924227A; TWI778155B; CN111034052A; KR20200074084A; DE112018004698T5; JP6944047B2; US10547321B2; JP2020537368A; CN111034052B; US20190123758A1

Abstract

A differential successive approximation register (SAR) analog-to-digital converter (ADC) with wide input common-mode range adds one step to its conversion process. No additional circuitry is required for full rail-to-rail common mode voltage operation. In a first step the top-plate nodes vcp and vcn may be reset to a fixed voltage vcm. Then in a next step sampling may be performed while leaving vcp and vcn floating but shorted. Whereby a single node vx is formed, which provides for simple capacitive voltage division. Thereafter a standard sequential SAR bit-by-bit analog-to-digital conversion is performed. the voltage at node vx will follow vcmin during the entire sampling phase, with a limitation in rate of change only limited by the RC time constant of the shorting switch and the sampling capacitors. This will have much higher bandwidth than any active OTA-based tracking circuit.

Description

METHOD AND APPARATUS FOR ENABLING WIDE INPUT COMMON-MODE RANGE IN SAR ADCS WITH NO ADDITIONAL ACTIVE CIRCUITRY

RELATED PATENT APPLICATION

This application claims priority to commonly owned United States Provisional Patent Application Serial Number 62/576,350; filed October 24, 2017; entitled "Method for Enabling Wide Input Common-Mode Range in SAR ADCs with No Additional Active Circuitry," by Anders Vinje and Ivar L0kken; and is hereby incorporated by reference herein for all purposes.

TECHNICAL FIELD

The present disclosure relates to analog-to-digital converters (ADC) and, more particularly, to enabling wide input common-mode range in successive approximation register (SAR) ADCs with no additional active circuitry.

BACKGROUND

A successive approximation register (SAR) analog-to-digital converter (ADC) is a type of analog-to-digital converter that converts a continuous analog waveform into discrete digital representations by performing a binary search to converge to the closest quantization level of each sample taken of the analog waveform then providing a digital representations thereof.

SAR ADCs are among the most popular ADC architectures, and may be used in, for example, microcontrollers. A typical differential SAR ADC, including most on the market, have limited input common-mode range which can lead to reduced performance or failure if the input common-mode exceeds the SAR DAC's allowable range. This makes differential SAR ADCs less suited for applications where the input common-mode voltage cannot be controlled, like certain sensor applications, zero-crossing detection and more. This may be circumvented by using additional active circuitry, as shown in Figure 2, to sample the input common-mode voltage and subtract it during conversion as so as to cancel out its effects. This however is costly in terms of current consumption and integrated circuit die area, and also puts limitations on the input common-mode rate of change allowed.

SUMMARY

Therefore, what is needed is a differential SAR ADC that has better common-mode voltage rejection and amplitude handling capabilities while requiring minimal or no additional circuitry.

According to an embodiment, a method for providing wide input common-mode range in a successive approximation register (SAR) analog-to-digital convertor (ADC) may comprise the steps of: resetting top plate nodes vcp and vcn of a plurality of binary weighted capacitors to a voltage vcm; sampling differential voltages Vinp and Vinn on bottom plate nodes vcp and vcn, respectively, while coupling the top plate nodes vcp and vcn together and floating; and performing a sequential SAR analog-to-digital conversion on the sampled differential voltages Vinp and Vinn.

According to a further embodiment of the method, the SAR ADC may be a differential input SAR ADC. According to a further embodiment of the method, the SAR ADC may be fabricated in integrated circuit device. According to a further embodiment of the method, the integrated circuit device may be a microcontroller.

According to another embodiment, a method for providing wide input common- mode range in a successive approximation register (SAR) analog-to-digital converter (ADC), may comprise the steps of: coupling top plates of a first half of a plurality of binary weighted capacitors to a first input of a voltage comparator and coupling top plates of a second half of the plurality of binary weighted capacitors to a second input of the voltage comparator; coupling a top plate of a first dummy capacitor to the first input of the voltage comparator and coupling a top plate of a second dummy capacitor to the second input of the voltage comparator; coupling a previous first reference voltage to bottom plates of the first half of the plurality of binary weighted capacitors; coupling a previous second reference voltage to bottom plates of the second half of the plurality of binary weighted capacitors; coupling a third reference voltage to the top plates of the plurality of binary weighted capacitors, and to the top and bottom plates of the first and second dummy capacitors; decoupling the bottom plates of the plurality of binary weighted capacitors from the previous first and second reference voltages; coupling the bottom plates of the first half of the plurality of binary weighted capacitors and the bottom plate of the first dummy capacitor to a positive input voltage, Vinp; coupling the bottom plates of the second half of the plurality of binary weighted capacitors and the bottom plate of the second dummy capacitor to a negative input voltage, Vinn; coupling the top plates of the plurality of binary weighted capacitors and the first and second dummy capacitors together; decoupling the top plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor from the top plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor; coupling the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors to the third reference voltage; determining whether a first voltage on the first input of the voltage comparator is greater than a second voltage on the second input thereof; wherein if the first voltage is greater than the second voltage then provide a first logic level output from the voltage comparator, and if the first voltage is less than the second voltage then provide a second logic level output from the voltage comparator; and continue doing a successive approximation analog-to-digital conversion until finished with the conversion.

According to a further embodiment of the method, the previous first reference voltage may be from a first digital-to-analog converter (DAC), and the previous second reference voltage may be from a second DAC. According to a further embodiment of the method, the previous first and second reference voltages may be Vref, and the third reference voltage may be Vref/2. According to a further embodiment of the method, the first logic level may be a logic high or logic "1", and the second logic level may be a logic low or logic "0". According to a further embodiment of the method, the SAR ADC may be a differential input SAR ADC. According to a further embodiment of the method, the SAR ADC may be fabricated in integrated circuit device. According to a further embodiment of the method, the integrated circuit device may be a microcontroller.

According to yet another embodiment, a successive approximation register (SAR) analog-to-digital converter (ADC) may be comprise circuitry configured to: couple a third reference voltage to top plates of a plurality of binary weighted capacitors and top and bottom plates of first and second dummy capacitors; couple a previous first reference voltage to bottom plates of a first half of the plurality of binary weighted capacitors; couple a previous second reference voltage to bottom plates of a second half of the plurality of binary weighted capacitors; decouple the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors from the respective first, second and third reference voltages; couple together the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors; couple a positive input voltage, Vinp, to the bottom plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor; couple a negative input voltage, Vinn, to the bottom plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor; decouple the bottom plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor from the bottom plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor; compare a voltage Vx at the top plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor with a voltage Vy at the top plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor; wherein if the voltage Vx is greater than the voltage Vy then couple a fourth voltage to the bottom plate of a most significant bit (MSB) one of the first half of the plurality of binary weighted capacitors, couple a fifth voltage to the bottom plate of a MSB one of the second half of the plurality of binary weighted capacitors, and couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors, or if the voltage Vx is less than the voltage Vy then couple the fifth voltage to the bottom plate of the MSB one of the first half of the plurality of binary weighted capacitors, couple the fourth voltage to the bottom plate of the MSB one of the second half of the plurality of binary weighted capacitors, and couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors; and continue doing a successive approximation analog-to- digital conversion until finished with the conversion.

According to a further embodiment, the first previous reference voltage may be from a first digital-to-analog converter; the second previous reference voltage may be from a second digital-to-analog converter; the third reference voltage may be Vref/2; the fourth reference voltage may be zero volts; and the fifth reference voltage may be Vref According to a further embodiment, the successive approximation register (SAR) analog- to-digital converter (ADC) may be a differential input SAR ADC. According to a further embodiment, the SAR ADC may be fabricated in integrated circuit device. According to a further embodiment, the integrated circuit device may be a microcontroller.

According to another embodiment, a SAR ADC may include control circuitry, first capacitors, and second capacitors. Each capacitor of the first capacitors may include a top plate and a bottom plate. The top plate may be closer to the control circuitry than the bottom plate of each of the first capacitors. Each capacitor of the second capacitors may include a top plate and a bottom plate. The top plate may be closer to the control circuitry than the bottom plate of each of the second capacitors. Respective ones of the first capacitors and the second capacitors may form binary weighted capacitor pairs. The control circuitry may be configured to reset the top plates of each of the first capacitors and the top plates of each of the second capacitors to a common mode voltage, sample a first differential voltage on the bottom plates of the first capacitors and sample a second differential voltage on the bottom plates of the second capacitor while coupling the top plates of the first capacitors and the second capacitors while floating, and perform a sequential SAR analog-to-digital conversion on the first and second differential voltages.

In combination with any of the above embodiments, the SAR ADC may further include a first dummy capacitor in parallel with the first capacitors. The first dummy capacitor may include a top plate and a bottom plate, the top plate closer to the control circuitry than the bottom plate of each of the first capacitors. The SAR ADC may include second dummy capacitor in parallel with the second capacitors. The second dummy capacitor may include a top plate and a bottom plate. The top plate may be closer to the control circuitry than the bottom plate of each of the first capacitors. The control circuity may be further configured to couple the top plates of a first portion of the binary weighted capacitor pairs to a first input of a voltage comparator, then couple the top plates of a second portion of the binary weighted capacitor pairs to a second input of the voltage comparator, then couple a top plate of a first dummy capacitor to the first input of the voltage comparator and coupling a top plate of a second dummy capacitor to the second input of the voltage comparator, then couple a previous first reference voltage to bottom plates of the first portion of the binary weighted capacitors, then couple a previous second reference voltage to bottom plates of the second portion of the binary weighted capacitors, then couple a third reference voltage to the top plates of the binary weighted capacitors, and to the top and bottom plates of the first and second dummy capacitors, then decouple the bottom plates of binary weighted capacitors from the previous first and second reference voltages, then couple the bottom plates of the first portion of the binary weighted capacitors and the bottom plate of the first dummy capacitor to a positive input voltage, then couple the bottom plates of the second portion of the binary weighted capacitors and the bottom plate of the second dummy capacitor to a negative input voltage, then couple the top plates of the binary weighted capacitors and the first and second dummy capacitors together, then decouple the top plates of the first portion of the binary weighted capacitors and the first dummy capacitor from the top plates of the second portion of the binary weighted capacitors and the second dummy capacitor, and then couple the bottom plates of the binary weighted capacitors and the first and second dummy capacitors to the third reference voltage. The voltage comparator may be configured to determine whether a first voltage on the first input of the voltage comparator is greater than a second voltage on the second input of the voltage comparator. In combination with any of the above embodiments, the voltage comparator is further configured to may be configured to provide a first logic level output if the first voltage is greater than the second voltage, and then provide a second logic level output if the first voltage is less than the second voltage. In combination with any of the above embodiments, the control circuitry may be further configured to perform successive approximation analog-to-digital conversion until finished with the conversion. In combination with any of the above embodiments, the previous first reference voltage is from a first DAC and the previous second reference voltage is from a second DAC. In combination with any of the above embodiments, the previous first and second reference voltages are a value Vref, and the third reference voltage is a value Vref/2.

Embodiments of the present disclosure include a SAR ADC, including circuitry to configured to couple a third reference voltage to top plates of a plurality of binary weighted capacitors and top and bottom plates of first and second dummy capacitors, then couple a previous first reference voltage to bottom plates of a first portion of the plurality of binary weighted capacitors, then couple a previous second reference voltage to bottom plates of a second portion of the plurality of binary weighted capacitors, then decouple the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors from the respective first, second and third reference voltages, then couple together the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors, then couple a positive input voltage (Vinp) to the bottom plates of the first portion of the plurality of binary weighted capacitors and the first dummy capacitor, then couple a negative input voltage (Vinn) to the bottom plates of the second portion of the plurality of binary weighted capacitors and the second dummy capacitor, then decouple the bottom plates of the first portion of the plurality of binary weighted capacitors and the first dummy capacitor from the bottom plates of the second portion of the plurality of binary weighted capacitors and the second dummy capacitor, and then compare a voltage Vx at the top plates of the first portion of the plurality of binary weighted capacitors and the first dummy capacitor with a voltage Vy at the top plates of the second portion of the plurality of binary weighted capacitors and the second dummy capacitor. In combination with any of the above embodiments, the circuity may be further configured to, if the voltage Vx is greater than the voltage Vy, then couple a fourth voltage to the bottom plate of a most significant bit (MSB) one of the first portion of the plurality of binary weighted capacitors, couple a fifth voltage to the bottom plate of a MSB one of the second portion of the plurality of binary weighted capacitors, and couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors. In combination with any of the above embodiments, the circuity may be further configured to, if the voltage Vx is less than the voltage Vy then couple the fifth voltage to the bottom plate of the MSB one of the first portion of the plurality of binary weighted capacitors, couple the fourth voltage to the bottom plate of the MSB one of the second portion of the plurality of binary weighted capacitors, and couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors. In combination with any of the above embodiments, the circuitry may be further configured to continue doing a successive approximation analog-to-digital conversion until finished with the conversion. In combination with any of the above embodiments, the first previous reference voltage may be from a first digital-to-analog converter, the second previous reference voltage may be from a second digital-to-analog converter, the third reference voltage may be a value Vref/2, the fourth reference voltage may be zero volts, and the fifth reference voltage may be a value Vref

In combination with any of the above embodiments, the SAR ADC may be a differential input SAR ADC. In combination with any of the above embodiments, the SAR ADC may be fabricated in an integrated circuit device. In combination with any of the above embodiments, the integrated circuit device may be a microcontroller.

In a further embodiment, a method may include operation of any of the SAR ADCs of the above embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:

Figure 1 illustrates a simplified schematic diagram of a VCM-based sampling SAR

ADC with capacitive DAC, according to the teachings of this disclosure; Figure 2 illustrates a schematic diagram of a prior technology solution for enabling rail- to-rail input common mode operation;

Figure 3 illustrates schematic diagrams of passive input common-mode tracking in reset and sampling phases, according to specific example embodiments of this disclosure;

Figure 4 illustrates schematic diagrams of the transition of sampling to MSB determination phases with passive input common-mode tracking, according to specific example embodiments of this disclosure;

Figure 5 illustrates a schematic diagram of a passive input common-mode tracking circuit, according to specific example embodiments of this disclosure;

Figure 6 illustrates a schematic flow diagram of passive input common-mode tracking, according to specific example embodiments of this disclosure;

Figure 7 illustrates schematic diagrams of a SAR ADC with vcm-based sampling showing the first two steps of successive approximation, according to the teachings of this disclosure;

Figure 8 illustrates schematic diagrams of a prior technology SAR ADC with vcm- based sampling showing the first two steps of successive approximation; and

Figure 9 illustrates schematic diagrams of a SAR ADC with vcm-based sampling showing the first two steps of successive approximation, according to specific example embodiments of this disclosure.

While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the forms disclosed herein.

DETAILED DESCRIPTION

Generally, present technology differential SAR ADCs have limited input common- mode range. This makes them less suited for applications where the input common-mode voltage cannot be controlled, like certain sensor applications, zero-crossing detection and the like. Previously published solutions, and earlier solutions developed for various microcontrollers, have relied upon extra circuitry to sample the input common-mode voltage and apply it during conversion so that the common mode voltage is cancelled out. This is, however, costly in terms of current consumption and area, and also puts limitations on the input common-mode rate of change. Embodiments of the present disclosure, in contrast, remove these limitations and require no additional power consuming circuitry or chip area. The only thing required, according to specific example embodiments of this disclosure, is one additional clock cycle per conversion to perform a reset of floating nodes. All required hardware switches are already provided in the SAR DAC circuit; whereby embodiments of the present disclosure achieve rail-to-rail input common-mode range without requiring any circuit modifications or additions.

The SAR DAC circuit disclosed and claimed herein may be easily implemented into an integrated circuit device such as, for example but not limited to, a mixed signal (both analog and digital circuits) microcontroller.

Referring now to the drawings, the details of example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower-case letter suffix.

Referring to Figure 1, depicted is a simplified schematic diagram of a VCM-based sampling SAR ADC with capacitive DAC, according to the teachings of this disclosure. Some SAR ADCs use vcm-based sampling to sample and convert input signals, which is approximately 80% more energy efficient than a conventional SAR algorithm. The signal is sampled and coupled to the input of the comparator 102 as shown in Figure 1. First the positive and negative inputs are sampled on the bottom plates of a capacitor array, here shown as a single capacitor, with the top-plates shorted to an internally generated common-mode voltage vcmsamp = vcm. Next, in the so-called MSB-phase the bottom plates are connected to the voltage vcm while the top plates are left floating, shifting the nodes vcp and vcn to 2*vcm-vinp and 2*vcm-vinn, respectively. Then the comparator 102 makes the first bit decision (MSB decision) and a binary search algorithm is used to shift binary scaled parts of the capacitor to the reference voltages depending on the comparator output, thereby leading to a successive approximation of the differential input voltage. This approach is similar to top-plate sampling but does not have the same high sensitivity to parasitic capacitance at the comparator input node. .

If the comparator common-mode voltage is defined as vcmcomp = (vcp+vcn)/2, then:

vcp+pcn 2-vcm-vinp+2-TPcm—vitm „ vino+vlnn, vcmcomp— = ^: = i * van ^: (1

2 2

The voltage (vinp+vinn)/2 is equal to the input common-mode voltage, or vcmin, reducing the above equation to: vcmcomp = 2 * vcm— vcmin (2)

If vcmin = vcm, then the comparator common-mode voltage simplifies to vcmcomp = vcm, which is typically vref/2, but may be chosen at the optimum operating point of the comparator 102. However, if rail-to-rail input common-mode is to be enabled, or vcmin is to be anywhere from 0 to vref, it means vcmcomp can also vary anywhere between 0 to vref This may lead to a substantial performance reduction of the ADC and a much more complicated comparator design. In some ADCs using this architecture, this can lead to a specified limitation of the allowable range of the input common-mode. Such a limitation is also often seen in datasheets of SAR ADCs from various sources. However, the embodiments of the present disclosure may achieve rail-to-rail input common-mode capability, which gives significant added value to the ADC.

Referring to Figure 2, depicted is a schematic diagram of a prior technology solution for enabling rail-to-rail input common mode operation. Now during the MSB phase, the nodes vcp and vcn when opened are shifted to (vcm+vcmsamp-vinp) and (vcm+vcmsamp-vinn), respectively, and if vcmsamp = vcmin, equation (1) can be rewritten to:

I' p+vcn

vcmcomp—— -— = vcm + vcmsamp — vcmin = vcm {$)

This means that the comparator will maintain its optimum common-mode voltage regardless of the input common-mode voltage. However, the cost is significant, requiring separate sampling capacitors and a switching network to sample the input common-mode voltage, as well as an operational transconductance amplifier (OTA) 204 needing rail-to-rail input and output. In addition, there is an inherent limitation in that vcmsamp is sampled at the start of the sampling phase while vcp and vcn are disconnected at the end of the sampling phase. Thus, any change in vcmin during the sampling phase time will lead to a resulting error in vcmsamp. Some solutions might use an improved continuous-time input common mode tracker to eliminate the latter problem, but still there is significant circuit and area overhead.

Referring to Figure 3, depicted are schematic diagrams of passive input common-mode tracking in reset and sampling phases, according to specific example embodiments of this disclosure. The circuit shown in Figure 3 overcome the limitations of common mode range without requiring any separate rail-to-rail circuitry (Figure 2). This is accomplished by introducing a new cycle (step) to the sampling process. First, the top-plate nodes vcp and vcn may be reset to the fixed voltage vcm, Figure 3(a). Then, in the second step sampling may be performed while leaving vcp and vcn floating but shorted, Figure 3(b). Whereby a single node vx is formed, which provides for simple capacitive voltage division:

vtnp-vtnn vinv+vinn

vcp = vcn = vx = vinn -i =— ^: = vcmm i < Referring to Figure 4, depicted are schematic diagrams of the transition of sampling to

MSB determination phases with passive input common-mode tracking, according to specific example embodiments of this disclosure. When the MSB phase occurs, the operation performs as shown in Figure 4, and it follows from it that the relation in equation (3), that vcmcomp=vcm, always holds. Furthermore, the voltage at node vx will follow vcmin during the entire sampling phase, with a limitation in rate of change only limited by the RC time constant of the shorting switch and the sampling capacitors. This will have much higher bandwidth than any active OTA-based tracking circuit (Figure 2). Also, no additional noise is added by an additional amplifier (204) driving to the top plate nodes. Figure 4 illustrates going from sampling to MSB phase with passive input common-mode tracking.

Since it is known from the SAR mode of operation that the inputs of the comparator 102, vcp and vcn, will converge towards vcm during the conversion, it means that by the end of a conversion vcp and vcn will both be approximately equal vcm. Thus, when the reset phase shown in Figure 3(a) is entered, no strong driver is required to settle vx to vcm, since both nodes vcp and vcn already have a voltage which is substantially equal to vcm within one LSB error.

Referring to Figure 5, depicted is a schematic diagram of a passive input common-mode tracking circuit, according to specific example embodiments of this disclosure. The only additional step needed is the generation of one extra reset signal prior to sampling, which resets the top-plate nodes to vcm before they are left floating. Thus, an analog hardware realization of passive input common-mode tracking may use the circuits shown in Figure 5.

Referring to Figure 6, depicted is a schematic flow diagram of passive input common- mode tracking, according to specific example embodiments of this disclosure. In step 610 the top plates are reset to vx. Then a voltage sample is taken in step 612. In step 614 a SAR bit conversion is performed. Step 616 determines whether the SAR bit conversion is finished. If NO, then return to step 614. If YES, then return to step 610. Thus, the digital realization will require only one additional reset phase without requiring any additional hardware, e.g., switches.

Simulations have shown that embodiments of the present disclosure correctly operate even with large scale vcmin changes at many MHz and giving no performance reduction of the ADC. The proposed solution provides continuous-time, rail-to-rail input common-mode capability to the SAR ADC with no additional analog hardware, no practical bandwidth limitations, and only requires one additional clock cycle per conversion to perform the top plate reset. This innovation is applicable to all SAR ADC s using the vcm-based sampling approach.

Many SAR ADCs use a capacitive DAC that provides an inherent track/hold function. Capacitive DACs employ the principle of charge redistribution to generate an analog output voltage. Because these types of DACs are prevalent in SAR ADCs, it is beneficial to discuss their operation. A capacitive DAC consists of an array of N capacitors with binary weighted values plus one "dummy LSB" capacitor. Figures 7-9 show examples of a 3-bit capacitive DAC connected to a comparator. The example uses a single positive vrefp and gnd as the differential references. This means that the reference common mode equals vrefp/2. During the acquisition phase, the array's common terminals (the terminals at which all the positive input and negative input capacitors share connections, respectively), is connected to Vref/2 and all free terminals are connected to the input signal (analog in +/- or Vinp/Vinn). After acquisition, the common terminal is disconnected from Vref/2 and the free terminals are disconnected from Vinp/Vinn, thus effectively trapping a charge proportional to the +/- input voltages on the capacitor array. The free terminals of all the capacitors are then connected to Vref/2, driving the common terminals to

As the first step in the binary search algorithm, the bottom plate of the MSB capacitor is disconnected from ground and connected to VREF. This drives the common terminal in the positive direction by an amount equal to ½VREF. Therefore, VCOMMON = -VIN + ½ x VREF. The comparator output yields a logic 1 if VCOMMON < 0 (i.e., VIN > ½ x VREF). The comparator output yields logic 0 if VIN < ½ x VREF. If the comparator output is logic 1, then the bottom plate of the MSB capacitor stays connected to VREF. Otherwise, the bottom plate of the MSB capacitor is connected back to ground. The bottom plate of the next smaller capacitor is then connected to VREF and the new VCOMMON voltage is compared with ground. This continues until all the bits have been determined. In general, VCOMMON = -VIN + BN-I ^X VREF/2 + BN-2 ^x VREF/4 + BN-I . . . + BO VREF/2^n_1 (B_ comparator output/ADC output bits). Referring to Figure 7, depicted are schematic diagrams of a SAR ADC with vcm-based sampling showing the first two steps of successive approximation, according to the teachings of this disclosure. Only the first two steps of successive approximation are shown in Figure 7. As discussed hereinabove, the comparator common-mode voltage is:

Vref - Vinp ·(· Vref - Vinn

= 2

Vinp + Vinn

=^Vr°f - 2

= Vref — Vcmirt

If Vcmin = Vref/2, Vcmcomp is also Vref/2. But if Vcmin is close to 0 or Vref, Vcmcomp is far from Vref/2. This can lead to a performance reduction or even failure. Often a safe, restricted Vcmin range is specified. As discussed above, this can be solved by sampling inputs again instead of the fixed voltage Vref/2. The comparator common-mode voltage may be given as:

Vx Vy

Vcmcomp =

Vcmin + Vref/2— Vinp + Vcmin + Vref/2— Vinn

~ 2

2 · Vcmin _i Vref (Vinp + Vinn)

= 2 2

Vref

^~ 2

The input common-mode is cancelled. The comparator is always at the same common-mode voltage and can set Vcmcomp to other fixed voltages than Vref/2 if desired.

Referring to Figure 8, depicted are schematic diagrams of a prior technology SAR ADC with vcm-based sampling showing the first two steps of successive approximation. The circuit shown in Figure 8 samples input common-mode voltage and buffers to the top-plates during sampling. However, this requires circuitry for averaging of the differential inputs, an additional buffer amplifier 204, and Vcmin must be sampled before the sampling inputs, so this SAR DAC solution cannot handle rapid changes in Vcmin.

Referring to Figure 9, depicted are schematic diagrams of a SAR ADC with vcm-based sampling showing the first two steps of successive approximation, according to specific example embodiments of this disclosure. If nodes Vx and Vy are floating but shorted together during sampling, capacitive voltage division provides that Vx=Vy=Vcmin. νίηρ + νίηη

= = vcmai

2

In conversion step (a) the capacitor top plates are reset to Vref/2. In conversion step (b) a voltage sample is taken. In conversion step (c) a SAR bit conversion is performed. In conversion steps (d) and (e) the conversion bit is determined to be either a "1" or a "0". As discussed above, this solution may prevent Vx and Vy from drifting over time. Accordingly, an additional clock cycle may be added before each sample + convert step to reset Vx and Vy to some fixed voltage.

The present disclosure has been described in terms of one or more embodiments, and it should be appreciated that many equivalents, alternatives, variations, and modifications, aside from those expressly stated, are possible and within the scope of the disclosure. While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein.

Claims

CLAIMS What is claimed is:

1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:

control circuitry;

a plurality of first capacitors, each capacitor of the first capacitors including a top plate and a bottom plate, the top plate closer to the control circuitry than the bottom plate of each of the first capacitors;

a plurality of second capacitors, each capacitor of the second capacitors including a top plate and a bottom plate, the top plate closer to the control circuitry than the bottom plate of each of the second capacitors;

wherein:

respective ones of the first capacitors and the second capacitors form binary weighted capacitor pairs; and

the control circuitry is configured to:

reset the top plates of each of the first capacitors and the top plates of each of the second capacitors to a common mode voltage;

sample a first differential voltage on the bottom plates of the first capacitors and sample a second differential voltage on the bottom plates of the second capacitor while coupling the top plates of the first capacitors and the second capacitors while floating; and

perform a sequential SAR analog-to-digital conversion on the first and second differential voltages.

2. The SAR ADC of Claim 1 , wherein the SAR ADC is a differential input

SAR ADC.

3. The SAR ADC of any of Claims 1-2, wherein the SAR ADC is fabricated in an integrated circuit device.

4. The SAR ADC of Claim 3, wherein the integrated circuit device is a microcontroller.

5. The SAR ADC of any of Claims 1 -4, further comprising:

a first dummy capacitor in parallel with the first capacitors, the first dummy capacitor including a top plate and a bottom plate, the top plate closer to the control circuitry than the bottom plate of each of the first capacitors; and

a second dummy capacitor in parallel with the second capacitors, the second dummy capacitor including a top plate and a bottom plate, the top plate closer to the control circuitry than the bottom plate of each of the second capacitors;

wherein the control circuity is further configured to:

couple the top plates of a first portion of the binary weighted capacitor pairs to a first input of a voltage comparator;

couple the top plates of a second portion of the binary weighted capacitor pairs to a second input of the voltage comparator;

couple a top plate of a first dummy capacitor to the first input of the voltage comparator and coupling a top plate of a second dummy capacitor to the second input of the voltage comparator;

couple a previous first reference voltage to bottom plates of the first portion of the binary weighted capacitors;

couple a previous second reference voltage to bottom plates of the second portion of the binary weighted capacitors;

couple a third reference voltage to the top plates of the binary weighted capacitors, and to the top and bottom plates of the first and second dummy capacitors;

decouple the bottom plates of binary weighted capacitors from the previous first and second reference voltages;

couple the bottom plates of the first portion of the binary weighted capacitors and the bottom plate of the first dummy capacitor to a positive input voltage;

couple the bottom plates of the second portion of the binary weighted capacitors and the bottom plate of the second dummy capacitor to a negative input voltage;

couple the top plates of the binary weighted capacitors and the first and second dummy capacitors together;

decouple the top plates of the first portion of the binary weighted capacitors and the first dummy capacitor from the top plates of the second portion of the binary weighted capacitors and the second dummy capacitor; and

couple the bottom plates of the binary weighted capacitors and the first and second dummy capacitors to the third reference voltage;

wherein the voltage comparator is configured to determine whether a first voltage on the first input of the voltage comparator is greater than a second voltage on the second input of the voltage comparator.

6. The SAR ADC of Claim 5, wherein the voltage comparator is further configured to:

provide a first logic level output if the first voltage is greater than the second voltage, and

provide a second logic level output if the first voltage is less than the second voltage.

7. The SAR ADC of any of Claims 5-6, wherein the control circuitry is further configured to perform successive approximation analog-to-digital conversion until finished with the conversion.

8. The SAR ADC of any of Claims 5-7, wherein the previous first reference voltage is from a first digital-to-analog converter (DAC), and the previous second reference voltage is from a second DAC.

9. The SAR ADC of any of Claims 5-8, wherein the previous first and second reference voltages are a value Vref, and the third reference voltage is a value Vref/2.

10. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising circuitry configured to: couple a third reference voltage to top plates of a plurality of binary weighted capacitors and top and bottom plates of first and second dummy capacitors;

couple a previous first reference voltage to bottom plates of a first portion of the plurality of binary weighted capacitors;

couple a previous second reference voltage to bottom plates of a second portion of the plurality of binary weighted capacitors;

decouple the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors from the respective first, second and third reference voltages;

couple together the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors;

couple a positive input voltage, Vinp, to the bottom plates of the first portion of the plurality of binary weighted capacitors and the first dummy capacitor;

couple a negative input voltage, Vinn, to the bottom plates of the second portion of the plurality of binary weighted capacitors and the second dummy capacitor;

decouple the bottom plates of the first portion of the plurality of binary weighted capacitors and the first dummy capacitor from the bottom plates of the second portion of the plurality of binary weighted capacitors and the second dummy capacitor; and

compare a voltage Vx at the top plates of the first portion of the plurality of binary weighted capacitors and the first dummy capacitor with a voltage Vy at the top plates of the second portion of the plurality of binary weighted capacitors and the second dummy capacitor.

1 1. The SAR ADC of Claim 10, wherein the circuity is further configured to, if the voltage Vx is greater than the voltage Vy then:

couple a fourth voltage to the bottom plate of a most significant bit (MSB) one of the first portion of the plurality of binary weighted capacitors;

couple a fifth voltage to the bottom plate of a MSB one of the second portion of the plurality of binary weighted capacitors; and couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors.

12. The SAR ADC of any of Claims 10-1 1, wherein the circuity is further configured to, if the voltage Vx is less than the voltage Vy then:

couple the fifth voltage to the bottom plate of the MSB one of the first portion of the plurality of binary weighted capacitors;

couple the fourth voltage to the bottom plate of the MSB one of the second portion of the plurality of binary weighted capacitors; and

couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors.

13. The SAR ADC of any of Claims 10-12, wherein the circuitry is further configured to continue doing a successive approximation analog-to-digital conversion until finished with the conversion.

14. The SAR ADC of any of Claims 10-13, wherein

the first previous reference voltage is from a first digital-to-analog converter;

the second previous reference voltage is from a second digital-to-analog converter;

the third reference voltage is a value Vref/2;

the fourth reference voltage is zero volts; and

the fifth reference voltage is a value Vref

15. The SAR ADC of any of Claims 10-14, wherein the SAR ADC is a differential input SAR ADC.

16. The SAR ADC of any of Claims 10-15, wherein the SAR ADC is fabricated in integrated circuit device.

17. The SAR ADC according to claim 16, wherein the integrated circuit device rocontroller.

18. A method, comprising operation of any of the SAR ADCs of Claims 1-17.