WO2019013891A1 - Cyclic conformal deposition/anneal/etch for si gapfill - Google Patents

Cyclic conformal deposition/anneal/etch for si gapfill Download PDF

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WO2019013891A1
WO2019013891A1 PCT/US2018/034877 US2018034877W WO2019013891A1 WO 2019013891 A1 WO2019013891 A1 WO 2019013891A1 US 2018034877 W US2018034877 W US 2018034877W WO 2019013891 A1 WO2019013891 A1 WO 2019013891A1
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amorphous silicon
substrate
features
silicon film
etching
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WO2019013891A9 (en
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Rui CHENG
Yi Yang
Abhijit Basu Mallick
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Applied Materials Inc
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Applied Materials Inc
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Priority to CN201880046268.5A priority patent/CN110892505B/en
Priority to JP2020500218A priority patent/JP7252935B2/en
Publication of WO2019013891A1 publication Critical patent/WO2019013891A1/en
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    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
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    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
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    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
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    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
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    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
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    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/416—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
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    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
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    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
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    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
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    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H10P95/906—Thermal treatments, e.g. annealing or sintering for altering the shape of semiconductors, e.g. smoothing the surface
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches

Definitions

  • Embodiments of the present disclosure generally relate to semiconductor manufacturing processes, and more particularly, to methods for gapfilling high aspect ratio trenches of semiconductor devices with amorphous silicon film, and to form seam or void-free semiconductor devices.
  • amorphous silicon has been used in semiconductor manufacturing processes since a-Si generally provides good etch selectivity with respect to other films, such as silicon oxide (SiO) and amorphous carbon (a-C).
  • the conventional a-Si deposition methods such as plasma-enhanced chemical vapor deposition (PECVD) and conformai deposition, however, cannot be used to gapfill high aspect ratio trenches, the deposition rate of conventional a-Si deposition methods is generally higher towards the top of the trenches and lower towards the bottom of the trenches, and seams are formed between the high aspect ratio trenches because of the uneven deposition rates.
  • seams are further opened up during post-curing processes and ultimately cause decreased throughput or even semiconductor device failure.
  • Seams have conventionally been healed by thermal annealing.
  • the thermal annealing generally causes shrinking of the deposited ids inside of the trenches. [0004] Therefore, there is a need for methods for gapfilling high aspect ratio trenches of semiconductor devices that can provide seam and void-free film growth.
  • a method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features.
  • the deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfill without any seam or void between the one or more features.
  • a method for manufacturing a semiconductor device includes positioning a substrate having one or more features formed in a surface of the substrate, each of the one or more features having sidewalis and a bottom surface, in a process chamber, depositing an amorphous silicon film over the substrate having one or more features, annealing the amorphous silicon film, and etching a portion of the amorphous silicon film.
  • a method for manufacturing a semiconductor device includes positioning a substrate having one or more high aspect ratio trenches formed in a surface of the substrate, each of the one or more high aspect ratio trenches having sidewalis and a bottom surface, in a process chamber, depositing an amorphous silicon film in the one or more high aspect ratio trenches, annealing the amorphous silicon film to heal one or more seams formed in the one or more high aspect ratio trenches, and etching the amorphous silicon film to a distance below a top surface of the substrate, the distance being equal to a distance between the top surface of the substrate and the bottom of the lowermost of one or more voids in the one or more features.
  • a method for manufacturing a semiconductor device includes positioning a substrate having one or more features formed in a surface of the substrate, each of the one or more features having sidewa!ls and a bottom surface, in a first chamber, depositing a material over the substrate having one or more features in the first chamber, annealing the material in the first chamber to heal one or more seams in the material, transferring the substrate having one or more features to a second chamber, and etching a portion of the annealed material to remove one or more voids in the annealed material.
  • Figure 1 is a flow diagram summarizing a method according to embodiments of the present disclosure.
  • Figures 2A-2E depict stages of fabrication of a semiconductor device according to embodiments of the present disclosure.
  • Figure 3 is a schematic view of an apparatus for performing a method according to embodiments of the present disclosure.
  • a method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features.
  • the deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfili without any seam or void between the one or more features.
  • trenchfilling high aspect ratio trenches formed on a substrate with amorphous silicon will refer to gapfilling high aspect ratio trenches formed on a substrate with amorphous silicon as an example.
  • the methods described herein are generally useful to gapfili any device features with any material or to remove seams and/or voids from a deposited material.
  • feature means any intentional surface irregularity.
  • Features generally have any suitable shape, including, but not limited to, vias, trenches, lines, contact holes, through-holes or other feature definitions utilized in semiconductor, solar, or other electronic devices, such as high ratio contact plugs.
  • Trenches which are used as an example herein, generally have a top and two sidewalis and are formed between peaks, which generally have a top and two sidewalis.
  • Features can be of any suitable aspect ratio, which is the ratio of the depth of the feature to the width of the feature.
  • a high aspect ratio trench is a trench having an aspect ratio greater than or equal to about 5:1 , 10: 1 , 15: 1 , 25:1 , 30:1 , 35:1 , or 40:1.
  • Figure 1 is a flow diagram summarizing a method 100 for gapfiiiing device features with amorphous silicon film according to embodiments of the present disclosure.
  • Figures 2A-2E depict stages of fabrication of a semiconductor device 200 according to embodiments of the present disclosure, for example, in accordance with the method 00. Therefore, as an example, the method 100 is desc ibed below in accordance with the stages of gapfiliing high aspect ratio trenches of a semiconductor device 200 with amorphous silicon film as illustrated in Figures 2A-2E,
  • Method 100 begins at operation 110 by positioning a substrate 202 having one or more features 204 (shown as two high aspect ratio trenches) formed in a layer 206, such as a silicon or carbon-containing layer, on the substrate 202, as shown in Figure 2A, into a position or environment, such as a process chamber, for further processing.
  • the substrate 202 is generally any suitable substrate for processing, including but not limited to, silicon (Si) and/or germanium (Ge) substrates, and may include other elements such as, oxygen (O), nitrogen (N), and carbon (C).
  • the one or more features 204 generally include a first sidewail 210, a second sidewail 212, and a bottom 214.
  • the first sidewail 210 and the second sidewail 212 define the width (W) of the one or more features 204.
  • a height (H) of the one or more features is generally from a top surface 208 of the layer 208 to a bottom surface 216 of the layer 206. While Figure 2A shows two features, the present disclosure further contemplates that the substrate 202 can have one or more than one feature 204.
  • a material 218 is deposited over the one or more features 204 of the substrate 202 to fill the one or more features 204, as shown in Figure 2B.
  • the material 218 is generally deposited by any suitable deposition process. Examples of suitable deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD, atomic layer deposition (ALD), and plasma-enhanced ALD (PEALD). In one example, the material 218 is deposited by thermal CVD.
  • the material 218 is an amorphous silicon film and depositing the material 218 includes exposing the one or more features 204 of the substrate 202 to a silicon precursor.
  • suitable silicon e, but are not limited to, one or more of silane (S1H4), disiiane (H 3 Si2), dichlorosilane (DCS), trisi!ane (HgSis), and tetrasiiane (S14H10).
  • the silicon precursor is optionally heated in a hot can to increase the vapor pressure and then delivered to the process chamber for deposition using ultrahigh purity (UHP) argon (Ar) carrier gas.
  • UHP ultrahigh purity
  • Ar argon
  • suitable carrier gasses which are generally co-introduced with the silicon precursor include, but are not limited to, helium (He) and hydrogen gas (H2).
  • the material 218 is a doped amorphous silicon film deposited by exposing the one or more features 204 of the substrate 202 to a doping precursor in addition to the silicon precursor.
  • a doping precursor in addition to the silicon precursor.
  • dopants include, but are not limited to, boron (B), phosphorous (P), gallium (Ga), Sn (Tin), arsenic (As), germanium (Ge), carbon (C), nitrogen (N), and antimony (Sb).
  • Suitable doping precursors include, but are not limited to, dimethylamine borane [NH(CH3)2BH3] (DMAB), diborane (B2H6), germane (GeH 4 ), and phosphane (PH 3 ),
  • Depositing the material 218 over the one or more features 204 of the substrate 202 generally occurs at a temperature between about 150 degrees Celsius (°C) and about 500°C.
  • the deposition can be performed with or without capacitively coupled plasma (CCP) or inductively coupled remote plasma (ICP).
  • CCP capacitively coupled plasma
  • ICP inductively coupled remote plasma
  • a pressure in the process chamber is generally between about 100 mTorr and about 350 Torr.
  • one or more seams 220 are generally formed in the one or more features 204 during the deposition of the material 218. if left untreated, the one or more seams 220 often open up during further processing of the semiconductor device 200, which leads to defective device performance.
  • the deposited material 2 8 is annealed to heal the one or more seams 220.
  • the material 218 is annealed by an in-situ thermal anneal process.
  • the temperature during the anneal iraily between about 400°C and about 1 , 100°C.
  • the anneal process may be performed over any suitable amount of time, for example, for between about 0.1 seconds and about 5 hours.
  • a gas ambient for the anneal process generally includes one or more of H 2 , Ar, He, and nitrogen gas (N 2 ).
  • a process chamber pressure generally ranges between about 100 mTorr and about 1 atmosphere (atm) during the annealing.
  • the one or more seams 220 are healed with a plasma treatment. In yet another embodiment, the one or more seams 220 are healed with an e-beam treatment. In further embodiments, the one or more seams 220 are healed with any suitable process to reflow silicon (Si) atoms of the amorphous silicon.
  • one or more voids 222 (three are shown as an example) form in the material 218 during the anneal process, as shown in Figure 2C.
  • any surface tensions of the substrate 202 or the layer 206 often result in the formation of the one or more voids 222 in the material 218.
  • the performance of the semiconductor device 200 is generally negatively affected.
  • etching a portion of the annealed material 218 includes exposing the material 218 on the one or more features 204 of the substrate 202 to an etchant.
  • the material 218 is etched down into the one or more features 204 a distance below the top surface 208 of the layer 206 of the substrate 202, the distance being equal to a distance between the top surface 208 and the bottom of the lowermost of one or more voids 222 in the one or more features 204.
  • the one or more voids 222 are removed prior to subsequent deposition of additional material 218 or another material.
  • the etch process is generally any suitable etch process, including, :o, thermal etching or plasma etching with a capacitively coupled plasma (CCP) or an inductively coupled plasma (ICP).
  • suitable etchants include, but are not limited to, one or more of nitrogen trifluoride (NF 3 ), chlorine gas (C ), hydrochloric acid (HCI), hydrogen bromide (HBr), hexafiuoro-2-butyne (C 4 F6) , tetrafluoroethylene (C2F4), H 2 , Ar, He, and N 2 .
  • Operation 120, operation 130, and operation 140 are generally repeated any suitable number of times to fill the one or more features 204 with material 2 8 without any, or with reduced, seams or voids, as shown in Figure 2E.
  • FIG. 3 is a schematic view of an apparatus 300 for performing a method according to embodiments described herein. More specifically, the apparatus 300 is a cluster tool for fabricating semiconductor devices according to the methods described above.
  • the apparatus 300 is a cluster tool for fabricating semiconductor devices according to the methods described above.
  • a transfer chamber 310 At the center of the apparatus 300 is a transfer chamber 310.
  • the substrate transferring mechanism 312 transfers a substrate from one of the first, second, or third process chambers, 330, 340, and 350, respectively, to the load lock chamber 320 and vice versa.
  • the first, second, and third process chambers, 330, 340, and 350, are connected to the transfer chamber 310.
  • the load lock chamber 320 is connected to the transfer chamber 310 through a substrate alignment chamber 322.
  • the apparatus 300 includes three process chambers. However, the apparatus 300 generally includes any suitable number of chambers.
  • the first process chamber 330 is a deposition chamber
  • the second process chamber 340 is a chamber suitable for performing annealing processes
  • the third process chamber 350 is an eteh chamber.
  • Suitable chambers include chambers available from Applied Materials, Inc. of Santa Clara, California, such as PRODUCER® chambers and VANTAGE® chambers.
  • Operation 120 generally occurs in the first process chamber 330.
  • the substrate 202 remains in the first process chamber 330 for the annealing process at operation 130.
  • the substrate 202 is transferred to the second process chamber 340 for the annealing process at operation 130.
  • the substrate 202 is generally then transferred to the third process chamber 350 for the etching process at operation 140.
  • Process chamber for performing operations disclosed herein are available from Applied Materials, inc., of Santa Clara, California. However, it is contemplated that other process chambers, including those from other manufacturers, may also be used and may benefit from aspects of the disclosure.
  • Embodiments of the present disclosure provide seam and void-free gapfill for semiconductor device features, such as amorphous silicon gapfili for high aspect ratio trenches. Since the gapfill is seam and void-free, or includes a reduced number of seams and voids, the overall performance of the semiconductor device is improved,

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
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  • Drying Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Memories (AREA)

Abstract

Methods for seam and void-free gapfilling, such as gapfilling high aspect ratio trenches with amorphous silicon, are provided. A method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features. The deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfill without any seam or void between the one or more features.

Description

CYCLIC CQNFQRSVSAL DEPOSITION/ANNEAL7ETCH FOR SI GAPFILL
Figure imgf000003_0001
[0001] Embodiments of the present disclosure generally relate to semiconductor manufacturing processes, and more particularly, to methods for gapfilling high aspect ratio trenches of semiconductor devices with amorphous silicon film, and to form seam or void-free semiconductor devices.
Description of the Related Art
[0002] For many semiconductor device manufacturing processes, there is a need to fill narrow trenches having high aspect ratios greater than, for example, 10: 1. One example of such a process is shallow trench isolation (ST!) in which the film needs to be of high quality and have very low leakage throughout the trench. As the dimensions of semiconductor device structures continue to decrease and the aspect ratios increase, post-curing processes become increasingly difficult and result in films with varying composition throughout the filled trench.
[0003] Conventionally, amorphous silicon (a-Si) has been used in semiconductor manufacturing processes since a-Si generally provides good etch selectivity with respect to other films, such as silicon oxide (SiO) and amorphous carbon (a-C). The conventional a-Si deposition methods, such as plasma-enhanced chemical vapor deposition (PECVD) and conformai deposition, however, cannot be used to gapfill high aspect ratio trenches, the deposition rate of conventional a-Si deposition methods is generally higher towards the top of the trenches and lower towards the bottom of the trenches, and seams are formed between the high aspect ratio trenches because of the uneven deposition rates. The seams are further opened up during post-curing processes and ultimately cause decreased throughput or even semiconductor device failure. Seams have conventionally been healed by thermal annealing. However, the thermal annealing generally causes shrinking of the deposited ids inside of the trenches. [0004] Therefore, there is a need for methods for gapfilling high aspect ratio trenches of semiconductor devices that can provide seam and void-free film growth.
SUIVljVIA Y
[0005] Methods for seam and void-free gapfilling, such as gapfilling high aspect ratio trenches with amorphous silicon, are provided. A method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features. The deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfill without any seam or void between the one or more features.
[00Θ8] In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes positioning a substrate having one or more features formed in a surface of the substrate, each of the one or more features having sidewalis and a bottom surface, in a process chamber, depositing an amorphous silicon film over the substrate having one or more features, annealing the amorphous silicon film, and etching a portion of the amorphous silicon film.
[0007] In another embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes positioning a substrate having one or more high aspect ratio trenches formed in a surface of the substrate, each of the one or more high aspect ratio trenches having sidewalis and a bottom surface, in a process chamber, depositing an amorphous silicon film in the one or more high aspect ratio trenches, annealing the amorphous silicon film to heal one or more seams formed in the one or more high aspect ratio trenches, and etching the amorphous silicon film to a distance below a top surface of the substrate, the distance being equal to a distance between the top surface of the substrate and the bottom of the lowermost of one or more voids in the one or more features.
[0008] In yet another embodiment a method for manufacturing a semiconductor device is disclosed. The method includes positioning a substrate having one or more features formed in a surface of the substrate, each of the one or more features having sidewa!ls and a bottom surface, in a first chamber, depositing a material over the substrate having one or more features in the first chamber, annealing the material in the first chamber to heal one or more seams in the material, transferring the substrate having one or more features to a second chamber, and etching a portion of the annealed material to remove one or more voids in the annealed material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.
[0010] Figure 1 is a flow diagram summarizing a method according to embodiments of the present disclosure.
[0011] Figures 2A-2E depict stages of fabrication of a semiconductor device according to embodiments of the present disclosure.
[0012] Figure 3 is a schematic view of an apparatus for performing a method according to embodiments of the present disclosure.
[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION
[0014] Methods for seam and void-free gapfilling, such as gapfilling high aspect ratio trenches with amorphous silicon, are provided. A method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features. The deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfili without any seam or void between the one or more features.
[0015] The description that follows will refer to gapfilling high aspect ratio trenches formed on a substrate with amorphous silicon as an example. However, the methods described herein are generally useful to gapfili any device features with any material or to remove seams and/or voids from a deposited material. Generally, "feature" means any intentional surface irregularity. Features generally have any suitable shape, including, but not limited to, vias, trenches, lines, contact holes, through-holes or other feature definitions utilized in semiconductor, solar, or other electronic devices, such as high ratio contact plugs.
[0016] Trenches, which are used as an example herein, generally have a top and two sidewalis and are formed between peaks, which generally have a top and two sidewalis. Features can be of any suitable aspect ratio, which is the ratio of the depth of the feature to the width of the feature. In some examples, a high aspect ratio trench is a trench having an aspect ratio greater than or equal to about 5:1 , 10: 1 , 15: 1 , 25:1 , 30:1 , 35:1 , or 40:1.
[0017] Figure 1 is a flow diagram summarizing a method 100 for gapfiiiing device features with amorphous silicon film according to embodiments of the present disclosure. Figures 2A-2E depict stages of fabrication of a semiconductor device 200 according to embodiments of the present disclosure, for example, in accordance with the method 00. Therefore, as an example, the method 100 is desc ibed below in accordance with the stages of gapfiliing high aspect ratio trenches of a semiconductor device 200 with amorphous silicon film as illustrated in Figures 2A-2E,
[0018] Method 100 begins at operation 110 by positioning a substrate 202 having one or more features 204 (shown as two high aspect ratio trenches) formed in a layer 206, such as a silicon or carbon-containing layer, on the substrate 202, as shown in Figure 2A, into a position or environment, such as a process chamber, for further processing. The substrate 202 is generally any suitable substrate for processing, including but not limited to, silicon (Si) and/or germanium (Ge) substrates, and may include other elements such as, oxygen (O), nitrogen (N), and carbon (C).
[0019] As shown in Figure 2A, the one or more features 204 generally include a first sidewail 210, a second sidewail 212, and a bottom 214. The first sidewail 210 and the second sidewail 212 define the width (W) of the one or more features 204. A height (H) of the one or more features is generally from a top surface 208 of the layer 208 to a bottom surface 216 of the layer 206. While Figure 2A shows two features, the present disclosure further contemplates that the substrate 202 can have one or more than one feature 204.
[0020] At operation 120, a material 218 is deposited over the one or more features 204 of the substrate 202 to fill the one or more features 204, as shown in Figure 2B. The material 218 is generally deposited by any suitable deposition process. Examples of suitable deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD, atomic layer deposition (ALD), and plasma-enhanced ALD (PEALD). In one example, the material 218 is deposited by thermal CVD.
[0021] In one embodiment, the material 218 is an amorphous silicon film and depositing the material 218 includes exposing the one or more features 204 of the substrate 202 to a silicon precursor. Examples of suitable silicon e, but are not limited to, one or more of silane (S1H4), disiiane (H3Si2), dichlorosilane (DCS), trisi!ane (HgSis), and tetrasiiane (S14H10). The silicon precursor is optionally heated in a hot can to increase the vapor pressure and then delivered to the process chamber for deposition using ultrahigh purity (UHP) argon (Ar) carrier gas. Other suitable carrier gasses, which are generally co-introduced with the silicon precursor include, but are not limited to, helium (He) and hydrogen gas (H2).
[0022] In another embodiment, the material 218 is a doped amorphous silicon film deposited by exposing the one or more features 204 of the substrate 202 to a doping precursor in addition to the silicon precursor. By doping the amorphous silicon, the temperature for subsequent processing operations, such as etching of the doped a-Si layer, is generally reduced. Examples of dopants include, but are not limited to, boron (B), phosphorous (P), gallium (Ga), Sn (Tin), arsenic (As), germanium (Ge), carbon (C), nitrogen (N), and antimony (Sb). Examples of suitable doping precursors include, but are not limited to, dimethylamine borane [NH(CH3)2BH3] (DMAB), diborane (B2H6), germane (GeH4), and phosphane (PH3),
[0023] Depositing the material 218 over the one or more features 204 of the substrate 202 generally occurs at a temperature between about 150 degrees Celsius (°C) and about 500°C. The deposition can be performed with or without capacitively coupled plasma (CCP) or inductively coupled remote plasma (ICP). During the deposition process, a pressure in the process chamber is generally between about 100 mTorr and about 350 Torr.
[0024] As discussed above, one or more seams 220 are generally formed in the one or more features 204 during the deposition of the material 218. if left untreated, the one or more seams 220 often open up during further processing of the semiconductor device 200, which leads to defective device performance.
[0025] At operation 130, the deposited material 2 8 is annealed to heal the one or more seams 220. in one embodiment, the material 218 is annealed by an in-situ thermal anneal process. The temperature during the anneal iraily between about 400°C and about 1 , 100°C. The anneal process may be performed over any suitable amount of time, for example, for between about 0.1 seconds and about 5 hours. A gas ambient for the anneal process generally includes one or more of H2, Ar, He, and nitrogen gas (N2). A process chamber pressure generally ranges between about 100 mTorr and about 1 atmosphere (atm) during the annealing.
[0026] In another embodiment, the one or more seams 220 are healed with a plasma treatment. In yet another embodiment, the one or more seams 220 are healed with an e-beam treatment. In further embodiments, the one or more seams 220 are healed with any suitable process to reflow silicon (Si) atoms of the amorphous silicon.
[0027] Generally, one or more voids 222 (three are shown as an example) form in the material 218 during the anneal process, as shown in Figure 2C. For example, any surface tensions of the substrate 202 or the layer 206 often result in the formation of the one or more voids 222 in the material 218. Like the one or more seams 220, if the one or more voids 222 are not partially or completely removed, the performance of the semiconductor device 200 is generally negatively affected.
[0028] At operation 140, at least a portion of the annealed material 218 is etched to remove the one or more voids 222, as shown in Figure 2D. In one embodiment, etching a portion of the annealed material 218 includes exposing the material 218 on the one or more features 204 of the substrate 202 to an etchant. The material 218 is etched down into the one or more features 204 a distance below the top surface 208 of the layer 206 of the substrate 202, the distance being equal to a distance between the top surface 208 and the bottom of the lowermost of one or more voids 222 in the one or more features 204. By etching a portion of the material 218 to a distance equal to or below the bottom of the lowermost of the one or more voids 222, the one or more voids 222 are removed prior to subsequent deposition of additional material 218 or another material.
[0029] The etch process is generally any suitable etch process, including, :o, thermal etching or plasma etching with a capacitively coupled plasma (CCP) or an inductively coupled plasma (ICP). Examples of suitable etchants include, but are not limited to, one or more of nitrogen trifluoride (NF3), chlorine gas (C ), hydrochloric acid (HCI), hydrogen bromide (HBr), hexafiuoro-2-butyne (C4F6) , tetrafluoroethylene (C2F4), H2, Ar, He, and N2.
[0030] Operation 120, operation 130, and operation 140 are generally repeated any suitable number of times to fill the one or more features 204 with material 2 8 without any, or with reduced, seams or voids, as shown in Figure 2E.
[0031] Figure 3 is a schematic view of an apparatus 300 for performing a method according to embodiments described herein. More specifically, the apparatus 300 is a cluster tool for fabricating semiconductor devices according to the methods described above. At the center of the apparatus 300 is a transfer chamber 310. Within the transfer chamber 310 is a substrate transferring mechanism 312. The substrate transferring mechanism 312 transfers a substrate from one of the first, second, or third process chambers, 330, 340, and 350, respectively, to the load lock chamber 320 and vice versa. The first, second, and third process chambers, 330, 340, and 350, are connected to the transfer chamber 310. The load lock chamber 320 is connected to the transfer chamber 310 through a substrate alignment chamber 322. As illustrated in Figure 3, the apparatus 300 includes three process chambers. However, the apparatus 300 generally includes any suitable number of chambers.
[0032] In one embodiment, the first process chamber 330 is a deposition chamber, the second process chamber 340 is a chamber suitable for performing annealing processes, and the third process chamber 350 is an eteh chamber. Suitable chambers include chambers available from Applied Materials, Inc. of Santa Clara, California, such as PRODUCER® chambers and VANTAGE® chambers. Operation 120 generally occurs in the first process chamber 330. In one embodiment, the substrate 202 remains in the first process chamber 330 for the annealing process at operation 130. In another embodiment, the substrate 202 is transferred to the second process chamber 340 for the annealing process at operation 130. The substrate 202 is generally then transferred to the third process chamber 350 for the etching process at operation 140.
[0033] Process chamber for performing operations disclosed herein are available from Applied Materials, inc., of Santa Clara, California. However, it is contemplated that other process chambers, including those from other manufacturers, may also be used and may benefit from aspects of the disclosure.
[0034] Embodiments of the present disclosure provide seam and void-free gapfill for semiconductor device features, such as amorphous silicon gapfili for high aspect ratio trenches. Since the gapfill is seam and void-free, or includes a reduced number of seams and voids, the overall performance of the semiconductor device is improved,
[0035] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

What is claimed is:
1. A method for manufacturing a semiconductor device, comprising:
positioning a substrate having one or more features formed in a surface of the substrate, each of the one or more features having sidewalis and a bottom surface, in a process chamber;
depositing an amorphous silicon film over the substrate having one or more features;
annealing the amorphous silicon film; and
etching a portion of the amorphous silicon film,
2. The method of claim 1 , wherein the depositing an amorphous silicon film comprises exposing the substrate to a silicon precursor selected from the group consisting of siiane, disiiane, dichiorosilane, trisilane, and tetrasilane.
3. The method of claim 2, further comprising:
exposing the substrate to a boron, phosphorous, gallium, tin, arsenic, germanium, carbon, nitrogen, antimony or indium precursor.
4. The method of claim 1 , wherein the etching a portion of the amorphous silicon film comprises recessing the amorphous silicon film a distance below the top surface of the substrate, the distance being equal to a distance between the top surface of the substrate and the bottom of the lowermost of one or more voids in the one or more features.
5. A method for manufacturing a semiconductor device, comprising:
positioning a substrate having one or more high aspect ratio trenches formed in a surface thereof, each of the one or more high aspect ratio trenches having sidewalis and a bottom surface, in a process chamber;
depositing an amorphous silicon film in the one or more high aspect ratio trenches;
annealing the amorphous silicon film to heal one or more seams formed in " " " '" igh aspect ratio trenches; and etching the amorphous silicon film to a distance below a top surface of the substrate, the distance being equal to a distance between the top surface of the substrate and the bottom of the lowermost of one or more voids in the one or more features.
6. The method of claim 5, wherein the amorphous silicon film is doped.
7. The method of claim 6, wherein the depositing an amorphous silicon film comprises:
exposing the substrate to a silicon precursor; and
exposing the substrate to a boron, phosphorous, gallium, tin, arsenic, germanium, carbon, nitrogen, antimony or indium precursor.
8. The method of claim 7, wherein the depositing an amorphous silicon film occurs at a temperature between about 150 degrees Celsius and about 500 degrees Celsius and at a pressure between about 100 mTorr and about 350 Torr.
9. The method of claim 8, wherein the annealing an amorphous silicon film occurs at a temperature between about 400 degrees Celsius and about 1 ,100 degrees Celsius and at a pressure between about 100 mTorr and about 1 atm.
10. The method of claim 9, wherein the etching a portion of the amorphous silicon film comprises exposing the amorphous silicon film to an efchanf comprising one or more of NF3> Cl2, HCi, HBr, C4F6, C2F4, H2, Ar, He, and N2.
1 1. A method for manufacturing a semiconductor device, comprising:
positioning a substrate having one or more features formed in a surface of the substrate, each of the one or more features having sidewails and a bottom surface, in a first chamber;
depositing a material over the substrate having one or more features in the first chamber;
annealing the material in the first chamber to heal one or more seams in the transferring the substrate having one or more features to a second chamber; and
etching a portion of the annealed material to remove one or more voids in the annealed material.
12. The method of claim 1 , wherein the material is amorphous silicon.
13. The method of claim 11 , wherein the depositing a material occurs at a temperature between about 150 degrees Celsius and about 500 degrees Celsius and at a pressure between about 00 mTorr and about 350 Torr.
14. The method of claim 13, wherein the annealing the material occurs at a temperature between about 400 degrees Celsius and about 1 , 100 degrees Celsius and at a pressure between about 100 mTorr and about 1 atm,
15. The method of claim 14, wherein the etching a portion of the annealed material comprises recessing the annealed material a distance below the top surface of the substrate, the distance being equal to a distance between the top surface of the substrate and the bottom of the lowermost of the one or more voids in the one or more features.
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