WO2019011749A1

WO2019011749A1 - Method and circuit for current integration

Info

Publication number: WO2019011749A1
Application number: PCT/EP2018/068103
Authority: WO
Inventors: Fridolin Michel
Original assignee: Ams International AG
Current assignee: Ams International AG
Priority date: 2017-07-13
Filing date: 2018-07-04
Publication date: 2019-01-17
Anticipated expiration: 2020-01-13
Also published as: TWI775881B; CN110870206A; US20200295774A1; CN110870206B; EP3429083A1; TW201918035A; US10951222B2; EP3429083B1

Abstract

An input current (I_in) is transformed into an output integrated voltage (V_{out_int}) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (T_{clk_DAC}) defining time intervals between successive rising edges of the feedback pulses.Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T_{clk_DAC}).

Description

METHOD AND CIRCUIT FOR CURRENT INTEGRATION The present disclosure is related to current integration.

An integration circuit is a circuit block often employed in delta-sigma analog-to-digital converters. Delta-sigma

modulation converts an analog voltage into a pulse frequency. A particular type of Delta-Sigma converter consists of two conversion stages, where after a coarse voltage conversion, the residual voltage is sampled and converted to a digital signal by the second converter stage. A general schematic of a current integration configuration is depicted in Figure 6a. Figure 6b is a corresponding timing diagram, which shows the temporal variation of the relevant signals and quantities on a time line pointing towards the right. The signal indicated as "elk" is the clock signal providing the minimum time unit employed in the circuit. The signal indicated as "sample" is high only during the sampling time, which in this example equals the clock period. The signal indicated as "clk_DAC" is derived from "elk" and is the clock signal provided for the feedback DAC to produce a synchronized feedback voltage "V_{out &}" based on the previous comparator decision. "Ι±_η" is the input current, which is assumed to be constant in the example of Figure 6b. "V_out int " is the output integrated voltage, which is indicated in

Figure 6a.

The input current I i_n is integrated on the integration capacitor C±_ntr thus leading to a growing output integrated voltage V_out int · 1

V.... [ /,.„ - dt

r Jo ^m

The output integrated voltage V_out ±_nt will eventually saturate and is kept in the allowed range by means of a feedback loop. Pulsed feedback is effected by a digital-to-analog converter (DAC) , which may be a switched capacitor digital-to-analog converter or a switched current source digital-to-analog converter. The DAC removes charge packages from the

integration capacitor Ci_nt during the feedback clock period Tcik DAc when the previous comparator decision was logic zero to keep I V_out__int | < I_max · T_ci_k__DAC for a maximal input current I_max. Owing to the pulsed nature of the feedback clock signal clk_DAC, settling is required within one feedback clock period Tcik DAc- This impacts the output noise and increases the power consumption significantly.

The total output noise V_noi_{se 0}ut,rm_S is calculated as follows. The input referred noise of the operational transconductance amplifier (OTA) is applied at the positive input in the voltage domain (Vi_n ⁺ in Figure 6a) . Thus it is not integrated, but amplified by the inverse feedback factor β^_1 = 1+ (C_p/Ci_nt) :

In order to obtain the total output noise after sampling, noise out must be inte rated over the whole spectrum:

Assuming constant white noise Vi_n = k_n/g_m with

transconductance and noise constant k_n, this yields

V n.oise out,rms

GBW g _

Inserting BW = =—— - , where GBW is the gain-bandwidth product and C_e = C_s + (C_int || C_p) , yields

Consequently, the output noise is independent of the

transconductance g_m and therefore independent of the power consumption. The reason is that a smaller transconductance g increases noise, but at the same time reduces the gain- bandwidth product GBW, resulting in higher noise filtering. The calculation so far assumed that the GBW value is not relevant, i. e. the power consumption can be arbitrarily reduced at the cost of settling speed. However, typically there is a settling requirement related to feedback clock period T

r , T T T n

settling _ factor =—= =—= =— g_m - fi (2)

BW

Solving equation (2) for C_eq and substituting the expression thus obtained in equation (1) yields

V_{noise out,rms} = J— · settling _ factor

4 ' T_{dk DAC} · g_m ^■ β

The settling time is tied to the DAC clock period due to the pulsed nature of the feedback DAC. Using a non-pulsed continuous feedback current would alleviate the settling constraint. However, this does not provide the inherent analog-to-digital conversion present in the DAC based feedback .

Alternatively, a smoothing filter could be used after the DAC, but this can cause instability in a higher order feedback path. Furthermore, the feedback current does not have a one to one correspondence to the DAC pulses, because it is not known how much of the current comes from the feedback pulses directly before and after output sampling. It is an object of the invention to provide power savings in current integration.

This object is achieved with the method of current

integration according to claim 1 and claim 8, respectively, and with the circuit for current integration according to claim 9 and claim 14, respectively. Variants and embodiments derive from the dependent claims.

The definitions as described above also apply to the

following description unless stated otherwise.

In one aspect of the invention, a method of current

integration is applied, which comprises transforming an input current into an output integrated voltage using a parallel connection of an operational transconductance amplifier (OTA) and an integration capacitor, reducing the output integrated voltage by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter (DAC) generating feedback pulses, a feedback clock period defining time intervals between successive rising edges of the feedback pulses, and sampling during an extended feedback clock period after a lapse of a plurality of feedback clock periods. The extended feedback clock period may especially be twice as long as the feedback clock period.

In a variant of the method, the gain-bandwidth product (GBW) of the operational transconductance amplifier is reduced during sampling. In a further variant of the method, a range check is

performed for the output integrated voltage before sampling. The range check is based on the number of feedback pulses occurring prior to sampling.

In further variants of the method, a switched capacitor digital-to-analog converter or a switched current source digital-to-analog converter is applied.

In a further variant of the method, further feedback pulses are generated between the feedback pulses generated by the digital-to-analog converter. For this purpose a further digital-to-analog converter is applied in the feedback loop.

In a further aspect of the invention, the method of current integration comprises transforming an input current into an output integrated voltage using a parallel connection of an operational transconductance amplifier and an integration capacitor, reducing the output integrated voltage by

repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, applying an electric power for the

operational transconductance amplifier, and elevating the applied electric power only for sampling during a sampling time .

In a further aspect of the invention, a circuit for current integration is provided, which comprises a parallel

connection of an integration capacitor, an operational transconductance amplifier and a feedback loop, the

operational transconductance amplifier being configured to transform an input current into an output integrated voltage, a digital-to-analog converter in the feedback loop, the digital-to-analog converter being configured to generate feedback pulses triggering discharges of the integration capacitor, a feedback clock period defining time intervals between successive rising edges of the feedback pulses, and a controller configured to provide an extended feedback clock period after a lapse of a plurality of feedback clock periods . In an embodiment of the circuit, the controller is configured to perform a range check for the output integrated voltage before sampling, the range check being based on a number of feedback pulses prior to sampling. In further embodiments of the circuit, the digital-to-analog converter is a switched capacitor digital-to-analog converter or a switched current source digital-to-analog converter.

A further embodiment of the circuit comprises a further digital-to-analog converter in the feedback loop, the

controller being configured to enable an alternative

operation of the digital-to-analog converter and the further digital-to-analog converter. In a further aspect of the invention, the circuit comprises a parallel connection of an integration capacitor, an

operational transconductance amplifier and a feedback loop, the operational transconductance amplifier being configured to transform an input current into an output integrated voltage, a digital-to-analog converter in the feedback loop, the digital-to-analog converter being configured to generate feedback pulses triggering discharges of the integration capacitor, a supply of electric power for the operational transconductance amplifier, and a controller configured to elevate the applied electric power only during sampling.

The method can be implemented, for example, by one of the corresponding embodiments of the current integration circuit.

The following is a more detailed description of examples of the method and the circuit in conjunction with the appended figures .

Figure 1 shows timing diagrams for unmodulated operation,

sampling time modulation and power modulation.

Figure 2 shows timing diagrams for sampling time modulation.

Figure 3 shows circuit diagrams for GBW reduction of the OTA.

Figure 4 shows an embodiment of the circuit.

Figure 5 shows a timing diagram for the embodiment according to Figure 4.

Figure 6 shows a circuit diagram for a current integrator

with feedback and a corresponding timing diagram.

According to one aspect of the invention, doubling the T_{cik DAC} takes place during the last cycle, just before sampling, depending on the input current level. As the noise of the OTA is not integrated, only the instantaneous noise during the sampling instant is relevant. The OTA noise power during the rest of the integration time is irrelevant. For input levels below half range of the input current, the frequency of the feedback pulse is smaller than the clock frequency (in the example of Figure lb, the frequency of the pulses shown as " out a" is half the frequency of the clock signal "elk") .

When the OTA is allowed to settle longer by increasing the feedback clock period T_{cik DAC}, a smaller transconductance g_m is required and therefore less power for the same output noise. However, the feedback clock period T_{cik DAC} is tied to the frequency of feedback pulses needed to keep the output integrated voltage V_out ±_nt in the required voltage range.

Hence, the speed of the OTA can be set high during the major integration time but lower for higher noise filtering during the last cycle right before the sampling instant, if the signal range during that cycle is below half range. The last condition is important, because the last DAC clock cycle has to be doubled, thus allowing only one feedback pulse to occur .

As a result, low noise performance is achieved for the lower signal range where high SNR (signal-to-noise ratio) is most important. For the larger input range, the noise of the DAC is dominant, making the higher OTA noise insignificant.

Increasing the DAC period for the last cycle by a factor N increases the available time for settling by N, thus

resulting in a factor N power saving for the same output noise (assuming the power is proportional to g_m which is the case for OTA input transistors close to weak inversion) .

A timing diagram for a conventional operation is depicted in Figure la, which shows the temporal variation of the relevant signals, quantities and parameters on a time line pointing towards the right. The signal indicated as "elk" is the clock signal providing the clock period T_cik as the minimum time unit employed in the circuit. The signal indicated as

"sample" is high only during the sampling time, which in this example equals the clock period T_cik. The signal indicated as "clk_DAC" is the clock signal provided for the feedback loop and is the same as the signal "elk" during conventional operation. Hence in Figure la the feedback clock period

T_cik DAc is the same as the clock period Τ_αι¾. "V_out a" is the feedback voltage indicated in Figure 6a. "Ι±_η" is the input current, which is assumed to be constant in the example of Figure la. "V_out i_nt" is the output integrated voltage, which is indicated in the circuit diagram of Figure 6a. "GBW" is the gain-bandwidth product of the OTA, "g_m" is the

transconductance of the OTA and "P" is the consumed power of the OTA.

A timing diagram for operation by sampling time modulation is depicted in Figure lb. Compared with the conventional

operation according to Figure la, the feedback clock period Tcik DAc that corresponds to the sampling time T_sampi_e is

increased. In the example shown in Figure lb, sampling is performed during an extended feedback clock period T*, which is N times as long (in the example of Figure lb especially twice as long) as the regular feedback clock period Τ_αι¾ DAC- Moreover, the GBW is reduced during sampling. Thus the sampling time is increased, especially doubled.

In a prescribed time interval, which is highlighted in Figure lb, a range check is performed based on the number of

feedback pulses immediately prior to sampling. Important for the feasibility is the assumption that the time constant of the input current is significantly below the sampling time. This constraint does not result in loss of signal information, because the total integration time is a multiple of the feedback clock period T_ci_{k DAC} .

In Figure 2 two different scenarios are exemplified. The worst case scenario in terms of the range of the output integrated voltage V_out ±_ntr which is depicted in Figure 2a, occurs for half range input when the output integrated voltage V_out ±_nt is just below the reference voltage V_ref

(indicated in Figure 6a) upon entering the sample period, i. e. feedback is not triggered. This results in the maximal possible value of the output integrated voltage V_out ±_nt at the moment when sampling is required, because the next feedback pulse is delayed by two clock periods T_cik. However, as shown in Figure 2a, by limiting the application of the extended feedback clock period T* to input signals below half range, the risk of exceeding the allowed output range can be

obviated .

For signals above half range, T_{cik DAC} is kept equal to T_cik to avoid out of range conditions, according to Figure 2b, corresponding to a conventional operation according to Figure la. As in this regime DAC noise is typically dominant, the power consumption can still be reduced to one half compared to the power consumption for conventional operation.

A timing diagram for an alternative operation by power modulation is depicted in Figure lc. In the method according to Figure lc, the feedback clock period T_{cik DAC} is kept constant, but the supply power P and the transconductance g_m are increased during sampling in combination with a reduction of the GBW of the OTA. In this way the majority of clock cycles can run at reduced power. However, the increase in supply current in the last cycle can result in supply noise, thus deteriorating accuracy. If a large number of parallel integrators with shifted sampling times is integrated on one chip, the supply current pulsing might smooth out on the main supply line.

The GBW of the OTA during sampling can either be reduced by implementing additional load capacitance, which may be achieved with the circuit according to Figure 3a, or by attenuating the output current of the OTA during sampling, which may be achieved with the circuit according to Figure 3b. The GBW can also be reduced by lowering the

transconductance g_m, but this would not yield any benefit regarding noise. Figure 3a is a diagram of a circuit for adding a load

capacitor, which can be implemented in the OTA. The inputs and the output of the OTA are indicated by the corresponding voltages V_in ^", V_in ⁺ and V_out OTA- Figure 3a also shows the connection of the integration capacitor Cint between the negative Input (V_in ^") and the output (V_out OTA) of the OTA.

Figure 3b is a diagram of a circuit for reducing the output current, which can be implemented in the OTA. The inputs and the output of the OTA are indicated by the corresponding voltages V_in ^", V_in ⁺ and V_out OTA- Figure 3b also shows the connection of the integration capacitor Cint between the negative Input (V_in ^") and the output (V_out OTA) of the OTA.

Figure 4 is a circuit diagram for a device wherein the described method can be employed. The device may be a photocurrent readout circuit. The photodiode current is converted to a voltage by a current controlled oscillator. The total number of feedback pulses n_counti + n_count2 during one full integration period Ti_nt provides a coarse analog to digital conversion value, which is combined with a fine conversion result by digitization of the output voltage residue V_resi_due of the current integrator. DAC feedback is realized by precharged capacitors that are periodically discharged into the virtual ground node. Two equivalent switched capacitor digital-to-analog converters SC DAC1, SC DAC2 are implemented. The first switched capacitor

digital-to-analog converter SC DAC1 is always active by default. The second switched capacitor digital-to-analog converter SC DAC2 is activated in case two consecutive DAC pulses are required. In this way, after triggering the first switched capacitor digital-to-analog converter SC DAC1, at least the time interval of one clock period is provided for precharging before the first switched capacitor digital-to- analog converter SC DAC1 is triggered again. According to this concept, the second switched capacitor digital-to-analog converter SC DAC2 is only activated for input currents above half range. Activation of the second switched capacitor digital-to-analog converter SC DAC2 triggers an

"out_of_range" flag that prevents activation of the double sampling time scheme for large input currents. Figure 5 is a timing diagram for the operation of a device comprising the circuit according to Figure 4. "Ti_nt" is the integration period between two sampling events. "V_pui_sei" and " p_Uise2" are the pulsed voltages provided by the controller as indicated in Figure 4. An out-of-range condition is present when the signal "out_of_range" is high. Figure 5 shows how the second switched capacitor digital-to-analog converter SC DAC2 is used after triggering the first switched capacitor digital-to-analog converter SC DAC1 in out-of-range conditions, when immediately successive feedback pulses are required and there is no time for sufficient recovery of the first switched-capacitor digital-to-analog converter SC DAC1 after triggering. In an out-of-range condition, sampling is only performed for a time interval corresponding to the regular feedback clock period T_{cik 0}TA (which is indicated at position "A" in Figure 5) , whereas the sampling time is increased when no such condition is met (which is indicated at position "B" in Figure 5) .

This invention enables to reduce the power consumed in an integration stage for output residual sampling by a factor N, in particular by a factor of two.

List of reference numerals

Cint integration capacitor

elk clock signal

clk_DAC feedback clock signal

DAC digital-to-analog converter

GBW gain-bandwidth product

g_m transconductance

Iin input current

OTA operational transconductance amplifier

P power

sample sampling signal

SC DAC1 first switched capacitor digital-to-analog converter

SC DAC2 second switched capacitor digital-to-analog converter T_ci_k clock period

Tci_k DAc feedback clock period

T* extended feedback clock period

Tsample sampling time

Vin^" negative input of the OTA

Vin⁺ positive input of the OTA

V_out a feedback voltage

Vout im output integrated voltage

out OTA output of the OTA

Vpuigei first pulsed voltage

Vp_Ui_SE2 second pulsed voltage

V_ref reference voltage

Vresidue output voltage residue

Claims

1. A method of current integration, comprising:

transforming an input current (Ι±_η) into an output integrated voltage (V_out ±_nt) using a parallel connection of an

operational transconductance amplifier (OTA) and an

integration capacitor (Cin_t) ,

reducing the output integrated voltage (V_out ±_nt) by repeatedly discharging the integration capacitor (Ci_nt) through a

feedback loop via a digital-to-analog converter (DAC,

SC DAC1) generating feedback pulses, a feedback clock period (T_ci_k DAC) defining time intervals between successive rising edges of the feedback pulses, and

sampling during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T_{cik DAC}) .

2. The method of claim 1, wherein

the extended feedback clock period (T*) is N times as long as the feedback clock period (T_{cik DAC}) .

3. The method of claim 1 or 2, further comprising:

reducing a gain-bandwidth product (GBW) of the operational transconductance amplifier (OTA) during sampling.

4. The method of one of claims 1 to 3, further comprising: performing a range check for the output integrated voltage (V_out i_nt) before sampling, the range check being based on a number of feedback pulses prior to sampling.

5. The method of one of claims 1 to 4, wherein

the digital-to-analog converter (DAC, SC DAC1) is a switched capacitor digital-to-analog converter.

6. The method of one of claims 1 to 4, wherein

the digital-to-analog converter (DAC) is a switched current source digital-to-analog converter.

7. The method of one of claims 1 to 6, further comprising: generating further feedback pulses between the feedback pulses generated by the digital-to-analog converter (SC DAC1) by applying a further digital-to-analog converter (SC DAC2) in the feedback loop.

8. A method of current integration, comprising:

operational transconductance amplifier (OTA) and an

integration capacitor (Cint) r

reducing the output integrated voltage (V_out ±_nt) by repeatedly discharging the integration capacitor (Cint) through a feedback loop via a digital-to-analog converter (DAC,

SC DAC1) generating feedback pulses,

applying an electric power (P) for the operational

transconductance amplifier (OTA) , and

elevating the applied electric power (P) only for sampling during a sampling time (T_sampi_e) .

9. A circuit for current integration, comprising:

a parallel connection of an integration capacitor (Cint) t an operational transconductance amplifier (OTA) and a feedback loop, the operational transconductance amplifier (OTA) being configured to transform an input current (Ii_n) into an output integrated voltage (V_out int) ,

a digital-to-analog converter (DAC, SC DAC1) in the feedback loop, the digital-to-analog converter (DAC, SC DAC1) being configured to generate feedback pulses triggering discharges of the integration capacitor (Ci_nt) , a feedback clock period (T_ci_k DAC) defining time intervals between successive rising edges of the feedback pulses, and

a controller configured to provide an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T_ci_k__DAC) .

10. The circuit of claim 9, wherein:

the controller is configured to perform a range check for the output integrated voltage (V_out ±_nt) before sampling, the range check being based on a number of feedback pulses prior to sampling .

11. The circuit of claim 9 or 10, wherein

12. The circuit of claim 9 or 10, wherein

13. The circuit of one of claims 9 to 12, further comprising: a further digital-to-analog converter (SC DAC2) in the feedback loop, the controller being configured to enable an alternative operation of the digital-to-analog converter (SC DAC1) and the further digital-to-analog converter

(SC DAC2 ) .

14. A circuit for current integration, comprising:

a parallel connection of an integration capacitor (Ci_nt) an operational transconductance amplifier (OTA) and a feedback loop, the operational transconductance amplifier (OTA) being configured to transform an input current (Ι±_η) into an output integrated voltage (V_out ±_nt) ,

a digital-to-analog converter (DAC, SC DAC1) in the feedback loop, the digital-to-analog converter (DAC, SC DAC1) being configured to generate feedback pulses triggering discharges of the integration capacitor (Ci_nt) ,

a supply of electric power (P) for the operational

transconductance amplifier (OTA) , and

a controller configured to elevate the applied electric power (P) only during sampling.