WO2018233415A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2018233415A1
WO2018233415A1 PCT/CN2018/087200 CN2018087200W WO2018233415A1 WO 2018233415 A1 WO2018233415 A1 WO 2018233415A1 CN 2018087200 W CN2018087200 W CN 2018087200W WO 2018233415 A1 WO2018233415 A1 WO 2018233415A1
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Prior art keywords
metal layer
gate
coupled
layer
metal
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PCT/CN2018/087200
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English (en)
French (fr)
Inventor
李泽尧
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/339,372 priority Critical patent/US20190243201A1/en
Publication of WO2018233415A1 publication Critical patent/WO2018233415A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display panel and a display device.
  • the display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the display devices on the market are backlight-type display devices, which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel substrates, and apply driving voltages on the two substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture.
  • the thin film transistor display device includes a liquid crystal panel including a color filter substrate (CF Substrate, also referred to as a color filter substrate) and a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate).
  • CF Substrate also referred to as a color filter substrate
  • TFT Substrate Thin Film Transistor Substrate
  • a transparent electrode is present on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (LC) is sandwiched between the two substrates.
  • the conventional liquid crystal panel generally has a CF substrate in front (herein, "the front” is defined herein as the human eye 20), and the TFT substrate is rear, and the CF substrate 11 has a BM (black matrix, black).
  • a matrix layer also called a light-shielding layer, is used to prevent background light leakage and improve display contrast.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • PCB board print circuit board
  • the timing controller TCON Timing Controller,
  • IC is processed, through the PCB board, through the source film chip-on-chip S-COF (Source-Chip on Film) and gate film flip-chip G-COF (gate-Chip on Film) ,) is connected to the display area, so that the LCD obtains the required power and signal.
  • the core device in the LCD is a thin film transistor array (TFT), and for a single thin film transistor, there are mainly two kinds of signal inputs of a data signal and a gate drive signal, wherein the gate drive signal functions to open and close the TFT, We played a crucial role in the accurate input of data signals into Pixel over time.
  • TFT thin film transistor array
  • the technical problem to be solved by the present application is to provide a display panel capable of reducing the delay of a scanning line transmission signal.
  • the present application also provides a display device including the above display panel.
  • the invention discloses a display panel comprising:
  • a plurality of scan lines are formed on the substrate and coupled to the active switch, and the scan lines are vertically arranged with the data lines to form a plurality of pixel regions;
  • a gate driving circuit coupled to the plurality of scan lines
  • the scan line includes at least two metal layers, and an insulating layer is disposed between two adjacent metal layers.
  • the different metal layers are capacitively coupled to each other, and the scan line includes a first metal layer and a second metal layer.
  • the insulating layer is disposed between the first metal layer and the second metal layer, the first metal layer and the second metal are made of the same material, and the active switch includes a gate, the first metal layer and the second Metal layers are respectively coupled to the gates, the gates include a first gate metal layer and a second gate metal layer, the first metal layer is coupled to the first gate metal layer, and the second The metal layer is coupled to the second gate metal layer, the first metal layer is coupled to the first pin of the gate driving circuit, and the second metal layer and the second pin of the gate driving circuit Coupling.
  • the invention also discloses a display panel comprising:
  • a plurality of scan lines are formed on the substrate and coupled to the active switch, and the scan lines are vertically arranged with the data lines to form a plurality of pixel regions;
  • the scan line includes at least two metal layers, and an insulating layer is disposed between two adjacent metal layers, and different metal layers are capacitively coupled to each other.
  • the scan line includes a first metal layer and a second metal layer.
  • the insulating layer is disposed between the first metal layer and the second metal layer, and the insulating layer is made of silicon nitride or silicon oxide.
  • the first metal layer and the second metal may be the same material.
  • the active switch includes a gate, and the first metal layer and the second metal layer are respectively coupled to the gate, and the gate is only a single metal layer.
  • the active switch includes a gate, and the first metal layer and the second metal layer are respectively coupled to the gate, and the gate includes a first gate metal layer and a second gate metal layer The first metal layer is coupled to the first gate metal layer, and the second metal layer is coupled to the second gate metal layer.
  • the display panel further includes a gate driving circuit, the first metal layer is coupled to the first pin of the gate driving circuit, and the second metal layer and the second driving of the gate driving circuit The feet are coupled.
  • the display panel further includes a gate driving circuit, and the first metal layer and the second metal layer are coupled to the same pin of the gate driving circuit.
  • the invention also discloses a display device comprising a control circuit and a display panel, the display panel comprising:
  • a plurality of scan lines are formed on the substrate and coupled to the active switch, and the scan lines are vertically arranged with the data lines to form a plurality of pixel regions;
  • the scan line includes at least two metal layers, and an insulating layer is disposed between two adjacent metal layers, and different metal layers are capacitively coupled to each other.
  • the scan line includes a first metal layer and a second metal layer.
  • the insulating layer is disposed between the first metal layer and the second metal layer, and the insulating layer is made of silicon nitride or silicon oxide.
  • the first metal layer and the second metal may be the same material.
  • the active switch includes a gate, and the first metal layer and the second metal layer are respectively coupled to the gate, and the gate is only a single metal layer.
  • the active switch includes a gate, and the first metal layer and the second metal layer are respectively coupled to the gate, and the gate includes a first gate metal layer and a second gate metal layer The first metal layer is coupled to the first gate metal layer, and the second metal layer is coupled to the second gate metal layer.
  • the display panel further includes a gate driving circuit, the first metal layer is coupled to the first pin of the gate driving circuit, and the second metal layer and the second driving of the gate driving circuit The feet are coupled.
  • the display panel further includes a gate driving circuit, and the first metal layer and the second metal layer are coupled to the same pin of the gate driving circuit.
  • the scan line includes a first metal layer and a second metal layer, the insulating layer is disposed between the first metal layer and the second metal layer, and the insulating layer is made of silicon nitride. Or silicon oxide,
  • the scan line includes a first metal layer and a second metal layer, and the first metal layer and the second metal may be the same material.
  • the scan line includes at least two metal layers, and an insulating layer is disposed between two adjacent metal layers, and different metal layers are capacitively coupled to each other, and the scan line includes a first metal layer and a second metal.
  • a layer, the insulating layer is disposed between the first metal layer and the second metal layer, the first metal layer and the second metal are made of the same material
  • the active switch comprises a gate, the first metal layer and The second metal layer is respectively coupled to the gate, the gate includes a first gate metal layer and a second gate metal layer, and the first metal layer is coupled to the first gate metal layer, a second metal layer coupled to the second gate metal layer, a first metal layer coupled to the first pin of the gate driving circuit, and a second metal layer and a second of the gate driving circuit Pin coupling.
  • the conventional gate insulating layer uses a silicon dioxide film, which has a poor ability to block the diffusion of impurity particles, thereby greatly reducing the stability of the active switch, and the silicon nitride or silicon oxide film has excellent electrical properties. It also has a large dielectric constant and a stronger ability to block sodium ion diffusion and water vapor permeation as well as other impurity particles.
  • the scan line of the present application includes at least two metal layers, and different metal layers are capacitively coupled to each other, and the loading pressure of the scan line is reduced by the capacitive coupling effect between the metal layers, so that the scan line reduces the delay of the capacitor resistance during the process of transmitting the signal. Enables the scan line to accurately transmit signals to the pixel electrodes.
  • FIG. 1 is a schematic structural view of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a display panel and a gate driving according to an embodiment of the present application
  • FIG. 3 is another schematic view of a display panel and a gate drive according to an embodiment of the present application.
  • FIG. 4 is a top plan view of a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIG. 6 is another schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • first and second are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining “first” and “second” may include one or more of the features either explicitly or implicitly.
  • a plurality means two or more unless otherwise stated.
  • the term “comprises” and its variations are intended to cover a non-exclusive inclusion.
  • connection In the description of the present application, it should be noted that the terms “installation”, “connected”, and “connected” are to be understood broadly, and may be fixed or detachable, for example, unless otherwise explicitly defined and defined. Connected, or integrally connected; may be mechanically connected or coupled; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • Connected, or integrally connected may be mechanically connected or coupled; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two elements.
  • the embodiment discloses a display panel, including:
  • a plurality of scan lines are formed on the substrate and coupled to the active switch, and the scan lines are vertically arranged with the data lines to form a plurality of pixel regions;
  • the scan line includes at least two metal layers, and an insulating layer is disposed between two adjacent metal layers, and different metal layers are capacitively coupled to each other.
  • the scan line in this embodiment may include two metal layers, three metal layers or multiple metal layers, but is not limited to the specific number of layers listed in this embodiment.
  • the scan line includes at least two metal layers, and different metal layers are capacitively coupled to each other.
  • the capacitive coupling effect between the metal layers reduces the loading pressure of the scan lines, so that the scan lines reduce the delay of the capacitor resistance during the transmission of the signal, so that the scan The line accurately transmits the signal to the active switch.
  • the scan line includes the first metal layer 1 and the second metal layer 2
  • the first metal layer 1 and the second metal layer 2 are capacitively coupled.
  • the scan line In the case where there is only one layer of the scan line, if the resolution is increased, only if the scan line has only one layer, the scan line is loaded more and more, and the scan line is loaded more and more, which will cause the scan line to transfer the gate. In the process of driving the signal, the delay of the capacitor resistance is also more and more serious, which will make the gate drive signal transmission cannot be turned on or off as accurately as originally thought, resulting in the failure to reach the expected effect when transmitting the input signal to the pixel electrode. Therefore, the desired display effect cannot be achieved.
  • a coupling capacitance is generated between the first metal layer 1 and the second metal layer 2, so that The capacitive coupling effect between the metal layers reduces the loading pressure of the scan line, so that the scan line reduces the delay of the capacitor resistance during the transmission of the signal, so that the scan line can accurately transmit the signal to the pixel electrode, thereby achieving better display. effect.
  • the display panel includes: a substrate, a plurality of data lines, a plurality of scan lines formed on the substrate, formed on the substrate, and the scan lines and the data lines are vertically arranged to form a plurality of pixel regions;
  • the scan line includes a first metal layer 1 and a second metal layer 2, and an insulating layer 3 is disposed between the first metal layer 1 and the second metal layer 2, and the first metal layer 1 and the second metal layer 2 are capacitively coupled.
  • An insulating layer 3 is disposed between the first metal layer 1 and the second metal layer 2, which can block the diffusion of the impurity particles and improve the stability of the active switch.
  • the display panel includes: a substrate, a plurality of data lines, a plurality of scan lines formed on the substrate, formed on the substrate, and the scan lines and the data lines are vertically arranged to form a plurality of pixel regions;
  • the scan line includes a first metal layer 1 and a second metal layer 2, the first metal layer 1 and the second metal layer 2 are capacitively coupled, and the first metal layer 1 and the second metal layer 2 may be of the same material.
  • the first metal layer 1 and the second metal layer 2 can be made of the same material, so that the capacitive coupling effect between the first metal layer 1 and the second metal layer 2 is better, and the loading pressure of the scan line can be better reduced. Thereby, the scan line reduces the delay of the capacitor resistance during the process of transmitting the signal, so that the scan line can accurately transmit the signal to the pixel electrode, thereby achieving a better display effect.
  • the display panel includes a display panel including: a substrate, a plurality of scan lines and scan lines formed on the substrate, the scan lines and the data lines are vertically arranged to form a plurality of pixel regions; and the active switch comprises
  • the gate and the gate are disposed on the substrate, the gate is provided with an insulating layer, the corresponding gate on the insulating layer is provided with a semiconductor layer, and the source and the drain of the separated active switch are provided on both ends of the semiconductor layer, the source and the A channel is provided between the drains, and the bottom of the channel is a semiconductor layer.
  • the scan line includes a first metal layer 1 and a second metal layer 2, respectively, the first metal layer 1 and the second metal layer 2 are coupled to the gate, and the gate is only a single metal layer.
  • the display panel includes a display panel including: a substrate, a plurality of scan lines and scan lines formed on the substrate, the scan lines and the data lines are vertically arranged to form a plurality of pixel regions; and an active switch,
  • the active switch includes a gate, the gate is disposed on the substrate, the gate is provided with an insulating layer, the corresponding gate on the insulating layer is provided with a semiconductor layer, and the source and the drain of the separated active switch are disposed at two ends of the semiconductor layer, A channel is provided between the source and the drain, and the bottom of the channel is a semiconductor layer.
  • the scan line includes a first metal layer 1 and a second metal layer 2, respectively, the first metal layer 1 and the second metal layer 2 are coupled to the gate, and the gate includes a first gate metal layer and a second gate metal layer.
  • the first metal layer 1 is coupled to the first gate metal layer
  • the second metal layer 2 is coupled to the second gate metal layer.
  • the display panel includes a display panel including: a substrate, a plurality of scan lines and scan lines formed on the substrate, the scan lines and the data lines are vertically arranged to form a plurality of pixel regions; and the display panel further Including the gate driving circuit 4, the first metal layer 1 is coupled to the first pin of the gate driving circuit 4, and the second metal layer 2 is coupled to the second pin of the gate driving circuit 4.
  • the first metal layer 1 is directly connected to the first pin, and the second metal layer 2 is directly connected to the second pin, so that the production process is simpler in production.
  • the display panel includes a display panel including: a substrate, a plurality of scan lines and scan lines formed on the substrate, the scan lines and the data lines are vertically arranged to form a plurality of pixel regions; and the display panel further
  • the gate driving circuit 4 is included, and the first metal layer 1 and the second metal layer 2 are coupled to the same pin of the gate driving circuit 4.
  • the first metal layer 1 and the second metal layer 2 share a pin for coupling, so that when the signal is transmitted to the first metal layer 1 and the second metal layer 2, the first metal layer 1 and the second metal can be simultaneously input. Layer 2, thereby achieving the function of capacitive coupling.
  • the display panel includes: a substrate, a plurality of scan lines and scan lines formed on the substrate, the scan lines and the data lines are vertically arranged to form a plurality of pixel regions; and the scan lines include the first metal Layer 1 and second metal layer 2, the first metal layer 1 and the second metal layer 2 of the scan line are arranged in parallel, an insulating layer 3 is disposed between the first metal layer 1 and the second metal layer 2, and the insulating layer 3 is made of nitrogen.
  • the display panel further comprises an active switch, the active switch comprises a gate, the gate is arranged on the substrate, the gate is provided with an insulating layer, the corresponding gate on the insulating layer is provided with a semiconductor layer, and the semiconductor layer is provided on both ends thereof
  • a source and a drain are provided with a separate active switch, a channel is provided between the source and the drain, and a semiconductor layer is formed at the bottom of the channel.
  • the first metal layer 1 and the second metal layer 2 are respectively coupled to the gate, and the gate includes a first gate metal layer and a second gate metal layer, and the first metal layer 1 is coupled to the first gate metal layer.
  • the second metal layer 2 is coupled to the second gate metal layer.
  • the capacitive coupling effect between the metal layers reduces the loading pressure of the scan line, so that the scan line reduces the delay of the capacitor resistance during the transmission of the signal, so that the scan line can accurately transmit the signal to the pixel electrode, while the conventional gate
  • the insulating layer 3 is made of a silicon dioxide film, and the insulating layer 3 has a poor ability to block the diffusion of the impurity particles, thereby greatly reducing the stability of the active switch, and the silicon nitride or silicon oxide film has excellent electrical properties in addition to excellent electrical properties. Larger dielectric constant and stronger ability to block sodium ion diffusion and water vapor permeation and other impurity particles.
  • the metal layers partially overlap, and the overlapping portions are coupled through the via holes.
  • the edge of the substrate 10 is bound with a data driving circuit 13 and a gate driving circuit 4.
  • the display area of the substrate 10 includes a horizontally arranged scanning line 12 and a vertically disposed data line 11, and the active switch 14 and the data line respectively 11 and the scan line 12 are coupled; a plurality of pixels 15 are disposed in a rectangular area formed by sequentially intersecting the plurality of data lines and the plurality of scan lines, and the pixels 15 are electrically connected to the active switch 14.
  • the embodiment discloses a method of manufacturing a display panel.
  • Optional mask process cleaning the substrate, sputtering a first metal material layer on the cleaned substrate, performing a pre-film cleaning after the first metal material layer is sputtered, and then cleaning the first metal Coating a photoresist on the material layer, aligning and exposing the photoresist with a first mask, developing a pattern of the first metal layer with the developer in the first metal material layer, and then using the etching solution to the first metal material layer Etching is performed to obtain a first metal layer, and the residual photoresist is removed.
  • An optional mask process cleaning the substrate, depositing a first protective layer on the first metal layer by chemical vapor deposition on the first metal layer, and then sputtering a second metal material layer on the first protective layer to complete After the sputtering of the second metal material layer, the film is cleaned before film formation, and then the photoresist is coated on the second metal material layer after the cleaning, and the photoresist is aligned and exposed by the second mask, and the developer is used in the first layer.
  • the second metal material layer is developed to obtain a pattern of the second metal layer, and then the second metal material layer is etched with an etchant to obtain a second metal layer, and the residual photoresist is removed.
  • An optional mask process cleaning the substrate, depositing a second protective layer on the second metal layer on the second metal layer by chemical vapor deposition, and then sputtering the semiconductor material layer on the second protective layer to complete the semiconductor material
  • the pre-film cleaning is performed, then the photoresist is coated on the cleaned semiconductor material layer, the photoresist is aligned and exposed by the third mask, and the semiconductor layer is developed by the developer in the semiconductor material layer.
  • the pattern is then etched with an etchant to obtain a semiconductor layer to remove residual photoresist.
  • Optional mask process cleaning the substrate, forming a third metal material layer on the cleaned semiconductor layer, performing a pre-film cleaning after the third metal material layer is sputtered, and then cleaning the third metal material layer Coating the photoresist, aligning and exposing the photoresist with a fourth mask, developing a pattern of the third metal layer with the developer in the third metal material layer, and then etching the third metal material layer with an etching solution
  • the third metal layer is obtained, that is, the source and the drain of the active switch are removed, and the residual photoresist is removed.
  • Optional mask process cleaning the substrate, forming a third protective material layer on the cleaned third metal layer, then applying a photoresist on the third metal material layer, and aligning the photoresist with a fifth mask And exposing, developing a pattern of the passivation layer on the third protective material layer with a developing solution, and then etching the third protective material layer with an etching solution to obtain a passivation layer, and removing the residual photoresist.
  • Optional mask process cleaning the substrate, forming a transparent electrode material layer on the cleaned passivation layer, then coating the photoresist on the transparent electrode material layer, and aligning and exposing the photoresist with a sixth mask.
  • the pattern of the transparent electrode layer is obtained by developing the transparent electrode material layer with a developing solution, and then etching the transparent electrode material layer with an etching solution to obtain a transparent electrode layer, and removing the residual photoresist.
  • the embodiment discloses a method of manufacturing a display panel.
  • Optional mask process firstly, the substrate is cleaned, the first metal material layer is sputtered on the cleaned substrate, the first metal material layer is sputtered, the film is cleaned before film formation, and then the first after cleaning. Coating a photoresist on the metal material layer, aligning and exposing the photoresist with a first mask, developing a pattern of the first metal layer with the developer in the first metal material layer, and then using the etching solution to the first metal material The layer is etched to obtain a first metal layer, and the residual photoresist is removed.
  • An optional mask process cleaning the substrate, depositing a first protective layer on the first metal layer by chemical vapor deposition on the first metal layer, and then sputtering a second metal material layer on the first protective layer to complete After the sputtering of the second metal material layer, the film is cleaned before film formation, and then the photoresist is coated on the second metal material layer after the cleaning, and the photoresist is aligned and exposed by the second mask, and the developer is used in the first layer.
  • the second metal material layer is developed to obtain a pattern of the second metal layer, and then the second metal material layer is etched with an etchant to obtain a second metal layer, and the residual photoresist is removed.
  • An optional mask process cleaning the substrate, and sequentially sputtering the second protective layer material, the semiconductor material layer and the third metal material layer on the second metal layer by chemical vapor deposition on the second metal layer;
  • the pre-film cleaning is performed, then the photoresist is coated on the cleaned third metal material layer, the photoresist is aligned and exposed by the third mask, and the developing solution is used to develop the third metal material layer.
  • the pattern of the third metal layer is then etched with an etchant to obtain a third metal layer to remove residual photoresist.
  • Optional mask process cleaning the substrate, forming a third protective material layer on the cleaned third metal layer, then applying a photoresist on the third metal material layer, and aligning the photoresist with a fifth mask And exposing, developing a pattern of the passivation layer on the third protective material layer with a developing solution, and then etching the third protective material layer with an etching solution to obtain a passivation layer, and removing the residual photoresist.
  • Optional mask process cleaning the substrate, forming a transparent electrode material layer on the cleaned passivation layer, then coating the photoresist on the transparent electrode material layer, and aligning and exposing the photoresist with a sixth mask.
  • the pattern of the transparent electrode layer is obtained by developing the transparent electrode material layer with a developing solution, and then etching the transparent electrode material layer with an etching solution to obtain a transparent electrode layer, and removing the residual photoresist.
  • the display panel of the embodiment of the present application may be any of the following: a twisted nematic (TN) display panel or a Super Twisted Nematic (STN) type display panel, and an in-plane switching (In-Plane Switching, IPS) Type display panel, Vertical Alignment (VA) type display panel, liquid crystal display panel, OLED display panel, QLED display panel, curved display panel or other display panel.
  • TN twisted nematic
  • STN Super Twisted Nematic
  • IPS in-plane switching
  • VA Vertical Alignment
  • liquid crystal display panel OLED display panel
  • QLED display panel QLED display panel
  • curved display panel or other display panel curved display panel or other display panel.
  • the active switch of the present application includes a thin film transistor.
  • the embodiment discloses a display device 100.
  • the display device includes a control circuit board 200 and a display panel 300.
  • the specific structure of the display device 100 in this embodiment is shown. And the connection relationship can be seen in the display panel 300 in the above embodiment, and see FIGS. 1 to 3.
  • the display device will not be described in detail one by one.
  • the display device of the embodiment of the present application may be a liquid crystal display device, a QLED display device, an OLED (Organic Light-Emitting Diode) display device, or other display device.
  • the liquid crystal display device When the display device of the embodiment of the present application is a liquid crystal display device, the liquid crystal display device includes a backlight module, and the backlight module can be used as a light source for supplying a sufficient light source with uniform brightness and distribution.
  • the backlight module of this embodiment The group may be of the front light type or the backlight type. It should be noted that the backlight module of the embodiment is not limited thereto.

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Abstract

一种显示面板及显示装置，显示面板包括：基板（10），主动开关（14），形成于基板（10）上；多条数据线（11），形成于基板（10）上，与主动开关（14）耦接；多条扫描线（12），形成于基板（10）上，与主动开关（14）耦接，扫描线（12）与数据线（11）垂直排列，以形成多个像素区；扫描线（12）包括至少两层金属层（1，2），相邻两层金属层（1，2）之间设置有绝缘层（3），不同金属层之间相互电容耦合。

Description

一种显示面板及显示装置 【技术领域】
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
【背景技术】
显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的显示装置大部分为背光型显示装置，其包括液晶面板及背光模组(backlight module)。液晶面板的工作原理是在两片平行的基板当中放置液晶分子，并在两片基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管显示装置(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管显示装置包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)和薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。现有的液晶面板一般都是CF基板在前(在此将此处的“在前”定义为人眼20所视之处)，而TFT基板在后，CF基板11中具有BM(black matrix，黑矩阵)层，也称遮光层，用于防止背景光泄漏，提高显示对比度。
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管显示装置)是当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。TFT-LCD主要驱动原理，系统主板将R/G/B三色压缩信号、控制信号及动力通过线材与印刷板(print circuit board，PCB板)上的连接器connector相连接，数据经过PCB板上的时序控制器TCON(Timing Controller，)IC处理后，经PCB板，通过源极薄膜覆晶S-COF(Source-Chip on Film)和栅极薄膜覆晶G-COF(栅极 -Chip on Film，)与显示区连接，从而使得LCD获得所需的电源、信号。
LCD中的核心器件是薄膜晶体管阵列(TFT)，而对于单个薄膜晶体管而言主要有数据信号和栅极驱动信号两种信号输入，其中栅极驱动信号起到了打开和关闭TFT的作用，其对于我们在时间上向Pixel内精确的输入数据信号起到了至关重要的作用。
随着LCD分辨率越来越高，在显示区内一条扫描线上的负载(loading)也越来越大，而负载的增大使得栅极驱动信号在传输的过程中发生的阻容延时(RC delay)也越来越严重。
【发明内容】
本申请所要解决的技术问题是提供一种能够降低扫描线传输信号延迟的显示面板。
此外，本申请还提供一种包括以上所述显示面板的显示装置。
本申请的目的是通过以下技术方案来实现的：
本发明公开了一种显示面板，包括：
基板，
主动开关，形成于基板上；
多条数据线，形成于所述基板上，与主动开关耦接；
多条扫描线，形成于所述基板上，与主动开关耦接，所述扫描线与所述数据线垂直排列，以形成多个像素区；
栅极驱动电路，与多条所述扫描线耦接；
其中，所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合，所述扫描线包括第一金属层和第二金属层，所述绝缘层设置在所述第一金属层和第二金属层之间，所述第一金属层和第二金属采用相同的材料，主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一 金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
本发明还公开了一种显示面板，包括：
基板，
主动开关，形成于基板上；
多条数据线，形成于所述基板上，与主动开关耦接；
多条扫描线，形成于所述基板上，与主动开关耦接，所述扫描线与所述数据线垂直排列，以形成多个像素区；
所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合。
可选的，所述扫描线包括第一金属层和第二金属层。
可选的，所述绝缘层设置在所述第一金属层和第二金属层之间，所述绝缘层采用的材料为氮化硅或氧化硅。
可选的，所述第一金属层和第二金属可采用相同的材料。
可选的，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极仅为单层金属层。
可选的，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接。
可选的，所述显示面板还包括栅极驱动电路，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
可选的，所述显示面板还包括栅极驱动电路，所述第一金属层和所述第二金属层与所述栅极驱动电路的同一引脚耦接。
本发明还公开了一种显示装置，包括控制电路及与显示面板，所述显示面板包括：
基板；
主动开关，形成于基板上；
多条数据线，形成于所述基板上，与主动开关耦接；
多条扫描线，形成于所述基板上，与主动开关耦接，所述扫描线与所述数据线垂直排列，以形成多个像素区；
所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合。
可选的，所述扫描线包括第一金属层和第二金属层。
可选的，所述绝缘层设置在所述第一金属层和第二金属层之间，所述绝缘层采用的材料为氮化硅或氧化硅。
可选的，所述第一金属层和第二金属可采用相同的材料。
可选的，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极仅为单层金属层。
可选的，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接。
可选的，所述显示面板还包括栅极驱动电路，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
可选的，所述显示面板还包括栅极驱动电路，所述第一金属层和所述第二金属层与所述栅极驱动电路的同一引脚耦接。
可选的，所述扫描线包括第一金属层和第二金属层，所述绝缘层设置在所述第一金属层和第二金属层之间，所述绝缘层采用的材料为氮化硅或氧化硅，
可选的，所述扫描线包括第一金属层和第二金属层，所述第一金属层和第二金属可采用相同的材料。
可选的，所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合，所述扫描线包括第一金属层和第二金属 层，所述绝缘层设置在所述第一金属层和第二金属层之间，所述第一金属层和第二金属采用相同的材料，主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
传统的栅极绝缘层采用二氧化硅薄膜，这种绝缘层阻挡杂质粒子扩散的能力很差，从而大大降低了主动开关的稳定性能，而氮化硅或氧化硅薄膜除了优秀的电学性能外，还具有较大的介电常数及更强的阻挡钠离子扩散以及水汽渗透以及其他杂质粒子扩散的能力。
本申请扫描线至少包括两层金属层，不同金属层相互电容耦合，通过金属层之间电容耦合效应，降低扫描线的加载压力，从而使得扫描线在传输信号的过程中降低电容电阻的延迟，使得扫描线能够准确的将信号传输到像素电极。
【附图说明】
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一实施例显示面板结构示意图；
图2是本申请一实施例显示面板与栅极驱动示意图；
图3是本申请一实施例显示面板与栅极驱动另一个示意图；
图4是本申请一实施例显示面板的俯视示意图；
图5是本申请一实施例显示面板制造方法的流程示意图；
图6是本申请一实施例显示面板制造方法的另一个流程示意图；
图7是本申请一实施例显示装置结构示意图。
【具体实施方式】
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是耦接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和较佳的实施例对本申请作进一步详细说明。
如图1至3所示，本实施方式公开了一种显示面板，包括：
基板，
主动开关，形成于基板上；
多条数据线，形成于所述基板上，与主动开关耦接；
多条扫描线，形成于所述基板上，，与主动开关耦接，所述扫描线与所述数据线垂直排列，以形成多个像素区；
所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合。
需要说明的是，本实施例中扫描线可以包括两层金属层、三层金属层或者多种金属层，但是不限于本实施例中所列举的具体层数。
扫描线至少包括两层金属层，不同金属层相互电容耦合，通过金属层之间电容耦合效应，降低扫描线的加载压力，从而使得扫描线在传输信号的过程中降低电容电阻的延迟，使得扫描线能够准确的将信号传输到主动开关。
作为本实施例的进一步改进，其中，扫描线包括第一金属层1和第二金属层2，第一金属层1和第二金属层2电容耦合。
扫描线只有一层的情况下，如果分辨率增高，这样只有扫描线只有一层的情况下，扫描线加载也越来越大，而扫描线加载越来越大，将使得扫描线传输栅极驱动信号的过程中，电容电阻的延迟也越来越严重，这样将使得栅极驱动信号传输不能按照最初的设想一样准确的打开或者关闭，从而导致向像素电极传输输入信号时不能到达预期的效果，这样就不能达到预期的显示效果，因此，通过第一金属层1和第二金属层2相互电容耦合后，第一金属层1与第二金属层2之间会产生耦合电容，这样可以通过金属层之间电容耦合效应，降低扫描线的加载压力，从而使得扫描线在传输信号的过程中降低电容电阻的延迟，使得扫描线能够准确的将信号传输到像素电极，从而达到更好的显示效果。
作为本实施例的进一步改进，其中，显示面板包括：基板，多条数据线，形成于基板上多条扫描线，形成于基板上，扫描线与数据线垂直排列，以形成 多个像素区；扫描线包括第一金属层1和第二金属层2，第一金属层1和第二金属层2之间设有绝缘层3，第一金属层1和第二金属层2电容耦合。
第一金属层1和第二金属层2之间设有绝缘层3，这样可以阻挡杂质粒子的扩散，提高主动开关的稳定性能。
作为本实施例的进一步改进，其中，显示面板包括：基板，多条数据线，形成于基板上多条扫描线，形成于基板上，扫描线与数据线垂直排列，以形成多个像素区；扫描线包括第一金属层1和第二金属层2，第一金属层1和第二金属层2电容耦合，第一金属层1和第二金属层2可采用相同材料。
第一金属层1和第二金属层2可采用的相同的材料，这样第一金属层1和第二金属层2之间的电容耦合效果更好，能更好的降低扫描线的加载压力，从而使得扫描线在传输信号的过程中降低电容电阻的延迟，使得扫描线能够准确的将信号传输到像素电极，从而达到更好的显示效果。
作为本实施例的进一步改进，其中，显示面板包括显示面板包括：基板，形成于基板上的多条扫描线和扫描线，扫描线与数据线垂直排列，以形成多个像素区；主动开关包括栅极，栅极设在基板上，栅极上设有绝缘层，绝缘层上对应栅极设有半导体层，半导体层两端上设有分隔的主动开关的源极和漏极，源极和漏极之间设有沟道，沟道底部为半导体层。扫描线包括第一金属层1和第二金属层2，第一金属层1和第二金属层2分别与栅极耦接，栅极仅为单层金属层。
作为本实施例的进一步改进，其中，显示面板包括显示面板包括：基板，形成于基板上的多条扫描线和扫描线，扫描线与数据线垂直排列，以形成多个像素区；主动开关，主动开关包括栅极，栅极设在基板上，栅极上设有绝缘层，绝缘层上对应栅极设有半导体层，半导体层两端上设有分隔的主动开关的源极和漏极，源极和漏极之间设有沟道，沟道底部为半导体层。扫描线包括第一金属层1和第二金属层2，第一金属层1和第二金属层2分别与栅极耦接，栅极包括第一栅极金属层和第二栅极金属层，第一金属层1与第一栅极金属层耦接， 第二金属层2与第二栅极金属层耦接。
作为本实施例的进一步改进，其中，显示面板包括显示面板包括：基板，形成于基板上的多条扫描线和扫描线，扫描线与数据线垂直排列，以形成多个像素区；显示面板还包括栅极驱动电路4，第一金属层1与栅极驱动电路4第一引脚耦接，第二金属层2与栅极驱动电路4的第二引脚耦接。
第一金属层1和第一引脚直接连接，第二金属层2与第二引脚直接连接，这样在生产制造时，生产工艺更加简单。
作为本实施例的进一步改进，其中，显示面板包括显示面板包括：基板，形成于基板上的多条扫描线和扫描线，扫描线与数据线垂直排列，以形成多个像素区；显示面板还包括栅极驱动电路4，第一金属层1和第二金属层2与栅极驱动电路4的同一引脚耦接。
第一金属层1和第二金属层2共用一个引脚进行耦接，这样在信号传输到第一金属层1和第二金属层2时，能够同时输入到第一金属层1和第二金属层2，从而达到电容耦合的作用。
作为本实施例的进一步改进，其中，显示面板包括：基板，形成于基板上的多条扫描线和扫描线，扫描线与数据线垂直排列，以形成多个像素区；扫描线包括第一金属层1和第二金属层2，扫描线的第一金属层1和第二金属层2平行设置，第一金属层1和第二金属层2之间设有绝缘层3，绝缘层3采用氮化硅或氧化硅，显示面板还包括主动开关，主动开关包括栅极，栅极设在基板上，栅极上设有绝缘层，绝缘层上对应栅极设有半导体层，半导体层两端上设有分隔的主动开关的源极和漏极，源极和漏极之间设有沟道，沟道底部为半导体层。第一金属层1和第二金属层2分别与栅极耦接，栅极包括第一栅极金属层和第二栅极金属层，第一金属层1与第一栅极金属层耦接，第二金属层2与第二栅极金属层耦接。
通过金属层之间电容耦合效应，降低扫描线的加载压力，从而使得扫描线在传输信号的过程中降低电容电阻的延迟，使得扫描线能够准确的将信号传输 到像素电极，而传统的栅极绝缘层3采用二氧化硅薄膜，这种绝缘层3阻挡杂质粒子扩散的能力很差，从而大大降低了主动开关的稳定性能，而氮化硅或氧化硅薄膜除了优秀的电学性能外，还具有较大的介电常数及更强的阻挡钠离子扩散以及水汽渗透以及其他杂质粒子扩散的能力。
具体的，上述实施例中金属层部分重叠，重叠部分通过过孔耦接。
参考图4，基板10边缘绑定有数据驱动电路13和栅极驱动电路4，基板10的显示区域内包括水平设置的扫描线12和竖直设置的数据线11，主动开关14分别与数据线11和扫描线12耦合；多条所述数据线与多条所述扫描线依次相交形成的矩形区域内设置有多个像素15，像素15与主动开关14电连接。
参考图5，本实施方式公开一种显示面板的制造方法。
S41、在基板上形成第一金属层；
S42、在第一金属层上依次形成第一保护层和第二金属层；
S43、在第二金属层上依次形成第二保护层和半导体层；
S44、在半导体层上形成第三金属层；
S45、在第三金属层上形成钝化层；
S46、在钝化层上形成透明导电层。
上述六个过程代表了六个光罩制程，以下进一步阐述六道光罩制程的具体内容。
可选的光罩制程：对基板进行清洗，在清洗后的基板上溅镀第一金属材料层，完成第一金属材料层的溅镀后进行成膜前清洗，然后在清洗后的第一金属材料层上涂布光阻，采用第一光罩对光阻进行对准并曝光，用显影液在第一金属材料层显影获得第一金属层的图案，然后采用蚀刻液对第一金属材料层进行蚀刻获得第一金属层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在第一金属层上通过化学气相沉积技术将第一保护层沉积到第一金属层上，然后在第一保护层上溅镀第二金属材料层，完成第二金属材料层的溅镀后进行成膜前清洗，然后在清洗后的第二金属材料层 上涂布光阻，采用第二光罩对光阻进行对准并曝光，用显影液在第二金属材料层显影获得第二金属层的图案，然后采用蚀刻液对第二金属材料层进行蚀刻获得第二金属层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在第二金属层上通过化学气相沉积技术将第二保护层沉积到第二金属层上，然后在第二保护层上溅渡半导体材料层，完成半导体材料层的溅镀后进行成膜前清洗，然后在清洗后的半导体材料层上涂布光阻，采用第三光罩对光阻进行对准并曝光，用显影液在半导体材料层显影获得半导体层的图案，然后采用蚀刻液对半导体材料层进行蚀刻获得半导体层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在清洗后的半导体层上形成第三金属材料层，完成第三金属材料层的溅镀后进行成膜前清洗，然后在清洗后的第三金属材料层上涂布光阻，采用第四光罩对光阻进行对准并曝光，用显影液在第三金属材料层显影获得第三金属层的图案，然后采用蚀刻液对第三金属材料层进行蚀刻获得第三金属层，即可主动开关的源极和漏极，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在清洗后的第三金属层上形成第三保护材料层，然后在第三金属材料层上涂布光阻，采用第五光罩对光阻进行对准并曝光，用显影液在第三保护材料层显影获得钝化层的图案，然后采用蚀刻液对第三保护材料层进行蚀刻获得钝化层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在清洗后的钝化层上形成透明电极材料层，然后在透明电极材料层上涂布光阻，采用第六光罩对光阻进行对准并曝光，用显影液在透明电极材料层显影获得透明电极层的图案，然后采用蚀刻液对透明电极材料层进行蚀刻获得透明电极层，对残留的光阻进行去除。
参考图6，本实施方式公开一种显示面板的制造方法。
S51、在基板上形成第一金属层；
S52、在第一金属层上依次形成第一保护层和第二金属层；
S53、在第二金属层上依次形成第二保护层、半导体层和第三金属层；
S54、在第三金属层上形成钝化层；
S55、在钝化层上形成透明导电层。
上述五个过程代表了五个光罩制程，以下进一步阐述五道光罩制程的具体内容。
可选的光罩制程：首先对基板进行清洗，在清洗后的基板上溅镀第一金属材料层，完成第一金属材料层的溅镀后进行成膜前清洗，然后在清洗后的第一金属材料层上涂布光阻，采用第一光罩对光阻进行对准并曝光，用显影液在第一金属材料层显影获得第一金属层的图案，然后采用蚀刻液对第一金属材料层进行蚀刻获得第一金属层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在第一金属层上通过化学气相沉积技术将第一保护层沉积到第一金属层上，然后在第一保护层上溅镀第二金属材料层，完成第二金属材料层的溅镀后进行成膜前清洗，然后在清洗后的第二金属材料层上涂布光阻，采用第二光罩对光阻进行对准并曝光，用显影液在第二金属材料层显影获得第二金属层的图案，然后采用蚀刻液对第二金属材料层进行蚀刻获得第二金属层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在第二金属层上通过化学气相沉积技术在第二金属层上依次溅渡第二保护层材料、半导体材料层和第三金属材料层；
溅镀后进行成膜前清洗，然后在清洗后的第三金属材料层上涂布光阻，采用第三光罩对光阻进行对准并曝光，用显影液在第三金属材料层显影获得第三金属层的图案，然后采用蚀刻液对第三金属材料层进行蚀刻获得第三金属层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在清洗后的第三金属层上形成第三保护材料层，然后在第三金属材料层上涂布光阻，采用第五光罩对光阻进行对准并曝光，用显影液在第三保护材料层显影获得钝化层的图案，然后采用蚀刻液对第三保护材料层进行蚀刻获得钝化层，对残留的光阻进行去除。
可选的光罩制程：清洗基板，在清洗后的钝化层上形成透明电极材料层， 然后在透明电极材料层上涂布光阻，采用第六光罩对光阻进行对准并曝光，用显影液在透明电极材料层显影获得透明电极层的图案，然后采用蚀刻液对透明电极材料层进行蚀刻获得透明电极层，对残留的光阻进行去除。
本申请实施例的显示面板可以为以下任一种：扭曲向列(Twisted Nematic，TN)显示面板或超扭曲向列(Super Twisted Nematic，STN)型显示面板，平面转换(In-Plane Switching，IPS)型显示面板、垂直配向(Vertical Alignment，VA)型显示面板、液晶显示面板、OLED显示面板、QLED显示面板、曲面显示面板或其他显示面板。本申请的主动开关包括薄膜晶体管。
如图7所示，在本申请一个实施例中，本实施例公开了一种显示装置100，显示装置包括控制电路板200及显示面板300，其中，本实施例中的显示装置100的具体结构以及连接关系可参见以上实施例中的显示面板300，以及参见图1至图3。在此，不再对显示装置进行一一详述。本申请实施例的显示装置可以为液晶显示装置、QLED显示装置、OLED(Organic Light-Emitting Diode)显示装置或其他显示装置。其中，当本申请实施例的显示装置为液晶显示装置时，液晶显示装置包括有背光模组，背光模组可作为光源，用于供应充足的亮度与分布均匀的光源，本实施例的背光模组可以为前光式，也可以为背光式，需要说明的是，本实施例的背光模组并不限于此。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    基板，
    主动开关，形成于基板上；
    多条数据线，形成于所述基板上，与主动开关耦接；
    多条扫描线，形成于所述基板上，与主动开关耦接，所述扫描线与所述数据线垂直排列，以形成多个像素区；
    栅极驱动电路，与多条所述扫描线耦接；
    其中，所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合，所述扫描线包括第一金属层和第二金属层，所述绝缘层设置在所述第一金属层和第二金属层之间，所述第一金属层和第二金属采用相同的材料，主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
  2. 一种显示面板，包括：
    基板，
    主动开关，形成于基板上；
    多条数据线，形成于所述基板上，与主动开关耦接；
    多条扫描线，形成于所述基板上，与主动开关耦接，所述扫描线与所述数据线垂直排列，以形成多个像素区；
    所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合。
  3. 根据权利要求1所述的一种显示面板，其中，所述扫描线包括第一金属 层和第二金属层。
  4. 根据权利要求3所述的一种显示面板，其中，所述绝缘层设置在所述第一金属层和第二金属层之间，所述绝缘层采用的材料为氮化硅或氧化硅。
  5. 根据权利要求3所述的一种显示面板，其中，所述第一金属层和第二金属可采用相同的材料。
  6. 根据权利要求3所述的一种显示面板，其中，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极仅为单层金属层。
  7. 根据权利要求3所述的一种显示面板，其中，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接。
  8. 根据权利要求3所述的一种显示面板，其中，所述显示面板还包括栅极驱动电路，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
  9. 根据权利要求3所述的一种显示面板，其中，所述显示面板还包括栅极驱动电路，所述第一金属层和所述第二金属层与所述栅极驱动电路的同一引脚耦接。
  10. 一种显示装置，包括控制电路及与显示面板，所述显示面板包括：
    基板；
    主动开关，形成于基板上；
    多条数据线，形成于所述基板上，与主动开关耦接；
    多条扫描线，形成于所述基板上，与主动开关耦接，所述扫描线与所述数据线垂直排列，以形成多个像素区；
    所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合。
  11. 根据权利要求10所述的一种显示装置，其中，所述扫描线包括第一金 属层和第二金属层。
  12. 根据权利要求11所述的一种显示装置，其中，所述绝缘层设置在所述第一金属层和第二金属层之间，所述绝缘层采用的材料为氮化硅或氧化硅。
  13. 根据权利要求11所述的一种显示装置，其中，所述第一金属层和第二金属可采用相同的材料。
  14. 根据权利要求11所述的一种显示装置，其中，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极仅为单层金属层。
  15. 根据权利要求11所述的一种显示装置，其中，所述主动开关包括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接。
  16. 根据权利要求11所述的一种显示装置，其中，所述显示面板还包括栅极驱动电路，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
  17. 根据权利要求11所述的一种显示装置，其中，所述显示面板还包括栅极驱动电路，所述第一金属层和所述第二金属层与所述栅极驱动电路的同一引脚耦接。
  18. 根据权利要求10所述的一种显示装置，其中，所述扫描线包括第一金属层和第二金属层，所述绝缘层设置在所述第一金属层和第二金属层之间，所述绝缘层采用的材料为氮化硅或氧化硅，
  19. 根据权利要求10所述的一种显示装置，其中，所述扫描线包括第一金属层和第二金属层，所述第一金属层和第二金属可采用相同的材料。
  20. 根据权利要求10所述的一种显示装置，其中，所述扫描线包括至少两层金属层，相邻两层金属层之间设置有绝缘层，不同金属层之间相互电容耦合，所述扫描线包括第一金属层和第二金属层，所述绝缘层设置在所述第一金属层和第二金属层之间，所述第一金属层和第二金属采用相同的材料，主动开关包 括栅极，所述第一金属层和第二金属层分别与所述栅极耦接，所述栅极包括第一栅极金属层和第二栅极金属层，所述第一金属层与所述第一栅极金属层耦接，第二金属层与所述第二栅极金属层耦接，第一金属层与所述栅极驱动电路第一引脚耦接，所述第二金属层与所述栅极驱动电路的第二引脚耦接。
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CN107219702A (zh) * 2017-07-20 2017-09-29 深圳市华星光电技术有限公司 一种阵列基板及其制造方法、液晶显示装置
CN107966864B (zh) * 2017-12-15 2020-08-04 昆山龙腾光电股份有限公司 一种液晶显示装置
CN208706653U (zh) * 2018-10-23 2019-04-05 惠科股份有限公司 显示面板和显示装置
CN109270719A (zh) * 2018-12-12 2019-01-25 惠科股份有限公司 显示面板和显示装置
KR101993313B1 (ko) * 2019-04-15 2019-06-26 한국생산기술연구원 액체 금속을 이용한 유연성 필터 소자 및 그 제조 방법
CN110058469B (zh) * 2019-04-30 2020-11-27 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置及阵列基板的制造方法
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