WO2018220855A1 - Calculation process device, calculation process control method and calculation process control program - Google Patents

Calculation process device, calculation process control method and calculation process control program Download PDF

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Publication number
WO2018220855A1
WO2018220855A1 PCT/JP2017/020719 JP2017020719W WO2018220855A1 WO 2018220855 A1 WO2018220855 A1 WO 2018220855A1 JP 2017020719 W JP2017020719 W JP 2017020719W WO 2018220855 A1 WO2018220855 A1 WO 2018220855A1
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WIPO (PCT)
Prior art keywords
cpu
calculation
pointer
processor
result
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PCT/JP2017/020719
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French (fr)
Japanese (ja)
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清志 宮▲崎▼
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富士通コネクテッドテクノロジーズ株式会社
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Priority to PCT/JP2017/020719 priority Critical patent/WO2018220855A1/en
Publication of WO2018220855A1 publication Critical patent/WO2018220855A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Definitions

  • the present invention relates to an arithmetic processing device, an arithmetic processing control method, and an arithmetic processing control program.
  • the processing performance is improved by increasing the execution frequency of the processor and the memory.
  • the execution frequency increases, for example, not only the power consumption increases, but also the heat generation amount increases. Therefore, in recent years, arithmetic processing apparatuses that operate a plurality of processors in parallel and perform arithmetic processing in a distributed manner have become widespread. As a result, power consumption and heat generation are reduced.
  • each processor executes arithmetic processing in a distributed manner, and outputs the arithmetic results of each processor together.
  • the arithmetic processing apparatus when an arithmetic process is distributed and executed by each processor, if an interrupt process other than the arithmetic process is interrupted by a certain processor, the output of the arithmetic result of the arithmetic process of the processor is delayed. As a result, in the arithmetic processing device, since the time until the arithmetic results of all the processors are obtained is shifted, the throughput performance of the arithmetic processing is deteriorated.
  • each processor in order to suppress a decrease in throughput performance of arithmetic processing, each processor needs to grasp the status of arithmetic processing of other processors and the processing to be performed next. Communication between them is required. As a result, the overhead related to arithmetic processing increases.
  • An object of one aspect is to provide an arithmetic processing device or the like that can reduce overhead between processors related to arithmetic processing.
  • the arithmetic processing device includes a storage unit, a first addition unit, and a second addition unit.
  • the storage unit stores, for each processor, a first pointer indicating a first storage destination that stores operation source data of the processing to be executed by the processor, and an operation result of the operation source data to be executed by the processor.
  • the second pointer indicating the second storage destination is stored.
  • the storage unit provides the processor with the first pointer and the second pointer related to processing executed by each processor.
  • the first addition unit adds the extraction data length of the operation source data to the first pointer when the processor extracts the operation source data from the first storage destination corresponding to the processor, and the addition result Is updated and registered as the first pointer of the processor.
  • the second addition unit adds the storage data length of the calculation result to the second pointer when the processor stores the calculation result for the calculation source data in the second storage destination corresponding to the processor. The addition result is updated and registered as the second pointer of the processor.
  • the overhead between processors related to arithmetic processing can be reduced.
  • FIG. 1 is a block diagram illustrating an example of a terminal device according to the present embodiment.
  • FIG. 2 is an explanatory diagram illustrating an example of a functional configuration of the application unit.
  • FIG. 3 is an explanatory diagram of an example of the calculation source table.
  • FIG. 4 is an explanatory diagram illustrating an example of the calculation result table.
  • FIG. 5 is an explanatory diagram illustrating an example of a calculation source register, a calculation result register, and an update register.
  • FIG. 6 is an explanatory diagram of an example of the CPU update register.
  • FIG. 7 is an explanatory diagram illustrating an example of a functional configuration of the arbitration unit.
  • FIG. 8 is a flowchart showing an example of the processing operation of the CPU # 0 related to the first arithmetic processing.
  • FIG. 8 is a flowchart showing an example of the processing operation of the CPU # 0 related to the first arithmetic processing.
  • FIG. 9 is a flowchart illustrating an example of the processing operation of the CPU #n related to the second arithmetic processing.
  • FIG. 10 is a flowchart illustrating an example of the processing operation of the arbitration unit related to the arbitration process.
  • FIG. 11 is an explanatory diagram showing an example of an operation sequence of arithmetic processing of CPU # 0, CPU # 1, and CPU #n.
  • FIG. 12 is an explanatory diagram illustrating an example of an information processing apparatus that executes an arithmetic processing control program.
  • FIG. 1 is a block diagram illustrating an example of the terminal device 1 according to the present embodiment.
  • the terminal device 1 illustrated in FIG. 1 includes a wireless antenna 11, a wireless unit 12, a display unit 13, an operation unit 14, a flash memory 15, and an SDRAM (Synchronous Dynamic Random Access Memory) 16. Further, the terminal device 1 includes a wireless LAN (Local Area Network) LSI (Large Scale Integrated) 17 and a system LSI 18.
  • the terminal device 1 is a terminal device such as a smartphone with a built-in communication function, for example.
  • the smart phone was illustrated for convenience of explanation, it is not limited to this, and terminal devices, such as a tablet terminal, may be sufficient.
  • the wireless antenna 11 is an antenna that transmits and receives wireless signals.
  • the wireless unit 12 is a communication interface that manages a communication function for transmitting and receiving wireless signals through the wireless antenna 11.
  • the display unit 13 is an output interface that displays various types of information.
  • the operation unit 14 is an input interface for inputting various information.
  • the flash memory 15 is an area for storing information such as various programs.
  • the SDRAM 16 is an area for storing various information.
  • the SDRAM 16 has a calculation source table 16A and a calculation result table 16B.
  • the calculation source table 16A is an area for storing calculation source data to be described later.
  • the calculation result table 16B is an area for storing calculation results to be described later.
  • the system LSI 18 is an LSI that controls the entire terminal device 1.
  • the system LSI 18 includes a wireless control unit 21 and an application unit 22.
  • the wireless control unit 21 controls the wireless unit 12.
  • the wireless control unit 21 includes a DSP (Digital Signal Processor) 21A and a BB (Base Band) circuit 21B.
  • the DSP 21A is a signal processing unit that executes various types of signal processing of radio signals.
  • the BB circuit 21B is a signal processing unit that performs baseband processing of a radio signal.
  • the application unit 22 is, for example, an application that manages a multi-CPU function that executes arithmetic processing distributed to a plurality of CPUs 31.
  • FIG. 2 is an explanatory diagram illustrating an example of a functional configuration of the application unit 22.
  • the application unit 22 illustrated in FIG. 2 includes a plurality of CPUs 31 (# 0 to #n), a cache memory 32, a display control unit 33, an arbitration unit 34, and a common bus 35.
  • the CPUs # 0 to #n are control units that execute arithmetic processing.
  • the CPUs # 0 to #n execute the calculation process of the calculation source data based on the calculation source data stored in the calculation source table 16A, and obtain the calculation result of the calculation process.
  • the CPUs # 0 to # 3 are the normal CPU group 31A
  • the CPUs # 4 to #n are the high-speed processing CPU group 31B.
  • the cache memory 32 is a work area for arithmetic processing executed by any CPU 31 of the CPUs # 0 to #n.
  • the display control unit 33 controls display of the display unit 13.
  • the arbitration unit 34 supports the multi-CPU function of the arithmetic processing of the CPUs # 0 to #n.
  • the common bus 35 is a bus line that transmits and receives signals from the CPUs # 0 to #n, the cache memory 32, the display control unit 33, and the arbitration unit 34.
  • FIG. 3 is an explanatory diagram showing an example of the calculation source table 16A.
  • the calculation source table 16A shown in FIG. 3 is a storage area for storing calculation source data related to calculation processing.
  • the storage area is identified by the operation source data pointer.
  • FIG. 4 is an explanatory diagram showing an example of the calculation result table 16B.
  • the calculation result table 16B shown in FIG. 4 is a storage area for storing calculation results.
  • the storage area is identified by a calculation result pointer.
  • FIG. 5 is an explanatory diagram illustrating an example of the calculation source register 41, the calculation result register 42, and the update register 43.
  • the arbitration unit 34 includes, for example, a storage unit for an operation source register 41, an operation result register 42, and an update register 43.
  • the calculation source register 41 is a register that registers, for each CPU 31, a calculation source data pointer that is a first pointer indicating the storage destination of the calculation source table 16A that stores calculation source data of calculation processing used by the CPU 31.
  • the calculation source register 41 registers a CPU # 0 calculation source data pointer as a storage destination for storing calculation source data of the CPU # 0.
  • the calculation result register 42 is a register that registers, for each CPU 31, a calculation result pointer that is a second pointer indicating the storage destination of the calculation result table 16B that stores calculation results of calculation processing used by the CPU 31.
  • a CPU # 2 calculation result pointer is registered as a storage destination for storing a calculation result of the CPU # 2.
  • the update register 43 is a register that stores state information of arithmetic processing for each CPU 31. For example, it is assumed that the update register 43 registers the CPU # 2 update register as the register of the CPU # 2.
  • FIG. 6 is an explanatory diagram showing an example of the CPU update register 45. It is assumed that the CPU update register 45 is managed in the update register 43 for each CPU 31.
  • the CPU update register 45 illustrated in FIG. 6 includes a BUSY 45A, an STB 45B, an OPE 45C, a remaining data length 45D, an extraction data length 45E, and a storage data length 45F.
  • the BUSY 45A is a flag indicating whether or not the CPU update register 45 is being updated. When BUSY 45A is “1”, it indicates that the CPU update register 45 is being updated, and when it is “0”, it indicates that the CPU update register 45 is not being updated.
  • the STB 45B is a flag indicating the presence / absence of the STB in the CPU update register 45.
  • the STB 45B corresponds to a register setting strobe.
  • the OPE 45C is a flag indicating whether or not the CPU update register 45 is performing an arithmetic process.
  • the remaining data length 45D is information indicating the remaining data length of the operation source data, for example, the number of remaining bytes.
  • the extracted data length 45E is information indicating the data length of the calculation source data extracted from the calculation source table 16A, for example, the number of bytes.
  • the storage data length 45F is information indicating the data length, for example, the number of bytes, in which the calculation result of the calculation process is stored in the calculation result table 16B.
  • FIG. 7 is an explanatory diagram illustrating an example of a functional configuration of the arbitration unit 34.
  • the arbitration unit 34 illustrated in FIG. 7 includes a first addition unit 51, a subtraction unit 52, and a second addition unit 53.
  • the arbitrating unit 34 registers a calculation source data pointer indicating a storage destination for storing calculation source data of the designated CPU #n in the calculation source register 41 as a CPU #n calculation source data pointer.
  • the first addition unit 51 adds the extraction data length 45E of the calculation data to the CPU # n calculation source data pointer.
  • the first addition unit 51 updates and registers the addition result in the operation source register 41 as a CPU #n operation source data pointer.
  • the subtraction unit 52 subtracts the fetched data length 45E from the remaining data length 45D in the CPU # n update register, and updates and registers the subtraction result in the CPU update register 45 as the remaining data length 45D of the designated CPU # n.
  • the update unit subtracts the fetched data length 45E from the remaining data length 45D in the CPU # n update register, and updates and registers the subtraction result in the CPU update register 45 as the remaining data length 45D of the designated CPU # n.
  • the arbitrating unit 34 updates and registers the calculation result pointer of the designated CPU #n in the calculation result register 42 as the CPU #n calculation result pointer.
  • the second addition unit 53 adds the storage data length 45F to the CPU #n calculation result pointer, and the addition result is displayed.
  • the CPU #n is updated and registered in the calculation result register 42 as a calculation result pointer.
  • FIG. 8 is a flowchart showing an example of the processing operation of the CPU # 0 related to the first arithmetic processing.
  • the CPU # 0 is the CPU 31 that receives a processing request for an arithmetic process.
  • the CPU # 0 determines whether or not a processing request for an arithmetic process corresponding to an input operation of the operation unit 14 is detected (step S21).
  • CPU # 0 detects a processing request for the arithmetic process (Yes at Step S21)
  • CPU # 0 distributes the arithmetic processing corresponding to the processing request for the arithmetic process for each target CPU 31 (Step S22).
  • the target CPU 31 is a CPU in which CPU # 0 distributes the arithmetic processing corresponding to the arithmetic process and executes the distributed arithmetic processing.
  • CPU # 0 requests the arbitration unit 34 to perform initial setting for each target CPU 31 (step S23).
  • the initial setting includes a request for the arbitrating unit 34 to update the OPE 45C in the CPU update register 45 of the target CPU 31 to “1”.
  • CPU # 0 requests the target CPU 31 to execute arithmetic processing (step S24).
  • CPU # 0 obtains a CPU # 0 computation source data pointer indicating the storage location of computation source data corresponding to CPU # 0 from computation source register 41 of arbitration unit 34 (step S25).
  • CPU # 0 acquires the operation source data corresponding to CPU # 0 from the operation source table 16A based on the CPU # 0 operation source data pointer (step S26).
  • the CPU # 0 notifies the arbitration unit 34 of the extracted data length when the calculation source data corresponding to the CPU # 0 is acquired from the calculation source table 16A (step S27).
  • CPU # 0 executes calculation processing of calculation source data corresponding to CPU # 0 (step S28), and acquires a calculation result corresponding to CPU # 0 (step S29).
  • the CPU # 0 obtains a CPU # 0 calculation result pointer indicating the storage destination for storing the calculation result corresponding to the CPU # 0 from the arbitrating unit 34 (step S30).
  • the CPU # 0 stores the calculation result of the CPU # 0 in the storage destination in the calculation result table 16B corresponding to the CPU # 0 calculation result pointer (step S31). Further, the CPU # 0 notifies the arbitration unit 34 of the storage data length 45F when the calculation result of the CPU # 0 is stored in the calculation result table 16B (step S32).
  • CPU # 0 refers to the remaining data length 45D in the CPU # 0 update register 45 of the arbitration unit 34, and determines whether or not the remaining data length 45D is “0” (step S33). If the remaining data length 45D is not “0” (No at Step S33), the CPU # 0 proceeds to Step S25 in order to obtain the next CPU # 0 calculation source data pointer from the arbitration unit 34.
  • the CPU # 0 requests the arbitration unit 34 to set the OPE 45C in the CPU # 0 update register 45 to “0” (Step S34). .
  • the CPU # 0 determines whether or not calculation processing completion notifications have been received from all the target CPUs 31 (step S35).
  • CPU # 0 acquires the calculation result pointer of the target CPU 31 from the calculation result register 42 of the arbitration unit 34 (step S36) when receiving notification of the completion of the calculation process from all the target CPUs 31 (Yes in step S35). Then, the CPU # 0 acquires the calculation result of the target CPU 31 from the calculation result table 16B based on the calculation result pointer of the target CPU 31 (step S37). The CPU # 0 outputs the calculation result corresponding to the calculation process based on the calculation result of the target CPU 31 (step S38), and ends the processing operation shown in FIG. When the CPU # 0 does not detect the calculation process request (No at Step S21), the processing operation illustrated in FIG. If the CPU # 0 has not detected the calculation completion notifications of all the target CPUs 31 (No in step S35), the CPU # 0 continues the determination process of step S35 until the calculation completion notifications of all the target CPUs 31 are detected.
  • CPU # 0 acquires the CPU # 0 calculation source data pointer of the calculation source register 41 in the arbitration unit 34, and acquires calculation source data from the calculation source table 16A based on the CPU # 0 calculation source data pointer. As a result, the CPU # 0 can obtain the calculation source data corresponding to the CPU # 0 with reference to the calculation source register 41 in the arbitration unit 34.
  • CPU # 0 acquires the CPU # 0 calculation result pointer of the calculation result register 42 in the arbitration unit 34, and stores the calculation result in the storage destination of the calculation result table 16B based on the CPU # 0 calculation result pointer.
  • the CPU # 0 can refer to the calculation result register 42 in the arbitration unit 34 and specify the storage destination of the calculation result corresponding to the CPU # 0.
  • CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E when the calculation source data corresponding to CPU # 0 is acquired from the calculation source table 16A.
  • the arbitration unit 34 can update the CPU # 0 computation source data pointer indicating the storage location of the computation data of the next CPU # 0 according to the fetch data length 45E.
  • CPU # 0 notifies the arbitration unit 34 of the stored data length 45F when the calculation result corresponding to CPU # 0 is stored in the calculation result table 16B.
  • the arbitrating unit 34 can update the CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the next CPU # 0 according to the stored data length 45F.
  • the CPU # 0 refers to the CPU # 0 update register in the update register 43 in the arbitration unit 34, and sets the OPE of the CPU # 0 to “0” when the remaining data length 45D is “0”. As a result, the arbitrating unit 34 can recognize the completion of the arithmetic processing of the CPU # 0.
  • CPU # 0 When CPU # 0 receives the completion of the calculation process of the target CPU 31, the CPU # 0 refers to the calculation result pointer corresponding to each target CPU 31 in the arbitration unit 34, and acquires the calculation result of each target CPU 31 based on the calculation result pointer. Then, the CPU # 0 can acquire the calculation result corresponding to the calculation process based on the calculation result of the target CPU 31.
  • FIG. 9 is a flowchart showing an example of the processing operation of CPU #n related to the second arithmetic processing.
  • the CPU #n is illustrated, but is not limited to the CPU #n, and is executed by each target CPU 31.
  • the CPU #n determines whether or not an arithmetic processing request has been detected from the CPU # 0 (step S41).
  • CPU #n detects a calculation processing request (Yes at step S41)
  • CPU #n reads out its own CPU-ID, that is, CPU #n (step S42).
  • CPU #n acquires the CPU #n operation source data pointer corresponding to CPU #n from the operation source register 41 in the arbitration unit 34 (step S43).
  • the CPU #n acquires the operation source data corresponding to the CPU #n from the operation source table 16A based on the CPU #n operation source data pointer (step S44).
  • the CPU #n notifies the arbitration unit 34 of the fetched data length when the computation source data corresponding to the CPU #n is acquired from the computation source table 16A (step S45).
  • CPU # n executes calculation processing of calculation source data corresponding to CPU # n (step S46), and acquires a calculation result corresponding to CPU # n (step S47).
  • the CPU #n acquires a CPU #n calculation result pointer from the calculation result register 42 in the arbitration unit 34 (step S48).
  • the CPU #n stores the calculation result of the CPU #n in the storage destination in the calculation result table 16B corresponding to the CPU #n calculation result pointer (step S49). Further, the CPU #n notifies the arbitration unit 34 of the storage data length 45F when the calculation result of the CPU #n is stored in the calculation result table 16B (step S50).
  • CPU # n refers to the remaining data length 45D in the CPU # n update register 45 of the arbitration unit 34, and determines whether or not the remaining data length 45D is “0” (step S51). When the remaining data length 45D is not “0” (No at Step S51), the CPU #n proceeds to Step S43 in order to obtain the CPU #n calculation source data pointer from the calculation source register 41 in the arbitration unit 34.
  • the CPU #n When the remaining data length 45D is “0” (Yes at Step S51), the CPU #n requests the arbitration unit 34 to update to set the OPE 45C in the CPU #n update register 45 to “0” ( Step S52). Then, the CPU #n notifies the CPU # 0 of completion of the arithmetic processing (step S53), and ends the processing operation shown in FIG. On the other hand, if the CPU #n has not detected an arithmetic processing request from the CPU # 0 (No at step S41), the CPU #n ends the processing operation shown in FIG.
  • CPU #n acquires the CPU #n calculation source data pointer of the calculation source register 41 in the arbitration unit 34, and acquires calculation source data from the calculation source table 16A based on the CPU #n calculation source data pointer.
  • the CPU #n refers to the calculation source register 41 in the arbitration unit 34 and can acquire calculation source data corresponding to the CPU #n.
  • CPU # n acquires the CPU # n calculation result pointer of the calculation result register 42 in the arbitration unit 34, and stores the calculation result in the storage destination of the calculation result table 16B based on the CPU # n calculation result pointer. As a result, the CPU #n can specify the storage destination of the calculation result corresponding to the CPU #n with reference to the calculation result register 42 in the arbitration unit 34.
  • CPU # n notifies the arbitration unit 34 of the extraction data length 45E when the calculation source data corresponding to CPU # n is acquired from the calculation source table 16A.
  • the arbitrating unit 34 can update the CPU #n calculation source data pointer indicating the storage location of the calculation data of the next CPU #n according to the fetch data length 45E.
  • CPU # n notifies the arbitration unit 34 of the storage data length 45F when the calculation result corresponding to CPU # n is stored in the calculation result table 16B.
  • the arbitrating unit 34 can update the CPU #n calculation result pointer indicating the storage destination of the calculation result of the next CPU #n according to the stored data length 45F.
  • CPU #n refers to the CPU #n update register in the update register 43 in the arbitration unit 34, and sets the OPE of CPU #n to “0” when the remaining data length 45D is “0”.
  • the arbitrating unit 34 can recognize the completion of the arithmetic processing of the CPU #n.
  • FIG. 10 is a flowchart showing an example of the processing operation of the arbitration unit 34 related to the arbitration process.
  • the arbitrating unit 34 determines whether or not an initial setting request is detected from the CPU # 0 (step S61).
  • the arbitration unit 34 detects an initial setting request from the CPU # 0 (Yes in step S61)
  • the calculation source data pointer indicating the storage destination of the calculation source data for each target CPU 31 is used as the calculation source data pointer for each target CPU 31. Registration is made in the register 41 (step S62).
  • the arbitrating unit 34 registers the calculation result pointer indicating the storage destination of the calculation result for each target CPU 31 in the calculation result register 42 as the calculation result pointer for each target CPU 31 (step S63). Further, the arbitrating unit 34 registers the remaining data length 45D corresponding to the byte amount of the operation source data in the CPU update register 45 for each target CPU 31 (step S64).
  • the arbitrating unit 34 designates an undesignated CPU 31 from the target CPU 31 (step S65).
  • the arbitrating unit 34 updates and registers BUSY 45A in the CPU update register 45 of the designated CPU 31 to “1” (step S66), and determines whether or not the fetched data length 45E has been received from the designated CPU 31 (step S67). .
  • the first adder 51 in the arbitration unit 34 adds the fetch data length 45E to the calculation source data pointer of the designated CPU 31.
  • the first addition unit 51 updates and registers the addition result in the calculation source register 41 as the calculation source data pointer of the designated CPU 31 (step S68).
  • the arbitrating unit 34 determines whether or not the storage data length 45F has been received from the designated CPU 31 after the update registration of the calculation source data pointer of the designated CPU 31 (step S69).
  • the second addition unit 53 in the arbitration unit 34 adds the storage data length 45F to the calculation result pointer of the designated CPU 31.
  • the second addition unit 53 updates and registers the addition result in the calculation result register 42 as the calculation result pointer of the designated CPU 31 (step S70).
  • the subtraction unit 52 in the arbitration unit 34 subtracts the fetched data length 45E from the remaining data length 45D in the CPU update register 45 of the designated CPU 31, and updates and registers the subtraction result in the CPU update register 45 as the remaining data length 45D. (Step S71).
  • the arbitrating unit 34 sets BUSY 45A in the CPU update register 45 of the designated CPU 31 to “0” (step S72). Then, the arbitrating unit 34 determines whether there is an unspecified CPU 31 from the target CPU 31 (step S73). When there is an undesignated CPU 31 from the target CPU 31 (Yes at Step S73), the arbitrating unit 34 proceeds to Step S65 to designate the undesignated CPU 31.
  • the arbitrating unit 34 ends the processing operation shown in FIG.
  • the arbitration unit 34 has not detected the initial setting request from the CPU # 0 (No at Step S61)
  • the arbitrating unit 34 ends the processing operation illustrated in FIG.
  • step S67 when the fetched data length 45E has not been received from the designated CPU 31 (No at step S67), the arbitrating unit 34 proceeds to step S67 until the fetched data length 45E from the designated CPU 31 has been received. Further, when the storage data length 45F has not been received from the designated CPU 31 (No in step S69), the arbitrating unit 34 proceeds to step S69 until the storage data length 45F from the designated CPU 31 has been received.
  • the arbitration unit 34 registers a calculation source data pointer indicating a storage destination of calculation source data for each CPU 31 in the calculation source register 41. As a result, the arbitrating unit 34 can provide the storage destination of the calculation source data to the target CPU 31.
  • the arbitration unit 34 When the arbitration unit 34 receives the fetch data length 45E from the CPU 31, the arbitration unit 34 adds the fetch data length 45E to the computation source data pointer of the CPU 31, and updates and registers the addition result in the computation source register 41 as the computation source data pointer. . As a result, the arbitrating unit 34 can provide the storage destination of the next calculation source data to the target CPU 31.
  • the arbitration unit 34 registers a calculation result pointer indicating the storage destination of the calculation result for each CPU 31 in the calculation result register 42. As a result, the arbitrating unit 34 can provide the target CPU 31 with the storage location of the calculation result.
  • the arbitration unit 34 When the arbitration unit 34 receives the storage data length 45F from the CPU 31, the arbitration unit 34 adds the storage data length 45F to the calculation result pointer of the CPU 31, and updates and registers the addition result in the calculation result register 42 as the calculation result pointer. As a result, the arbitration unit 34 can provide the storage destination of the next calculation result to the target CPU 31.
  • the arbitration unit 34 When the arbitration unit 34 receives the fetched data length 45E from the CPU 31, the arbitration unit 34 subtracts the fetched data length 45E from the remaining data length 45D of the CPU 31, and updates and registers the subtraction result in the update register 43 as the remaining data length 45D. As a result, the arbitrating unit 34 can recognize the CPU 31 that has completed the arithmetic processing with reference to the remaining data length 45D.
  • FIG. 11 is an explanatory diagram showing an example of an operation sequence of arithmetic processing of CPU # 0, CPU # 1, and CPU #n.
  • the example of FIG. 11 shows a state in which the CPU # 0 receives a request for a calculation process and distributes the calculation process to the CPU # 1 and the CPU #n and the CPU #n interrupts the high priority process.
  • CPU # 0 when CPU # 0 detects a command operation for executing the arithmetic process, the CPU # 0 distributes the arithmetic process to its own CPU # 0, CPU # 1, and CPU #n (step S81).
  • the CPU # 0 refers to and updates the CPU # 0 operation source data pointer in the operation source register 41, the CPU # 0 operation result pointer in the operation result register 42, and the CPU # 0 update register in the update register 43.
  • CPU # 0 sequentially executes arithmetic processing 1-1, arithmetic processing 1-2, and arithmetic processing 1-3.
  • the CPU # 0 refers to the calculation source register 41 and obtains the CPU # 0 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 1-1. Based on the CPU # 0 calculation source data pointer, the CPU # 0 acquires the calculation source data of the calculation process 1-1 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 1-1 (step S1). S82). Then, the CPU # 0 acquires the calculation result of the calculation process 1-1. The CPU # 0 refers to the calculation result register 42 and acquires a CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the calculation process 1-1.
  • the CPU # 0 stores the calculation result of the calculation process 1-1 in the calculation result table 16B based on the CPU # 0 calculation result pointer.
  • the CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 1-1 and the storage data length 45F of the calculation result.
  • the arbitration unit 34 adds the fetched data length 45E to the CPU # 0 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 0 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 0 calculation result pointer, and updates and registers the addition result in the calculation result register 42 as the CPU # 0 calculation result pointer.
  • the CPU # 0 refers to the calculation source register 41 and acquires a CPU # 0 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 1-2. Based on the CPU # 0 calculation source data pointer, the CPU # 0 acquires the calculation source data of the calculation process 1-2 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 1-2 (step S83). Then, the CPU # 0 acquires the calculation result of the calculation process 1-2. The CPU # 0 refers to the calculation result register 42 and obtains a CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the calculation process 1-2.
  • the CPU # 0 stores the calculation result of the calculation process 1-2 in the calculation result table 16B based on the CPU # 0 calculation result pointer.
  • the CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 1-2 and the storage data length 45F of the calculation result.
  • the arbitration unit 34 adds the fetched data length 45E to the CPU # 0 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 0 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 0 calculation result pointer, and updates and registers the addition result in the calculation result register 42 as the CPU # 0 calculation result pointer.
  • the CPU # 0 refers to the calculation source register 41 and acquires a CPU # 0 calculation source data pointer indicating the storage destination of calculation source data of the calculation process 1-3. Based on the CPU # 0 calculation source data pointer, the CPU # 0 acquires the calculation source data of the calculation process 1-3 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 1-3 (step S84). Then, the CPU # 0 acquires the calculation result of the calculation process 1-3.
  • the CPU # 0 refers to the calculation result register 42 and acquires a CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the calculation process 1-3.
  • the CPU # 0 stores the calculation result of the calculation process 1-3 in the calculation result table 16B based on the CPU # 0 calculation result pointer.
  • the CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 1-3 and the storage data length 45F of the calculation result.
  • the arbitration unit 34 adds the fetched data length 45E to the CPU # 0 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 0 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 0 calculation result pointer, and updates and registers the addition result in the calculation result register 42 as the CPU # 0 calculation result pointer. Then, after storing the calculation result of the calculation process 1-3 in the calculation result table 16B, the CPU # 0 sets the OPE in the CPU # 0 update register to “1” when the remaining data length 45D becomes “0”. Set.
  • the CPU # 1 also refers to and updates the CPU # 1 calculation source data pointer in the calculation source register 41, the CPU # 1 calculation result pointer in the calculation result register 42, and the CPU # 1 update register in the update register 43. Then, CPU # 1 sequentially executes arithmetic processing 2-1, arithmetic processing 2-2, and arithmetic processing 2-3.
  • the CPU # 1 refers to the calculation source register 41 and obtains the CPU # 1 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 2-1. Based on the CPU # 1 calculation source data pointer, the CPU # 1 acquires the calculation source data of the calculation process 2-1 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 2-1. S85). Then, CPU # 1 acquires the calculation result of the calculation process 2-1. The CPU # 1 refers to the calculation result register 42 and acquires a CPU # 1 calculation result pointer indicating the storage destination of the calculation result of the calculation process 2-1. Based on the CPU # 1 calculation result pointer, the CPU # 1 stores the calculation result of the calculation process 2-1 in the calculation result table 16B.
  • the CPU # 1 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 2-1 and the storage data length 45F of the calculation result.
  • the arbitrating unit 34 adds the fetched data length 45E to the CPU # 1 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 1 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 1 calculation result pointer, and updates and registers it in the calculation result register 42 as the CPU # 1 calculation result pointer.
  • the CPU # 1 refers to the calculation source register 41, and obtains a CPU # 1 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 2-2. Based on the CPU # 1 calculation source data pointer, the CPU # 1 acquires the calculation source data of the calculation process 2-2 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 2-2 (Step S1). S86). Then, the CPU # 1 acquires the calculation result of the calculation process 2-2. The CPU # 1 refers to the calculation result register 42 and obtains a CPU # 1 calculation result pointer indicating the storage destination of the calculation result of the calculation process 2-2.
  • the CPU # 1 stores the calculation result of the calculation process 2-2 in the calculation result table 16B.
  • the CPU # 1 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 2-2 and the storage data length 45F of the calculation result.
  • the arbitrating unit 34 adds the fetched data length 45E to the CPU # 1 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 1 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 1 calculation result pointer, and updates and registers it in the calculation result register 42 as the CPU # 1 calculation result pointer.
  • the CPU # 1 refers to the calculation source register 41 and acquires a CPU # 1 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 2-3. Based on the CPU # 1 calculation source data pointer, the CPU # 1 acquires the calculation source data of the calculation process 2-3 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 2-3 (step S1). S87). Then, the CPU # 1 acquires the calculation result of the calculation process 2-3.
  • the CPU # 1 refers to the calculation result register 42 and obtains a CPU # 1 calculation result pointer indicating the storage destination of the calculation result of the calculation process 2-3. Based on the CPU # 1 calculation result pointer, the CPU # 1 stores the calculation result of the calculation process 2-3 in the calculation result table 16B.
  • the CPU # 1 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 2-3 and the storage data length 45F of the calculation result.
  • the arbitrating unit 34 adds the fetched data length 45E to the CPU # 1 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 1 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 1 calculation result pointer, and updates and registers it in the calculation result register 42 as the CPU # 1 calculation result pointer. Then, after storing the calculation result of the calculation process 2-3 in the calculation result table 16B, the CPU # 1 sets the OPE in the CPU # 1 update register to “1” when the remaining data length 45D becomes “0”. Set and notify CPU # 0 of the completion of arithmetic processing.
  • the CPU #n executes the CPU #n calculation source data pointer in the calculation source register 41 in the arbitration unit 34, and the CPU #n calculation result pointer in the calculation result register 42.
  • the CPU #n update register in the update register 43 is referred to.
  • the CPU #n refers to the calculation source register 41 and acquires a CPU #n calculation source data pointer indicating the storage destination of the calculation source data of the calculation process n-1.
  • CPU # n executes calculation processing of calculation source data of calculation processing n ⁇ 1 (step S89). Then, the CPU #n stores the calculation result of the calculation process n ⁇ 1 in the calculation result table 16B.
  • the CPU #n sets the OPE in the CPU #n update register to “1” when the remaining data length 45D becomes “0”. Set and notify CPU # 0 of the completion of arithmetic processing.
  • CPU # 0 When CPU # 0 receives the completion of calculation processing from the target CPU 31, for example, CPU # 1 and CPU #n, CPU # 0 displays the calculation result corresponding to the calculation process based on the calculation results of CPU # 0, CPU # 1 and CPU #n. Post-processing of the calculation process to be output is executed (step S90).
  • the arbitration unit 34 registers a CPU calculation source data pointer, a CPU calculation result pointer, and a CPU update register 45 for each CPU 31.
  • the arbitration unit 34 includes a first addition unit 51, a second addition unit 53, and a subtraction unit 52.
  • the first adder 51 fetches CPU computation source data from the computation source table 16A based on the CPU computation source data pointer
  • the first addition unit 51 adds the fetched data length 45E to the CPU computation source data pointer, and the addition result is CPU computation. Update and register as the original data pointer.
  • the second addition unit 52 adds the storage data length 45F to the CPU calculation result pointer, and updates and registers the addition result as the CPU calculation result pointer.
  • the subtraction unit 52 subtracts the extracted data length 45E from the remaining data length 45D, and updates and registers the completion of the arithmetic processing when the subtraction result is “0”.
  • the arbitration unit 34 When the arbitration unit 34 receives the fetch data length 45E from the CPU 31, the arbitration unit 34 adds the fetch data length 45E to the computation source data pointer of the CPU 31, and updates and registers the addition result in the computation source register 41 as the computation source data pointer. . As a result, the arbitrating unit 34 can provide the storage destination of the next calculation source data to the target CPU 31.
  • the parallel operation in each CPU 31 can be executed without idle time according to the load state of each CPU 31 without increasing the load due to communication for performing cooperation / synchronization between the CPUs 31, and the process can be executed efficiently.
  • the vacant CPU 31 sequentially moves from the arbitration unit 34 to the next. Read the operation data to be executed directly and continue the operation process. As a result, the final waiting time can be minimized and the processing can be executed at high speed.
  • the arbitration unit 34 When the arbitration unit 34 receives the storage data length 45F from the CPU 31, the arbitration unit 34 adds the storage data length 45F to the calculation result pointer of the CPU 31, and updates and registers the addition result in the calculation result register 42 as the calculation result pointer. As a result, the arbitration unit 34 can provide the storage destination of the next calculation result to the target CPU 31.
  • the arbitration unit 34 When the arbitration unit 34 receives the fetched data length 45E from the CPU 31, the arbitration unit 34 subtracts the fetched data length 45E from the remaining data length 45D of the CPU 31, and updates and registers the subtraction result in the update register 43 as the remaining data length 45D. As a result, the arbitrating unit 34 can recognize the CPU 31 that has completed the arithmetic processing with reference to the remaining data length 45D. And the overhead between CPU31 regarding a calculation process can be reduced.
  • a terminal device including a wireless unit such as a smartphone is illustrated, but the present invention is not limited to the wireless unit, and can be applied to a terminal device including a wired communication unit.
  • the present invention is also applicable to an information processing apparatus that does not incorporate a communication function such as a wireless unit or a communication unit.
  • a system LSI having a plurality of CPUs with a hardware configuration is illustrated.
  • the present invention can also be applied to a system LSI in which a plurality of virtual CPUs are developed on a memory.
  • each component of each part illustrated does not necessarily need to be physically configured as illustrated.
  • the specific form of distribution / integration of each part is not limited to the one shown in the figure, and all or a part thereof may be functionally or physically distributed / integrated in arbitrary units according to various loads and usage conditions. Can be configured.
  • processing functions performed in each device are executed on the CPU (or a micro computer such as MPU (Micro Processing Unit), MCU (Micro Controller Unit), etc.) or all of them. Also good. Various processing functions may be executed entirely or arbitrarily on a program that is analyzed and executed by a CPU (or a microcomputer such as an MPU or MCU) or hardware based on wired logic. Needless to say.
  • MPU Micro Processing Unit
  • MCU Micro Controller Unit
  • Various processing functions may be executed entirely or arbitrarily on a program that is analyzed and executed by a CPU (or a microcomputer such as an MPU or MCU) or hardware based on wired logic. Needless to say.
  • FIG. 12 is an explanatory diagram illustrating an example of an information processing apparatus that executes an arithmetic processing control program.
  • the information processing apparatus 100 that executes the arithmetic processing control program shown in FIG. 12 includes a plurality of processors 110, a ROM 120, a RAM 130, and a CPU 140. Further, the plurality of processors 110, the ROM 120, the RAM 130, and the CPU 140 are connected via a bus 150.
  • the ROM 120 stores in advance an arithmetic processing control program that exhibits the same function as in the above embodiment.
  • the ROM 120 stores a provision program 120A, a first addition program 120B, and a second addition program 120C as arithmetic processing control programs.
  • the arithmetic processing control program may be recorded not on the ROM 120 but on a computer-readable recording medium using a drive (not shown).
  • the recording medium may be, for example, a portable recording medium such as a CD-ROM, a DVD disk, or a USB memory, or a semiconductor memory such as a flash memory.
  • the CPU 140 reads the provision program 120A from the ROM 120 and functions as the provision process 140A.
  • the CPU 140 reads the first addition program 120B from the ROM 120 and functions as the first addition process 140B.
  • the CPU 140 reads the second addition program 120C from the ROM 120 and functions as the second addition process 140C.
  • the RAM 130 stores, for each processor 110, a first pointer that indicates a first storage destination that stores operation source data of processing to be executed by the processor 110, and a second result that stores an operation result of operation source data to be executed by the processor. A second pointer indicating the storage destination is stored.
  • the CPU 140 provides the processor 110 with a first pointer and a second pointer related to processing executed by each processor 110.
  • the processor 110 fetches the operation source data from the first storage destination corresponding to the processor 110
  • the CPU 140 adds the extraction data length of the operation source data to the first pointer, and the addition result is added to the processor 110.
  • the processor 110 stores the calculation result for the calculation source data in the second storage destination corresponding to the processor 110
  • the CPU 140 adds the storage data length of the calculation result to the second pointer, and adds the addition result to the processor.
  • the update is registered as the second pointer 110.

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Abstract

This calculation process device disperses, into a plurality of processors, a plurality of processes into which a calculation process is divided, executes the plurality of processes, and includes a storage unit, a first adding unit, and a second adding unit. The storage unit stores, for each of the processors, a first pointer which indicates a first storage destination that stores calculation source data, and a second pointer which indicates a second storage destination that stores a calculation result. The storage unit provides, to the corresponding processor, the first pointer and the second pointer pertaining to the process executed by each of the processors. When the processor extracts, from the first storage destination, the calculation source data, the first adding unit adds the length of the extracted data to the first pointer, and updates and registers, as the first pointer, the added result. When the processor stores, to the second storage destination, the calculation result, the second adding unit adds the length of the stored data to the second pointer, and updates and registers, as the second pointer, the added result. An overhead pertaining to the calculation process can be reduced between the processors.

Description

演算処理装置、演算処理制御方法及び演算処理制御プログラムArithmetic processing device, arithmetic processing control method, and arithmetic processing control program
　本発明は、演算処理装置、演算処理制御方法及び演算処理制御プログラムに関する。 The present invention relates to an arithmetic processing device, an arithmetic processing control method, and an arithmetic processing control program.
　演算処理装置では、例えば、プロセッサやメモリの実行周波数を高くすることで処理性能の向上を図っている。しかしながら、実行周波数が高くなると、例えば、電力消費量の増加は勿論のこと、その発熱量も増加する。そこで、近年では、複数のプロセッサを並列動作して演算処理を分散して実行する演算処理装置が普及している。その結果、電力消費量の減少及び発熱量の低下を図っている。 In the arithmetic processing unit, for example, the processing performance is improved by increasing the execution frequency of the processor and the memory. However, as the execution frequency increases, for example, not only the power consumption increases, but also the heat generation amount increases. Therefore, in recent years, arithmetic processing apparatuses that operate a plurality of processors in parallel and perform arithmetic processing in a distributed manner have become widespread. As a result, power consumption and heat generation are reduced.
　複数のプロセッサを並列動作して演算処理を分散して実行する演算処理装置では、例えば、各プロセッサが演算処理を分散して実行し、各プロセッサの演算結果を揃えて出力することになる。 In an arithmetic processing apparatus that operates a plurality of processors in parallel and distributes and executes arithmetic processing, for example, each processor executes arithmetic processing in a distributed manner, and outputs the arithmetic results of each processor together.
特開平６－６６１２号公報Japanese Patent Laid-Open No. 6-6612 特開２０１４－１２３３６５号公報JP 2014-123365 A 特開平８－１６１２８０号公報JP-A-8-161280
　しかしながら、演算処理装置では、各プロセッサで演算処理を分散して実行する際に、あるプロセッサで演算処理以外の他の割込み処理が割り込まれると、当該プロセッサの演算処理の演算結果の出力が遅れる。その結果、演算処理装置では、全てのプロセッサの演算結果が出そろうまでの時間がずれるため、演算処理のスループット性能が低下してしまう。 However, in the arithmetic processing apparatus, when an arithmetic process is distributed and executed by each processor, if an interrupt process other than the arithmetic process is interrupted by a certain processor, the output of the arithmetic result of the arithmetic process of the processor is delayed. As a result, in the arithmetic processing device, since the time until the arithmetic results of all the processors are obtained is shifted, the throughput performance of the arithmetic processing is deteriorated.
　そこで、演算処理装置では、演算処理のスループット性能の低下を抑制すべく、各プロセッサが他のプロセッサの演算処理の状況や次に演算すべき処理を把握する必要があるため、演算処理に関わるプロセッサ間の通信が必要となる。その結果、演算処理に関わるオーバーヘッドが増加する。 Therefore, in the arithmetic processing unit, in order to suppress a decrease in throughput performance of arithmetic processing, each processor needs to grasp the status of arithmetic processing of other processors and the processing to be performed next. Communication between them is required. As a result, the overhead related to arithmetic processing increases.
　一つの側面では、演算処理に関わるプロセッサ間のオーバーヘッドを低減できる演算処理装置等を提供することを目的とする。 An object of one aspect is to provide an arithmetic processing device or the like that can reduce overhead between processors related to arithmetic processing.
　一つの案では、演算処理を分割した複数の処理を複数のプロセッサに分散して実行させる演算処理装置である。演算処理装置は、記憶部と、第１の加算部と、第２の加算部とを有する。記憶部は、前記プロセッサ毎に、当該プロセッサに実行させる前記処理の演算元データを格納する第１の格納先を示す第１のポインタ及び、当該プロセッサに実行させる前記演算元データの演算結果を格納する第２の格納先を示す第２のポインタを記憶する。記憶部は、各プロセッサが実行する処理に関わる前記第１のポインタ及び前記第２のポインタを当該プロセッサに提供する。第１の加算部は、プロセッサが当該プロセッサ対応の前記第１の格納先から前記演算元データを取り出した場合に当該第１のポインタに前記演算元データの取出しデータ長を加算し、その加算結果を当該プロセッサの前記第１のポインタとして更新登録する。第２の加算部は、前記プロセッサが前記演算元データに対する前記演算結果を当該プロセッサ対応の前記第２の格納先に格納した場合に当該第２のポインタに前記演算結果の格納データ長を加算し、その加算結果を当該プロセッサの前記第２のポインタとして更新登録する。 One proposal is an arithmetic processing unit that executes a plurality of processes obtained by dividing an arithmetic process in a distributed manner by a plurality of processors. The arithmetic processing device includes a storage unit, a first addition unit, and a second addition unit. The storage unit stores, for each processor, a first pointer indicating a first storage destination that stores operation source data of the processing to be executed by the processor, and an operation result of the operation source data to be executed by the processor. The second pointer indicating the second storage destination is stored. The storage unit provides the processor with the first pointer and the second pointer related to processing executed by each processor. The first addition unit adds the extraction data length of the operation source data to the first pointer when the processor extracts the operation source data from the first storage destination corresponding to the processor, and the addition result Is updated and registered as the first pointer of the processor. The second addition unit adds the storage data length of the calculation result to the second pointer when the processor stores the calculation result for the calculation source data in the second storage destination corresponding to the processor. The addition result is updated and registered as the second pointer of the processor.
　演算処理に関わるプロセッサ間のオーバーヘッドを低減できる。 The overhead between processors related to arithmetic processing can be reduced.
図１は、本実施例の端末装置の一例を示すブロック図である。FIG. 1 is a block diagram illustrating an example of a terminal device according to the present embodiment. 図２は、アプリ部の機能構成の一例を示す説明図である。FIG. 2 is an explanatory diagram illustrating an example of a functional configuration of the application unit. 図３は、演算元テーブルの一例を示す説明図である。FIG. 3 is an explanatory diagram of an example of the calculation source table. 図４は、演算結果テーブルの一例を示す説明図である。FIG. 4 is an explanatory diagram illustrating an example of the calculation result table. 図５は、演算元レジスタ、演算結果レジスタ及び更新レジスタの一例を示す説明図である。FIG. 5 is an explanatory diagram illustrating an example of a calculation source register, a calculation result register, and an update register. 図６は、ＣＰＵ更新レジスタの一例を示す説明図である。FIG. 6 is an explanatory diagram of an example of the CPU update register. 図７は、調停部の機能構成の一例を示す説明図である。FIG. 7 is an explanatory diagram illustrating an example of a functional configuration of the arbitration unit. 図８は、第１の演算処理に関わるＣＰＵ＃０の処理動作の一例を示すフローチャートである。FIG. 8 is a flowchart showing an example of the processing operation of the CPU # 0 related to the first arithmetic processing. 図９は、第２の演算処理に関わるＣＰＵ＃ｎの処理動作の一例を示すフローチャートである。FIG. 9 is a flowchart illustrating an example of the processing operation of the CPU #n related to the second arithmetic processing. 図１０は、調停処理に関わる調停部の処理動作の一例を示すフローチャートである。FIG. 10 is a flowchart illustrating an example of the processing operation of the arbitration unit related to the arbitration process. 図１１は、ＣＰＵ＃０、ＣＰＵ＃１及びＣＰＵ＃ｎの演算処理の動作シーケンスの一例を示す説明図である。FIG. 11 is an explanatory diagram showing an example of an operation sequence of arithmetic processing of CPU # 0, CPU # 1, and CPU #n. 図１２は、演算処理制御プログラムを実行する情報処理装置の一例を示す説明図である。FIG. 12 is an explanatory diagram illustrating an example of an information processing apparatus that executes an arithmetic processing control program.
　以下、図面に基づいて、本願の開示する演算処理装置、演算処理制御方法及び演算処理制御プログラムの実施例を詳細に説明する。尚、本実施例により、開示技術が限定されるものではない。また、以下に示す各実施例は、矛盾を起こさない範囲で適宜組み合わせても良い。 Hereinafter, embodiments of the arithmetic processing device, the arithmetic processing control method, and the arithmetic processing control program disclosed in the present application will be described in detail based on the drawings. The disclosed technology is not limited by the present embodiment. Moreover, you may combine suitably each Example shown below in the range which does not cause contradiction.
　図１は、本実施例の端末装置１の一例を示すブロック図である。図１に示す端末装置１は、無線アンテナ１１と、無線部１２と、表示部１３と、操作部１４と、フラッシュメモリ１５と、ＳＤＲＡＭ(Synchronous　Dynamic　Random　Access　Memory)１６とを有する。更に、端末装置１は、無線ＬＡＮ（Local　Area　Network）用ＬＳＩ(Large　Scale　Integrated)１７と、システムＬＳＩ１８とを有する。端末装置１は、例えば、通信機能を内蔵したスマートフォン等の端末装置である。尚、説明の便宜上、スマートフォンを例示したが、これに限定されるものではなく、タブレット端末等の端末装置であっても良い。 FIG. 1 is a block diagram illustrating an example of the terminal device 1 according to the present embodiment. The terminal device 1 illustrated in FIG. 1 includes a wireless antenna 11, a wireless unit 12, a display unit 13, an operation unit 14, a flash memory 15, and an SDRAM (Synchronous Dynamic Random Access Memory) 16. Further, the terminal device 1 includes a wireless LAN (Local Area Network) LSI (Large Scale Integrated) 17 and a system LSI 18. The terminal device 1 is a terminal device such as a smartphone with a built-in communication function, for example. In addition, although the smart phone was illustrated for convenience of explanation, it is not limited to this, and terminal devices, such as a tablet terminal, may be sufficient.
　無線アンテナ１１は、無線信号を送受信するアンテナである。無線部１２は、無線アンテナ１１を通じて無線信号を送受信する通信機能を司る通信インタフェースである。表示部１３は、各種情報を表示する出力インタフェースである。操作部１４は、各種情報を入力する入力インタフェースである。フラッシュメモリ１５は、各種プログラム等の情報を記憶する領域である。ＳＤＲＡＭ１６は、各種情報を記憶する領域である。ＳＤＲＡＭ１６は、演算元テーブル１６Ａと、演算結果テーブル１６Ｂとを有する。演算元テーブル１６Ａは、後述する演算元データを格納する領域である。演算結果テーブル１６Ｂは、後述する演算結果を格納する領域である。システムＬＳＩ１８は、端末装置１全体を制御するＬＳＩである。システムＬＳＩ１８は、無線制御部２１と、アプリ部２２とを有する。無線制御部２１は、無線部１２を制御する。無線制御部２１は、ＤＳＰ(Digital　Signal　Processor)２１Ａと、ＢＢ(Base　Band)回路２１Ｂとを有する。ＤＳＰ２１Ａは、無線信号の各種信号処理を実行する信号処理部である。ＢＢ回路２１Ｂは、無線信号のベースバンド処理を実行する信号処理部である。アプリ部２２は、例えば、演算処理を複数のＣＰＵ３１に分散して実行するマルチＣＰＵ機能を司るアプリである。 The wireless antenna 11 is an antenna that transmits and receives wireless signals. The wireless unit 12 is a communication interface that manages a communication function for transmitting and receiving wireless signals through the wireless antenna 11. The display unit 13 is an output interface that displays various types of information. The operation unit 14 is an input interface for inputting various information. The flash memory 15 is an area for storing information such as various programs. The SDRAM 16 is an area for storing various information. The SDRAM 16 has a calculation source table 16A and a calculation result table 16B. The calculation source table 16A is an area for storing calculation source data to be described later. The calculation result table 16B is an area for storing calculation results to be described later. The system LSI 18 is an LSI that controls the entire terminal device 1. The system LSI 18 includes a wireless control unit 21 and an application unit 22. The wireless control unit 21 controls the wireless unit 12. The wireless control unit 21 includes a DSP (Digital Signal Processor) 21A and a BB (Base Band) circuit 21B. The DSP 21A is a signal processing unit that executes various types of signal processing of radio signals. The BB circuit 21B is a signal processing unit that performs baseband processing of a radio signal. The application unit 22 is, for example, an application that manages a multi-CPU function that executes arithmetic processing distributed to a plurality of CPUs 31.
　図２は、アプリ部２２の機能構成の一例を示す説明図である。図２に示すアプリ部２２は、複数のＣＰＵ３１（＃０～＃ｎ）と、キャッシュメモリ３２と、表示制御部３３と、調停部３４と、共通バス３５とを有する。ＣＰＵ＃０～＃ｎは、演算処理を実行する制御部である。ＣＰＵ＃０～＃ｎは、演算元テーブル１６Ａに記憶中の演算元データに基づき、演算元データの演算処理を実行すると共に、その演算処理の演算結果を取得する。例えば、ＣＰＵ＃０～＃３は通常ＣＰＵグループ３１Ａとし、ＣＰＵ＃４～＃ｎは高速処理用ＣＰＵグループ３１Ｂとする。 FIG. 2 is an explanatory diagram illustrating an example of a functional configuration of the application unit 22. The application unit 22 illustrated in FIG. 2 includes a plurality of CPUs 31 (# 0 to #n), a cache memory 32, a display control unit 33, an arbitration unit 34, and a common bus 35. The CPUs # 0 to #n are control units that execute arithmetic processing. The CPUs # 0 to #n execute the calculation process of the calculation source data based on the calculation source data stored in the calculation source table 16A, and obtain the calculation result of the calculation process. For example, the CPUs # 0 to # 3 are the normal CPU group 31A, and the CPUs # 4 to #n are the high-speed processing CPU group 31B.
　キャッシュメモリ３２は、ＣＰＵ＃０～＃ｎの任意のＣＰＵ３１で実行する演算処理の作業領域である。表示制御部３３は、表示部１３を表示制御する。調停部３４は、ＣＰＵ＃０～＃ｎの演算処理のマルチＣＰＵ機能を支援する。共通バス３５は、ＣＰＵ＃０～＃ｎ、キャッシュメモリ３２、表示制御部３３及び調停部３４の信号を送受信するバスラインである。 The cache memory 32 is a work area for arithmetic processing executed by any CPU 31 of the CPUs # 0 to #n. The display control unit 33 controls display of the display unit 13. The arbitration unit 34 supports the multi-CPU function of the arithmetic processing of the CPUs # 0 to #n. The common bus 35 is a bus line that transmits and receives signals from the CPUs # 0 to #n, the cache memory 32, the display control unit 33, and the arbitration unit 34.
　図３は、演算元テーブル１６Ａの一例を示す説明図である。図３に示す演算元テーブル１６Ａは、演算処理に関わる演算元データを格納する格納領域である。格納領域は、演算元データポインタで識別する。図４は、演算結果テーブル１６Ｂの一例を示す説明図である。図４に示す演算結果テーブル１６Ｂは、演算結果を格納する格納領域である。尚、格納領域は、演算結果ポインタで識別する。 FIG. 3 is an explanatory diagram showing an example of the calculation source table 16A. The calculation source table 16A shown in FIG. 3 is a storage area for storing calculation source data related to calculation processing. The storage area is identified by the operation source data pointer. FIG. 4 is an explanatory diagram showing an example of the calculation result table 16B. The calculation result table 16B shown in FIG. 4 is a storage area for storing calculation results. The storage area is identified by a calculation result pointer.
　図５は、演算元レジスタ４１、演算結果レジスタ４２及び更新レジスタ４３の一例を示す説明図である。調停部３４は、例えば、演算元レジスタ４１、演算結果レジスタ４２及び更新レジスタ４３の記憶部を有する。演算元レジスタ４１は、ＣＰＵ３１毎に、当該ＣＰＵ３１が使用する演算処理の演算元データを格納する演算元テーブル１６Ａの格納先を示す第１のポインタである演算元データポインタを登録するレジスタである。演算元レジスタ４１は、例えば、ＣＰＵ＃０の演算元データを格納する格納先としてＣＰＵ＃０演算元データポインタを登録しているものとする。演算結果レジスタ４２は、ＣＰＵ３１毎に、当該ＣＰＵ３１が使用する演算処理の演算結果を格納する演算結果テーブル１６Ｂの格納先を示す第２のポインタである演算結果ポインタを登録するレジスタである。演算結果テーブル１６Ｂは、例えば、ＣＰＵ＃２の演算結果を格納する格納先としてＣＰＵ＃２演算結果ポインタを登録しているものとする。更新レジスタ４３は、ＣＰＵ３１毎に、演算処理の状態情報を格納するレジスタである。更新レジスタ４３は、例えば、ＣＰＵ＃２のレジスタとしてＣＰＵ＃２更新レジスタを登録しているものとする。 FIG. 5 is an explanatory diagram illustrating an example of the calculation source register 41, the calculation result register 42, and the update register 43. The arbitration unit 34 includes, for example, a storage unit for an operation source register 41, an operation result register 42, and an update register 43. The calculation source register 41 is a register that registers, for each CPU 31, a calculation source data pointer that is a first pointer indicating the storage destination of the calculation source table 16A that stores calculation source data of calculation processing used by the CPU 31. For example, the calculation source register 41 registers a CPU # 0 calculation source data pointer as a storage destination for storing calculation source data of the CPU # 0. The calculation result register 42 is a register that registers, for each CPU 31, a calculation result pointer that is a second pointer indicating the storage destination of the calculation result table 16B that stores calculation results of calculation processing used by the CPU 31. In the calculation result table 16B, for example, a CPU # 2 calculation result pointer is registered as a storage destination for storing a calculation result of the CPU # 2. The update register 43 is a register that stores state information of arithmetic processing for each CPU 31. For example, it is assumed that the update register 43 registers the CPU # 2 update register as the register of the CPU # 2.
　図６は、ＣＰＵ更新レジスタ４５の一例を示す説明図である。ＣＰＵ更新レジスタ４５は、ＣＰＵ３１毎に更新レジスタ４３内で管理されるものとする。図６に示すＣＰＵ更新レジスタ４５は、ＢＵＳＹ４５Ａと、ＳＴＢ４５Ｂと、ＯＰＥ４５Ｃと、残りデータ長４５Ｄと、取出しデータ長４５Ｅと、格納データ長４５Ｆとを有する。ＢＵＳＹ４５Ａは、当該ＣＰＵ更新レジスタ４５の更新中の有無を示すフラグである。尚、ＢＵＳＹ４５Ａが“１”の場合、ＣＰＵ更新レジスタ４５が更新中であることを示し、“０”の場合、ＣＰＵ更新レジスタ４５が更新中でないことを示す。ＳＴＢ４５Ｂは、ＣＰＵ更新レジスタ４５のＳＴＢの有無を示すフラグである。尚、ＳＴＢ４５Ｂは、レジスタ設定ストローブに相当し、ＳＴＢ４５Ｂを“１”の場合、取出しデータ長の取り込み開始を示し、ＳＴＢ４５Ｂが“０”の場合、取出しデータ長の取り込み完了を示す。ＯＰＥ４５Ｃは、ＣＰＵ更新レジスタ４５の演算処理中の有無を示すフラグである。尚、ＯＰＥ４５Ｃが“１”の場合、ＣＰＵ更新レジスタ４５が演算処理中であることを示し、ＯＰＥ４５Ｃが“０”の場合、ＣＰＵ更新レジスタ４５が演算処理中でないことを示す。残りデータ長４５Ｄは、演算元データの残りデータ長、例えば、残りバイト数を示す情報である。取出しデータ長４５Ｅは、演算元テーブル１６Ａから取り出した演算元データのデータ長、例えばバイト数を示す情報である。格納データ長４５Ｆは、演算処理の演算結果を演算結果テーブル１６Ｂに格納するデータ長、例えば、バイト数を示す情報である。 FIG. 6 is an explanatory diagram showing an example of the CPU update register 45. It is assumed that the CPU update register 45 is managed in the update register 43 for each CPU 31. The CPU update register 45 illustrated in FIG. 6 includes a BUSY 45A, an STB 45B, an OPE 45C, a remaining data length 45D, an extraction data length 45E, and a storage data length 45F. The BUSY 45A is a flag indicating whether or not the CPU update register 45 is being updated. When BUSY 45A is “1”, it indicates that the CPU update register 45 is being updated, and when it is “0”, it indicates that the CPU update register 45 is not being updated. The STB 45B is a flag indicating the presence / absence of the STB in the CPU update register 45. The STB 45B corresponds to a register setting strobe. When the STB 45B is “1”, the fetch start of the fetch data length is indicated, and when the STB 45B is “0”, the fetch of the fetch data length is completed. The OPE 45C is a flag indicating whether or not the CPU update register 45 is performing an arithmetic process. When the OPE 45C is “1”, it indicates that the CPU update register 45 is being processed, and when the OPE 45C is “0”, the CPU update register 45 is not being processed. The remaining data length 45D is information indicating the remaining data length of the operation source data, for example, the number of remaining bytes. The extracted data length 45E is information indicating the data length of the calculation source data extracted from the calculation source table 16A, for example, the number of bytes. The storage data length 45F is information indicating the data length, for example, the number of bytes, in which the calculation result of the calculation process is stored in the calculation result table 16B.
　図７は、調停部３４の機能構成の一例を示す説明図である。図７に示す調停部３４は、第１の加算部５１と、減算部５２と、第２の加算部５３とを有する。調停部３４は、指定ＣＰＵ＃ｎの演算元データを格納する格納先を示す演算元データポインタをＣＰＵ＃ｎ演算元データポインタとして演算元レジスタ４１に登録する。第１の加算部５１は、ＣＰＵ＃ｎ演算元データポインタの演算データを演算元テーブル１６Ａから取り出した場合、ＣＰＵ＃ｎ演算元データポインタに演算データの取出しデータ長４５Ｅを加算する。更に、第１の加算部５１は、その加算結果をＣＰＵ＃ｎ演算元データポインタとして演算元レジスタ４１内に更新登録する。 FIG. 7 is an explanatory diagram illustrating an example of a functional configuration of the arbitration unit 34. The arbitration unit 34 illustrated in FIG. 7 includes a first addition unit 51, a subtraction unit 52, and a second addition unit 53. The arbitrating unit 34 registers a calculation source data pointer indicating a storage destination for storing calculation source data of the designated CPU #n in the calculation source register 41 as a CPU #n calculation source data pointer. When the calculation data of the CPU # n calculation source data pointer is extracted from the calculation source table 16A, the first addition unit 51 adds the extraction data length 45E of the calculation data to the CPU # n calculation source data pointer. Furthermore, the first addition unit 51 updates and registers the addition result in the operation source register 41 as a CPU #n operation source data pointer.
　減算部５２は、ＣＰＵ＃ｎ更新レジスタ内の残りデータ長４５Ｄから取出しデータ長４５Ｅを減算し、その減算結果を指定ＣＰＵ＃ｎの残りデータ長４５ＤとしてＣＰＵ更新レジスタ４５内に更新登録する、例えば、更新部である。 The subtraction unit 52 subtracts the fetched data length 45E from the remaining data length 45D in the CPU # n update register, and updates and registers the subtraction result in the CPU update register 45 as the remaining data length 45D of the designated CPU # n. The update unit.
　調停部３４は、指定ＣＰＵ＃ｎの演算結果ポインタをＣＰＵ＃ｎ演算結果ポインタとして演算結果レジスタ４２内に更新登録する。第２の加算部５３は、ＣＰＵ＃ｎ演算結果ポインタで示す格納先に指定ＣＰＵ＃ｎの演算結果を格納する場合、ＣＰＵ＃ｎ演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果をＣＰＵ＃ｎ演算結果ポインタとして演算結果レジスタ４２内に更新登録する。 The arbitrating unit 34 updates and registers the calculation result pointer of the designated CPU #n in the calculation result register 42 as the CPU #n calculation result pointer. When storing the calculation result of the designated CPU #n in the storage location indicated by the CPU #n calculation result pointer, the second addition unit 53 adds the storage data length 45F to the CPU #n calculation result pointer, and the addition result is displayed. The CPU #n is updated and registered in the calculation result register 42 as a calculation result pointer.
　次に本実施例の端末装置１の動作について説明する。図８は、第１の演算処理に関わるＣＰＵ＃０の処理動作の一例を示すフローチャートである。尚、ＣＰＵ＃０は、演算プロセスの処理要求を受け付けるＣＰＵ３１とする。図８においてＣＰＵ＃０は、例えば、操作部１４の入力操作に応じた演算プロセスの処理要求を検出したか否かを判定する（ステップＳ２１）。ＣＰＵ＃０は、演算プロセスの処理要求を検出した場合（ステップＳ２１肯定）、演算プロセスの処理要求に対応した演算処理を対象ＣＰＵ３１毎に分散する（ステップＳ２２）。尚、対象ＣＰＵ３１は、ＣＰＵ＃０が演算プロセスに対応する演算処理を分散し、分散した演算処理を実行するＣＰＵである。 Next, the operation of the terminal device 1 of this embodiment will be described. FIG. 8 is a flowchart showing an example of the processing operation of the CPU # 0 related to the first arithmetic processing. The CPU # 0 is the CPU 31 that receives a processing request for an arithmetic process. In FIG. 8, for example, the CPU # 0 determines whether or not a processing request for an arithmetic process corresponding to an input operation of the operation unit 14 is detected (step S21). When CPU # 0 detects a processing request for the arithmetic process (Yes at Step S21), CPU # 0 distributes the arithmetic processing corresponding to the processing request for the arithmetic process for each target CPU 31 (Step S22). The target CPU 31 is a CPU in which CPU # 0 distributes the arithmetic processing corresponding to the arithmetic process and executes the distributed arithmetic processing.
　ＣＰＵ＃０は、調停部３４に対して対象ＣＰＵ３１毎の初期設定を要求する（ステップＳ２３）。尚、初期設定は、調停部３４に対して対象ＣＰＵ３１のＣＰＵ更新レジスタ４５内のＯＰＥ４５Ｃを“１”に更新する要求を含む。ＣＰＵ＃０は、対象ＣＰＵ３１に対して演算処理の実行を要求する（ステップＳ２４）。ＣＰＵ＃０は、調停部３４の演算元レジスタ４１からＣＰＵ＃０対応の演算元データの格納先を示すＣＰＵ＃０演算元データポインタを取得する（ステップＳ２５）。 CPU # 0 requests the arbitration unit 34 to perform initial setting for each target CPU 31 (step S23). The initial setting includes a request for the arbitrating unit 34 to update the OPE 45C in the CPU update register 45 of the target CPU 31 to “1”. CPU # 0 requests the target CPU 31 to execute arithmetic processing (step S24). CPU # 0 obtains a CPU # 0 computation source data pointer indicating the storage location of computation source data corresponding to CPU # 0 from computation source register 41 of arbitration unit 34 (step S25).
　ＣＰＵ＃０は、ＣＰＵ＃０演算元データポインタに基づき、演算元テーブル１６ＡからＣＰＵ＃０対応の演算元データを取得する（ステップＳ２６）。ＣＰＵ＃０は、演算元テーブル１６ＡからＣＰＵ＃０対応の演算元データを取得した際の取出しデータ長を調停部３４に通知する（ステップＳ２７）。 CPU # 0 acquires the operation source data corresponding to CPU # 0 from the operation source table 16A based on the CPU # 0 operation source data pointer (step S26). The CPU # 0 notifies the arbitration unit 34 of the extracted data length when the calculation source data corresponding to the CPU # 0 is acquired from the calculation source table 16A (step S27).
　ＣＰＵ＃０は、ＣＰＵ＃０対応の演算元データの演算処理を実行し（ステップＳ２８）、ＣＰＵ＃０対応の演算結果を取得する（ステップＳ２９）。ＣＰＵ＃０は、調停部３４からＣＰＵ＃０対応の演算結果を格納する格納先を示すＣＰＵ＃０演算結果ポインタを取得する（ステップＳ３０）。ＣＰＵ＃０は、ＣＰＵ＃０演算結果ポインタに対応する演算結果テーブル１６Ｂ内の格納先にＣＰＵ＃０の演算結果を格納する（ステップＳ３１）。更に、ＣＰＵ＃０は、ＣＰＵ＃０の演算結果を演算結果テーブル１６Ｂに格納した際の格納データ長４５Ｆを調停部３４に通知する（ステップＳ３２）。 CPU # 0 executes calculation processing of calculation source data corresponding to CPU # 0 (step S28), and acquires a calculation result corresponding to CPU # 0 (step S29). The CPU # 0 obtains a CPU # 0 calculation result pointer indicating the storage destination for storing the calculation result corresponding to the CPU # 0 from the arbitrating unit 34 (step S30). The CPU # 0 stores the calculation result of the CPU # 0 in the storage destination in the calculation result table 16B corresponding to the CPU # 0 calculation result pointer (step S31). Further, the CPU # 0 notifies the arbitration unit 34 of the storage data length 45F when the calculation result of the CPU # 0 is stored in the calculation result table 16B (step S32).
　ＣＰＵ＃０は、調停部３４のＣＰＵ＃０更新レジスタ４５内の残りデータ長４５Ｄを参照し、残りデータ長４５Ｄが“０”であるか否かを判定する（ステップＳ３３）。ＣＰＵ＃０は、残りデータ長４５Ｄが“０”でない場合（ステップＳ３３否定）、調停部３４から次のＣＰＵ＃０演算元データポインタを取得すべく、ステップＳ２５に移行する。 CPU # 0 refers to the remaining data length 45D in the CPU # 0 update register 45 of the arbitration unit 34, and determines whether or not the remaining data length 45D is “0” (step S33). If the remaining data length 45D is not “0” (No at Step S33), the CPU # 0 proceeds to Step S25 in order to obtain the next CPU # 0 calculation source data pointer from the arbitration unit 34.
　また、ＣＰＵ＃０は、残りデータ長４５Ｄが“０”の場合（ステップＳ３３肯定）、調停部３４に対してＣＰＵ＃０更新レジスタ４５内のＯＰＥ４５Ｃを“０”に設定要求する（ステップＳ３４）。ＣＰＵ＃０は、全ての対象ＣＰＵ３１から演算処理完了の通知を受信したか否かを判定する（ステップＳ３５）。 If the remaining data length 45D is “0” (Yes at Step S33), the CPU # 0 requests the arbitration unit 34 to set the OPE 45C in the CPU # 0 update register 45 to “0” (Step S34). . The CPU # 0 determines whether or not calculation processing completion notifications have been received from all the target CPUs 31 (step S35).
　ＣＰＵ＃０は、全ての対象ＣＰＵ３１から演算処理完了の通知を受信した場合（ステップＳ３５肯定）、調停部３４の演算結果レジスタ４２から対象ＣＰＵ３１の演算結果ポインタを取得する（ステップＳ３６）。そして、ＣＰＵ＃０は、対象ＣＰＵ３１の演算結果ポインタに基づき、演算結果テーブル１６Ｂから対象ＣＰＵ３１の演算結果を取得する（ステップＳ３７）。ＣＰＵ＃０は、対象ＣＰＵ３１の演算結果に基づき、演算プロセスに対応した演算結果を出力し（ステップＳ３８）、図８に示す処理動作を終了する。ＣＰＵ＃０は、演算プロセス要求を検出しなかった場合（ステップＳ２１否定）、図８に示す処理動作を終了する。ＣＰＵ＃０は、全ての対象ＣＰＵ３１の演算完了通知を検出しなかった場合（ステップＳ３５否定）、全ての対象ＣＰＵ３１の演算完了通知を検出するまでステップＳ３５の判定処理を継続する。 CPU # 0 acquires the calculation result pointer of the target CPU 31 from the calculation result register 42 of the arbitration unit 34 (step S36) when receiving notification of the completion of the calculation process from all the target CPUs 31 (Yes in step S35). Then, the CPU # 0 acquires the calculation result of the target CPU 31 from the calculation result table 16B based on the calculation result pointer of the target CPU 31 (step S37). The CPU # 0 outputs the calculation result corresponding to the calculation process based on the calculation result of the target CPU 31 (step S38), and ends the processing operation shown in FIG. When the CPU # 0 does not detect the calculation process request (No at Step S21), the processing operation illustrated in FIG. If the CPU # 0 has not detected the calculation completion notifications of all the target CPUs 31 (No in step S35), the CPU # 0 continues the determination process of step S35 until the calculation completion notifications of all the target CPUs 31 are detected.
　ＣＰＵ＃０は、調停部３４内の演算元レジスタ４１のＣＰＵ＃０演算元データポインタを取得し、ＣＰＵ＃０演算元データポインタに基づき、演算元テーブル１６Ａから演算元データを取得する。その結果、ＣＰＵ＃０は、調停部３４内の演算元レジスタ４１を参照し、ＣＰＵ＃０対応の演算元データを取得できる。 CPU # 0 acquires the CPU # 0 calculation source data pointer of the calculation source register 41 in the arbitration unit 34, and acquires calculation source data from the calculation source table 16A based on the CPU # 0 calculation source data pointer. As a result, the CPU # 0 can obtain the calculation source data corresponding to the CPU # 0 with reference to the calculation source register 41 in the arbitration unit 34.
　ＣＰＵ＃０は、調停部３４内の演算結果レジスタ４２のＣＰＵ＃０演算結果ポインタを取得し、ＣＰＵ＃０演算結果ポインタに基づき、演算結果テーブル１６Ｂの格納先に演算結果を格納する。その結果、ＣＰＵ＃０は、調停部３４内の演算結果レジスタ４２を参照し、ＣＰＵ＃０対応の演算結果の格納先を特定できる。 CPU # 0 acquires the CPU # 0 calculation result pointer of the calculation result register 42 in the arbitration unit 34, and stores the calculation result in the storage destination of the calculation result table 16B based on the CPU # 0 calculation result pointer. As a result, the CPU # 0 can refer to the calculation result register 42 in the arbitration unit 34 and specify the storage destination of the calculation result corresponding to the CPU # 0.
　ＣＰＵ＃０は、ＣＰＵ＃０対応の演算元データを演算元テーブル１６Ａから取得した場合、取出しデータ長４５Ｅを調停部３４に通知する。その結果、調停部３４は、取出しデータ長４５Ｅに応じて次のＣＰＵ＃０の演算データの格納先を示すＣＰＵ＃０演算元データポインタを更新できる。 CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E when the calculation source data corresponding to CPU # 0 is acquired from the calculation source table 16A. As a result, the arbitration unit 34 can update the CPU # 0 computation source data pointer indicating the storage location of the computation data of the next CPU # 0 according to the fetch data length 45E.
　ＣＰＵ＃０は、ＣＰＵ＃０対応の演算結果を演算結果テーブル１６Ｂに格納した場合、格納データ長４５Ｆを調停部３４に通知する。その結果、調停部３４は、格納データ長４５Ｆに応じて次のＣＰＵ＃０の演算結果の格納先を示すＣＰＵ＃０演算結果ポインタを更新できる。 CPU # 0 notifies the arbitration unit 34 of the stored data length 45F when the calculation result corresponding to CPU # 0 is stored in the calculation result table 16B. As a result, the arbitrating unit 34 can update the CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the next CPU # 0 according to the stored data length 45F.
　ＣＰＵ＃０は、調停部３４内の更新レジスタ４３内のＣＰＵ＃０更新レジスタを参照し、残りデータ長４５Ｄが“０”の場合、ＣＰＵ＃０のＯＰＥを“０”に設定する。その結果、調停部３４は、ＣＰＵ＃０の演算処理の完了を認識できる。 The CPU # 0 refers to the CPU # 0 update register in the update register 43 in the arbitration unit 34, and sets the OPE of the CPU # 0 to “0” when the remaining data length 45D is “0”. As a result, the arbitrating unit 34 can recognize the completion of the arithmetic processing of the CPU # 0.
　ＣＰＵ＃０は、対象ＣＰＵ３１の演算処理の完了を受信した場合、調停部３４内の各対象ＣＰＵ３１対応の演算結果ポインタを参照し、演算結果ポインタに基づき、各対象ＣＰＵ３１の演算結果を取得する。そして、ＣＰＵ＃０は、対象ＣＰＵ３１の演算結果に基づき、演算プロセスに対応した演算結果を取得できる。 When CPU # 0 receives the completion of the calculation process of the target CPU 31, the CPU # 0 refers to the calculation result pointer corresponding to each target CPU 31 in the arbitration unit 34, and acquires the calculation result of each target CPU 31 based on the calculation result pointer. Then, the CPU # 0 can acquire the calculation result corresponding to the calculation process based on the calculation result of the target CPU 31.
　図９は、第２の演算処理に関わるＣＰＵ＃ｎの処理動作の一例を示すフローチャートである。尚、図９の例では、ＣＰＵ＃ｎを例示したが、ＣＰＵ＃ｎに限定されるものではなく、各対象ＣＰＵ３１で実行するものとする。図９においてＣＰＵ＃ｎは、ＣＰＵ＃０から演算処理要求を検出したか否かを判定する（ステップＳ４１）。ＣＰＵ＃ｎは、演算処理要求を検出した場合（ステップＳ４１肯定）、自分のＣＰＵ－ＩＤ、すなわちＣＰＵ＃ｎを読み出す（ステップＳ４２）。 FIG. 9 is a flowchart showing an example of the processing operation of CPU #n related to the second arithmetic processing. In the example of FIG. 9, the CPU #n is illustrated, but is not limited to the CPU #n, and is executed by each target CPU 31. In FIG. 9, the CPU #n determines whether or not an arithmetic processing request has been detected from the CPU # 0 (step S41). When CPU #n detects a calculation processing request (Yes at step S41), CPU #n reads out its own CPU-ID, that is, CPU #n (step S42).
　ＣＰＵ＃ｎは、調停部３４内の演算元レジスタ４１からＣＰＵ＃ｎ対応のＣＰＵ＃ｎ演算元データポインタを取得する（ステップＳ４３）。ＣＰＵ＃ｎは、ＣＰＵ＃ｎ演算元データポインタに基づき、演算元テーブル１６ＡからＣＰＵ＃ｎ対応の演算元データを取得する（ステップＳ４４）。ＣＰＵ＃ｎは、演算元テーブル１６ＡからＣＰＵ＃ｎ対応の演算元データを取得した際の取出しデータ長を調停部３４に通知する（ステップＳ４５）。 CPU #n acquires the CPU #n operation source data pointer corresponding to CPU #n from the operation source register 41 in the arbitration unit 34 (step S43). The CPU #n acquires the operation source data corresponding to the CPU #n from the operation source table 16A based on the CPU #n operation source data pointer (step S44). The CPU #n notifies the arbitration unit 34 of the fetched data length when the computation source data corresponding to the CPU #n is acquired from the computation source table 16A (step S45).
　ＣＰＵ＃ｎは、ＣＰＵ＃ｎ対応の演算元データの演算処理を実行し（ステップＳ４６）、ＣＰＵ＃ｎ対応の演算結果を取得する（ステップＳ４７）。ＣＰＵ＃ｎは、調停部３４内の演算結果レジスタ４２からＣＰＵ＃ｎ演算結果ポインタを取得する（ステップＳ４８）。ＣＰＵ＃ｎは、ＣＰＵ＃ｎ演算結果ポインタに対応する演算結果テーブル１６Ｂ内の格納先にＣＰＵ＃ｎの演算結果を格納する（ステップＳ４９）。更に、ＣＰＵ＃ｎは、ＣＰＵ＃ｎの演算結果を演算結果テーブル１６Ｂに格納した際の格納データ長４５Ｆを調停部３４に通知する（ステップＳ５０）。 CPU # n executes calculation processing of calculation source data corresponding to CPU # n (step S46), and acquires a calculation result corresponding to CPU # n (step S47). The CPU #n acquires a CPU #n calculation result pointer from the calculation result register 42 in the arbitration unit 34 (step S48). The CPU #n stores the calculation result of the CPU #n in the storage destination in the calculation result table 16B corresponding to the CPU #n calculation result pointer (step S49). Further, the CPU #n notifies the arbitration unit 34 of the storage data length 45F when the calculation result of the CPU #n is stored in the calculation result table 16B (step S50).
　ＣＰＵ＃ｎは、調停部３４のＣＰＵ＃ｎ更新レジスタ４５内の残りデータ長４５Ｄを参照し、残りデータ長４５Ｄが“０”であるか否かを判定する（ステップＳ５１）。ＣＰＵ＃ｎは、残りデータ長４５Ｄが“０”でない場合（ステップＳ５１否定）、調停部３４内の演算元レジスタ４１からＣＰＵ＃ｎ演算元データポインタを取得すべく、ステップＳ４３に移行する。 CPU # n refers to the remaining data length 45D in the CPU # n update register 45 of the arbitration unit 34, and determines whether or not the remaining data length 45D is “0” (step S51). When the remaining data length 45D is not “0” (No at Step S51), the CPU #n proceeds to Step S43 in order to obtain the CPU #n calculation source data pointer from the calculation source register 41 in the arbitration unit 34.
　また、ＣＰＵ＃ｎは、残りデータ長４５Ｄが“０”の場合（ステップＳ５１肯定）、調停部３４に対してＣＰＵ＃ｎ更新レジスタ４５内のＯＰＥ４５Ｃを“０”に設定する更新を要求する（ステップＳ５２）。そして、ＣＰＵ＃ｎは、演算処理の完了をＣＰＵ＃０に通知し（ステップＳ５３）、図９に示す処理動作を終了する。また、ＣＰＵ＃ｎは、ＣＰＵ＃０から演算処理要求を検出したのでない場合（ステップＳ４１否定）、図９に示す処理動作を終了する。 When the remaining data length 45D is “0” (Yes at Step S51), the CPU #n requests the arbitration unit 34 to update to set the OPE 45C in the CPU #n update register 45 to “0” ( Step S52). Then, the CPU #n notifies the CPU # 0 of completion of the arithmetic processing (step S53), and ends the processing operation shown in FIG. On the other hand, if the CPU #n has not detected an arithmetic processing request from the CPU # 0 (No at step S41), the CPU #n ends the processing operation shown in FIG.
　ＣＰＵ＃ｎは、調停部３４内の演算元レジスタ４１のＣＰＵ＃ｎ演算元データポインタを取得し、ＣＰＵ＃ｎ演算元データポインタに基づき、演算元テーブル１６Ａから演算元データを取得する。その結果、ＣＰＵ＃ｎは、調停部３４内の演算元レジスタ４１を参照し、ＣＰＵ＃ｎ対応の演算元データを取得できる。 CPU #n acquires the CPU #n calculation source data pointer of the calculation source register 41 in the arbitration unit 34, and acquires calculation source data from the calculation source table 16A based on the CPU #n calculation source data pointer. As a result, the CPU #n refers to the calculation source register 41 in the arbitration unit 34 and can acquire calculation source data corresponding to the CPU #n.
　ＣＰＵ＃ｎは、調停部３４内の演算結果レジスタ４２のＣＰＵ＃ｎ演算結果ポインタを取得し、ＣＰＵ＃ｎ演算結果ポインタに基づき、演算結果テーブル１６Ｂの格納先に演算結果を格納する。その結果、ＣＰＵ＃ｎは、調停部３４内の演算結果レジスタ４２を参照し、ＣＰＵ＃ｎ対応の演算結果の格納先を特定できる。 CPU # n acquires the CPU # n calculation result pointer of the calculation result register 42 in the arbitration unit 34, and stores the calculation result in the storage destination of the calculation result table 16B based on the CPU # n calculation result pointer. As a result, the CPU #n can specify the storage destination of the calculation result corresponding to the CPU #n with reference to the calculation result register 42 in the arbitration unit 34.
　ＣＰＵ＃ｎは、ＣＰＵ＃ｎ対応の演算元データを演算元テーブル１６Ａから取得した場合、取出しデータ長４５Ｅを調停部３４に通知する。その結果、調停部３４は、取出しデータ長４５Ｅに応じて次のＣＰＵ＃ｎの演算データの格納先を示すＣＰＵ＃ｎ演算元データポインタを更新できる。 CPU # n notifies the arbitration unit 34 of the extraction data length 45E when the calculation source data corresponding to CPU # n is acquired from the calculation source table 16A. As a result, the arbitrating unit 34 can update the CPU #n calculation source data pointer indicating the storage location of the calculation data of the next CPU #n according to the fetch data length 45E.
　ＣＰＵ＃ｎは、ＣＰＵ＃ｎ対応の演算結果を演算結果テーブル１６Ｂに格納した場合、格納データ長４５Ｆを調停部３４に通知する。その結果、調停部３４は、格納データ長４５Ｆに応じて次のＣＰＵ＃ｎの演算結果の格納先を示すＣＰＵ＃ｎ演算結果ポインタを更新できる。 CPU # n notifies the arbitration unit 34 of the storage data length 45F when the calculation result corresponding to CPU # n is stored in the calculation result table 16B. As a result, the arbitrating unit 34 can update the CPU #n calculation result pointer indicating the storage destination of the calculation result of the next CPU #n according to the stored data length 45F.
　ＣＰＵ＃ｎは、調停部３４内の更新レジスタ４３内のＣＰＵ＃ｎ更新レジスタを参照し、残りデータ長４５Ｄが“０”の場合、ＣＰＵ＃ｎのＯＰＥを“０”に設定する。その結果、調停部３４は、ＣＰＵ＃ｎの演算処理の完了を認識できる。 CPU #n refers to the CPU #n update register in the update register 43 in the arbitration unit 34, and sets the OPE of CPU #n to “0” when the remaining data length 45D is “0”. As a result, the arbitrating unit 34 can recognize the completion of the arithmetic processing of the CPU #n.
　図１０は、調停処理に関わる調停部３４の処理動作の一例を示すフローチャートである。図１０において調停部３４は、ＣＰＵ＃０から初期設定要求を検出したか否かを判定する（ステップＳ６１）。調停部３４は、ＣＰＵ＃０から初期設定要求を検出した場合（ステップＳ６１肯定）、対象ＣＰＵ３１毎の演算元データの格納先を示す演算元データポインタを対象ＣＰＵ３１毎の演算元データポインタとして演算元レジスタ４１内に登録する（ステップＳ６２）。 FIG. 10 is a flowchart showing an example of the processing operation of the arbitration unit 34 related to the arbitration process. In FIG. 10, the arbitrating unit 34 determines whether or not an initial setting request is detected from the CPU # 0 (step S61). When the arbitration unit 34 detects an initial setting request from the CPU # 0 (Yes in step S61), the calculation source data pointer indicating the storage destination of the calculation source data for each target CPU 31 is used as the calculation source data pointer for each target CPU 31. Registration is made in the register 41 (step S62).
　更に、調停部３４は、対象ＣＰＵ３１毎の演算結果の格納先を示す演算結果ポインタを対象ＣＰＵ３１毎の演算結果ポインタとして演算結果レジスタ４２内に登録する（ステップＳ６３）。更に、調停部３４は、対象ＣＰＵ３１毎のＣＰＵ更新レジスタ４５内の演算元データのバイト量相当の残りデータ長４５Ｄを登録する（ステップＳ６４）。 Further, the arbitrating unit 34 registers the calculation result pointer indicating the storage destination of the calculation result for each target CPU 31 in the calculation result register 42 as the calculation result pointer for each target CPU 31 (step S63). Further, the arbitrating unit 34 registers the remaining data length 45D corresponding to the byte amount of the operation source data in the CPU update register 45 for each target CPU 31 (step S64).
　調停部３４は、対象ＣＰＵ３１から未指定のＣＰＵ３１を指定する（ステップＳ６５）。調停部３４は、指定ＣＰＵ３１のＣＰＵ更新レジスタ４５内のＢＵＳＹ４５Ａを“１”に更新登録し（ステップＳ６６）、指定ＣＰＵ３１から取出しデータ長４５Ｅが受信済みであるか否かを判定する（ステップＳ６７）。調停部３４内の第１の加算部５１は、指定ＣＰＵ３１から取出しデータ長４５Ｅが受信済みの場合（ステップＳ６７肯定）、指定ＣＰＵ３１の演算元データポインタに取出しデータ長４５Ｅを加算する。そして、第１の加算部５１は、その加算結果を指定ＣＰＵ３１の演算元データポインタとして演算元レジスタ４１内に更新登録する（ステップＳ６８）。 The arbitrating unit 34 designates an undesignated CPU 31 from the target CPU 31 (step S65). The arbitrating unit 34 updates and registers BUSY 45A in the CPU update register 45 of the designated CPU 31 to “1” (step S66), and determines whether or not the fetched data length 45E has been received from the designated CPU 31 (step S67). . When the fetch data length 45E has been received from the designated CPU 31 (Yes in step S67), the first adder 51 in the arbitration unit 34 adds the fetch data length 45E to the calculation source data pointer of the designated CPU 31. Then, the first addition unit 51 updates and registers the addition result in the calculation source register 41 as the calculation source data pointer of the designated CPU 31 (step S68).
　更に、調停部３４は、指定ＣＰＵ３１の演算元データポインタの更新登録後、指定ＣＰＵ３１から格納データ長４５Ｆが受信済みであるか否かを判定する（ステップＳ６９）。調停部３４内の第２の加算部５３は、指定ＣＰＵ３１から格納データ長４５Ｆが受信済みの場合（ステップＳ６９肯定）、指定ＣＰＵ３１の演算結果ポインタに格納データ長４５Ｆを加算する。そして、第２の加算部５３は、その加算結果を指定ＣＰＵ３１の演算結果ポインタとして演算結果レジスタ４２内に更新登録する（ステップＳ７０）。 Further, the arbitrating unit 34 determines whether or not the storage data length 45F has been received from the designated CPU 31 after the update registration of the calculation source data pointer of the designated CPU 31 (step S69). When the storage data length 45F has been received from the designated CPU 31 (Yes in step S69), the second addition unit 53 in the arbitration unit 34 adds the storage data length 45F to the calculation result pointer of the designated CPU 31. Then, the second addition unit 53 updates and registers the addition result in the calculation result register 42 as the calculation result pointer of the designated CPU 31 (step S70).
　調停部３４内の減算部５２は、指定ＣＰＵ３１のＣＰＵ更新レジスタ４５内の残りデータ長４５Ｄから取出しデータ長４５Ｅを減算し、その減算結果を残りデータ長４５ＤとしてＣＰＵ更新レジスタ４５内に更新登録する（ステップＳ７１）。調停部３４は、指定ＣＰＵ３１のＣＰＵ更新レジスタ４５内のＢＵＳＹ４５Ａを“０”に設定する（ステップＳ７２）。そして、調停部３４は、対象ＣＰＵ３１から未指定のＣＰＵ３１があるか否かを判定する（ステップＳ７３）。調停部３４は、対象ＣＰＵ３１から未指定のＣＰＵ３１がある場合（ステップＳ７３肯定）、未指定のＣＰＵ３１を指定すべく、ステップＳ６５に移行する。 The subtraction unit 52 in the arbitration unit 34 subtracts the fetched data length 45E from the remaining data length 45D in the CPU update register 45 of the designated CPU 31, and updates and registers the subtraction result in the CPU update register 45 as the remaining data length 45D. (Step S71). The arbitrating unit 34 sets BUSY 45A in the CPU update register 45 of the designated CPU 31 to “0” (step S72). Then, the arbitrating unit 34 determines whether there is an unspecified CPU 31 from the target CPU 31 (step S73). When there is an undesignated CPU 31 from the target CPU 31 (Yes at Step S73), the arbitrating unit 34 proceeds to Step S65 to designate the undesignated CPU 31.
　更に、調停部３４は、未指定のＣＰＵ３１がない場合（ステップＳ７３否定）、図１０に示す処理動作を終了する。調停部３４は、ＣＰＵ＃０から初期設定要求を検出したのでない場合（ステップＳ６１否定）、図１０に示す処理動作を終了する。 Further, when there is no unspecified CPU 31 (No at Step S73), the arbitrating unit 34 ends the processing operation shown in FIG. When the arbitration unit 34 has not detected the initial setting request from the CPU # 0 (No at Step S61), the arbitrating unit 34 ends the processing operation illustrated in FIG.
　更に、調停部３４は、指定ＣＰＵ３１から取出しデータ長４５Ｅが受信済みでない場合（ステップＳ６７否定）、指定ＣＰＵ３１からの取出しデータ長４５Ｅが受信済みとなるまでステップＳ６７に移行する。更に、調停部３４は、指定ＣＰＵ３１から格納データ長４５Ｆが受信済みでない場合（ステップＳ６９否定）、指定ＣＰＵ３１からの格納データ長４５Ｆが受信済みとなるまでステップＳ６９に移行する。 Furthermore, when the fetched data length 45E has not been received from the designated CPU 31 (No at step S67), the arbitrating unit 34 proceeds to step S67 until the fetched data length 45E from the designated CPU 31 has been received. Further, when the storage data length 45F has not been received from the designated CPU 31 (No in step S69), the arbitrating unit 34 proceeds to step S69 until the storage data length 45F from the designated CPU 31 has been received.
　調停部３４は、ＣＰＵ３１毎の演算元データの格納先を示す演算元データポインタを演算元レジスタ４１に登録する。その結果、調停部３４は、対象ＣＰＵ３１に対して演算元データの格納先を提供できる。 The arbitration unit 34 registers a calculation source data pointer indicating a storage destination of calculation source data for each CPU 31 in the calculation source register 41. As a result, the arbitrating unit 34 can provide the storage destination of the calculation source data to the target CPU 31.
　調停部３４は、ＣＰＵ３１から取出しデータ長４５Ｅを受信した場合、当該ＣＰＵ３１の演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果を演算元データポインタとして演算元レジスタ４１内に更新登録する。その結果、調停部３４は、対象ＣＰＵ３１に対して次の演算元データの格納先を提供できる。 When the arbitration unit 34 receives the fetch data length 45E from the CPU 31, the arbitration unit 34 adds the fetch data length 45E to the computation source data pointer of the CPU 31, and updates and registers the addition result in the computation source register 41 as the computation source data pointer. . As a result, the arbitrating unit 34 can provide the storage destination of the next calculation source data to the target CPU 31.
　調停部３４は、ＣＰＵ３１毎の演算結果の格納先を示す演算結果ポインタを演算結果レジスタ４２に登録する。その結果、調停部３４は、対象ＣＰＵ３１に対して演算結果の格納先を提供できる。 The arbitration unit 34 registers a calculation result pointer indicating the storage destination of the calculation result for each CPU 31 in the calculation result register 42. As a result, the arbitrating unit 34 can provide the target CPU 31 with the storage location of the calculation result.
　調停部３４は、ＣＰＵ３１から格納データ長４５Ｆを受信した場合、当該ＣＰＵ３１の演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果を演算結果ポインタとして演算結果レジスタ４２内に更新登録する。その結果、調停部３４は、対象ＣＰＵ３１に対して次の演算結果の格納先を提供できる。 When the arbitration unit 34 receives the storage data length 45F from the CPU 31, the arbitration unit 34 adds the storage data length 45F to the calculation result pointer of the CPU 31, and updates and registers the addition result in the calculation result register 42 as the calculation result pointer. As a result, the arbitration unit 34 can provide the storage destination of the next calculation result to the target CPU 31.
　調停部３４は、ＣＰＵ３１から取出しデータ長４５Ｅを受信した場合、当該ＣＰＵ３１の残りデータ長４５Ｄから取出しデータ長４５Ｅを減算し、その減算結果を残りデータ長４５Ｄとして更新レジスタ４３内に更新登録する。その結果、調停部３４は、残りデータ長４５Ｄを参照し、演算処理完了のＣＰＵ３１を認識できる。 When the arbitration unit 34 receives the fetched data length 45E from the CPU 31, the arbitration unit 34 subtracts the fetched data length 45E from the remaining data length 45D of the CPU 31, and updates and registers the subtraction result in the update register 43 as the remaining data length 45D. As a result, the arbitrating unit 34 can recognize the CPU 31 that has completed the arithmetic processing with reference to the remaining data length 45D.
　図１１は、ＣＰＵ＃０、ＣＰＵ＃１及びＣＰＵ＃ｎの演算処理の動作シーケンスの一例を示す説明図である。図１１の例では、ＣＰＵ＃０が、演算プロセスの要求を受付けてＣＰＵ＃１及びＣＰＵ＃ｎに演算処理を分散した状態でＣＰＵ＃ｎに高優先処理が割り込んだ状態を示している。 FIG. 11 is an explanatory diagram showing an example of an operation sequence of arithmetic processing of CPU # 0, CPU # 1, and CPU #n. The example of FIG. 11 shows a state in which the CPU # 0 receives a request for a calculation process and distributes the calculation process to the CPU # 1 and the CPU #n and the CPU #n interrupts the high priority process.
　ＣＰＵ＃０は、例えば、演算プロセス実行のコマンド操作を検出した場合、演算プロセスを自分のＣＰＵ＃０、ＣＰＵ＃１及びＣＰＵ＃ｎに分散する（ステップＳ８１）。ＣＰＵ＃０は、演算元レジスタ４１内のＣＰＵ＃０演算元データポインタ、演算結果レジスタ４２内のＣＰＵ＃０演算結果ポインタ、更新レジスタ４３内のＣＰＵ＃０更新レジスタを参照及び更新する。そして、ＣＰＵ＃０は、演算処理１－１、演算処理１－２及び演算処理１－３を順次実行する。 For example, when CPU # 0 detects a command operation for executing the arithmetic process, the CPU # 0 distributes the arithmetic process to its own CPU # 0, CPU # 1, and CPU #n (step S81). The CPU # 0 refers to and updates the CPU # 0 operation source data pointer in the operation source register 41, the CPU # 0 operation result pointer in the operation result register 42, and the CPU # 0 update register in the update register 43. Then, CPU # 0 sequentially executes arithmetic processing 1-1, arithmetic processing 1-2, and arithmetic processing 1-3.
　つまり、ＣＰＵ＃０は、演算元レジスタ４１を参照し、演算処理１－１の演算元データの格納先を示すＣＰＵ＃０演算元データポインタを取得する。ＣＰＵ＃０は、ＣＰＵ＃０演算元データポインタに基づき、演算処理１－１の演算元データを演算元テーブル１６Ａから取得し、演算処理１－１の演算元データの演算処理を実行する（ステップＳ８２）。そして、ＣＰＵ＃０は、演算処理１－１の演算結果を取得する。ＣＰＵ＃０は、演算結果レジスタ４２を参照し、演算処理１－１の演算結果の格納先を示すＣＰＵ＃０演算結果ポインタを取得する。ＣＰＵ＃０は、ＣＰＵ＃０演算結果ポインタに基づき、演算処理１－１の演算結果を演算結果テーブル１６Ｂに格納する。ＣＰＵ＃０は、演算処理１－１の演算元データの取出しデータ長４５Ｅ及び演算結果の格納データ長４５Ｆを調停部３４に通知する。調停部３４は、ＣＰＵ＃０演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果としてＣＰＵ＃０演算元データポインタとして演算元レジスタ４１内に更新登録する。更に、調停部３４は、ＣＰＵ＃０演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果としてＣＰＵ＃０演算結果ポインタとして演算結果レジスタ４２内に更新登録する。 That is, the CPU # 0 refers to the calculation source register 41 and obtains the CPU # 0 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 1-1. Based on the CPU # 0 calculation source data pointer, the CPU # 0 acquires the calculation source data of the calculation process 1-1 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 1-1 (step S1). S82). Then, the CPU # 0 acquires the calculation result of the calculation process 1-1. The CPU # 0 refers to the calculation result register 42 and acquires a CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the calculation process 1-1. The CPU # 0 stores the calculation result of the calculation process 1-1 in the calculation result table 16B based on the CPU # 0 calculation result pointer. The CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 1-1 and the storage data length 45F of the calculation result. The arbitration unit 34 adds the fetched data length 45E to the CPU # 0 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 0 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 0 calculation result pointer, and updates and registers the addition result in the calculation result register 42 as the CPU # 0 calculation result pointer.
　更に、ＣＰＵ＃０は、演算元レジスタ４１を参照し、演算処理１－２の演算元データの格納先を示すＣＰＵ＃０演算元データポインタを取得する。ＣＰＵ＃０は、ＣＰＵ＃０演算元データポインタに基づき、演算処理１－２の演算元データを演算元テーブル１６Ａから取得し、演算処理１－２の演算元データの演算処理を実行する（ステップＳ８３）。そして、ＣＰＵ＃０は、演算処理１－２の演算結果を取得する。ＣＰＵ＃０は、演算結果レジスタ４２を参照し、演算処理１－２の演算結果の格納先を示すＣＰＵ＃０演算結果ポインタを取得する。ＣＰＵ＃０は、ＣＰＵ＃０演算結果ポインタに基づき、演算処理１－２の演算結果を演算結果テーブル１６Ｂに格納する。ＣＰＵ＃０は、演算処理１－２の演算元データの取出しデータ長４５Ｅ及び演算結果の格納データ長４５Ｆを調停部３４に通知する。調停部３４は、ＣＰＵ＃０演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果としてＣＰＵ＃０演算元データポインタとして演算元レジスタ４１内に更新登録する。更に、調停部３４は、ＣＰＵ＃０演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果としてＣＰＵ＃０演算結果ポインタとして演算結果レジスタ４２内に更新登録する。 Furthermore, the CPU # 0 refers to the calculation source register 41 and acquires a CPU # 0 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 1-2. Based on the CPU # 0 calculation source data pointer, the CPU # 0 acquires the calculation source data of the calculation process 1-2 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 1-2 (step S83). Then, the CPU # 0 acquires the calculation result of the calculation process 1-2. The CPU # 0 refers to the calculation result register 42 and obtains a CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the calculation process 1-2. The CPU # 0 stores the calculation result of the calculation process 1-2 in the calculation result table 16B based on the CPU # 0 calculation result pointer. The CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 1-2 and the storage data length 45F of the calculation result. The arbitration unit 34 adds the fetched data length 45E to the CPU # 0 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 0 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 0 calculation result pointer, and updates and registers the addition result in the calculation result register 42 as the CPU # 0 calculation result pointer.
　更に、ＣＰＵ＃０は、演算元レジスタ４１を参照し、演算処理１－３の演算元データの格納先を示すＣＰＵ＃０演算元データポインタを取得する。ＣＰＵ＃０は、ＣＰＵ＃０演算元データポインタに基づき、演算処理１－３の演算元データを演算元テーブル１６Ａから取得し、演算処理１－３の演算元データの演算処理を実行する（ステップＳ８４）。そして、ＣＰＵ＃０は、演算処理１－３の演算結果を取得する。ＣＰＵ＃０は、演算結果レジスタ４２を参照し、演算処理１－３の演算結果の格納先を示すＣＰＵ＃０演算結果ポインタを取得する。ＣＰＵ＃０は、ＣＰＵ＃０演算結果ポインタに基づき、演算処理１－３の演算結果を演算結果テーブル１６Ｂに格納する。ＣＰＵ＃０は、演算処理１－３の演算元データの取出しデータ長４５Ｅ及び演算結果の格納データ長４５Ｆを調停部３４に通知する。調停部３４は、ＣＰＵ＃０演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果としてＣＰＵ＃０演算元データポインタとして演算元レジスタ４１内に更新登録する。更に、調停部３４は、ＣＰＵ＃０演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果としてＣＰＵ＃０演算結果ポインタとして演算結果レジスタ４２内に更新登録する。そして、ＣＰＵ＃０は、演算処理１－３の演算結果を演算結果テーブル１６Ｂに格納した後、残りデータ長４５Ｄが“０”となる場合、ＣＰＵ＃０更新レジスタ内のＯＰＥを“１”に設定する。 Furthermore, the CPU # 0 refers to the calculation source register 41 and acquires a CPU # 0 calculation source data pointer indicating the storage destination of calculation source data of the calculation process 1-3. Based on the CPU # 0 calculation source data pointer, the CPU # 0 acquires the calculation source data of the calculation process 1-3 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 1-3 (step S84). Then, the CPU # 0 acquires the calculation result of the calculation process 1-3. The CPU # 0 refers to the calculation result register 42 and acquires a CPU # 0 calculation result pointer indicating the storage destination of the calculation result of the calculation process 1-3. The CPU # 0 stores the calculation result of the calculation process 1-3 in the calculation result table 16B based on the CPU # 0 calculation result pointer. The CPU # 0 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 1-3 and the storage data length 45F of the calculation result. The arbitration unit 34 adds the fetched data length 45E to the CPU # 0 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 0 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 0 calculation result pointer, and updates and registers the addition result in the calculation result register 42 as the CPU # 0 calculation result pointer. Then, after storing the calculation result of the calculation process 1-3 in the calculation result table 16B, the CPU # 0 sets the OPE in the CPU # 0 update register to “1” when the remaining data length 45D becomes “0”. Set.
　また、ＣＰＵ＃１も、演算元レジスタ４１内のＣＰＵ＃１演算元データポインタ、演算結果レジスタ４２内のＣＰＵ＃１演算結果ポインタ、更新レジスタ４３内のＣＰＵ＃１更新レジスタを参照及び更新する。そして、ＣＰＵ＃１は、演算処理２－１、演算処理２－２及び演算処理２－３を順次実行する。 The CPU # 1 also refers to and updates the CPU # 1 calculation source data pointer in the calculation source register 41, the CPU # 1 calculation result pointer in the calculation result register 42, and the CPU # 1 update register in the update register 43. Then, CPU # 1 sequentially executes arithmetic processing 2-1, arithmetic processing 2-2, and arithmetic processing 2-3.
　つまり、ＣＰＵ＃１は、演算元レジスタ４１を参照し、演算処理２－１の演算元データの格納先を示すＣＰＵ＃１演算元データポインタを取得する。ＣＰＵ＃１は、ＣＰＵ＃１演算元データポインタに基づき、演算処理２－１の演算元データを演算元テーブル１６Ａから取得し、演算処理２－１の演算元データの演算処理を実行する（ステップＳ８５）。そして、ＣＰＵ＃１は、演算処理２－１の演算結果を取得する。ＣＰＵ＃１は、演算結果レジスタ４２を参照し、演算処理２－１の演算結果の格納先を示すＣＰＵ＃１演算結果ポインタを取得する。ＣＰＵ＃１は、ＣＰＵ＃１演算結果ポインタに基づき、演算処理２－１の演算結果を演算結果テーブル１６Ｂに格納する。ＣＰＵ＃１は、演算処理２－１の演算元データの取出しデータ長４５Ｅ及び演算結果の格納データ長４５Ｆを調停部３４に通知する。調停部３４は、ＣＰＵ＃１演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果としてＣＰＵ＃１演算元データポインタとして演算元レジスタ４１内に更新登録する。更に、調停部３４は、ＣＰＵ＃１演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果としてＣＰＵ＃１演算結果ポインタとして演算結果レジスタ４２内に更新登録する。 That is, the CPU # 1 refers to the calculation source register 41 and obtains the CPU # 1 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 2-1. Based on the CPU # 1 calculation source data pointer, the CPU # 1 acquires the calculation source data of the calculation process 2-1 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 2-1. S85). Then, CPU # 1 acquires the calculation result of the calculation process 2-1. The CPU # 1 refers to the calculation result register 42 and acquires a CPU # 1 calculation result pointer indicating the storage destination of the calculation result of the calculation process 2-1. Based on the CPU # 1 calculation result pointer, the CPU # 1 stores the calculation result of the calculation process 2-1 in the calculation result table 16B. The CPU # 1 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 2-1 and the storage data length 45F of the calculation result. The arbitrating unit 34 adds the fetched data length 45E to the CPU # 1 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 1 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 1 calculation result pointer, and updates and registers it in the calculation result register 42 as the CPU # 1 calculation result pointer.
　更に、ＣＰＵ＃１は、演算元レジスタ４１を参照し、演算処理２－２の演算元データの格納先を示すＣＰＵ＃１演算元データポインタを取得する。ＣＰＵ＃１は、ＣＰＵ＃１演算元データポインタに基づき、演算処理２－２の演算元データを演算元テーブル１６Ａから取得し、演算処理２－２の演算元データの演算処理を実行する（ステップＳ８６）。そして、ＣＰＵ＃１は、演算処理２－２の演算結果を取得する。ＣＰＵ＃１は、演算結果レジスタ４２を参照し、演算処理２－２の演算結果の格納先を示すＣＰＵ＃１演算結果ポインタを取得する。ＣＰＵ＃１は、ＣＰＵ＃１演算結果ポインタに基づき、演算処理２－２の演算結果を演算結果テーブル１６Ｂに格納する。ＣＰＵ＃１は、演算処理２－２の演算元データの取出しデータ長４５Ｅ及び演算結果の格納データ長４５Ｆを調停部３４に通知する。調停部３４は、ＣＰＵ＃１演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果としてＣＰＵ＃１演算元データポインタとして演算元レジスタ４１内に更新登録する。更に、調停部３４は、ＣＰＵ＃１演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果としてＣＰＵ＃１演算結果ポインタとして演算結果レジスタ４２内に更新登録する。 Further, the CPU # 1 refers to the calculation source register 41, and obtains a CPU # 1 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 2-2. Based on the CPU # 1 calculation source data pointer, the CPU # 1 acquires the calculation source data of the calculation process 2-2 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 2-2 (Step S1). S86). Then, the CPU # 1 acquires the calculation result of the calculation process 2-2. The CPU # 1 refers to the calculation result register 42 and obtains a CPU # 1 calculation result pointer indicating the storage destination of the calculation result of the calculation process 2-2. Based on the CPU # 1 calculation result pointer, the CPU # 1 stores the calculation result of the calculation process 2-2 in the calculation result table 16B. The CPU # 1 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 2-2 and the storage data length 45F of the calculation result. The arbitrating unit 34 adds the fetched data length 45E to the CPU # 1 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 1 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 1 calculation result pointer, and updates and registers it in the calculation result register 42 as the CPU # 1 calculation result pointer.
　更に、ＣＰＵ＃１は、演算元レジスタ４１を参照し、演算処理２－３の演算元データの格納先を示すＣＰＵ＃１演算元データポインタを取得する。ＣＰＵ＃１は、ＣＰＵ＃１演算元データポインタに基づき、演算処理２－３の演算元データを演算元テーブル１６Ａから取得し、演算処理２－３の演算元データの演算処理を実行する（ステップＳ８７）。そして、ＣＰＵ＃１は、演算処理２－３の演算結果を取得する。ＣＰＵ＃１は、演算結果レジスタ４２を参照し、演算処理２－３の演算結果の格納先を示すＣＰＵ＃１演算結果ポインタを取得する。ＣＰＵ＃１は、ＣＰＵ＃１演算結果ポインタに基づき、演算処理２－３の演算結果を演算結果テーブル１６Ｂに格納する。ＣＰＵ＃１は、演算処理２－３の演算元データの取出しデータ長４５Ｅ及び演算結果の格納データ長４５Ｆを調停部３４に通知する。調停部３４は、ＣＰＵ＃１演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果としてＣＰＵ＃１演算元データポインタとして演算元レジスタ４１内に更新登録する。更に、調停部３４は、ＣＰＵ＃１演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果としてＣＰＵ＃１演算結果ポインタとして演算結果レジスタ４２内に更新登録する。そして、ＣＰＵ＃１は、演算処理２－３の演算結果を演算結果テーブル１６Ｂに格納した後、残りデータ長４５Ｄが“０”となる場合、ＣＰＵ＃１更新レジスタ内のＯＰＥを“１”に設定し、ＣＰＵ＃０に演算処理の完了を通知する。 Furthermore, the CPU # 1 refers to the calculation source register 41 and acquires a CPU # 1 calculation source data pointer indicating the storage destination of the calculation source data of the calculation process 2-3. Based on the CPU # 1 calculation source data pointer, the CPU # 1 acquires the calculation source data of the calculation process 2-3 from the calculation source table 16A, and executes the calculation process of the calculation source data of the calculation process 2-3 (step S1). S87). Then, the CPU # 1 acquires the calculation result of the calculation process 2-3. The CPU # 1 refers to the calculation result register 42 and obtains a CPU # 1 calculation result pointer indicating the storage destination of the calculation result of the calculation process 2-3. Based on the CPU # 1 calculation result pointer, the CPU # 1 stores the calculation result of the calculation process 2-3 in the calculation result table 16B. The CPU # 1 notifies the arbitration unit 34 of the extraction data length 45E of the calculation source data of the calculation process 2-3 and the storage data length 45F of the calculation result. The arbitrating unit 34 adds the fetched data length 45E to the CPU # 1 computation source data pointer, and updates and registers it in the computation source register 41 as the CPU # 1 computation source data pointer. Further, the arbitrating unit 34 adds the stored data length 45F to the CPU # 1 calculation result pointer, and updates and registers it in the calculation result register 42 as the CPU # 1 calculation result pointer. Then, after storing the calculation result of the calculation process 2-3 in the calculation result table 16B, the CPU # 1 sets the OPE in the CPU # 1 update register to “1” when the remaining data length 45D becomes “0”. Set and notify CPU # 0 of the completion of arithmetic processing.
　また、ＣＰＵ＃ｎは、高優先処理を実行した後（ステップＳ８８）、調停部３４内の演算元レジスタ４１内のＣＰＵ＃ｎ演算元データポインタ、演算結果レジスタ４２内のＣＰＵ＃ｎ演算結果ポインタ、更新レジスタ４３内のＣＰＵ＃ｎ更新レジスタを参照する。ＣＰＵ＃ｎは、演算元レジスタ４１を参照し、演算処理ｎ－１の演算元データの格納先を示すＣＰＵ＃ｎ演算元データポインタを取得する。ＣＰＵ＃ｎは、ＣＰＵ＃ｎ演算元データポインタに基づき、ＣＰＵ＃ｎは、演算処理ｎ－１の演算元データの演算処理を実行する（ステップＳ８９）。そして、ＣＰＵ＃ｎは、演算処理ｎ－１の演算結果を演算結果テーブル１６Ｂに格納する。そして、ＣＰＵ＃ｎは、演算処理ｎ－１の演算結果を演算結果テーブル１６Ｂに格納した後、残りデータ長４５Ｄが“０”となる場合、ＣＰＵ＃ｎ更新レジスタ内のＯＰＥを“１”に設定し、ＣＰＵ＃０に演算処理の完了を通知する。 Further, after executing the high priority processing (step S88), the CPU #n executes the CPU #n calculation source data pointer in the calculation source register 41 in the arbitration unit 34, and the CPU #n calculation result pointer in the calculation result register 42. The CPU #n update register in the update register 43 is referred to. The CPU #n refers to the calculation source register 41 and acquires a CPU #n calculation source data pointer indicating the storage destination of the calculation source data of the calculation process n-1. Based on the CPU # n calculation source data pointer, CPU # n executes calculation processing of calculation source data of calculation processing n−1 (step S89). Then, the CPU #n stores the calculation result of the calculation process n−1 in the calculation result table 16B. Then, after storing the calculation result of the calculation process n−1 in the calculation result table 16B, the CPU #n sets the OPE in the CPU #n update register to “1” when the remaining data length 45D becomes “0”. Set and notify CPU # 0 of the completion of arithmetic processing.
　ＣＰＵ＃０は、対象ＣＰＵ３１、例えばＣＰＵ＃１及びＣＰＵ＃ｎから演算処理の完了を受信した場合、ＣＰＵ＃０、ＣＰＵ＃１及びＣＰＵ＃ｎの演算結果に基づき演算プロセスに対応した演算結果を出力する演算プロセスの後処理を実行する（ステップＳ９０）。 When CPU # 0 receives the completion of calculation processing from the target CPU 31, for example, CPU # 1 and CPU #n, CPU # 0 displays the calculation result corresponding to the calculation process based on the calculation results of CPU # 0, CPU # 1 and CPU #n. Post-processing of the calculation process to be output is executed (step S90).
　実施例１の調停部３４は、ＣＰＵ３１毎に、ＣＰＵ演算元データポインタ、ＣＰＵ演算結果ポインタ及びＣＰＵ更新レジスタ４５を登録する。調停部３４は、第１の加算部５１と、第２の加算部５３と、減算部５２とを有する。第１の加算部５１は、ＣＰＵ演算元データポインタに基づき、演算元テーブル１６ＡからＣＰＵ演算元データを取り出した場合、ＣＰＵ演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果をＣＰＵ演算元データポインタとして更新登録する。第２の加算部５２は、演算結果をＣＰＵ演算結果ポインタの格納先に格納した場合、ＣＰＵ演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果をＣＰＵ演算結果ポインタとして更新登録する。減算部５２は、残りデータ長４５Ｄから取出しデータ長４５Ｅを減算し、減算結果が“０”の場合に演算処理の完了を更新登録する。 The arbitration unit 34 according to the first embodiment registers a CPU calculation source data pointer, a CPU calculation result pointer, and a CPU update register 45 for each CPU 31. The arbitration unit 34 includes a first addition unit 51, a second addition unit 53, and a subtraction unit 52. When the first adder 51 fetches CPU computation source data from the computation source table 16A based on the CPU computation source data pointer, the first addition unit 51 adds the fetched data length 45E to the CPU computation source data pointer, and the addition result is CPU computation. Update and register as the original data pointer. When the calculation result is stored in the CPU calculation result pointer storage destination, the second addition unit 52 adds the storage data length 45F to the CPU calculation result pointer, and updates and registers the addition result as the CPU calculation result pointer. The subtraction unit 52 subtracts the extracted data length 45E from the remaining data length 45D, and updates and registers the completion of the arithmetic processing when the subtraction result is “0”.
　調停部３４は、ＣＰＵ３１から取出しデータ長４５Ｅを受信した場合、当該ＣＰＵ３１の演算元データポインタに取出しデータ長４５Ｅを加算し、その加算結果を演算元データポインタとして演算元レジスタ４１内に更新登録する。その結果、調停部３４は、対象ＣＰＵ３１に対して次の演算元データの格納先を提供できる。ＣＰＵ３１間での協調・同期を行うための通信による負荷を増やさずに、各ＣＰＵ３１の負荷状態にしたがって、各ＣＰＵ３１での並列動作を空き時間なしに実行し、効率よく処理の実行ができる。マルチメディアデータ処理等の大量データに対し、多数の演算処理を行うアプリケーション処理について、高優先の処理や、演算時間の変化が発生しても、空いているＣＰＵ３１が順次、調停部３４から次に実行すべき演算データを直接読出し、演算処理を続行する。その結果、最終的な待ち合わせ時間を最小限に抑え、その処理を高速に実行出来る。 When the arbitration unit 34 receives the fetch data length 45E from the CPU 31, the arbitration unit 34 adds the fetch data length 45E to the computation source data pointer of the CPU 31, and updates and registers the addition result in the computation source register 41 as the computation source data pointer. . As a result, the arbitrating unit 34 can provide the storage destination of the next calculation source data to the target CPU 31. The parallel operation in each CPU 31 can be executed without idle time according to the load state of each CPU 31 without increasing the load due to communication for performing cooperation / synchronization between the CPUs 31, and the process can be executed efficiently. For application processing that performs a large number of arithmetic processing on a large amount of data such as multimedia data processing, even if a high-priority processing or a change in arithmetic time occurs, the vacant CPU 31 sequentially moves from the arbitration unit 34 to the next. Read the operation data to be executed directly and continue the operation process. As a result, the final waiting time can be minimized and the processing can be executed at high speed.
　調停部３４は、ＣＰＵ３１から格納データ長４５Ｆを受信した場合、当該ＣＰＵ３１の演算結果ポインタに格納データ長４５Ｆを加算し、その加算結果を演算結果ポインタとして演算結果レジスタ４２内に更新登録する。その結果、調停部３４は、対象ＣＰＵ３１に対して次の演算結果の格納先を提供できる。 When the arbitration unit 34 receives the storage data length 45F from the CPU 31, the arbitration unit 34 adds the storage data length 45F to the calculation result pointer of the CPU 31, and updates and registers the addition result in the calculation result register 42 as the calculation result pointer. As a result, the arbitration unit 34 can provide the storage destination of the next calculation result to the target CPU 31.
　調停部３４は、ＣＰＵ３１から取出しデータ長４５Ｅを受信した場合、当該ＣＰＵ３１の残りデータ長４５Ｄから取出しデータ長４５Ｅを減算し、その減算結果を残りデータ長４５Ｄとして更新レジスタ４３内に更新登録する。その結果、調停部３４は、残りデータ長４５Ｄを参照し、演算処理完了のＣＰＵ３１を認識できる。そして、演算処理に関わるＣＰＵ３１間のオーバーヘッドを低減できる。 When the arbitration unit 34 receives the fetched data length 45E from the CPU 31, the arbitration unit 34 subtracts the fetched data length 45E from the remaining data length 45D of the CPU 31, and updates and registers the subtraction result in the update register 43 as the remaining data length 45D. As a result, the arbitrating unit 34 can recognize the CPU 31 that has completed the arithmetic processing with reference to the remaining data length 45D. And the overhead between CPU31 regarding a calculation process can be reduced.
　上記実施例では、スマートフォン等の無線部を備えた端末装置を例示したが、無線部に限定されるものではなく、有線の通信部を備えた端末装置等にも適用可能である。また、無線部や通信部等の通信機能を内蔵しない情報処理装置にも適用可能である。上記実施例では、ハードウェア構成の複数のＣＰＵを内蔵したシステムＬＳＩを例示したが、ソフトウェア的に複数の仮想ＣＰＵをメモリ上に展開するシステムＬＳＩにも適用可能である。 In the above embodiment, a terminal device including a wireless unit such as a smartphone is illustrated, but the present invention is not limited to the wireless unit, and can be applied to a terminal device including a wired communication unit. The present invention is also applicable to an information processing apparatus that does not incorporate a communication function such as a wireless unit or a communication unit. In the above embodiment, a system LSI having a plurality of CPUs with a hardware configuration is illustrated. However, the present invention can also be applied to a system LSI in which a plurality of virtual CPUs are developed on a memory.
　また、図示した各部の各構成要素は、必ずしも物理的に図示の如く構成されていることを要しない。すなわち、各部の分散・統合の具体的形態は図示のものに限られず、その全部又は一部を、各種の負荷や使用状況等に応じて、任意の単位で機能的又は物理的に分散・統合して構成することができる。 In addition, each component of each part illustrated does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each part is not limited to the one shown in the figure, and all or a part thereof may be functionally or physically distributed / integrated in arbitrary units according to various loads and usage conditions. Can be configured.
　更に、各装置で行われる各種処理機能は、ＣＰＵ（又はＭＰＵ（Micro　Processing　Unit）、ＭＣＵ（Micro　Controller　Unit）等のマイクロ・コンピュータ）上で、その全部又は任意の一部を実行するようにしても良い。また、各種処理機能は、ＣＰＵ（又はＭＰＵ、ＭＣＵ等のマイクロ・コンピュータ）で解析実行するプログラム上、又はワイヤードロジックによるハードウェア上で、その全部又は任意の一部を実行するようにしても良いことは言うまでもない。 Furthermore, various processing functions performed in each device are executed on the CPU (or a micro computer such as MPU (Micro Processing Unit), MCU (Micro Controller Unit), etc.) or all of them. Also good. Various processing functions may be executed entirely or arbitrarily on a program that is analyzed and executed by a CPU (or a microcomputer such as an MPU or MCU) or hardware based on wired logic. Needless to say.
　ところで、本実施例で説明した各種の処理は、予め用意されたプログラムを情報処理装置内のＣＰＵ等のプロセッサで実行させることによって実現できる。そこで、以下では、上記実施例と同様の機能を有するプログラムを実行する情報処理装置の一例を説明する。図１２は、演算処理制御プログラムを実行する情報処理装置の一例を示す説明図である。 By the way, various processes described in the present embodiment can be realized by executing a prepared program by a processor such as a CPU in the information processing apparatus. Therefore, in the following, an example of an information processing apparatus that executes a program having the same function as in the above embodiment will be described. FIG. 12 is an explanatory diagram illustrating an example of an information processing apparatus that executes an arithmetic processing control program.
　図１２に示す演算処理制御プログラムを実行する情報処理装置１００は、複数のプロセッサ１１０と、ＲＯＭ１２０と、ＲＡＭ１３０と、ＣＰＵ１４０とを有する。更に、複数のプロセッサ１１０、ＲＯＭ１２０、ＲＡＭ１３０及びＣＰＵ１４０は、バス１５０を介して接続される。 The information processing apparatus 100 that executes the arithmetic processing control program shown in FIG. 12 includes a plurality of processors 110, a ROM 120, a RAM 130, and a CPU 140. Further, the plurality of processors 110, the ROM 120, the RAM 130, and the CPU 140 are connected via a bus 150.
　そして、ＲＯＭ１２０には、上記実施例と同様の機能を発揮する演算処理制御プログラムが予め記憶されている。ＲＯＭ１２０は、演算処理制御プログラムとして提供プログラム１２０Ａ、第１の加算プログラム１２０Ｂ及び第２の加算プログラム１２０Ｃが記憶されている。尚、ＲＯＭ１２０ではなく、図示せぬドライブでコンピュータ読取可能な記録媒体に演算処理制御プログラムが記録されていても良い。また、記録媒体としては、例えば、ＣＤ－ＲＯＭ、ＤＶＤディスク、ＵＳＢメモリ等の可搬型記録媒体、フラッシュメモリ等の半導体メモリ等でも良い。 The ROM 120 stores in advance an arithmetic processing control program that exhibits the same function as in the above embodiment. The ROM 120 stores a provision program 120A, a first addition program 120B, and a second addition program 120C as arithmetic processing control programs. Note that the arithmetic processing control program may be recorded not on the ROM 120 but on a computer-readable recording medium using a drive (not shown). The recording medium may be, for example, a portable recording medium such as a CD-ROM, a DVD disk, or a USB memory, or a semiconductor memory such as a flash memory.
　そして、ＣＰＵ１４０は、提供プログラム１２０ＡをＲＯＭ１２０から読み出して提供プロセス１４０Ａとして機能する。ＣＰＵ１４０は、第１の加算プログラム１２０ＢをＲＯＭ１２０から読み出して第１の加算プロセス１４０Ｂとして機能する。ＣＰＵ１４０は、第２の加算プログラム１２０ＣをＲＯＭ１２０から読み出して第２の加算プロセス１４０Ｃとして機能する。ＲＡＭ１３０は、プロセッサ１１０毎に、プロセッサ１１０に実行させる処理の演算元データを格納する第１の格納先を示す第１のポインタ及び、プロセッサに実行させる演算元データの演算結果を格納する第２の格納先を示す第２のポインタを記憶する。 Then, the CPU 140 reads the provision program 120A from the ROM 120 and functions as the provision process 140A. The CPU 140 reads the first addition program 120B from the ROM 120 and functions as the first addition process 140B. The CPU 140 reads the second addition program 120C from the ROM 120 and functions as the second addition process 140C. The RAM 130 stores, for each processor 110, a first pointer that indicates a first storage destination that stores operation source data of processing to be executed by the processor 110, and a second result that stores an operation result of operation source data to be executed by the processor. A second pointer indicating the storage destination is stored.
　ＣＰＵ１４０は、各プロセッサ１１０が実行する処理に関わる第１のポインタ及び第２のポインタを当該プロセッサ１１０に提供する。ＣＰＵ１４０は、プロセッサ１１０が当該プロセッサ１１０対応の第１の格納先から演算元データを取り出した場合に当該第１のポインタに演算元データの取出しデータ長を加算し、その加算結果を当該プロセッサ１１０の第１のポインタとして更新登録する。ＣＰＵ１４０は、プロセッサ１１０が演算元データに対する演算結果を当該プロセッサ１１０対応の第２の格納先に格納した場合に当該第２のポインタに演算結果の格納データ長を加算し、その加算結果を当該プロセッサ１１０の第２のポインタとして更新登録する。その結果、演算処理に関わるプロセッサ１１０間のオーバーヘッドを低減できる。 The CPU 140 provides the processor 110 with a first pointer and a second pointer related to processing executed by each processor 110. When the processor 110 fetches the operation source data from the first storage destination corresponding to the processor 110, the CPU 140 adds the extraction data length of the operation source data to the first pointer, and the addition result is added to the processor 110. Update registration as the first pointer. When the processor 110 stores the calculation result for the calculation source data in the second storage destination corresponding to the processor 110, the CPU 140 adds the storage data length of the calculation result to the second pointer, and adds the addition result to the processor. The update is registered as the second pointer 110. As a result, the overhead between the processors 110 related to the arithmetic processing can be reduced.
　１　端末装置
　２２　アプリ部
　３１　ＣＰＵ
　３４　調停部
　４１　演算元レジスタ
　４２　演算結果レジスタ
　４３　更新レジスタ
　５１　第１の加算部
　５２　減算部
　５３　第２の加算部 1 Terminal Device 22 Application Unit 31 CPU
34 Arbitration unit 41 Calculation source register 42 Calculation result register 43 Update register 51 First addition unit 52 Subtraction unit 53 Second addition unit

Claims (5)

  1. 　演算処理を分割した複数の処理を複数のプロセッサに分散して実行させる演算処理装置であって、
    　前記プロセッサ毎に、当該プロセッサに実行させる前記処理の演算元データを格納する第１の格納先を示す第１のポインタ及び、当該プロセッサに実行させる前記演算元データの演算結果を格納する第２の格納先を示す第２のポインタを記憶すると共に、各プロセッサが実行する処理に関わる前記第１のポインタ及び前記第２のポインタを当該プロセッサに提供する記憶部と、
    　前記プロセッサが当該プロセッサ対応の前記第１の格納先から前記演算元データを取り出した場合に当該第１のポインタに前記演算元データの取出しデータ長を加算し、その加算結果を当該プロセッサの前記第１のポインタとして更新登録する第１の加算部と、
    　前記プロセッサが前記演算元データに対する前記演算結果を当該プロセッサ対応の前記第２の格納先に格納した場合に当該第２のポインタに前記演算結果の格納データ長を加算し、その加算結果を当該プロセッサの前記第２のポインタとして更新登録する第２の加算部と
    　を有することを特徴とする演算処理装置。     An arithmetic processing device that distributes and executes a plurality of processes obtained by dividing an arithmetic process on a plurality of processors,
    For each of the processors, a first pointer that indicates a first storage destination that stores operation source data of the processing to be executed by the processor and a second result that stores an operation result of the operation source data to be executed by the processor. A storage unit that stores a second pointer indicating a storage destination, and provides the first pointer and the second pointer related to processing executed by each processor to the processor;
    When the processor extracts the calculation source data from the first storage destination corresponding to the processor, the extraction data length of the calculation source data is added to the first pointer, and the addition result is added to the first of the processor. A first addition unit that is updated and registered as a pointer of 1,
    When the processor stores the calculation result for the calculation source data in the second storage destination corresponding to the processor, the storage data length of the calculation result is added to the second pointer, and the addition result is added to the processor. And a second addition unit that updates and registers the second pointer as the second pointer.
  2. 　前記記憶部は、
    　前記プロセッサ毎に、当該プロセッサが演算処理中であるか否かを示す状態情報を記憶し、
    　前記プロセッサが演算処理の完了を検出した場合に、当該プロセッサの演算処理の完了を前記記憶部内の当該プロセッサの状態情報として更新登録する更新部を有することを特徴とする請求項１に記載の演算処理装置。     The storage unit
    For each processor, state information indicating whether or not the processor is processing is stored,
    2. The calculation according to claim 1, further comprising: an update unit configured to update and register completion of calculation processing of the processor as state information of the processor in the storage unit when the processor detects completion of calculation processing. Processing equipment.
  3. 　演算処理を分割した複数の処理を分散して実行する複数のプロセッサと、複数のプロセッサと通信する調停部とを有し、
    　前記調停部は、
    　前記プロセッサ毎に、当該プロセッサに実行させる前記処理の演算元データを格納する第１の格納先を示す第１のポインタ及び、当該プロセッサに実行させる前記演算元データの演算結果を格納する第２の格納先を示す第２のポインタを記憶すると共に、各プロセッサが実行する処理に関わる前記第１のポインタ及び前記第２のポインタを当該プロセッサに提供する記憶部と、
    　前記プロセッサが当該プロセッサ対応の前記第１の格納先から前記演算元データを取り出した場合に当該第１のポインタに前記演算元データの取出しデータ長を加算し、その加算結果を当該プロセッサの前記第１のポインタとして更新登録する第１の加算部と、
    　前記プロセッサが前記演算元データに対する前記演算結果を当該プロセッサ対応の前記第２の格納先に格納した場合に当該第２のポインタに前記演算結果の格納データ長を加算し、その加算結果を当該プロセッサの前記第２のポインタとして更新登録する第２の加算部と
    　を有することを特徴とする演算処理装置。     A plurality of processors that distribute and execute a plurality of processes obtained by dividing the arithmetic processing; and an arbitration unit that communicates with the plurality of processors;
    The mediation unit
    For each of the processors, a first pointer that indicates a first storage destination that stores operation source data of the processing to be executed by the processor and a second result that stores an operation result of the operation source data to be executed by the processor. A storage unit that stores a second pointer indicating a storage destination, and provides the first pointer and the second pointer related to processing executed by each processor to the processor;
    When the processor extracts the calculation source data from the first storage destination corresponding to the processor, the extraction data length of the calculation source data is added to the first pointer, and the addition result is added to the first of the processor. A first addition unit that is updated and registered as a pointer of 1,
    When the processor stores the calculation result for the calculation source data in the second storage destination corresponding to the processor, the storage data length of the calculation result is added to the second pointer, and the addition result is added to the processor. And a second addition unit that updates and registers the second pointer as the second pointer.
  4. 　演算処理を分割した複数の処理を複数のプロセッサに分散して実行させる演算処理装置が実行する演算処理制御方法であって、
    　前記演算処理装置が、
    　前記プロセッサ毎に、当該プロセッサに実行させる前記処理の演算元データを格納する第１の格納先を示す第１のポインタ及び、当該プロセッサに実行させる前記演算元データの演算結果を格納する第２の格納先を示す第２のポインタを記憶部に記憶し、
    　各プロセッサが実行する処理に関わる前記第１のポインタ及び前記第２のポインタを当該プロセッサに提供し、
    　前記プロセッサが当該プロセッサ対応の前記第１の格納先から前記演算元データを取り出した場合に当該第１のポインタに前記演算元データの取出しデータ長を加算し、その加算結果を当該プロセッサの前記第１のポインタとして更新登録し、
    　前記プロセッサが前記演算元データに対する前記演算結果を当該プロセッサ対応の前記第２の格納先に格納した場合に当該第２のポインタに前記演算結果の格納データ長を加算し、その加算結果を当該プロセッサの前記第２のポインタとして更新登録する
    　処理を実行することを特徴とする演算処理制御方法。     An arithmetic processing control method executed by an arithmetic processing device that distributes and executes a plurality of processes obtained by dividing an arithmetic process among a plurality of processors,
    The arithmetic processing unit is
    For each of the processors, a first pointer that indicates a first storage destination that stores operation source data of the processing to be executed by the processor and a second result that stores an operation result of the operation source data to be executed by the processor. Storing a second pointer indicating a storage destination in the storage unit;
    Providing the first pointer and the second pointer related to processing executed by each processor to the processor;
    When the processor extracts the calculation source data from the first storage destination corresponding to the processor, the extraction data length of the calculation source data is added to the first pointer, and the addition result is added to the first of the processor. Register as a pointer to 1,
    When the processor stores the calculation result for the calculation source data in the second storage destination corresponding to the processor, the storage data length of the calculation result is added to the second pointer, and the addition result is added to the processor. An arithmetic processing control method characterized by executing a process of updating and registering as the second pointer.
  5. 　演算処理を分割した複数の処理を複数のプロセッサに分散して実行させるコンピュータに、
    　前記プロセッサ毎に、当該プロセッサに実行させる前記処理の演算元データを格納する第１の格納先を示す第１のポインタ及び、当該プロセッサに実行させる前記演算元データの演算結果を格納する第２の格納先を示す第２のポインタを記憶部に記憶し、
    　各プロセッサが実行する処理に関わる前記第１のポインタ及び前記第２のポインタを当該プロセッサに提供し、
    　前記プロセッサが当該プロセッサ対応の前記第１の格納先から前記演算元データを取り出した場合に当該第１のポインタに前記演算元データの取出しデータ長を加算し、その加算結果を当該プロセッサの前記第１のポインタとして更新登録し、
    　前記プロセッサが前記演算元データに対する前記演算結果を当該プロセッサ対応の前記第２の格納先に格納した場合に当該第２のポインタに前記演算結果の格納データ長を加算し、その加算結果を当該プロセッサの前記第２のポインタとして更新登録する
    　処理を実行させることを特徴とする演算処理制御プログラム。     A computer that distributes and executes a plurality of processes obtained by dividing an arithmetic process on a plurality of processors,
    For each of the processors, a first pointer that indicates a first storage destination that stores operation source data of the processing to be executed by the processor and a second result that stores an operation result of the operation source data to be executed by the processor. Storing a second pointer indicating a storage destination in the storage unit;
    Providing the first pointer and the second pointer related to processing executed by each processor to the processor;
    When the processor extracts the calculation source data from the first storage destination corresponding to the processor, the extraction data length of the calculation source data is added to the first pointer, and the addition result is added to the first of the processor. Register as a pointer to 1,
    When the processor stores the calculation result for the calculation source data in the second storage destination corresponding to the processor, the storage data length of the calculation result is added to the second pointer, and the addition result is added to the processor. An arithmetic processing control program that executes a process of updating and registering as the second pointer.
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Citations (2)

* Cited by examiner, † Cited by third party
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WO2009096029A1 (en) * 2008-01-31 2009-08-06 Fujitsu Limited Packet processing device and packet processing program
JP2016024578A (en) * 2014-07-18 2016-02-08 富士通株式会社 Information processing apparatus, control method thereof, and control program thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096029A1 (en) * 2008-01-31 2009-08-06 Fujitsu Limited Packet processing device and packet processing program
JP2016024578A (en) * 2014-07-18 2016-02-08 富士通株式会社 Information processing apparatus, control method thereof, and control program thereof

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