WO2018163897A1 - Scan signal line driving circuit and display device provided therewith - Google Patents

Scan signal line driving circuit and display device provided therewith Download PDF

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Publication number
WO2018163897A1
WO2018163897A1 PCT/JP2018/007111 JP2018007111W WO2018163897A1 WO 2018163897 A1 WO2018163897 A1 WO 2018163897A1 JP 2018007111 W JP2018007111 W JP 2018007111W WO 2018163897 A1 WO2018163897 A1 WO 2018163897A1
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Prior art keywords
node
terminal
conduction terminal
transistor
output
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PCT/JP2018/007111
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French (fr)
Japanese (ja)
Inventor
泰章 岩瀬
卓哉 渡部
晶 田川
洋平 竹内
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シャープ株式会社
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Priority to JP2017041477 priority
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Publication of WO2018163897A1 publication Critical patent/WO2018163897A1/en

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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Abstract

The present invention has the purpose of implementing a gate driver (scan signal line driving circuit) which is capable of sufficiently securing a charging time with low power consumption. A reset signal (R) is provided to a control terminal of a thin film transistor (T02) for turning off a gate output, wherein a voltage level of the reset signal becomes a voltage level (Vgh2) of a high-level voltage of a gate clock signal (GCK), when the thin film transistor (T02) is to be turned on. Here, "a difference between the voltage level (Vgh2) of the high-level voltage of the gate clock signal (GCK) and a voltage level (Vg1) of a low-level voltage of the gate clock signal (GCK)" is made larger than "a difference between a voltage level (Vgh) of a DC power supply voltage (VDD) (given to a gate bus line (GL) being in a selection state) and the voltage level (Vg1) of the low-level voltage of the gate clock signal (GCK)".

Description

Scanning signal line driving circuit and display device including the same

The present invention relates to a display device, and more particularly to a scanning signal line driving circuit for driving a gate bus line (scanning signal line) disposed in a display unit of the display device.

Conventionally, a liquid crystal display device having a display unit including a plurality of source bus lines (video signal lines) and a plurality of gate bus lines (scanning signal lines) is known. In such a liquid crystal display device, a pixel formation portion for forming a pixel is provided at the intersection of the source bus line and the gate bus line. Each pixel forming portion includes a thin film transistor (pixel TFT) that is a switching element having a gate terminal connected to a gate bus line passing through a corresponding intersection and a source terminal connected to a source bus line passing through the intersection. The pixel capacity for holding the voltage value is included. The liquid crystal display device is also provided with a gate driver (scanning signal line driving circuit) for driving the gate bus line and a source driver (video signal line driving circuit) for driving the source bus line.

The video signal indicating the pixel voltage value is transmitted through the source bus line. However, each source bus line cannot transmit video signals indicating pixel voltage values for a plurality of rows at a time (simultaneously). For this reason, video signal writing (charging) to the pixel capacitors in the plurality of pixel formation portions provided in the display portion is sequentially performed row by row. Therefore, the gate driver is constituted by a shift register having a plurality of stages so that a plurality of gate bus lines are sequentially selected for a predetermined period. Then, by sequentially outputting active scanning signals from each stage of the shift register, writing of video signals to the pixel capacitors is sequentially performed row by row as described above. In the present specification, a circuit constituting each stage of the shift register is referred to as a “unit circuit”.

The shift register that constitutes the gate driver operates based on a multi-phase clock signal called a “gate clock signal”. In this regard, hereinafter, a gate clock signal as a generic term of the clock signals of the plurality of phases will be denoted by a symbol GCK, and a gate clock signal input to the unit circuit among the clock signals of the plurality of phases will be denoted by a symbol GCKin. Attached.

By the way, conventionally, the gate driver is often mounted as an IC (Integrated Circuit) chip around the periphery of the substrate constituting the liquid crystal panel. However, in recent years, gate drivers are often formed directly on a substrate. Such a gate driver is called a “monolithic gate driver”.

The configuration of a conventional PowerClock monolithic gate driver (hereinafter referred to as “first conventional example”) is disclosed in, for example, Japanese Patent No. 5318117. According to the first conventional example, as shown in FIG. 30, a gate clock signal GCKin is given to one conduction terminal of a thin film transistor T901 called a buffer TFT provided for driving a gate load (thin film transistor The other conduction terminal of T901 is connected to the gate bus line GL). Since such a configuration is employed, a relatively large capacity needs to be driven by the gate clock signal GCKin which is an AC signal. Therefore, according to the first conventional example, power consumption increases.

Therefore, in Japanese Patent No. 5405570, as shown in FIG. 31, a high-level DC power supply voltage VDD is applied to one conduction terminal of a thin film transistor T911 called a buffer TFT (hereinafter referred to as “ It is referred to as “second conventional example”). According to the second conventional example, since the gate load is driven by the high-level DC power supply voltage VDD, the capacity that needs to be driven by the gate clock signal GCKin is reduced. As a result, power consumption is reduced compared to the first conventional example.

Japanese Patent No. 5318117 Specification Japanese Patent No. 5405570 Specification

As described above, according to the second conventional example, a monolithic gate driver having low power consumption is realized. However, according to the second conventional example, the time required for rising and falling of the scanning signal output to the gate bus line GL becomes relatively long. For this reason, in particular, when a panel that performs high-speed driving or a high-definition panel is employed, it is not possible to ensure sufficient time for charging the pixel capacitance. This will be described below with reference to FIG.

FIG. 32 is a diagram for comparing the waveform of the gate output (the voltage of the scanning signal output from the gate driver) between the first conventional example and the second conventional example. In FIG. 32, the waveform of the gate clock signal GCK is represented by a solid line denoted by reference numeral 91, the waveform of the gate output in the first conventional example is represented by a thick solid line denoted by reference numeral 92, and the gate output in the second conventional example is shown. The waveform is represented by a thick dotted line denoted by reference numeral 93. From FIG. 32, it is understood that both the rise time of the gate output and the fall time of the gate output are longer in the second conventional example than in the first conventional example. The reason for this is as follows. In the first conventional example, when the gate output is lowered, the gate clock signal GCKin changes from the high level to the low level, so that charges are extracted from the gate bus line GL to the input terminal for the gate clock signal GCKin. . On the other hand, in the second conventional example, when the reset signal R applied to the control terminal of the thin film transistor T912 (see FIG. 31) provided for lowering the gate output is lowered when the gate output is lowered. When the thin film transistor T912 is turned on from the low level to the high level, the charge is extracted from the gate bus line GL to the input terminal for the low-level DC power supply voltage VSS. That is, in the second conventional example, the gate output falls after the rising edge of the reset signal R, so that a delay occurs in the fall of the gate output as compared with the first conventional example. Note that, in the first conventional example, as in the second conventional example, electric charges are also drawn from the gate bus line GL to the input terminal for the DC power supply voltage VSS.

As described above, according to the first conventional example, the charging time of the pixel capacity is sufficiently ensured, but the power consumption increases. On the other hand, according to the second conventional example, power consumption is reduced, but a sufficient charging time for the pixel capacity cannot be secured.

Therefore, an object of the present invention is to realize a gate driver (scanning signal line driving circuit) that can secure a sufficient charging time with low power consumption.

According to a first aspect of the present invention, a display unit of a display device includes a shift register including a plurality of unit circuits that operate based on a plurality of clock signals that are switched between a first level voltage and a second level voltage. A scanning signal line driving circuit for driving a plurality of arranged scanning signal lines,
Each unit circuit is
A first output node that outputs a first output signal to be applied to a corresponding scanning signal line;
A second output node that outputs a second output signal for controlling the operation of another unit circuit;
Selection control having a control terminal, a first conduction terminal to which a selection level voltage, which is a DC voltage to be supplied to the scanning signal line to be selected, is provided, and a second conduction terminal connected to the first output node. A transistor,
A control terminal to which a second output signal output from the second output node of the subsequent unit circuit is applied as a reset signal, a first conduction terminal connected to the first output node, and a scanning signal line to be in a non-selected state A non-selection control transistor having a second conduction terminal to which a non-selection level voltage which is a DC voltage to be supplied to
The second output signal output from the second output node of each unit circuit is the first level voltage during a period in which the corresponding scanning signal line is to be maintained in the selected state,
The non-selection control transistor is turned on when the reset signal is the first level voltage,
The plurality of unit circuits are connected to each other so that a reset signal applied to a control terminal of a non-selection control transistor included in a unit circuit corresponding to a scanning signal line to be in a non-selected state becomes the first level voltage,
The difference between the first level voltage and the second level voltage is greater than the difference between the selection level voltage and the second level voltage.

According to a second aspect of the present invention, in the first aspect of the present invention,
Each unit circuit is
A first node connected to a control terminal of the selection control transistor;
An output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second output node;
A non-output control transistor having a control terminal to which the reset signal is applied, a first conduction terminal connected to the second output node, and a second conduction terminal to which the non-selection level voltage is applied;
A first node for receiving the second output signal output from the second output node of the unit circuit of the preceding stage as a set signal and changing the potential of the first node toward the on level based on the set signal A turn-on transistor;
A first first-node turn-off transistor having a control terminal, a first conduction terminal connected to the first node, and a second conduction terminal to which the non-selection level voltage is applied;
A second node connected to a control terminal of the first first node turn-off transistor;
A second node turn-on transistor for maintaining the second node potential at an on level during a period in which the first node potential is to be maintained at an off level;
A second node turn-off transistor having a control terminal connected to the first node, a first conduction terminal connected to the second node, and a second conduction terminal to which the non-selection level voltage is applied; It is characterized by including.

According to a third aspect of the present invention, in the second aspect of the present invention,
Each unit circuit is
A second first-node turn-off transistor having a control terminal to which the reset signal is applied, a first conduction terminal connected to the first node, and a second conduction terminal to which the non-selection level voltage is applied;
A first output node turn-off transistor having a control terminal connected to the second node, a first conduction terminal connected to the first output node, and a second conduction terminal to which the non-selection level voltage is applied; ,
A second output node turn-off transistor having a control terminal connected to the second node, a first conduction terminal connected to the second output node, and a second conduction terminal to which the non-selection level voltage is applied; Is further included.

According to a fourth aspect of the present invention, in the third aspect of the present invention,
Each unit circuit is
A third node;
A capacitive element having one end connected to the first node and the other end connected to the third node;
A control terminal to which a clock signal applied to the first conduction terminal of the output control transistor is applied, a first conduction terminal to which the selection level voltage is applied, and a second conduction terminal connected to the third node. A three-node turn-on transistor;
And a third node turn-off transistor having a control terminal to which the set signal is applied, a first conduction terminal connected to the third node, and a second conduction terminal to which the non-selection level voltage is applied. It is characterized by.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
The first node turn-on transistor has a control terminal to which the set signal is applied and a first conduction terminal, and a second conduction terminal connected to the first node,
The second node turn-on transistor has a control terminal to which a clock signal applied to the first conduction terminal of the output control transistor is applied, a first conduction terminal, and a second conduction terminal connected to the second node. It is characterized by that.

The sixth aspect of the present invention is the fourth aspect of the present invention,
The first node turn-on transistor has a control terminal to which the set signal is applied, a first conduction terminal to which the first level voltage is applied, and a second conduction terminal connected to the first node,
The second node turn-on transistor has a control terminal to which the first level voltage is applied and a first conduction terminal, and a second conduction terminal connected to the second node.

According to a seventh aspect of the present invention, in the third aspect of the present invention,
Each unit circuit further includes a capacitive element having one end connected to the first node and the other end connected to the second output node.

The eighth aspect of the present invention is the seventh aspect of the present invention,
The first node turn-on transistor has a control terminal to which the set signal is applied and a first conduction terminal, and a second conduction terminal connected to the first node,
The second node turn-on transistor has a control terminal to which a clock signal applied to the first conduction terminal of the output control transistor is applied, a first conduction terminal, and a second conduction terminal connected to the second node. It is characterized by that.

According to a ninth aspect of the present invention, in a seventh aspect of the present invention,
The first node turn-on transistor has a control terminal to which the set signal is applied, a first conduction terminal to which the first level voltage is applied, and a second conduction terminal connected to the first node,
The second node turn-on transistor has a control terminal to which the first level voltage is applied and a first conduction terminal, and a second conduction terminal connected to the second node.

According to a tenth aspect of the present invention, in the first aspect of the present invention,
The plurality of scanning signal lines are driven so that a scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are maintained in a non-selected state appear alternately. It can be done.

An eleventh aspect of the present invention is the tenth aspect of the present invention,
The selection control transistor and the non-selection control transistor have a characteristic that current does not flow between the first conduction terminal and the second conduction terminal when the voltage between the control terminal and the second conduction terminal is 0.
The selection level voltage is applied to the first conduction terminal of the selection control transistor throughout the scanning period and the rest period.

The twelfth aspect of the present invention is the tenth aspect of the present invention,
The selection control transistor and the non-selection control transistor have a characteristic of flowing a current between the first conduction terminal and the second conduction terminal when the voltage between the control terminal and the second conduction terminal is 0.
In the idle period, the non-selection level voltage or the second level voltage is supplied to the first conduction terminal of the selection control transistor instead of the selection level voltage.

A thirteenth aspect of the present invention is the first aspect of the present invention,
The selection control transistor and the non-selection control transistor are n-channel thin film transistors,
The first level voltage is higher than the second level voltage;
The selection level voltage is higher than the non-selection level voltage;
The first level voltage is higher than the selection level voltage.

A fourteenth aspect of the present invention is a display device,
The scanning signal line driving circuit according to the first aspect of the present invention is provided.

According to the first aspect of the present invention, a scanning signal having a shift register comprising a plurality of unit circuits that operate based on a plurality of clock signals that are switched between a first level voltage and a second level voltage. In the line drive circuit, the on / off state of the non-selection control transistor provided in each unit circuit for bringing the scanning signal line into the non-selected state is a reset that is a second output signal output from the unit circuit at the subsequent stage. Controlled by signal. The second output signal becomes the first level voltage during the period in which the corresponding scanning signal line is to be maintained in the selected state. Here, since the “difference between the first level voltage and the second level voltage” is larger than the “difference between the selection level voltage and the second level voltage”, the non-selection control transistor is changed from the off state to the on state. At this time, the voltage of the reset signal applied to the control terminal of the non-selected control transistor changes at a faster speed than in the prior art. As a result, the time required for the scanning signal line to change from the selected state to the non-selected state is shorter than in the past. Thereby, even when a panel that performs high-speed driving or a high-definition panel is employed, a sufficient charging time for the pixel capacitance is ensured. In addition, since a configuration in which the scanning signal line is driven by a DC voltage (a configuration in which a DC voltage is applied to the first conduction terminal of the selection control transistor) is employed, power consumption is low. As described above, a scanning signal line driving circuit that can secure a sufficient charging time with low power consumption is realized.

According to the second aspect of the present invention, in the shift register configured to output the first output signal given to the scanning signal line from each unit circuit and the second output signal given to the other unit circuit, Shift operation is performed.

According to the third aspect of the present invention, when the scanning signal line is changed from the selected state to the non-selected state, the potentials of the first node, the first output node, and the second output node are quickly turned off from the on level. The level can be changed. Thereby, occurrence of malfunction is suppressed.

According to the fourth to ninth aspects of the present invention, when the scanning signal line is changed from the non-selected state to the selected state, the potential of the first node is changed to a sufficient on level via the capacitive element. It becomes possible.

According to the tenth to twelfth aspects of the present invention, since so-called sleep driving is performed, it is possible to sufficiently ensure the charging time while further reducing power consumption.

According to the thirteenth aspect of the present invention, the effect of the first aspect of the present invention can be obtained in the configuration using the n-channel thin film transistor.

According to the fourteenth aspect of the present invention, a display device including a scanning signal line drive circuit that achieves the effects of the first aspect of the present invention is realized.

It is a figure for demonstrating the characteristic common to all embodiment of this invention. 1 is a block diagram illustrating an overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. FIG. 3 is a block diagram for explaining a configuration of a gate driver in the first embodiment. FIG. 3 is a block diagram showing a configuration of a shift register in a gate driver in the first embodiment. FIG. 6 is a signal waveform diagram for describing an operation of a gate driver in the first embodiment. FIG. 6 is a diagram for describing input / output signals of each unit circuit of the shift register in the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a unit circuit (a configuration of one stage of a shift register) in the first embodiment. FIG. 6 is a signal waveform diagram for describing an operation of a unit circuit in the first embodiment. It is a figure for comparing the waveform of a gate output with the said 1st Embodiment and a 2nd prior art example. In the said 1st Embodiment, it is a figure for demonstrating the result of simulation. In the said 1st Embodiment, it is a figure for demonstrating the result of simulation. In the said 1st Embodiment, it is a figure for demonstrating the result of simulation. In the said 1st Embodiment, it is a figure for demonstrating the result of simulation. FIG. 10 is a block diagram showing a configuration of a shift register in a gate driver in a modification of the first embodiment. FIG. 10 is a signal waveform diagram for describing an operation of a gate driver in a modification of the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a unit circuit (a configuration of one stage of a shift register) in a modification of the first embodiment. FIG. 6 is a circuit diagram showing a configuration of a unit circuit (a configuration of one stage of a shift register) in a second embodiment of the present invention. FIG. 10 is a signal waveform diagram for describing an operation of a unit circuit in the second embodiment. In the said 2nd Embodiment, it is a figure for demonstrating the result of simulation. In the said 2nd Embodiment, it is a figure for demonstrating the result of simulation. In the said 2nd Embodiment, it is a figure for demonstrating the result of simulation. FIG. 11 is a circuit diagram showing a configuration of a unit circuit (a configuration of one stage of a shift register) in a modification of the second embodiment. In the 3rd Embodiment of this invention, it is a signal waveform diagram of a drive signal when an operation mode is normal drive. In the said 3rd Embodiment, it is a signal waveform diagram of the drive signal when an operation mode is rest drive (when a thin-film transistor has the characteristic shown in FIG. 25). It is a figure which shows an example of the Vds-Ids characteristic of a thin-film transistor regarding the said 3rd Embodiment. FIG. 10 is a diagram showing another example of the Vds-Ids characteristics of the thin film transistor in the third embodiment. It is a figure for demonstrating the electric current which can flow in the unit circuit during an idle period regarding the said 3rd Embodiment. In the said 3rd Embodiment, it is a signal waveform diagram of a drive signal when an operation mode is rest drive (when a thin-film transistor has the characteristic shown in FIG. 26). It is a figure for demonstrating the case where the p channel type thin-film transistor is used. It is a circuit diagram for demonstrating the 1st prior art example. It is a circuit diagram for demonstrating the 2nd prior art example. It is a figure for comparing the waveform of a gate output with a 1st prior art example and a 2nd prior art example.

<0. Introduction>
Before describing embodiments of the present invention, items common to all embodiments will be described. In FIG. 1, the configuration in the vicinity of the output unit of one unit circuit included in the shift register configuring the gate driver is shown within a dotted line denoted by reference numeral 61. Near the output part of the unit circuit, a thin film transistor T01 called a buffer TFT for driving the gate load 6 and a thin film transistor T02 for lowering the gate output are provided. The thin film transistors T01 and T02 are n-channel type and have a control terminal, a first conduction terminal, and a second conduction terminal. For the thin film transistor T01, a high-level DC power supply voltage VDD is applied to the first conduction terminal, and the second conduction terminal is connected to the gate bus line GL. As for the thin film transistor T02, the reset signal R is given to the control terminal, the first conduction terminal is connected to the gate bus line GL, and the low-level DC power supply voltage VSS is given to the second conduction terminal. The reset signal R is a signal that is output from the subsequent unit circuit and that is the first level voltage during the period in which the gate bus line GL corresponding to the subsequent unit circuit is to be maintained in the selected state. is there.

As described above, the circuit configuration itself in the vicinity of the output unit of the unit circuit is the same as the configuration in the second conventional example described above. However, the high level voltage / low level voltage of the gate clock signal GCK, the DC power supply voltage VDD, and the voltage level of the DC power supply voltage VSS are as shown in the dotted line denoted by reference numeral 62 in FIG. That is, the voltage level Vgh2 of the high level voltage of the gate clock signal GCK is higher than the voltage level Vgh of the DC power supply voltage VDD. In other words, "the voltage level Vgh2 of the high level voltage of the gate clock signal GCK and the gate clock signal GCK rather than the" difference between the voltage level Vgh of the DC power supply voltage VDD and the voltage level Vgl of the low level voltage of the gate clock signal GCK ". The difference between the low level voltage and the voltage level Vgl ”is larger.

Based on the above points, embodiments of the present invention will be described. In the following description, the gate terminal (gate electrode) of the thin film transistor corresponds to the control terminal, the drain terminal (drain electrode) corresponds to the first conduction terminal, and the source terminal (source electrode) corresponds to the second conduction terminal. Corresponds to the terminal. In this regard, the higher of the drain and the source is generally called the drain, but in the description of this specification, one is defined as the drain and the other is defined as the source. The source potential may be higher.

<1. First Embodiment>
<1.1 Overall configuration and operation overview>
FIG. 2 is a block diagram showing the overall configuration of the active matrix liquid crystal display device according to the first embodiment of the present invention. As shown in FIG. 2, this liquid crystal display device is common to a power supply 100, a DC / DC converter 110, a display control circuit 200, a source driver (video signal line driving circuit) 300, and a gate driver (scanning signal line driving circuit) 400. An electrode driving circuit 500 and a display unit 600 are provided. In the present embodiment, the gate driver 400 and the display unit 600 are formed on the same substrate (TFT substrate which is one of the two substrates constituting the liquid crystal panel). That is, the gate driver 400 in this embodiment is a monolithic gate driver.

The display unit 600 includes a plurality (j) of source bus lines (video signal lines) SL1 to SLj, a plurality (i) of gate bus lines (scanning signal lines) GL1 to GLi, and a plurality of these. A plurality of (i × j) pixel forming portions provided corresponding to the intersections of the source bus lines SL1 to SLj and the plurality of gate bus lines GL1 to GLi are formed. The plurality of pixel forming portions are arranged in a matrix to form a pixel array. Each pixel forming portion includes a thin film transistor (TFT) 60 which is a switching element having a gate terminal connected to a gate bus line passing through a corresponding intersection and a source terminal connected to a source bus line passing through the intersection. A pixel electrode connected to the drain terminal of the thin film transistor 60, a common electrode Ec which is a common electrode provided in common to the plurality of pixel formation portions, and a pixel provided in common to the plurality of pixel formation portions. The liquid crystal layer is sandwiched between the electrode and the common electrode Ec. A pixel capacitor Cp is constituted by a liquid crystal capacitor formed by the pixel electrode and the common electrode Ec. Normally, an auxiliary capacitor is provided in parallel with the liquid crystal capacitor in order to hold the electric charge in the pixel capacitor Cp with certainty. However, since the auxiliary capacitor is not directly related to the present invention, its description and illustration are omitted. In the present embodiment, the thin film transistor 60 is an n-channel type.

By the way, as the thin film transistor 60, a thin film transistor (a-Si TFT) using amorphous silicon as a semiconductor layer, a thin film transistor using microcrystalline silicon as a semiconductor layer, a thin film transistor using an oxide semiconductor as a semiconductor layer (oxide TFT), A thin film transistor (LTPS-TFT) using low-temperature polysilicon for the semiconductor layer can be employed. As the oxide TFT, for example, a thin film transistor including an oxide semiconductor layer containing an In—Ga—Zn—O-based semiconductor (eg, indium gallium zinc oxide) can be used.

The power supply 100 supplies a predetermined power supply voltage to the DC / DC converter 110, the display control circuit 200, and the common electrode drive circuit 500. The DC / DC converter 110 generates DC voltages (DC power supply voltage VDD and DC power supply voltage VSS) for operating the source driver 300 and the gate driver 400 from the power supply voltage, and supplies them to the source driver 300 and the gate driver 400. Supply. The common electrode drive circuit 500 gives a common electrode drive voltage Vcom to the common electrode Ec.

The display control circuit 200 receives an image signal DAT and a timing signal group TG such as a horizontal synchronization signal and a vertical synchronization signal sent from the outside, and receives a digital video signal DV and a source start pulse for controlling image display on the display unit 600. A signal SSP, a source clock signal SCK, a latch strobe signal LS, a gate start pulse signal GSP, a gate end pulse signal GEP, and a gate clock signal GCK are output. In the present embodiment, the gate clock signal GCK is composed of a four-phase clock signal having a duty ratio of 1/2 (that is, 50%).

The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and drives the video signal S for driving to the source bus lines SL1 to SLj. (1) to S (j) are applied.

Based on the gate start pulse signal GSP, the gate end pulse signal GEP, and the gate clock signal GCK output from the display control circuit 200, the gate driver 400 generates each gate of the active scanning signals GOUT (1) to GOUT (i). The application to the bus lines GL1 to GLi is repeated with one vertical scanning period as a cycle. A detailed description of the gate driver 400 will be given later.

As described above, the driving video signals S (1) to S (j) are applied to the source bus lines SL1 to SLj, and the scanning signals GOUT (1) to GOUT (i) are applied to the gate bus lines GL1 to GLi. Is applied, an image based on the image signal DAT sent from the outside is displayed on the display unit 600.

<1.2 Gate driver>
<1.2.1 Overall Configuration and Operation of Shift Register>
Next, an outline of the configuration and operation of the gate driver 400 in this embodiment will be described with reference to FIGS. FIG. 3 is a block diagram for explaining the configuration of the gate driver 400 in the present embodiment. As shown in FIG. 3, the gate driver 400 includes a shift register 410 having a plurality of stages. In the display portion 600, a pixel matrix of i rows × j columns is formed, and each stage of the shift register 410 is provided so as to correspond to each row of the pixel matrix on a one-to-one basis. That is, the shift register 410 includes i unit circuits 4 (1) to 4 (i).

FIG. 4 is a block diagram showing the configuration of the shift register 410 in the gate driver 400. As described above, the shift register 410 includes i unit circuits 4 (1) to 4 (i). FIG. 4 shows unit circuits 4 (n−2) to 4 (n + 2) from the (n−2) th stage to the (n + 2) th stage. In the following, when it is not necessary to distinguish i unit circuits 4 (1) to 4 (i) from each other, the unit circuit is simply denoted by reference numeral 4. The gate clock signal GCK is composed of four-phase clock signals (gate clock signals GCK1, GCK1B, GCK2, and GCK2B). The gate start pulse signal GSP is composed of a first gate start pulse signal GSP1 and a second gate start pulse signal GSP2. The gate end pulse signal GEP is a first gate end pulse signal GEP1 and a second gate end. It consists of a pulse signal GEP2 (omitted in FIG. 4).

The signals given to the input terminals of each stage (each unit circuit 4) of the shift register 410 are as follows (see FIG. 4). With respect to the gate clock signal GCK, the gate clock signal GCK1 is supplied to the unit circuit 4 (n-2) at the (n-2) stage, and the unit circuit 4 (n-1) at the (n-1) stage is supplied to the unit circuit 4 (n-1). Is supplied with a gate clock signal GCK2, a gate clock signal GCK1B is supplied to the n-th unit circuit 4 (n), and a gate clock signal GCK2B is supplied to the (n + 1) -th unit circuit 4 (n + 1). . Such a configuration is repeated four stages through all stages of the shift register 410. As shown in FIG. 5, the gate clock signal GCK1 and the gate clock signal GCK1B are 180 degrees out of phase, and the gate clock signal GCK2 and the gate clock signal GCK2B are 180 degrees out of phase. The phase of GCK1 is advanced 90 degrees from the phase of the gate clock signal GCK2. For the unit circuit 4 (k) at an arbitrary stage (here, k-th stage), the output signal Q (k-2) output from the unit circuit 4 (k-2) two stages before is a set signal. An output signal Q (k + 2) that is given as S and output from the unit circuit 4 (k + 2) after two stages is given as the reset signal R (see FIG. 6). However, for the first stage unit circuit 4 (1), the first gate start pulse signal GSP1 is given as the set signal S, and for the second stage unit circuit 4 (2), the second gate start pulse signal is supplied. The signal GSP2 is given as the set signal S. For the unit circuit 4 (i-1) at the (i-1) th stage, the first gate end pulse signal GEP1 is given as the reset signal R, and for the unit circuit 4 (i) at the ith stage, The second gate end pulse signal GEP is given as the reset signal R. The DC power supply voltage VDD and the DC power supply voltage VSS are commonly applied to all the unit circuits 4 (1) to 4 (i).

Two signals (an output signal G and an output signal Q) are output from the output terminal of each stage (each unit circuit 4) of the shift register 410 (see FIGS. 4 and 6). An output signal G output from an arbitrary stage is applied to the gate bus line GL as a scanning signal GOUT. Further, an output signal Q output from an arbitrary stage (here, k-th stage) is given as a reset signal R to the unit circuit 4 (k-2) two stages before and as a set signal S, two stages. This is given to the later unit circuit 4 (k + 2).

In the above-described configuration, the first gate start pulse signal GSP1 as the set signal S is supplied to the first stage unit circuit 4 (1) of the shift register 410, and the second stage unit of the shift register 410 is supplied. When the pulse of the second gate start pulse signal GSP2 as the set signal S is given to the circuit 4 (2), it is included in the output signal Q output from each unit circuit 4 based on the clock operation of the gate clock signal GCK. Shift pulses are sequentially transferred from the first stage unit circuit 4 (1) to the i stage unit circuit 4 (i). In response to the transfer of the shift pulse, the output signal Q and the output signal G (scanning signal GOUT) output from each unit circuit 4 sequentially become high level. As a result, as shown in FIG. 5, scanning signals GOUT (1) to GOUT (i) that sequentially become high level (active) every predetermined period are applied to the gate bus lines GL1 to GLi in the display unit 600. That is, i gate bus lines GL1 to GLi are sequentially selected. After the scanning signal GOUT (i) becomes high level, the first gate end pulse signal GEP1 as the reset signal R is sent to the unit circuit 4 (i-1) in the (i-1) stage of the shift register 410. And a pulse of the second gate end pulse signal GEP2 as the reset signal R is given to the i-th unit circuit 4 (i) of the shift register 410. Thereby, the shift operation in the shift register 410 ends.

By the way, in the present embodiment, the voltage level Vgh2 of the high level voltage of the gate clock signal GCK (gate clock signals GCK1, GCK1B, GCK2, and GCK2B) is higher than the voltage level Vgh of the DC power supply voltage VDD. . The DC power supply voltage VSS and the low level voltage of the gate clock signal GCK have the same voltage level Vgl. The high level voltages of the gate start pulse signal GSP and the gate end pulse signal GEP are not particularly limited, but preferably have a voltage level Vgh2.

In the present embodiment, a four-phase clock signal having a duty ratio of 1/2 (that is, 50%) is used as the gate clock signal GCK. However, the present invention is not limited to this. When Za and Zb are integers and a Za phase clock signal having a duty ratio of Zb / Za is used, the output signal Q output from the unit circuit before the Zb stage is given as the set signal S for each stage. The output signal Q output from the unit circuit after the Zb stage may be provided as the reset signal R. For example, when a 6-phase clock signal having a duty ratio of 2/6 is used, an output signal Q output from the unit circuit two stages before is supplied as the set signal S for each stage, and two stages after The output signal Q output from the unit circuit may be given as the reset signal R. For example, when an 8-phase clock signal having a duty ratio of 4/8 is used, the output signal Q output from the unit circuit four stages before is supplied as the set signal S for each stage, and the four stages The output signal Q output from the subsequent unit circuit may be given as the reset signal R.

<1.2.2 Unit circuit configuration>
FIG. 7 is a circuit diagram showing the configuration of the unit circuit 4 in this embodiment (configuration of one stage of the shift register 410). As shown in FIG. 7, the unit circuit 4 includes 13 thin film transistors T11, T12, T13, T14, T15, T16, T17, T18, T19, T1A, T1B, T1C, and T1D, and one capacitor ( Capacitive element) C1. The unit circuit 4 has four input terminals 41 to 44 and two output terminals 48 and 49 in addition to the input terminal for the DC power supply voltage VSS. Here, the input terminal that receives the set signal S is denoted by reference numeral 41, the input terminal that receives the reset signal R is denoted by reference numeral 42, the input terminal that receives the gate clock signal GCKin is denoted by reference numeral 43, and direct current is received. An input terminal that receives the power supply voltage VDD is denoted by reference numeral 44. An output terminal for outputting the output signal G is denoted by reference numeral 48, and an output terminal for outputting the output signal Q is denoted by reference numeral 49. Note that the thin film transistors T11, T12, T13, T14, T15, T16, T17, T18, T19, T1A, T1B, T1C, and T1D in the unit circuit 4 are the thin film transistors 60 in the pixel forming unit 4 (see FIG. 2). ).

Next, the connection relationship between the components in the unit circuit 4 will be described. The gate terminal of the thin film transistor T11, the gate terminal of the thin film transistor T13, the drain terminal of the thin film transistor T15, the source terminal of the thin film transistor T16, the drain terminal of the thin film transistor T17, the gate terminal of the thin film transistor T19, and one end of the capacitor C1 are connected. A region (wiring) in which these are connected to each other is referred to as a “first node” for convenience. The first node is denoted by reference numeral N1. The gate terminal of the thin film transistor T17, the source terminal of the thin film transistor T18, the drain terminal of the thin film transistor T19, the gate terminal of the thin film transistor T1A, and the gate terminal of the thin film transistor T1B are connected to each other. A region (wiring) in which these are connected to each other is referred to as a “second node” for convenience. The second node is denoted by reference numeral N2. The source terminal of the thin film transistor T1C, the drain terminal of the thin film transistor T1D, and the other end of the capacitor C1 are connected to each other. A region (wiring) in which these are connected to each other is referred to as a “third node” for convenience. The third node is denoted by reference numeral N3.

As for the thin film transistor T11, the gate terminal is connected to the first node N1, the drain terminal is connected to the input terminal 44, and the source terminal is connected to the output terminal 48. As for the thin film transistor T12, the gate terminal is connected to the input terminal 42, the drain terminal is connected to the output terminal 48, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T13, the gate terminal is connected to the first node N1, the drain terminal is connected to the input terminal 43, and the source terminal is connected to the output terminal 49. As for the thin film transistor T14, the gate terminal is connected to the input terminal 42, the drain terminal is connected to the output terminal 49, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T15, the gate terminal is connected to the input terminal 42, the drain terminal is connected to the first node N1, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T16, the gate terminal and the drain terminal are connected to the input terminal 41 (that is, diode connection), and the source terminal is connected to the first node N1.

Regarding the thin film transistor T17, the gate terminal is connected to the second node N2, the drain terminal is connected to the first node N1, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T18, the gate terminal and the drain terminal are connected to the input terminal 43 (that is, diode connection), and the source terminal is connected to the second node N2. As for the thin film transistor T19, the gate terminal is connected to the first node N1, the drain terminal is connected to the second node N2, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T1A, the gate terminal is connected to the second node N2, the drain terminal is connected to the output terminal 48, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T1B, the gate terminal is connected to the second node N2, the drain terminal is connected to the output terminal 49, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T1C, the gate terminal is connected to the input terminal 43, the drain terminal is connected to the input terminal 44, and the source terminal is connected to the third node N3. As for the thin film transistor T1D, the gate terminal is connected to the input terminal 41, the drain terminal is connected to the third node N3, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. The capacitor C1 has one end connected to the first node N1 and the other end connected to the third node N3.

Next, the function of each component in the unit circuit 4 will be described. The thin film transistor T11 applies the DC power supply voltage VDD to the output terminal 48 when the potential of the first node N1 is at a high level. The thin film transistor T12 changes the output signal G toward the low level when the reset signal R is at the high level. The thin film transistor T13 applies the voltage of the gate clock signal GCKin to the output terminal 49 when the potential of the first node N1 is at a high level. The thin film transistor T14 changes the output signal Q toward the low level when the reset signal R is at the high level. The thin film transistor T15 changes the potential of the first node N1 toward the low level when the reset signal R is at the high level.

The thin film transistor T16 changes the potential of the first node N1 toward the high level when the set signal S is at the high level. The thin film transistor T17 changes the potential of the first node N1 toward the low level when the potential of the second node N2 is at the high level. The thin film transistor T18 changes the potential of the second node N2 toward the high level when the gate clock signal GCKin is at the high level. The thin film transistor T19 changes the potential of the second node N2 toward the low level when the potential of the first node N1 is at the high level. The thin film transistor T1A changes the output signal G toward the low level when the potential of the second node N2 is at the high level. The thin film transistor T1B changes the output signal Q toward the low level when the potential of the second node N2 is at the high level. The thin film transistor T1C changes the potential of the third node N3 toward the high level when the gate clock signal GCKin is at the high level. The thin film transistor T1D changes the potential of the third node N3 toward the low level when the set signal S is at the high level. The capacitor C1 functions as a bootstrap capacitor for raising the potential of the first node N1.

In this embodiment, the potential of the second node N2 is controlled by the thin film transistors T18 and T19 having the configuration shown in FIG. 7, but the present invention is not limited to this. During the period in which the potential of the first node N1 is to be maintained at the high level, the gate clock during the period in which the potential of the second node N2 is at the low level and the potential of the first node N1 is to be maintained at the low level. If the potential of the second node N2 is high during the period when the signal GCKin is high, the potential of the second node N2 is controlled by a configuration other than the configuration shown in FIG. Also good.

In this embodiment, a selection control transistor transistor is realized by the thin film transistor T11, a non-selection control transistor is realized by the thin film transistor T12, an output control transistor is realized by the thin film transistor T13, and a non-output control transistor is realized by the thin film transistor T14. A second first node turn-off transistor is realized by the thin film transistor T15, a first node turn-on transistor is realized by the thin film transistor T16, a first first node turn-off transistor is realized by the thin film transistor T17, and a first transistor is turned on by the thin film transistor T18. A two-node turn-on transistor is realized, and a second node turn-off transistor is formed by the thin film transistor T19. A first output node turn-off transistor is realized by the thin film transistor T1A, a second output node turn-off transistor is realized by the thin film transistor T1B, a third node turn-on transistor is realized by the thin film transistor T1C, and a first transistor is turned on by the thin film transistor T1D. A three-node turn-off transistor is realized. Further, a first output node is realized by the output terminal 48, and a second output node is realized by the output terminal 49.

<1.2.3 Unit circuit operation>
Next, the operation of the unit circuit 4 in the present embodiment will be described with reference to FIG. Here, the waveform delay is ignored.

Before the time point t11, the set signal S is low level, the potential of the first node N1 is low level, the potential of the second node N1 is high level, the potential of the third node N3 is high level, and the output signal Q is low The level, the output signal G is low level, and the reset signal R is low level. As for the gate clock signal GCKin, the high level and the low level are alternately repeated. Incidentally, the thin film transistor in the unit circuit 4 has a parasitic capacitance. For this reason, during the period before time t11, the potential of the first node N1 may fluctuate due to the clock operation of the gate clock signal GCKin and the presence of the parasitic capacitance of the thin film transistor T13 (see FIG. 7). Thereby, the voltage of the output signal G, that is, the voltage of the scanning signal GOUT applied to the gate bus line GL can be increased. However, the thin film transistor T17 is maintained in an on state during a period in which the potential of the second node N2 is maintained at a high level. Therefore, during the period before time t11, the thin film transistor T17 is maintained in the on state, and the potential of the first node N1 is reliably maintained at the low level. As described above, even if noise due to the clock operation of the gate clock signal GCKin is mixed into the first node N1, the voltage of the corresponding scanning signal GOUT does not increase. As a result, it is possible to prevent the occurrence of defects such as display defects due to the clock operation of the gate clock signal GCKin.

At time t11, the set signal S changes from the low level to the high level. Since the thin film transistor T16 is diode-connected as shown in FIG. 7, the thin film transistor T16 is turned on by the pulse of the set signal S, and the potential of the first node N1 rises. Thereby, the thin film transistors T11, T13, and T19 are turned on. When the thin film transistor T11 is turned on, the voltage of the output signal G increases. However, the voltage level rises to a voltage level lower than the voltage level Vgh of the DC power supply voltage VDD by the threshold voltage of the thin film transistor T11. Further, when the thin film transistor T19 is turned on, the potential of the second node N2 becomes a low level. Note that since the gate clock signal GCKin is at the low level during the period from the time point t11 to the time point t12, the output signal Q is maintained at the low level even when the thin film transistor T13 is in the on state. At time t11, the thin film transistor T1D is turned on by the pulse of the set signal S. As a result, the potential of the third node N3 becomes low level. During the period from time t11 to time t12, the reset signal R is maintained at a low level, and the potential of the second node N2 is also maintained at a low level. Accordingly, the potential of the first node N1 does not decrease during this period due to the provision of the thin film transistors T15 and T17.

At time t12, the gate clock signal GCKin changes from low level to high level. As a result, the potential of the third node N3 rises through the thin film transistor T1C. Here, as shown in FIG. 7, since the capacitor C1 is provided between the first node N1 and the third node N3, the potential of the first node N1 rises with the rise of the potential of the third node N3 (the first node N3). 1 node N1 is bootstrapped). As a result, the potential of the first node N1 is raised to a voltage level equal to or higher than the voltage level Vgh of the DC power supply voltage VDD. As a result, a large voltage is applied to the gate terminals of the thin film transistors T11 and T13, the voltage of the output signal G rises to the voltage level Vgh of the DC power supply voltage VDD, and the voltage of the output signal Q becomes the high level of the gate clock signal GCKin. The voltage rises to the voltage level Vgh2. In this regard, as described above, the voltage level Vgh2 of the high level voltage of the gate clock signal GCKin is higher than the voltage level Vgh of the DC power supply voltage VDD. Note that during the period from time t12 to time t13, the reset signal R is maintained at a low level, and the potential of the second node N2 is also maintained at a low level. Therefore, during this period, the potential of the first node N1 does not decrease due to the provision of the thin film transistors T15 and T17, and the output signal is attributable to the provision of the thin film transistors T12 and T1A. The voltage of G does not decrease, and the voltage of the output signal Q does not decrease due to the provision of the thin film transistors T14 and T1B.

At time t13, the reset signal R changes from low level to high level. Thereby, the thin film transistors T12, T14, and T15 are turned on. At this time, the voltage applied to the gate terminals of the thin film transistors T12, T14, and T15 changes from the voltage level Vgl to the voltage level Vgh2 (see FIG. 1). Therefore, the thin film transistors T12, T14, and T15 change from the off state to the on state more rapidly than in the past. When the thin film transistor T12 is turned on, the output signal G (that is, the scanning signal GOUT) is at a low level, when the thin film transistor T14 is turned on, the output signal Q is at a low level, and when the thin film transistor T15 is turned on, the output signal G is turned on. The potential of one node N1 is at a low level.

At time t14, the gate clock signal GCKin changes from low level to high level. Since the thin film transistor T18 is diode-connected as shown in FIG. 7, when the gate clock signal GCKin changes from low level to high level, the potential of the second node N2 becomes high level. In the period after time t14, the same operation as in the period before time t11 is performed.

By performing the operation as described above in each unit circuit 4, a plurality of gate bus lines GL (1) to GL (i) provided in the liquid crystal display device are sequentially selected, and the pixel capacitance is obtained. Are sequentially written. As a result, an image based on the image signal DAT sent from the outside is displayed on the display unit 600 (see FIG. 2).

<1.3 Effect>
According to the present embodiment, the ON / OFF state of the thin film transistor T12 for lowering the gate output provided in each unit circuit 4 is the reset signal that is the output signal Q output from the unit circuit 4 after two stages. Controlled by R. In such a configuration, the voltage of the output signal Q output from the unit circuit 4 corresponding to the gate bus line GL to be selected rises to the voltage level Vgh2 of the high level voltage of the gate clock signal GCK. Here, since the voltage level Vgh2 of the high level voltage of the gate clock signal GCK is higher than the voltage level Vgh of the DC power supply voltage VDD, when the thin film transistor T12 is turned on, the voltage higher than the conventional voltage level is lower. It is given to the gate terminal of T12. That is, the time required for the reset signal R to rise is shorter than in the prior art. As a result, the fall time of the gate output is shorter than before, and a sufficient charge time for the pixel capacitance is ensured even when a panel that performs high-speed driving or a high-definition panel is employed. In the present embodiment, a configuration in which the gate load 6 is driven by the DC power supply voltage VDD (a configuration in which the DC power supply voltage VDD is applied to the drain terminal of the thin film transistor T11 called a buffer TFT) is adopted. Is low. As described above, according to the present embodiment, the gate driver 400 that can secure a sufficient charging time with low power consumption is realized.

FIG. 9 is a diagram for comparing the waveform of the gate output between the above-described second conventional example and this embodiment. In FIG. 9, the waveform of the gate clock signal GCK in the second conventional example is represented by a solid line denoted by reference numeral 70, and the waveform of the gate clock signal GCK in the present embodiment is represented by a dotted line denoted by reference numeral 71. The waveform of the gate output in the example is represented by a thick dotted line with a reference numeral 72, and the waveform of the gate output in this embodiment is represented by a thick solid line with a reference numeral 73. From FIG. 9, it can be understood that the fall time of the gate output is shorter than that of the second conventional example by increasing the voltage level of the high level voltage of the gate clock signal GCK in this embodiment.

Here, the results of a certain simulation will be described with reference to FIGS. In this simulation, in a panel using a four-phase clock signal having a duty ratio of 1/2 as the gate clock signal GCK, the fall time of the scanning signal GOUT (the gate output voltage is − The target for the time until reaching 6V is 1200 nanoseconds. The measurement position of the fall time is a position farthest from the signal input point to the panel (for example, in a configuration in which the shift register 410 is provided on both sides of the display unit 600, the reference numeral 66 is schematically given in FIG. Position). Further, Vgh = 18V, Vgl = −12V, the voltage level of the DC power supply voltage VDD is set to Vgh, and the voltage level of the DC power supply voltage VSS is set to Vgl. For the low level voltage of the gate clock signal GCK, the voltage level is set to Vgl. Under the above assumption, the voltage level Vgh2 set to the high level voltage of the gate clock signal GCK is changed in the range of 18V to 23V. The difference between the high level voltage and the low level voltage of the gate clock signal GCK is represented by VGPP.

FIG. 11 shows the relationship between the value of VGPP and the fall time as a result of the simulation. When the voltage level Vgh2 of the high level voltage of the gate clock signal GCK is set to the same voltage level Vgh (that is, 18V) as before, VGPP is 30V and the fall time is 1350 nanoseconds. That is, the fall time goal cannot be achieved. On the other hand, when the voltage level Vgh2 of the high level voltage of the gate clock signal GCK is set to 21 V or more, VGPP is 33 V or more and the fall time is 1200 nanoseconds or less.

FIG. 12 shows changes in the potential of the first node N1, changes in the voltage of the output signal G (scanning signal GOUT), and changes in the voltage of the output signal Q as simulation results. In FIG. 12, the change in the state of “VGPP = 30V” is represented by a thick dotted line, and the change in the state of “VGPP = 35V” is represented by a thick solid line. Further, FIG. 13 shows a detailed waveform change as a result of the simulation. In FIG. 13, the change in the waveform of the gate clock signal GCK in the state of “VGPP = 30V” is represented by a dotted line denoted by reference numeral 74a, and the change in the waveform of the gate clock signal GCK in the state of “VGPP = 35V” is indicated by a sign. The change in the waveform of the reset signal R in the state of “VGPP = 30V” is indicated by a dotted line with the reference numeral 75a, and the change in the waveform of the reset signal R in the state of “VGPP = 35V” is indicated by the solid line with 74b. The change of the waveform of the output signal G in the state of “VGPP = 30V” is indicated by a dotted line with the reference numeral 76a, and the change of the waveform of the output signal G in the state of “VGPP = 35V” is indicated by the solid line indicated by 75b. This is indicated by a solid line with 76b. According to the result of this simulation, in the state of “VGPP = 30 V”, the fall time of the gate output (the time indicated by the arrow with the symbol T (a) in FIG. 13) is the target 1200 nanoseconds. However, in the state of “VGPP = 35V”, the fall time of the gate output (the time indicated by the arrow with the symbol T (b) in FIG. 13) is the target 1200 nanoseconds or less. Yes.

From the simulation results as described above, it can be understood that the time required for the reset signal R to rise is shorter than before by setting the high level voltage of the gate clock signal GCK to a high voltage level.

Note that according to the present embodiment, the logic unit is driven at a higher voltage than in the past. This increases the operating point of each thin film transistor. Thereby, the secondary effect that the circuit margin can be increased is also obtained. By the way, since the logic unit is driven at a higher voltage than the conventional one, the power consumption increases as compared with the second conventional example described above. However, since the thin film transistor T13 only drives the output signal Q given as the set signal S and the reset signal R to the unit circuit 4 at the other stage, a thin film transistor T13 can be employed. Therefore, since the capacity can be reduced, the increase in power consumption is extremely small. On the other hand, as described above, according to the first conventional example, since the buffer TFT needs to drive a large capacity, the power consumption is large. As described above, although the power consumption is larger than that of the second conventional example, the increase is slight, and the power consumption is greatly reduced as compared with the first conventional example.

<1.4 Modification>
In the first embodiment, only the voltage level of the high level voltage of the gate clock signal GCK is set to a level higher than the voltage level of the DC power supply voltage VDD. However, the present invention is not limited to this. In addition to the high level voltage of the gate clock signal GCK, a signal having a voltage level higher than the voltage level of the DC power supply voltage VDD is applied to the shift register 410 constituting the gate driver 400. You may be allowed to. This will be described below. However, the description will focus on differences from the first embodiment.

FIG. 14 is a block diagram showing the configuration of the gate driver 400 in this modification. In addition to the input signal in the first embodiment, the control signal VDD2 is input to each unit circuit 4 included in the shift register 410 constituting the gate driver 400. The control signal VDD2 is commonly applied to all the unit circuits 4 (1) to 4 (i).

As shown in FIG. 15, the control signal VDD2 changes between a high level voltage and a low level voltage. Specifically, the control signal VDD2 becomes a high level voltage during the effective horizontal scanning period and becomes a low level voltage during the blanking period. The high level voltage of the control signal VDD2 and the high level voltage of the gate clock signal GCK have the same voltage level Vgh2, and the low level voltage of the control signal VDD2 and the low level voltage of the gate clock signal GCK are the same voltage level Vgl. have.

FIG. 16 is a circuit diagram showing the configuration of the unit circuit 4 (configuration of one stage of the shift register 410) in the present modification. In FIG. 16, the input terminal that receives the control signal VDD2 is denoted by reference numeral 45. In this modification, the connection destination of the thin film transistor T16 and the connection destination of the thin film transistor T18 are different from those of the first embodiment. As for the thin film transistor T16, the gate terminal is connected to the input terminal 41, the drain terminal is connected to the input terminal 45, and the source terminal is connected to the first node N1. As for the thin film transistor T18, the gate terminal and the drain terminal are connected to the input terminal 45 (that is, diode connection), and the source terminal is connected to the second node N2.

In this modification, operations similar to those in the first embodiment are performed except for the following points. When the set signal S becomes high level, the high voltage of the control signal VDD2 is applied to the first node N1 via the thin film transistor T16. Except for the blanking period, the second node N2 is always supplied with the high level voltage of the control signal VDD2 via the thin film transistor T18. Accordingly, the potential of the second node N2 is maintained at a high level throughout a period other than a period during which the potential of the first node N1 is at a high level (a period in which the thin film transistor T19 is in an on state).

As in the first embodiment, also in this modification, the gate driver 400 that can secure a sufficient charging time with low power consumption is realized.

As described above, in order to operate the shift register 410 constituting the gate driver 400, in addition to the gate clock signal GCK, the gate start pulse signal GSP, and the gate end pulse signal GEP, other signals (control signal in the above-described modification example). The present invention can also be applied when VDD2) is used. Further, the other signal may be a signal having the voltage level Vgh2 described above. In addition to the above-described modifications, for example, the following configuration may be employed in a panel used as a touch panel.

In a panel used as a touch panel, a thin film transistor for maintaining the voltage level of the scanning signal GOUT at the voltage level of the DC power supply voltage VSS throughout the blanking period and the rest period may be provided in each unit circuit 4 in the shift register 410. is there. In such a configuration, the voltage level of the high level voltage of the signal for controlling the on / off state of the thin film transistor is the above-described voltage level Vgh2.

<2. Second Embodiment>
A second embodiment of the present invention will be described. Since the overall configuration and the schematic configuration of the gate driver 400 are the same as those in the first embodiment, description thereof is omitted (see FIGS. 2 to 4 and 6). Hereinafter, a description will be given centering on differences from the first embodiment.

Note that, here, a description will be given assuming that a four-phase clock signal having a duty ratio of 1/2 (that is, 50%) is used as the gate clock signal GCK, but the present invention is not limited to this. When Zc and Zd are integers and a Zc-phase clock signal having a duty ratio of Zd / Zc is used, the output signal Q output from the unit circuit before the Zd stage or (Zd-1) stage is set signal for each stage. The output signal Q outputted from the unit circuit after the Zd stage may be given as the reset signal R. For example, when a 6-phase clock signal having a duty ratio of 2/6 is used, the output signal Q output from the unit circuit two stages before or one stage before is supplied as the set signal S for each stage. The output signal Q output from the unit circuit after two stages may be provided as the reset signal R.

<2.1 Unit circuit configuration>
FIG. 17 is a circuit diagram showing a configuration of the unit circuit 4 (configuration of one stage of the shift register 410) in the present embodiment. As shown in FIG. 17, this unit circuit 4 includes 11 thin film transistors T21, T22, T23, T24, T25, T26, T27, T28, T29, T2A, and T2B, and one capacitor (capacitance element) C2. And.

Next, the connection relationship between the components in the unit circuit 4 will be described. The gate terminal of the thin film transistor T21, the gate terminal of the thin film transistor T23, the drain terminal of the thin film transistor T25, the source terminal of the thin film transistor T26, the drain terminal of the thin film transistor T27, the gate terminal of the thin film transistor T29, and one end of the capacitor C2 are connected via the first node N1. Are connected to each other. The gate terminal of the thin film transistor T27, the source terminal of the thin film transistor T28, the drain terminal of the thin film transistor T29, the gate terminal of the thin film transistor T2A, and the gate terminal of the thin film transistor T2B are connected to each other via the second node N2.

Regarding the thin film transistor T21, the gate terminal is connected to the first node N1, the drain terminal is connected to the input terminal 44, and the source terminal is connected to the output terminal 48. As for the thin film transistor T22, the gate terminal is connected to the input terminal 42, the drain terminal is connected to the output terminal 48, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T23, the gate terminal is connected to the first node N1, the drain terminal is connected to the input terminal 43, and the source terminal is connected to the output terminal 49. As for the thin film transistor T24, the gate terminal is connected to the input terminal 42, the drain terminal is connected to the output terminal 49, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T25, the gate terminal is connected to the input terminal 42, the drain terminal is connected to the first node N1, and the source terminal is connected to the input terminal for the DC power supply voltage VSS.

Regarding the thin film transistor T26, the gate terminal and the drain terminal are connected to the input terminal 41 (that is, diode connection), and the source terminal is connected to the first node N1. As for the thin film transistor T27, the gate terminal is connected to the second node N2, the drain terminal is connected to the first node N1, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T28, the gate terminal and the drain terminal are connected to the input terminal 43 (that is, diode connection), and the source terminal is connected to the second node N2. As for the thin film transistor T29, the gate terminal is connected to the first node N1, the drain terminal is connected to the second node N2, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T2A, the gate terminal is connected to the second node N2, the drain terminal is connected to the output terminal 48, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. As for the thin film transistor T2B, the gate terminal is connected to the second node N2, the drain terminal is connected to the output terminal 49, and the source terminal is connected to the input terminal for the DC power supply voltage VSS. The capacitor C2 has one end connected to the first node N1 and the other end connected to the output terminal 49.

Next, the function of each component in the unit circuit 4 will be described. The thin film transistor T21 supplies the DC power supply voltage VDD to the output terminal 48 when the potential of the first node N1 is at a high level. The thin film transistor T22 changes the output signal G toward the low level when the reset signal R is at the high level. The thin film transistor T23 supplies the voltage of the gate clock signal GCKin to the output terminal 49 when the potential of the first node N1 is at a high level. The thin film transistor T24 changes the output signal Q toward the low level when the reset signal R is at the high level. The thin film transistor T25 changes the potential of the first node N1 toward the low level when the reset signal R is at the high level.

The thin film transistor T26 changes the potential of the first node N1 toward the high level when the set signal S is at the high level. The thin film transistor T27 changes the potential of the first node N1 toward the low level when the potential of the second node N2 is at the high level. The thin film transistor T28 changes the potential of the second node N2 toward the high level when the gate clock signal GCKin is at the high level. The thin film transistor T29 changes the potential of the second node N2 toward the low level when the potential of the first node N1 is at the high level. The thin film transistor T2A changes the output signal G toward the low level when the potential of the second node N2 is at the high level. The thin film transistor T2B changes the output signal Q toward the low level when the potential of the second node N2 is at the high level. The capacitor C2 functions as a bootstrap capacitor for raising the potential of the first node N1.

Similarly to the first embodiment, in this embodiment, the potential of the second node N2 may be controlled by a configuration other than the configuration shown in FIG.

In this embodiment, a selection control transistor transistor is realized by the thin film transistor T21, a non-selection control transistor is realized by the thin film transistor T22, an output control transistor is realized by the thin film transistor T23, and a non-output control transistor is realized by the thin film transistor T24. A second first node turn-off transistor is realized by the thin film transistor T25, a first node turn-on transistor is realized by the thin film transistor T26, a first first node turn-off transistor is realized by the thin film transistor T27, and a first transistor is turned on by the thin film transistor T28. A two-node turn-on transistor is realized, and a second node turn-off transistor is formed by the thin film transistor T29. Register is implemented, the first output node turn-off transistor is realized by thin film transistors T2A, the second output node turn-off transistor is realized by a thin film transistor T2B.

<2.2 Unit circuit operation>
Next, the operation of the unit circuit 4 in this embodiment will be described with reference to FIG. Here again, the waveform delay is ignored.

Before the time point t21, the set signal S is low level, the potential of the first node N1 is low level, the potential of the second node N1 is high level, the output signal Q is low level, the output signal G is low level, reset The signal R is at a low level. As for the gate clock signal GCKin, the high level and the low level are alternately repeated. As described above, parasitic capacitance exists in the thin film transistor in the unit circuit 4. Therefore, in the period before time t21, the potential of the first node N1 may fluctuate due to the clock operation of the gate clock signal GCKin and the presence of the parasitic capacitance of the thin film transistor T23 (see FIG. 17). Thereby, the voltage of the output signal G, that is, the voltage of the scanning signal GOUT applied to the gate bus line GL can be increased. However, the thin film transistor T27 is maintained in the on state during the period in which the potential of the second node N2 is maintained at the high level. Therefore, during the period before time t21, the thin film transistor T27 is maintained in the on state, and the potential of the first node N1 is reliably maintained at the low level. As described above, even if noise due to the clock operation of the gate clock signal GCKin is mixed into the first node N1, the voltage of the corresponding scanning signal GOUT does not increase. As a result, it is possible to prevent the occurrence of defects such as display defects due to the clock operation of the gate clock signal GCKin.

At time t21, the set signal S changes from the low level to the high level. Since the thin film transistor T26 is diode-connected as shown in FIG. 17, the thin film transistor T26 is turned on by the pulse of the set signal S, and the potential of the first node N1 rises. Thereby, the thin film transistors T21, T23, and T29 are turned on. When the thin film transistor T21 is turned on, the voltage of the output signal G increases. However, it rises to a voltage level lower than the voltage level Vgh of the DC power supply voltage VDD by the threshold voltage of the thin film transistor T21. Further, when the thin film transistor T29 is turned on, the potential of the second node N2 becomes a low level. Note that since the gate clock signal GCKin is at the low level during the period from the time point t21 to the time point t22, the output signal Q is maintained at the low level even when the thin film transistor T23 is in the on state. In the period from time t21 to time t22, the reset signal R is maintained at a low level, and the potential of the second node N2 is also maintained at a low level. Therefore, the potential of the first node N1 does not decrease during this period due to the provision of the thin film transistors T25 and T27.

At time t22, the gate clock signal GCKin changes from low level to high level. At this time, since the thin film transistor T23 is in the ON state, the potential of the output terminal 49 increases as the potential of the input terminal 43 increases. Here, as shown in FIG. 17, since the capacitor C2 is provided between the first node N1 and the output terminal 49, the potential of the first node N1 increases as the potential of the output terminal 49 increases (first node). N1 is bootstrapped). As a result, the potential of the first node N1 is raised to a voltage level equal to or higher than the voltage level Vgh of the DC power supply voltage VDD. As a result, a large voltage is applied to the gate terminals of the thin film transistors T21 and T23, the voltage of the output signal G rises to the voltage level Vgh of the DC power supply voltage VDD, and the voltage of the output signal Q becomes the high level of the gate clock signal GCKin. The voltage rises to the voltage level Vgh2. In this regard, as in the first embodiment, the voltage level Vgh2 of the high level voltage of the gate clock signal GCKin is higher than the voltage level Vgh of the DC power supply voltage VDD. Note that the reset signal R is maintained at a low level during the period from the time point t22 to the time point t23, and the potential of the second node N2 is also maintained at a low level. Therefore, during this period, the potential of the first node N1 does not decrease due to the provision of the thin film transistors T25 and T27, and the output signal due to the provision of the thin film transistors T22 and T2A. The voltage of G does not decrease, and the voltage of the output signal Q does not decrease due to the provision of the thin film transistors T24 and T2B.

At time t23, the reset signal R changes from low level to high level. Thereby, the thin film transistors T22, T24, and T25 are turned on. At this time, the voltage applied to the gate terminals of the thin film transistors T22, T24, and T25 changes from the voltage level Vgl to the voltage level Vgh2 (see FIG. 1). Therefore, the thin film transistors T22, T24, and T25 change from the off state to the on state more rapidly than in the past. When the thin film transistor T22 is turned on, the output signal G (that is, the scanning signal GOUT) becomes a low level, when the thin film transistor T24 is turned on, the output signal Q becomes a low level, and when the thin film transistor T25 is turned on, the output signal G becomes low. The potential of one node N1 is at a low level.

At time t24, the gate clock signal GCKin changes from low level to high level. Since the thin film transistor T28 is diode-connected as shown in FIG. 17, when the gate clock signal GCKin changes from low level to high level, the potential of the second node N2 becomes high level. In the period after time t24, the same operation as in the period before time t21 is performed.

By performing the operation as described above in each unit circuit 4, as in the first embodiment, a plurality of gate bus lines GL (1) to GL (i) provided in the liquid crystal display device are provided. The selected state is sequentially selected, and writing to the pixel capacitor is sequentially performed. As a result, an image based on the image signal DAT sent from the outside is displayed on the display unit 600 (see FIG. 2).

<2.3 Effects>
Also in the present embodiment, as in the first embodiment, the gate output fall time is shorter than in the prior art, and the charge time of the pixel capacitance is also used when a panel or a high-definition panel that is driven at high speed is adopted. Sufficiently secured. Also in the present embodiment, a configuration in which the gate load 6 is driven by the DC power supply voltage VDD (configuration in which the DC power supply voltage VDD is applied to the drain terminal of the thin film transistor T21 called a buffer TFT) is adopted. Is low. As described above, according to the present embodiment, as in the first embodiment, the gate driver 400 capable of sufficiently securing the charging time with low power consumption is realized.

Here, the results of a certain simulation will be described with reference to FIGS. In this simulation, the target of the fall time of the scanning signal GOUT is set to 1000 nanoseconds. Further, Vgh = 18V, Vgl = −12V, the voltage level of the DC power supply voltage VDD is set to Vgh, and the voltage level of the DC power supply voltage VSS is set to Vgl. For the low level voltage of the gate clock signal GCK, the voltage level is set to Vgl. Under the above assumption, the voltage level Vgh2 set to the high level voltage of the gate clock signal GCK is changed in the range of 30V to 35V. The difference between the high level voltage and the low level voltage of the gate clock signal GCK is represented by VGPP.

FIG. 19 shows the relationship between the value of VGPP and the fall time as a result of the simulation. When the voltage level Vgh2 of the high level voltage of the gate clock signal GCK is set to the same voltage level Vgh (that is, 18V) as before, VGPP is 30V and the fall time is about 1300 nanoseconds. That is, the fall time goal cannot be achieved. On the other hand, when the voltage level Vgh2 of the high level voltage of the gate clock signal GCK is set to 21.5V or more, VGPP is 33.5V or more and the fall time is 1000 nanoseconds or less.

FIG. 20 shows changes in the potential of the first node N1, changes in the voltage of the output signal G (scanning signal GOUT), and changes in the voltage of the output signal Q as simulation results. In FIG. 20, the change in the state of “VGPP = 30V” is represented by a thick dotted line, and the change in the state of “VGPP = 35V” is represented by a thick solid line. FIG. 21 shows a detailed waveform change as a result of the simulation. In FIG. 21, the change in the waveform of the gate clock signal GCK in the state of “VGPP = 30V” is represented by a dotted line denoted by reference numeral 77a, and the change in the waveform of the gate clock signal GCK in the state of “VGPP = 35V” is indicated by a sign. The change in the waveform of the reset signal R in the state of “VGPP = 30V” is indicated by a dotted line indicated by the reference numeral 78a, and the change in the waveform of the reset signal R in the state of “VGPP = 35V” is indicated by the solid line indicated by 77b. The change of the waveform of the output signal G in the state of “VGPP = 30V” is represented by a dotted line with the reference numeral 79a, and the change of the waveform of the output signal G in the state of “VGPP = 35V” is represented by the solid line with 78b. This is indicated by a solid line with 79b. According to the result of this simulation, in the state of “VGPP = 30 V”, the fall time of the gate output (the time represented by the arrow with the symbol T (a) in FIG. 21) is the target of 1000 nanoseconds. However, in the state of “VGPP = 35V”, the fall time of the gate output (the time indicated by the arrow with the symbol T (b) in FIG. 21) is the target 1000 nanoseconds or less. Yes.

From the simulation results as described above, it can be understood that the time required for the reset signal R to rise is shorter than before by setting the high level voltage of the gate clock signal GCK to a high voltage level.

<2.4 Modification>
Also in the second embodiment, as in the modified example of the first embodiment, a signal having a voltage level higher than the voltage level of the DC power supply voltage VDD is shifted in addition to the high level voltage of the gate clock signal GCK. A configuration in which the register 410 is provided can be employed. This will be described focusing on differences from the second embodiment.

About the schematic structure of the gate driver 400, it becomes a structure as shown in FIG. 14 similarly to the modification of the said 1st Embodiment. That is, the control signal VDD2 is input to each unit circuit 4 included in the shift register 410 constituting the gate driver 400 in addition to the input signal in the second embodiment. The control signal VDD2 is commonly applied to all the unit circuits 4 (1) to 4 (i). Similar to the modification of the first embodiment, the high level voltage of the control signal VDD2 and the high level voltage of the gate clock signal GCK have the same voltage level Vgh2, and the low level voltage of the control signal VDD2 and the gate clock. The signal GCK has the same voltage level Vgl as the low level voltage.

FIG. 22 is a circuit diagram showing the configuration of the unit circuit 4 (configuration of one stage of the shift register 410) in the present modification. In this modification, the connection destination of the thin film transistor T26 and the connection destination of the thin film transistor T28 are different from those of the second embodiment. As for the thin film transistor T26, the gate terminal is connected to the input terminal 41, the drain terminal is connected to the input terminal 45, and the source terminal is connected to the first node N1. As for the thin film transistor T28, the gate terminal and the drain terminal are connected to the input terminal 45 (that is, diode connection), and the source terminal is connected to the second node N2.

In this modification, operations similar to those of the second embodiment are performed except for the following points. When the set signal S becomes high level, the high voltage of the control signal VDD2 is applied to the first node N1 via the thin film transistor T26. Further, except for the blanking period, the second node N2 is always supplied with the high level voltage of the control signal VDD2 via the thin film transistor T28. Accordingly, the potential of the second node N2 is maintained at a high level throughout a period other than a period during which the potential of the first node N1 is at a high level (a period in which the thin film transistor T29 is in an on state).

As in the second embodiment, also in this modification, the gate driver 400 that can secure a sufficient charging time with low power consumption is realized.

As described above, in order to operate the shift register 410 constituting the gate driver 400, in addition to the gate clock signal GCK, the gate start pulse signal GSP, and the gate end pulse signal GEP, other signals (control signal in the above-described modification example). The present invention can also be applied when VDD2) is used. Further, the other signal may be a signal having the voltage level Vgh2 described above.

<3. Third Embodiment>
<3.1 Overview>
Regarding display devices such as the above-described liquid crystal display device, it has been a challenge to reduce power consumption. Accordingly, development of a driving method is underway that “provides a pause period in which scanning of the gate bus line is stopped and the video signal writing operation is paused (a pause period is provided between the scan period and the scan period)”. . Such a driving method for providing a pause period during which the writing operation is paused is called “pause driving”. Even in a general liquid crystal display device, the gate bus line is not scanned during the blanking period, but the blanking period is a part of the scanning period. A longer period of inactivity is provided. In the liquid crystal display device adopting such pause driving, it is not necessary to give a control signal or the like to a driver (driving circuit) such as a gate driver or a source driver during the pause period. For this reason, the driving frequency of the driver or the like is reduced as a whole, and the power consumption can be reduced. Therefore, a configuration that employs pause driving will be described below as a third embodiment of the present invention.

<3.2 Configuration and operation>
Regarding the present embodiment, the circuit configuration of the unit circuit 4 and the like constituting the shift register 410 is not particularly limited. Therefore, for example, the circuit configuration in the first embodiment (including modifications) and the second embodiment (including modifications) can be employed.

In the present embodiment, it is possible to switch the operation mode between normal driving and pause driving. The operation mode is switched by the display control circuit 200, for example. FIG. 23 is a signal waveform diagram of a drive signal (a signal for driving the shift register 410 included in the gate driver 400) when the operation mode is normal drive. FIG. 24 is a signal waveform diagram of drive signals when the operation mode is pause drive. Note that although the gate clock signal GCK is composed of a plurality of clock signals, FIGS. 23 and 24 show only one waveform of the plurality of clock signals (the same applies to FIG. 27).

During normal driving, as shown in FIG. 23, the gate start pulse signal GSP rises every 1/60 seconds. After the rise of the gate start pulse signal GSP, the shift register 410 performs a shift operation based on the clock operation of the gate clock signal GCK. Thereafter, when the gate end pulse signal GEP rises, the shift operation in the shift register 410 is stopped. Such an operation is repeated every 1/60 seconds. Thereby, the screen is refreshed every 1/60 seconds.

During the pause driving, as shown in FIG. 24, the gate start pulse signal GSP rises every 1/30 seconds. In each frame, the same operation as during normal driving is performed for the first 1/60 second. Here, during the pause driving, all signals other than the DC power supply voltage VDD are passed through the period until the next frame starts after the shift operation in the shift register 410 is stopped by the rise of the gate end pulse signal GEP. Here, the voltage levels of the gate start pulse signal GSP, the gate clock signal GCK, the gate end pulse signal GEP, and the DC power supply voltage VSS are fixed at the voltage level Vgl described above. Accordingly, the operation of the shift register 410 is completely stopped for at least 1/60 second in each frame period (1/30 second). The above operation is repeated every 1/30 seconds. Thereby, the screen is refreshed every 1/30 seconds. Note that, here, an example in which the drive frequency during the pause drive is 30 Hz is described, but the present invention is not limited to this. For example, the driving frequency during pause driving can be set to 20 Hz. In this case, the length of each frame period is 1/20 second, and after the same operation as during normal driving is performed in the first 1/60 second of the period, the operation of the shift register 410 is completely stopped. .

By the way, various types of thin film transistors in each unit circuit 4 constituting the shift register 410 can be employed. In this regard, paying attention to the Vds-Ids characteristics when the Vgs (gate-source voltage) of the thin film transistor is 0 V (Vds: drain-source voltage, Ids: drain-source current), Vds has a predetermined magnitude Va. In this case, there are a thin film transistor in which Ids is 0 as shown in FIG. 25 and a thin film transistor in which Ids is larger than 0 as shown in FIG. 26 when Vds is the predetermined size Va.

During the rest period, in the vicinity of the output portion of each unit circuit 4, Vgs of the thin film transistor T01 called a buffer TFT for driving the gate load 6 and Vgs of the thin film transistor T02 for lowering the gate output are substantially zero ( (See FIG. 27). Here, when a thin film transistor having the characteristics shown in FIG. 25 is used as the thin film transistor in each unit circuit 4, the current flowing as indicated by the arrow 80 in FIG. It hardly occurs. Therefore, as shown in FIG. 24, the DC power supply voltage VDD may be maintained at the above-described voltage level Vgh even during the suspension period. In addition, if a configuration in which the voltage level of the DC power supply voltage VDD is lowered during the suspension period is required, the drain of the thin film transistor T01 needs to be charged each time the shift operation in the shift register 410 is restarted. For this reason, power consumption increases. Since it becomes necessary to control the voltage level of the DC power supply voltage VDD, the circuit becomes complicated. Also from the above viewpoint, when the thin film transistor having the characteristics shown in FIG. 25 is used, the above-described voltage level Vgh should be maintained even during the idle period for the DC power supply voltage VDD. .

On the other hand, when a thin film transistor having the characteristics shown in FIG. 26 is used as the thin film transistor in each unit circuit 4, a current flowing as indicated by an arrow 80 in FIG. obtain. Therefore, as shown in FIG. 28, it is preferable to reduce the voltage level of the DC power supply voltage VDD to, for example, the above-described voltage level Vgl during the idle period. More specifically, “power consumed by the current flowing in each unit circuit 4 during the pause period when the voltage level of the DC power supply voltage VDD is maintained at the voltage level Vgh described above during the pause period” and “ When the voltage level of the DC power supply voltage VDD is lowered during the idle period, the power consumed by charging the drain of the thin film transistor T01 in each unit circuit 4 in each frame is compared. It is preferable to adopt the configuration with the smaller number.

During normal driving, as shown in FIG. 23, the voltage level of the DC power supply voltage VDD is preferably maintained at the voltage level Vgh described above. This is because, for example, if the voltage level of the DC power supply voltage VDD is lowered during the blanking period, it is necessary to charge the drain of the thin film transistor T01 every time the frame is switched, and the power consumption increases.

<3.3 Effects>
According to the present embodiment, since the pause drive is adopted, it is possible to sufficiently ensure the charging time while further reducing the power consumption as compared with the first embodiment and the second embodiment. A gate driver 400 is realized.

<4. Other>
The present invention is not limited to the above-described embodiments (including modifications), and various modifications can be made without departing from the spirit of the present invention. For example, each of the above embodiments has been described on the assumption that an n-channel thin film transistor is used. However, the present invention can also be applied to a case where a p-channel thin film transistor is used. In this regard, when a p-channel type thin film transistor is used, the polarities of the voltages are all reversed from those of the above embodiments. Therefore, as indicated by the dotted line denoted by reference numeral 63 in FIG. 29, a low-level DC power supply voltage VSS is applied to the first conduction terminal of the thin film transistor T01 called a buffer TFT in the vicinity of the output portion of the unit circuit, and the gate A high-level DC power supply voltage VDD is applied to the second conduction terminal of the thin film transistor T02 for lowering the output. In the configuration as described above, the low-level voltage level Vgl2 of the gate clock signal GCK may be set lower than the voltage level Vgl of the DC power supply voltage VSS, as indicated by the dotted line denoted by reference numeral 64 in FIG. In other words, rather than the “difference between the voltage level Vgh of the high level voltage of the gate clock signal GCK and the voltage level Vgl of the DC power supply voltage VSS”, the voltage level Vgh of the high level voltage of the gate clock signal GCK and the low level voltage What is necessary is just to enlarge "the difference with voltage level Vgl2."

Furthermore, regardless of the type of thin film transistor used, it can be considered that the voltage level of each voltage may be set as follows. A gate bus which operates based on a plurality of clock signals switched between the first level voltage and the second level voltage and is supplied with the first level voltage to the control terminal of the thin film transistor T02 for lowering the gate output. In a shift register including a plurality of unit circuits configured so that a non-selection voltage is applied to the line GL, the “first level voltage and the second level voltage” are more than the “difference between the selection level voltage and the second level voltage”. Increase the difference. Here, the selection level voltage is a DC voltage to be supplied to the gate bus line GL to be selected, and the non-selection level voltage is a DC voltage to be supplied to the gate bus line GL to be unselected. It is.

In the configuration shown in FIG. 1 (configuration in which an n-channel thin film transistor is used), the voltage level Vgh2 corresponds to the first level voltage, and the voltage level Vgl corresponds to the second level voltage. The DC power supply voltage VDD corresponds to the selection level voltage, and the DC power supply voltage VSS corresponds to the non-selection level voltage.

In the configuration shown in FIG. 29 (a configuration in which a p-channel thin film transistor is used), the voltage level Vgl2 corresponds to the first level voltage, and the voltage level Vgh corresponds to the second level voltage. The DC power supply voltage VSS corresponds to the selection level voltage, and the DC power supply voltage VDD corresponds to the non-selection level voltage.

Note that it is preferable to use an oxide semiconductor TFT (for example, IGZO-TFT) as the thin film transistor of the circuit of the present invention because it has effects in terms of low power consumption and circuit area reduction.

This application is an application claiming priority based on Japanese application No. 2017-41477 entitled “Scanning signal line driving circuit and display device including the same” filed on March 6, 2017. The contents are hereby incorporated by reference.

4, 4 (1) to 4 (i): unit circuit 6: gate load 400: gate driver (scanning signal line driving circuit)
410: Shift registers GL (1) to GL (i) ... Gate bus lines T11 to T19, T1A to T1D, T21 to T29, T2A, T2B ... Thin film transistors GCK, GCKin, GCK1, GCK1B, GCK2, GCK2B in the unit circuit Gate clock signal G, Q ... Output signal (from unit circuit) S ... Set signal R ... Reset signal VDD ... High level DC power supply voltage VSS ... Low level DC power supply voltage Vgh2 ... High level voltage of gate clock signal Level Vgh: High-level DC power supply voltage level Vgl: Gate clock signal low-level voltage level

Claims (14)

  1. A plurality of scanning signal lines arranged in a display unit of a display device, including a shift register including a plurality of unit circuits that operate based on a plurality of clock signals switched between the first level voltage and the second level voltage A scanning signal line driving circuit for driving
    Each unit circuit is
    A first output node that outputs a first output signal to be applied to a corresponding scanning signal line;
    A second output node that outputs a second output signal for controlling the operation of another unit circuit;
    Selection control having a control terminal, a first conduction terminal to which a selection level voltage, which is a DC voltage to be supplied to the scanning signal line to be selected, is provided, and a second conduction terminal connected to the first output node. A transistor,
    A control terminal to which a second output signal output from the second output node of the subsequent unit circuit is applied as a reset signal, a first conduction terminal connected to the first output node, and a scanning signal line to be in a non-selected state A non-selection control transistor having a second conduction terminal to which a non-selection level voltage which is a DC voltage to be supplied to
    The second output signal output from the second output node of each unit circuit is the first level voltage during a period in which the corresponding scanning signal line is to be maintained in the selected state,
    The non-selection control transistor is turned on when the reset signal is the first level voltage,
    The plurality of unit circuits are connected to each other so that a reset signal applied to a control terminal of a non-selected control transistor included in a unit circuit corresponding to a scanning signal line to be in a non-selected state becomes the first level voltage,
    The scanning signal line driving circuit according to claim 1, wherein a difference between the first level voltage and the second level voltage is larger than a difference between the selection level voltage and the second level voltage.
  2. Each unit circuit is
    A first node connected to a control terminal of the selection control transistor;
    An output control transistor having a control terminal connected to the first node, a first conduction terminal to which one of the plurality of clock signals is applied, and a second conduction terminal connected to the second output node;
    A non-output control transistor having a control terminal to which the reset signal is applied, a first conduction terminal connected to the second output node, and a second conduction terminal to which the non-selection level voltage is applied;
    A first node for receiving the second output signal output from the second output node of the unit circuit of the preceding stage as a set signal and changing the potential of the first node toward the on level based on the set signal A turn-on transistor;
    A first first-node turn-off transistor having a control terminal, a first conduction terminal connected to the first node, and a second conduction terminal to which the non-selection level voltage is applied;
    A second node connected to a control terminal of the first first node turn-off transistor;
    A second node turn-on transistor for maintaining the second node potential at an on level during a period in which the first node potential is to be maintained at an off level;
    A second node turn-off transistor having a control terminal connected to the first node, a first conduction terminal connected to the second node, and a second conduction terminal to which the non-selection level voltage is applied; The scanning signal line drive circuit according to claim 1, further comprising:
  3. Each unit circuit is
    A second first-node turn-off transistor having a control terminal to which the reset signal is applied, a first conduction terminal connected to the first node, and a second conduction terminal to which the non-selection level voltage is applied;
    A first output node turn-off transistor having a control terminal connected to the second node, a first conduction terminal connected to the first output node, and a second conduction terminal to which the non-selection level voltage is applied; ,
    A second output node turn-off transistor having a control terminal connected to the second node, a first conduction terminal connected to the second output node, and a second conduction terminal to which the non-selection level voltage is applied; The scanning signal line driving circuit according to claim 2, further comprising:
  4. Each unit circuit is
    A third node;
    A capacitive element having one end connected to the first node and the other end connected to the third node;
    A control terminal to which a clock signal applied to the first conduction terminal of the output control transistor is applied, a first conduction terminal to which the selection level voltage is applied, and a second conduction terminal connected to the third node. A three-node turn-on transistor;
    And a third node turn-off transistor having a control terminal to which the set signal is applied, a first conduction terminal connected to the third node, and a second conduction terminal to which the non-selection level voltage is applied. The scanning signal line drive circuit according to claim 3, wherein:
  5. The first node turn-on transistor has a control terminal to which the set signal is applied and a first conduction terminal, and a second conduction terminal connected to the first node,
    The second node turn-on transistor has a control terminal to which a clock signal applied to the first conduction terminal of the output control transistor is applied, a first conduction terminal, and a second conduction terminal connected to the second node. The scanning signal line drive circuit according to claim 4, wherein
  6. The first node turn-on transistor has a control terminal to which the set signal is applied, a first conduction terminal to which the first level voltage is applied, and a second conduction terminal connected to the first node,
    5. The second node turn-on transistor has a control terminal to which the first level voltage is applied and a first conduction terminal, and a second conduction terminal connected to the second node. 2. A scanning signal line driving circuit according to 1.
  7. 4. The scanning signal line drive circuit according to claim 3, wherein each unit circuit further includes a capacitive element having one end connected to the first node and the other end connected to the second output node.
  8. The first node turn-on transistor has a control terminal to which the set signal is applied and a first conduction terminal, and a second conduction terminal connected to the first node,
    The second node turn-on transistor has a control terminal to which a clock signal applied to the first conduction terminal of the output control transistor is applied, a first conduction terminal, and a second conduction terminal connected to the second node. The scanning signal line driving circuit according to claim 7, wherein
  9. The first node turn-on transistor has a control terminal to which the set signal is applied, a first conduction terminal to which the first level voltage is applied, and a second conduction terminal connected to the first node,
    8. The second node turn-on transistor has a control terminal to which the first level voltage is applied, a first conduction terminal, and a second conduction terminal connected to the second node. 2. A scanning signal line driving circuit according to 1.
  10. The plurality of scanning signal lines are driven so that a scanning period in which the plurality of scanning signal lines are sequentially selected and a pause period in which all of the plurality of scanning signal lines are maintained in a non-selected state appear alternately. The scanning signal line driving circuit according to claim 1, wherein the scanning signal line driving circuit can be used.
  11. The selection control transistor and the non-selection control transistor have a characteristic that current does not flow between the first conduction terminal and the second conduction terminal when the voltage between the control terminal and the second conduction terminal is 0.
    11. The scanning signal line driving circuit according to claim 10, wherein the selection level voltage is applied to a first conduction terminal of the selection control transistor throughout the scanning period and the pause period.
  12. The selection control transistor and the non-selection control transistor have a characteristic of flowing a current between the first conduction terminal and the second conduction terminal when the voltage between the control terminal and the second conduction terminal is 0.
    11. The non-selection level voltage or the second level voltage is supplied to the first conduction terminal of the selection control transistor in place of the selection level voltage during the idle period. Scanning signal line driving circuit.
  13. The selection control transistor and the non-selection control transistor are n-channel thin film transistors,
    The first level voltage is higher than the second level voltage;
    The selection level voltage is higher than the non-selection level voltage;
    The scanning signal line driving circuit according to claim 1, wherein the first level voltage is higher than the selection level voltage.
  14. A display device comprising the scanning signal line drive circuit according to claim 1.
PCT/JP2018/007111 2017-03-06 2018-02-27 Scan signal line driving circuit and display device provided therewith WO2018163897A1 (en)

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JP2017041477 2017-03-06

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WO2009084267A1 (en) * 2007-12-27 2009-07-09 Sharp Kabushiki Kaisha Shift register and display device
WO2011114569A1 (en) * 2010-03-15 2011-09-22 シャープ株式会社 Shift register, scanning signal line drive circuit, and display device
JP2011204343A (en) * 2010-03-24 2011-10-13 Au Optronics Corp Shift register with low power consumption
WO2011162057A1 (en) * 2010-06-25 2011-12-29 シャープ株式会社 Scanning signal line drive circuit and display device provided with same
WO2013125405A1 (en) * 2012-02-20 2013-08-29 シャープ株式会社 Drive device and display device
WO2013160941A1 (en) * 2012-04-25 2013-10-31 パナソニック株式会社 Shift register and display device
US20160140922A1 (en) * 2014-11-13 2016-05-19 Shenzhen China Star Optoelectronics Technology Co., Ltd. Goa circuit and liquid crystal display device applied to liquid crystal displays

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009084267A1 (en) * 2007-12-27 2009-07-09 Sharp Kabushiki Kaisha Shift register and display device
WO2011114569A1 (en) * 2010-03-15 2011-09-22 シャープ株式会社 Shift register, scanning signal line drive circuit, and display device
JP2011204343A (en) * 2010-03-24 2011-10-13 Au Optronics Corp Shift register with low power consumption
WO2011162057A1 (en) * 2010-06-25 2011-12-29 シャープ株式会社 Scanning signal line drive circuit and display device provided with same
WO2013125405A1 (en) * 2012-02-20 2013-08-29 シャープ株式会社 Drive device and display device
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