WO2018113318A1 - 一种多通道ddr交织控制方法及装置、存储介质 - Google Patents

一种多通道ddr交织控制方法及装置、存储介质 Download PDF

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Publication number
WO2018113318A1
WO2018113318A1 PCT/CN2017/097329 CN2017097329W WO2018113318A1 WO 2018113318 A1 WO2018113318 A1 WO 2018113318A1 CN 2017097329 W CN2017097329 W CN 2017097329W WO 2018113318 A1 WO2018113318 A1 WO 2018113318A1
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read
slave
write
address
host
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English (en)
French (fr)
Inventor
陈哲
李正卫
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

Definitions

  • the present invention relates to the field of storage technologies, and in particular, to a multi-channel DDR interleaving control method and apparatus, and a storage medium.
  • Today's chips typically integrate components such as a Central Processor Unit (CPU), Direct Memory Access (DMA), bus interconnects, memory, high-speed peripherals, and low-speed peripherals.
  • CPU Central Processor Unit
  • DMA Direct Memory Access
  • bus interconnects memory
  • memory high-speed peripherals
  • low-speed peripherals Low-speed peripherals
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • SoC System On Chip
  • the network on chip (NOC) product of the multi-channel DDR storage system is used for transmission interleaving control.
  • the product has the characteristics of rich parameters and configurability, strong command scheduling capability, but also has high authorization cost.
  • the command has the disadvantages of large delay, large area, and fixed interleaving.
  • the embodiments of the present invention provide a multi-channel DDR interleaving control method and device, and a storage medium, which solves the problem that the multi-channel DDR memory interleaving control device has a large delay, an area, and an interleaving manner in the prior art.
  • the problem is that the technical effects of small delay, small area, flexible interleaving, and low power consumption are achieved.
  • An embodiment of the present invention provides a multi-channel DDR interleaving control method, where the method includes:
  • An embodiment of the present invention provides a multi-channel DDR interleaving control method, where the method includes:
  • the embodiment of the invention provides a multi-channel DDR interleaving control device, and the device includes:
  • the first receiving module is configured to receive the write data sent by the host and the first write address; wherein
  • the host is a bus interconnect module;
  • a first determining module configured to determine, according to the preset interleave control configuration information, the second write address corresponding to the first write address and the identifier information of the slave corresponding to the first write address;
  • the first sending module is configured to send the write data and the second write address to the slave according to the identifier information of the slave; wherein the slave is a DDR controller;
  • a second receiving module configured to receive a write feedback message sent by the slave, where the write feedback message is used to indicate whether the write data is successfully written;
  • the second sending module is configured to send the write feedback message to the host.
  • the embodiment of the invention provides a multi-channel DDR interleaving control device, and the device includes:
  • a third receiving module configured to receive a first read address sent by the host
  • a second determining module configured to determine, according to the preset interleave control configuration information, the second read address corresponding to the first read address and the first slave device identifier information corresponding to the first read address;
  • the third sending module is configured to send the second read address to the first slave according to the identifier information of the first slave;
  • a fourth receiving module configured to receive the first read data and the first read response message sent by the first slave
  • the fourth sending module is configured to send the first read data and the first read response message to the host.
  • Embodiments of the present invention provide a computer readable storage medium having stored thereon a computer program, wherein the computer program is executed by a processor to implement the steps of the multi-channel DDR interleaving control method described above.
  • the multi-channel DDR interleaving control method and apparatus and the storage medium provided by the embodiment of the present invention determine the first write address by receiving the write data and the first write address sent by the host, and then according to the preset interleave control configuration information. a second write address corresponding to the first write address And identifying the write data and the second write address to the slave according to the identifier information of the slave, and receiving the write feedback message sent by the slave, and finally A write feedback message is sent to the host.
  • Interleave control configuration information such as interleave size, interleaving mode, etc. can be set in advance, thus increasing the flexibility of interleaving control.
  • FIG. 1 is a schematic flowchart of an implementation process of a multi-channel DDR interleaving control method according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of an implementation process of a multi-channel DDR interleaving control method according to Embodiment 2 of the present invention
  • 3-1 is a schematic structural diagram of a structure of a three-channel DDR interleaving control apparatus according to an embodiment of the present invention
  • 3-2 is a schematic flowchart of an implementation process of a three-channel DDR interleaving control method according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a structure of a four-channel DDR interleaving control apparatus according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a structure of a five-channel DDR interleaving control apparatus according to an embodiment of the present invention.
  • the embodiment of the present invention provides a multi-channel DDR interleaving control method, which is applied to a multi-channel DDR, where the multi-channel DDR includes at least: a processor, an interleave controller, a host, and at least one Slave.
  • 1 is a schematic flowchart of an implementation process of a multi-channel DDR interleaving control method according to an embodiment of the present invention. As shown in FIG. 1, the method includes the following steps:
  • Step S101 receiving write data and a first write address sent by the host
  • step S101 may be implemented by an interleaving control device, which may be an interleaving controller in an actual application.
  • the host may be a bus interconnect module, that is, a bus Matrix.
  • a network interface card (NIC) 400 is commonly used.
  • Step S102 determining, according to the preset interleave control configuration information, the second write address corresponding to the first write address and the identifier information of the slave corresponding to the first write address;
  • the processor configures some interleaving control configuration information of the interleaving controller in advance according to the actual usage of the system, such as an interleave size, a non-interleaved address range, and an interleaving manner.
  • the interleave controller may determine, according to the preset interleave control configuration information, the second write address corresponding to the first write address and the identifier information of the slave corresponding to the first write address.
  • the second write address is a write address obtained by re-mapping the first write address according to the interleave control configuration information, and is also a physical address of the DDR to which the write data is to be written.
  • Step S103 sending the write data and the second write address to the slave according to the identifier information of the slave;
  • the slave may be a DDR controller; after the slave receives the write data and the second write address, the write data is written into the DDR storage unit according to the second write address. And send write feedback information to the interleaving controller.
  • Step S104 Receive a write feedback message sent by the slave.
  • the write feedback message is used to characterize whether the write data is successfully written.
  • Step S105 sending the write feedback message to the host.
  • the interlace controller after receiving the write feedback message sent by the slave, the interlace controller sends the write feedback message to the host.
  • the step S105 includes: determining whether the write feedback receiving logic module is idle;
  • the method further includes: determining bandwidth information of the write data channel;
  • the response delay of the write command is a time difference between receiving the write data sent by the host and the first write address to sending the write feedback message to the host; storing the Write bandwidth information of the data channel and response delay information of the write command to detect bandwidth information of the write data path, and record a response delay of the write command and if there is no data within a preset low power consumption threshold threshold time Or when the message is transmitted, turn off its own control clock to reduce power consumption.
  • the second write address corresponding to the first write address is determined according to the write data sent by the host and the first write address, and then according to the preset interleave control configuration information. And the identifier information of the slave corresponding to the first write address, and then sending the write data and the second write address to the slave according to the identifier information of the slave, and receiving the slave The write feedback message is sent, and finally the write feedback message is sent to the host.
  • Interleave control configuration information such as interleave size, interleaving mode, etc. can be set in advance, thus increasing the flexibility of interleaving control. And if there is no data or message transmission during the preset low power timing threshold time, turn off its own control clock, which can reduce power consumption.
  • the embodiment of the present invention further provides a multi-channel DDR interleaving control method, which is applied to an interleaving controller of a multi-channel DDR, where the multi-channel DDR includes at least: an interleave controller, a host, and at least one slave.
  • FIG. 2 is a schematic flowchart of an implementation process of a multi-channel DDR interleaving control method according to Embodiment 2 of the present invention. As shown in FIG. 2, the method includes the following steps:
  • Step S201 the interlace controller receives the first read address sent by the host
  • Step S202 the interleaving controller determines the second read address corresponding to the first read address and the first slave device corresponding to the first read address according to the preset interleave control configuration information;
  • the processor configures some interleaving control configuration information of the interleaving controller in advance according to the actual usage of the system, such as an interleave size, a non-interleaved address range, and an interleaving manner.
  • the interleave controller may determine, according to the preset interleave control configuration information, the second read address corresponding to the first read address and the identifier information of the slave corresponding to the first read address.
  • the second read address is a read address remapped by the first read address according to the interleave control configuration information, that is, a physical address in the DDR where the data to be read is located.
  • Step S203 the interleaving controller sends the second read address to the first slave according to the identifier information of the first slave;
  • the first read data is read from the storage unit of the DDR according to the second read address, and the first read data and the first A read response message is sent to the interleaving controller.
  • Step S204 the interleaving controller receives the first read data and the first read response message sent by the first slave;
  • Step S205 the interleaving controller determines whether the second read data and the second read response message sent by the second slave are received; if yes, go to step S206, otherwise go to step S208;
  • the multi-channel DDR has at least one slave
  • when there are multiple slaves when other slaves also send read data and read response messages to the interleaver at the same time (for example, the second The slave sends the second read data and the second read response message to the interleaving controller, and needs to determine whether the first read data and the first read response message are sent to the interleaving controller first, or the second The read data and the second read response message are sent to the interleaving controller.
  • Step S206 the interleaving controller determines whether the time that the first slave waits is less than or equal to The preset response timeout threshold; if yes, go to step S207, otherwise go to step S211;
  • Step S207 the interleaving controller determines whether the read priority of the first slave is higher than the read priority of the second slave; if yes, proceeds to step S208, otherwise proceeds to step S209;
  • Step S208 the interleaving controller sends the first read data and the first read response message to the host.
  • Step S209 the interleaving controller determines whether the read priority of the first slave is the same as the read priority of the second slave; if yes, go to step S210, otherwise go to step S211;
  • Step S210 the interleaving controller determines whether the port number of the first slave is smaller than the port number of the second slave; if yes, go to step S208, otherwise go to step S211;
  • Step S211 the interleaving controller sends the second read data and the second read response message to the host; then proceeds to step S205.
  • the method further includes: determining the response delay information of the read command by determining the bandwidth information of the read data channel; where the response delay of the read command is the first sent from the receiving host Reading the address to the time difference between sending the first read data and the first read response message to the host, that is, from receiving the first read address sent by the host to sending the last read data to the host The time difference. And storing bandwidth information of the read data channel and response delay information of the read command to detect bandwidth information of the read data path, and recording a response delay of the read command.
  • the method further includes:
  • the low power consumption timer is started to start timing
  • the read data and the read response message and/or the write feedback message sent by any of the slaves are not received and the read address sent by the host is not received. Or write address or write data, then turn off its own control clock.
  • the second read address corresponding to the first read address is determined by receiving the first read address sent by the host, and then according to the preset interleave control configuration information. Decoding information of the first slave corresponding to the first read address, and then sending the second read address to the first slave according to the identifier information of the first slave, and receiving the first slave to send The first read data and the first read response message, and send the first read data and the first read response message to the host.
  • Interleave control configuration information such as interleave size, interleaving mode, etc. can be set in advance, thus increasing the flexibility of interleaving control. And if there is no data or message transmission during the preset low power timing threshold time, turn off its own control clock, which can reduce power consumption.
  • the embodiment of the present invention first provides a multi-channel DDR interleaving control apparatus, and the interleaving control apparatus according to the embodiment of the present invention further provides a multi-channel DDR interleaving control method.
  • 3-1 is a schematic structural diagram of a structure of a three-channel DDR interleaving control apparatus according to an embodiment of the present invention. As shown in FIG. 3-1, the apparatus includes: read data, read response control 301, read address mapping control 302, and write address. Mapping, write data, write feedback control 303, bus monitor 304, and register configuration 305, where:
  • the read data and read response control 301 are configured to return the read data and the read response returned by each slave to the host.
  • the read address mapping control 302 is configured to map the read address sent by the host to the corresponding slave according to the interleaving configuration.
  • the write address mapping, the write data, and the write feedback control 303 are configured to map the write address sent by the host to the corresponding slave according to the interleaving configuration, and send the write data to the slave of the corresponding address, and the slave receives the write. Feedback to the host.
  • the bus monitor 304 detects bandwidth information of the read data path, the write data path, and multiple reads. Write the information (outstanding information) that the command executes simultaneously, and record the respective average response delays of the read and write commands. This information can be stored in the register configuration 105 for the processor to acquire.
  • the register configuration 305 is configured to complete interleave control, including interleave size, interleave mode, non-interleave area, read data channel timeout threshold, ignore interleave control, low power consumption timing threshold, etc., to register bus monitoring information.
  • the multi-channel DDR control device provided by the embodiment of the present invention mainly has the following functions:
  • Interleave controller configuration completes the configuration of interleave control, including interleave size, interleaving mode, non-interleaving area, read data channel timeout threshold, ignore interleaving control, low power consumption timing threshold, and the like.
  • Write channel control complete write channel address mapping, write priority register, improved Microcontroller Bus Architecture (AMBA), and improved Advanced eXtensible Interface (AXI) write identifier (Identification, ID) registration, write data transmission, write feedback reception.
  • AMBA Microcontroller Bus Architecture
  • AXI Advanced eXtensible Interface
  • Read channel control complete read channel address mapping, read priority register, AMBA, AXI protocol read ID register, read data, read response return control.
  • Read data, read response return control return read data to the host according to the read priority level. When the priority is the same, the read data is returned according to the sequence of the slave port number. If a slave reads the read data, When the data channel time exceeds the read data channel timeout threshold, it responds to read data from other slaves other than the slave.
  • Low-power control The inter-controller clock is automatically turned off when there is no read request or write request for a period of time and there is no ongoing read or write operation.
  • Bus monitoring monitor the bandwidth information and transmission delay information of the bus.
  • FIG. 3-2 is a third multi-channel DDR interleaving control method according to an embodiment of the present invention.
  • a schematic diagram of the implementation process is shown in Figure 3-2. The method includes the following steps:
  • Step S301 the processor configures an register of the interleave controller, such as an interleave size register, an interleaved mode register, a non-interleaved address range register, and the like;
  • Step S302 the host sends a write address and writes data to the interleaving controller.
  • Step S303 the interleave controller maps the write address to the corresponding slave according to the set interleave size, interleave mode, non-interleave address range, and the like, and sends the write data to the slave;
  • Step S304 the interleaving controller receives the write feedback returned by the slave
  • Step S305 the interleaving controller determines whether the write feedback receiving logic is busy
  • Step S306 if the write feedback receiving logic is idle, the interleaving controller returns write feedback to the host;
  • Step S307 if the write feedback receiving logic is busy, then wait for idle and then return to step S305;
  • Step S308 the host sends a read address to the interleaving controller
  • Step S309 the interleave controller maps the read address to the corresponding slave according to the set interleave size, interleave mode, non-interleave address range, and the like;
  • Step S310 the interleave controller receives the read data and the read response returned by the slave
  • Step S311 the interleaving controller determines whether other slaves return read data and read response at the same time
  • Step S312 if there are other slaves returning read data and read response at the same time, the interleaving controller determines whether the waiting time of the slave is less than or equal to the response timeout threshold; if yes, then proceeds to step S313, otherwise proceeds to step S316;
  • Step S313 the interleaving controller determines whether the read priority of the slave is higher than the read priority of other slaves; if yes, then proceeds to step S314, otherwise proceeds to step S315;
  • Step S314 the interleaving controller returns read data and read response to the host
  • Step S315 the interleave controller determines whether the slave has the same priority as the other slaves and the slave port number is smaller than the other slaves; if yes, the process proceeds to step S314, otherwise proceeds to step S316;
  • Step S316 the interleave controller waits for other slaves to return the read data and the read response to the host, and then returns to step S311.
  • the interleave controller may repeat steps S302-S307 for a write operation, and repeat steps S308-S316 for a read operation.
  • the processor configures the interleave size, the non-interleave address range, the interleaving manner, and the like of the interleave controller in advance;
  • the interleave size may be 64 bytes (Byte, B), 128B, 256B, 512B, 1 kilobyte (Kilo Byte, KB), 2KB, 4KB;
  • non-interleaved address range is a contiguous address (KB alignment), it can be agreed that the address will only be mapped to a fixed slave, not interleaved memory
  • the interleaving mode is a different type of interleaving address mapping in the interleaving address range, and the interleaving mode has different bandwidth utilization rates in different application scenarios.
  • the write address data stream is sent to the corresponding slave DDR write channel according to the interleave setting, the write data is sent to the slave according to the mapping of the write address, and the write feedback is sent to the host by the slave side;
  • the read address data stream is sent to the corresponding slave DDR read channel according to the interleave setting, the slave side receives the read data and feeds back to the host in a certain order, and the slave side transmits the read response and the read data to the host.
  • the write channel includes: 1. Write address channel: the host sends the write address to the interleave controller, and the interleave controller completes the address mapping according to the interleave configuration and sends the mapped write address to the corresponding slave; 2. Write the data channel: according to The mapped write address is sent to the corresponding slave; 3. The write feedback channel: the slave returns the write feedback to the host according to the write address.
  • the read channel includes: 1.
  • the read address channel the host sends the read address to the interleave controller, and the interleave controller completes the address mapping according to the interleave configuration and sends the mapped read address to the corresponding slave; 2, the read data, the read response channel: The slave receives the read data and returns the read data and the read response in turn according to the priority of each slave read data, the read data timeout timer of the slave, and the polling response control of each slave.
  • the interleave size, interleave mode, and non-interleave address of the interleaver controller Parameters such as range can be configured in advance, adding flexibility.
  • the host can perform read and write interleaving access to the multi-channel DDR of the slave through the interleave controller, and the read and write information arrives at the slave according to the rules and returns relevant information to the host.
  • the interleaving control method and the control device provided by the embodiments of the present invention have the characteristics of small delay, small area, flexible and configurable interleaving mode, and low power consumption.
  • FIG. 4 is a schematic structural diagram of a fourth multi-channel DDR interleaving control device according to an embodiment of the present invention.
  • the control device includes: a first receiving module 401. a first determining module 402, a first sending module 403, a second receiving module 404, and a second sending module 405, wherein:
  • the first receiving module 401 is configured to receive write data and a first write address sent by the host, where the host is a bus interconnect module;
  • the first determining module 402 is configured to determine, according to the preset interleave control configuration information, the second write address corresponding to the first write address and the identifier information of the slave corresponding to the first write address;
  • the first determining module 402 includes: a first determining unit, configured to determine a second write address corresponding to the first write address according to an interleave size, a non-interleave address range, and an interleaving manner of a preset interleave controller The identification information of the slave corresponding to the first write address.
  • the first sending module 403 is configured to send the write data and the second write address to the slave according to the identifier information of the slave; wherein the slave is a DDR controller;
  • the second receiving module 404 is configured to receive a write feedback message sent by the slave, where the write feedback message is used to indicate whether the write data is successfully written;
  • the second sending module 405 is configured to send the write feedback message to the host.
  • the second sending module 405 includes: a first determining unit configured to determine whether the write feedback receiving logic module is idle; and a first sending unit configured to: if the write feedback receiving logic module is idle, the write feedback message Sent to the host. a second determining unit configured to If the write feedback logic module is not idle, after waiting for a preset time, determining whether the write feedback receiving logic module is idle; and the second sending unit is configured to: if the write feedback receiving logic module is idle, A feedback message is sent to the host.
  • a third determining module configured to determine bandwidth information of the write data path
  • a fourth determining module configured to determine response delay information of the write command, where the response delay of the write command is from sending data sent by the host to the first write address to sending a write feedback message to the host Time difference between
  • the first storage module is configured to store bandwidth information of the write data path and response delay information of the write command.
  • the first startup module is configured to start low power consumption if the read data and the read response message or the write feedback information sent by any of the slaves are not received, and the read address or the write address or the write data sent by the host is not received.
  • the timer starts counting;
  • a first shutdown module configured to receive no read data and read response messages and/or write feedback messages sent by any of the slaves if the timing of the low power timer reaches a low power timing threshold If the read address or write address or write data sent by the host is not received, its own control clock is turned off.
  • FIG. 5 is a schematic structural diagram of a fifth multi-channel DDR interleaving control apparatus according to an embodiment of the present invention.
  • the control apparatus 500 includes: a third receiving The module 501, the second determining module 502, the third sending module 503, the fourth receiving module 504, and the fourth sending module 505, wherein:
  • the third receiving module 501 is configured to receive a first read address sent by the host
  • the second determining module 502 is configured to determine the second read address corresponding to the first read address and the first slave device corresponding to the first read address according to the preset interleave control configuration information;
  • the third sending module 503 is configured to send the second read address to the first slave according to the identifier information of the first slave;
  • the fourth receiving module 504 is configured to receive the first read data and the first read response message sent by the first slave;
  • the fourth sending module 505 is configured to send the first read data and the first read response message to the host.
  • the fourth sending module 505 includes:
  • a third determining unit configured to determine whether the second read data and the second read response message sent by the second slave are received
  • a third sending unit configured to send the first read data and the first read response message to the host if the second read data and the second read response message sent by the second slave are not received.
  • a fourth determining unit configured to determine whether the time that the first slave waits is less than or equal to a preset response timeout threshold if the second read data and the second read response message sent by the second slave are received;
  • a fifth determining unit configured to determine whether the read priority of the first slave is higher than the read priority of the second slave if the time that the first slave waits is less than or equal to a preset response timeout threshold
  • a fourth sending unit configured to send the first read data and the first read response message to the host if the read priority of the first slave is higher than the read priority of the second slave.
  • a sixth determining unit configured to determine whether the port number of the first slave is smaller than the port of the second slave if the read priority of the first slave is the same as the read priority of the second slave number
  • the fifth sending unit is configured to send the first read data and the first read response message to the host if the port number of the first slave is smaller than the port number of the second slave.
  • a sixth sending unit configured to send the second read data and the second read response message to the host if the read priority of the first slave is lower than the read priority of the second slave;
  • a seventh determining unit configured to determine whether the third read data and the third read response message sent by the third slave are received
  • the seventh sending unit is configured to send the first read data and the first read response message to the host if the third read data and the second read response message sent by the third slave are not received.
  • the eighth sending unit is configured to send the second read data and the second read response message to the host if the time that the first slave waits is greater than a preset response timeout threshold;
  • the eighth determining unit is configured to determine whether the third read data and the third read response message sent by the third slave are received;
  • a ninth sending unit configured to send the first read data and the first read response message to the host if the third read data and the third read response message sent by the third slave are not received.
  • a fifth determining module configured to determine bandwidth information of the read data path
  • a sixth determining module configured to determine response delay information of the read command, where the response delay of the read command is from receiving the first read address sent by the host to sending the first read data to the host and the first The time difference between reading response messages;
  • the first storage module is configured to store bandwidth information of the read data path and response delay information of the read command.
  • the second startup module is configured to start low power consumption if the read data and the read response message or the write feedback information sent by any of the slaves are not received, and the read address or the write address or the write data sent by the host is not received.
  • the timer starts counting;
  • a second shutdown module configured to receive no read data and read response messages and/or write feedback messages sent by any of the slaves if the timing of the low power timer reaches a low power timing threshold If the read address or write address or write data sent by the host is not received, its own control clock is turned off.
  • each module included in the multi-channel DDR interleaving control device and each unit included in each module can be implemented by a processor in the DDR, and can also be implemented by a logic circuit; in the process of the embodiment.
  • the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).
  • the above multi-channel DDR interleaving control method is implemented in the form of a software function module, and is sold or used as a stand-alone product, it may also be stored in a computer readable storage medium.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • program codes such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • an embodiment of the present invention provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are configured to perform the multi-channel DDR interleaving control method provided above.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • Embodiments of the subject matter described in the specification can be implemented in digital electronic circuits or in computer software, firmware or hardware, including the structures disclosed in the specification and their structural equivalents, or One or more of its structural equivalents Combine.
  • Embodiments of the subject matter described in the specification can be implemented as one or more computer programs, ie, one or more computer program instructions modules, encoded onto one or more computer storage media for execution or control of data by a data processing device The operation of the processing device.
  • computer instructions can be encoded onto an artificially generated propagating signal (eg, a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode the information for transmission to a suitable receiver.
  • the device is executed by a data processing device.
  • the computer storage medium can be, or be included in, a computer readable storage device, a computer readable storage medium, a random or sequential access memory array or device, or a combination of one or more of the above.
  • the computer storage medium is not a propagated signal, the computer storage medium can be a source or a target of computer program instructions that are encoded in a manually generated propagated signal.
  • the computer storage medium can also be or be included in one or more separate components or media (eg, multiple CDs, disks, or other storage devices).
  • computer storage media can be tangible.
  • the operations described in the specification can be implemented as operations by data processing apparatus on data stored on or received from one or more computer readable storage devices.
  • client or “server” includes all types of devices, devices, and machines for processing data, including, for example, a programmable processor, a computer, a system on a chip, or a plurality or combination of the foregoing.
  • the device can include dedicated logic circuitry, such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Circuit
  • the apparatus can also include code to create an execution environment for the computer program of interest, for example, to constitute processor firmware, a protocol stack, a database management system, an operating system, a cross-platform operating environment, a virtual machine, or one or Multiple combinations.
  • the device and execution environment enables a variety of different computing model infrastructures, such as network services, distributed computing, and grid computing infrastructure.
  • a computer program (also referred to as a program, software, software application, script, or code) can be written in any programming language, including assembly or interpreted language, descriptive language, or procedural language, and can be in any form (including as an independent Program, or as a module, component, Subprograms, objects, or other units that are suitable for use in a computing environment.
  • a computer program can, but does not necessarily, correspond to a file in a file system.
  • the program can be stored in a portion of the file that holds other programs or data (eg, one or more scripts stored in the markup language document), in a single file dedicated to the program of interest, or in multiple collaborative files ( For example, storing one or more modules, submodules, or files in a code section).
  • the computer program can be deployed to be executed on one or more computers located at one site or distributed across multiple sites and interconnected by a communication network.
  • the processes and logic flows described in the specification can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating input data and generating output.
  • the above described processes and logic flows can also be performed by dedicated logic circuitry, and the apparatus can also be implemented as dedicated logic circuitry, such as an FPGA or ASIC.
  • processors suitable for the execution of a computer program include, for example, a general purpose microprocessor and a special purpose microprocessor, and any one or more processors of any type of digital computer.
  • a processor will receive instructions and data from a read only memory or a random access memory or both. The main elements of the calculation are the processor for performing the actions in accordance with the instructions and one or more memories for storing the instructions and data.
  • a computer also includes one or more mass storage devices (eg, magnetic disks, magneto-optical disks, or optical disks) for storing data, or is operatively coupled to receive data from or send data thereto, or Both are. However, the computer does not need to have such a device.
  • the computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio player or mobile video player, a game console, a global positioning system (GPS) receiver, or a mobile storage device.
  • PDA personal digital assistant
  • GPS global positioning system
  • Suitable devices for storing computer program instructions and data include all forms of non-volatile memory, media and storage devices, including, for example, semiconductor storage devices (eg, EPROM, EEPROM, and flash memory devices), magnetic disks (eg, internal hard drives or removable hard drives). ), magneto-optical disks, and CD-ROM and DVD-ROM discs.
  • the processor and memory can be powered by dedicated logic The path is supplemented or included in a dedicated logic circuit.
  • a computer including a display device, a keyboard, a pointing device (eg, a mouse, trackball, etc., or a touch screen, touch pad, etc.).
  • Display devices are, for example, cathode ray tubes (CRTs), liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), thin film transistors (TFTs), plasma, other flexible configurations, or any other monitor for displaying information to a user.
  • CTRs cathode ray tubes
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • TFTs thin film transistors
  • plasma other flexible configurations, or any other monitor for displaying information to a user.
  • the user is able to provide input to the computer through the keyboard and pointing device.
  • feedback provided to the user can be any form of sensory feedback, such as visual feedback, audible feedback, or haptic feedback; and input from the user can be in any form Received, including acoustic input, voice input, or touch input.
  • the computer can interact with the user by transmitting and receiving documents from the device used by the user; for example, transmitting the web page to a web browser on the user's client in response to a request received from the web browser.
  • Embodiments of the subject matter described in the specification can be implemented in a computing system.
  • the computing system includes a backend component (eg, a data server), or includes a middleware component (eg, an application server), or includes a front end component (eg, a client computer with a graphical user interface or web browser through which the user passes)
  • the end computer can interact with an embodiment of the subject matter described herein, or any combination of one or more of the above described backend components, middleware components, or front end components.
  • the components of the system can be interconnected by any form of digital data communication or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs) and wide area networks (WANs), interconnected networks (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks).
  • LANs local area networks
  • WANs wide area networks
  • interconnected networks e.g., the Internet
  • end-to-end networks
  • the features described in this application are implemented on a smart television module (or connected to a television module, hybrid television module, etc.).
  • the smart TV module can include processing circuitry configured to integrate more traditional television program sources (eg, program sources received via cable, satellite, air, or other signals) with Internet connectivity.
  • the smart TV module can be physically integrated into the television or can include Equipment such as set-top boxes, Blu-ray or other digital media players, game consoles, hotel television systems, and other ancillary equipment.
  • the smart TV module can be configured to enable viewers to search for and find videos, movies, pictures or other content on the network, on local cable channels, on satellite television channels, or on local hard drives.
  • a set top box (STB) or set top box unit (STU) may include an information-applicable device that includes a tuner and is coupled to the television set and an external source to tune the signal to be displayed on a television screen or other playback device.
  • the smart TV module can be configured to provide a home screen or a top screen including icons for a variety of different applications (eg, web browsers and multiple streaming services, connecting cable or satellite media sources, other network "channels", etc.).
  • the smart TV module can also be configured to provide electronic programming to the user.
  • a companion application of the smart television module can be run on the mobile computing device to provide the user with additional information related to the available programs, thereby enabling the user to control the smart television module and the like.
  • this feature can be implemented on a portable computer or other personal computer (PC), smart phone, other mobile phone, handheld computer, tablet PC, or other computing device.
  • the second write address corresponding to the first write address and the first write address are determined by receiving the write data sent by the host and the first write address, and then according to the preset interleave control configuration information. And identifying the slave information, and then sending the write data and the second write address to the slave according to the identifier information of the slave, and receiving a write feedback message sent by the slave, and finally The write feedback message is sent to the host.
  • Interleave control configuration information such as interleave size, interleaving mode, etc. can be set in advance, thus increasing the flexibility of interleaving control.

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Abstract

一种多通道DDR交织控制方法及装置、存储介质，其中，所述方法包括：接收主机发送的写数据和第一写地址(S101)；根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息(S102)；根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机(S103)；接收所述从机发送的写反馈消息(S104)，其中，所述写反馈消息用于表征所述写数据是否写成功；将所述写反馈消息发送给所述主机(S105)。

Description

一种多通道DDR交织控制方法及装置、存储介质
相关申请的交叉引用
本申请基于申请号为201611192741.X、申请日为2016年12月21日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以全文引入的方式引入本申请。
技术领域
本发明涉及存储技术领域，尤其涉及一种多通道DDR交织控制方法及装置、存储介质。
背景技术
现在的芯片一般都集成了中央处理器(Central Processor Unit，CPU)、直接存储器访问(Direct Memory Access，DMA)、总线互联、存储器、高速外设和低速外设等组件。随着集成电路工艺的不断提高，芯片的运行频率和性能要求也越来越高，芯片需要的带宽也越来越大，因此常规的双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，DDR SDRAM)子系统已经无法满足系统高带宽的需求，越来越多的片上系统(System On Chip，SoC)采用双(多)通道DDR作为动态存储的解决方案，与传统单通道DDR相比具有理论带宽高、传输效率高等特点。
目前实现多通道DDR存储系统的数据流多使用的片上网络(Network On Chip，NOC)产品进行传输交织控制，该产品具有参数丰富可配置、命令调度能力强等特点，但也存在授权费用高、命令延迟大、面积大、交织方式固定等缺点。
发明内容
为解决现有存在的技术问题，本发明实施例提供一种多通道DDR交织控制方法及装置、存储介质，解决了现有技术中多通道DDR存储器交织控制装置延迟大、面积、交织方式固定的问题，达到了延迟小、面积小、交织方式灵活可配置、功耗低的技术效果。
本发明实施例的技术方案是这样实现的：
本发明实施例提供一种多通道DDR交织控制方法，所述方法包括：
接收主机发送的写数据和第一写地址；其中，所述主机为总线互联模块；
根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息；
根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机；其中，所述从机为DDR控制器；
接收所述从机发送的写反馈消息，其中，所述写反馈消息用于表征所述写数据是否写成功；
将所述写反馈消息发送给所述主机。
本发明实施例提供一种多通道DDR交织控制方法，所述方法包括：
接收主机发送的第一读地址；
根据预先设置的交织控制配置信息，确定所述第一读地址对应的第二读地址和所述第一读地址对应的第一从机的标识信息；
根据所述第一从机的标识信息，将所述第二读地址发送给第一从机；
接收所述第一从机发送的第一读数据和第一读响应消息；
将所述第一读数据和第一读响应消息发送给所述主机。
本发明实施例提供一种多通道DDR交织控制装置，所述装置包括：
第一接收模块，配置为接收主机发送的写数据和第一写地址；其中， 所述主机为总线互联模块；
第一确定模块，配置为根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息；
第一发送模块，配置为根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机；其中，所述从机为DDR控制器；
第二接收模块，配置为接收所述从机发送的写反馈消息，其中，所述写反馈消息用于表征所述写数据是否写成功；
第二发送模块，配置为将所述写反馈消息发送给所述主机。
本发明实施例提供一种多通道DDR交织控制装置，所述装置包括：
第三接收模块，配置为接收主机发送的第一读地址；
第二确定模块，配置为根据预先设置的交织控制配置信息，确定所述第一读地址对应的第二读地址和所述第一读地址对应的第一从机的标识信息；
第三发送模块，配置为根据所述第一从机的标识信息，将所述第二读地址发送给第一从机；
第四接收模块，配置为接收所述第一从机发送的第一读数据和第一读响应消息；
第四发送模块，配置为将所述第一读数据和第一读响应消息发送给所述主机。
本发明实施例提供一种计算机可读存储介质，其上存储有计算机程序，其特征在于，该计算机程序被处理器执行时实现上述的多通道DDR交织控制方法的步骤。
本发明实施例所提供的多通道DDR交织控制方法及装置、存储介质，通过接收主机发送的写数据和第一写地址，再根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的 从机的标识信息，然后根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机，并接收所述从机发送的写反馈消息，最后将所述写反馈消息发送给所述主机。由于诸如交织大小、交织方式等交织控制配置信息可以提前进行设置，这样，增加了交织控制的灵活性。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本发明实施例一多通道DDR交织控制方法的实现流程示意图；
图2为本发明实施例二多通道DDR交织控制方法的实现流程示意图；
图3-1为本发明实施例三多通道DDR交织控制装置的组成结构示意图；
图3-2为本发明实施例三多通道DDR交织控制方法的实现流程示意图
图4为本发明实施例四多通道DDR交织控制装置的组成结构示意图；
图5为本发明实施例五多通道DDR交织控制装置的组成结构示意图。
具体实施方式
下面结合附图和具体实施例对本发明的技术方案进一步详细阐述。
为解决背景技术中存在的技术问题，本发明实施例提供一种多通道DDR交织控制方法，应用于多通道DDR，所述多通道DDR至少包括：处理器、交织控制器、一个主机和至少一个从机。图1为本发明实施例一多通道DDR交织控制方法的实现流程示意图，如图1所示，所述方法包括以下步骤：
步骤S101，接收主机发送的写数据和第一写地址；
这里，步骤S101可以是由交织控制装置来实现的，在实际的应用中，该交织控制装置可以为交织控制器。所述主机可以为总线互联模块，也即总线Matrix，目前常用的是网络适配器(Network Interface Card，NIC)400。
步骤S102，根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息；
这里，处理器会根据系统的实际使用情况，提前配置交织控制器的一些交织控制配置信息，比如交织大小、非交织地址范围、交织方式等。交织控制器根据预先设置的交织控制配置信息，可以确定出所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息。其中，第二写地址为将第一写地址根据所述交织控制配置信息重新映射得到的写地址，也是写数据要写入的DDR的物理地址。
步骤S103，根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机；
这里，所述从机可以为DDR控制器；所述从机接收到所述写数据和所述第二写地址后，根据所述第二写地址将所述写数据写入到DDR存储单元中，并向交织控制器发送写反馈信息。
步骤S104，接收所述从机发送的写反馈消息；
这里，所述写反馈消息用于表征所述写数据是否写成功。
步骤S105，将所述写反馈消息发送给所述主机。
这里，交织控制器接收到从机发送的写反馈消息后，将所述写反馈消息发送给所述主机。
在本发明的其他实施例中，所述步骤S105包括：判断写反馈接收逻辑模块是否空闲；
如果所述写反馈接收逻辑模块空闲，将所述写反馈消息发送给所述主机。
如果所述写反馈逻辑模块不空闲，则等待预设的时间后，判断所述写反馈接收逻辑模块是否空闲；
如果所述写反馈接收逻辑模块空闲，将所述写反馈消息发送给所述主机。
在所述步骤S105之后，所述方法还包括：通过确定写数据通道的带宽信息；
确定写命令的响应时延信息；这里，所述写命令的响应时延为从接收到主机发送的写数据和第一写地址到向所述主机发送写反馈消息之间的时间差；存储所述写数据通道的带宽信息和所述写命令的响应时延信息，来检测写数据通路的带宽信息，并记录写命令的响应时延并且在预设的低功耗计时阈值时间内如果没有任何数据或消息传输的时候，关断自身的控制时钟，以降低功耗。
在本发明实施提供的多通道DDR交织控制方法中，通过接收主机发送的写数据和第一写地址，再根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息，然后根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机，并接收所述从机发送的写反馈消息，最后将所述写反馈消息发送给所述主机。由于诸如交织大小、交织方式等交织控制配置信息可以提前进行设置，这样，增加了交织控制的灵活性。并且在预设的低功耗计时阈值时间内如果没有任何数据或消息传输的时候，关断自身的控制时钟，如此能够降低功耗。
基于前述的实施例，本发明实施例再提供一种多通道DDR交织控制方法，应用于多通道DDR的交织控制器，所述多通道DDR至少包括：交织控制器、一个主机和至少一个从机。图2为本发明实施例二多通道DDR交织控制方法的实现流程示意图，如图2所示，所述方法包括以下步骤：
步骤S201，交织控制器接收主机发送的第一读地址；
步骤S202，所述交织控制器根据预先设置的交织控制配置信息，确定所述第一读地址对应的第二读地址和所述第一读地址对应的第一从机的标识信息；
这里，处理器会根据系统的实际使用情况，提前配置交织控制器的一些交织控制配置信息，比如交织大小、非交织地址范围、交织方式等。交织控制器根据预先设置的交织控制配置信息，可以确定出所述第一读地址对应的第二读地址和所述第一读地址对应的从机的标识信息。第二读地址为第一读地址根据所述交织控制配置信息重新映射的读地址，也就是要读取的数据所在DDR中的物理地址。
步骤S203，所述交织控制器根据所述第一从机的标识信息，将所述第二读地址发送给第一从机；
这里，所述第一从机接收到所述第二读地址后，按照所述第二读地址从DDR的存储单元中读取出第一读数据，并将所述第一读数据和第一读响应消息发送给所述交织控制器。
步骤S204，所述交织控制器接收所述第一从机发送的第一读数据和第一读响应消息；
步骤S205，所述交织控制器判断是否接收到第二从机发送的第二读数据和第二读响应消息；是则进入步骤S206，否则进入步骤S208；
这里，因为多通道DDR有至少一个从机，当存在多个从机的时候，当有其他从机在同一时刻也要向所述交织控制器发送读数据和读响应消息时(比如是第二从机要向所述交织控制器发送第二读数据和第二读响应消息)，需要判断是先将第一读数据和第一读响应消息发送给所述交织控制器，还是先将第二读数据和第二读响应消息发送给所述交织控制器。
步骤S206，所述交织控制器判断所述第一从机等待的时间是否小于等 于预设的响应超时阈值；是则进入步骤S207，否则进入步骤S211；
步骤S207，所述交织控制器判断所述第一从机的读优先级是否高于第二从机的读优先级；是则，进入步骤S208，否则进入步骤S209；
步骤S208，所述交织控制器将所述第一读数据和第一读响应消息发送给所述主机。
步骤S209，所述交织控制器判断所述第一从机的读优先级与第二从机的读优先级是否相同；是则进入步骤S210，否则进入步骤S211；
步骤S210，所述交织控制器判断所述第一从机的端口号是否小于所述第二从机的端口号；是则进入步骤S208，否则进入步骤S211；
步骤S211，所述交织控制器将所述第二读数据和第二读响应消息发送给所述主机；然后进入步骤S205。
在本发明实施例中，所述方法还包括：通过确定读数据通道的带宽信息；确定读命令的响应时延信息；这里，所述读命令的响应时延为从接收到主机发送的第一读地址到向所述主机发送完第一读数据和第一读响应消息之间的时间差，也就是从接收到主机发送的第一读地址到向所述主机发送完最后一笔读数据之间的时间差。存储所述读数据通道的带宽信息和所述读命令的响应时延信息，来检测读数据通路的带宽信息，并记录读命令的响应时延。
在本发明及其他实施例中，所述方法还包括：
如果没有接收到任一从机发送的读数据和读响应消息或写反馈信息，并且也没有接收到主机发送的读地址或写地址或写数据，则启动低功耗计时器开始计时；
如果当低功耗计时器的计时时间达到低功耗计时阈值时，仍没有接收到任一从机发送的读数据和读响应消息和/或写反馈消息并且也没有接收到主机发送的读地址或写地址或写数据，则关断自身的控制时钟。
这样，在预设的低功耗计时阈值时间内如果没有读请求或者写请求并且没有正在进行的读写操作，关断自身的控制时钟，以降低功耗。
在本发明实施例提供的多通道DDR交织控制方法中，通过接收主机发送的第一读地址，再根据预先设置的交织控制配置信息，确定所述第一读地址对应的第二读地址和所述第一读地址对应的第一从机的标识信息，然后再根据所述第一从机的标识信息，将所述第二读地址发送给第一从机，接收所述第一从机发送的第一读数据和第一读响应消息，并将所述第一读数据和第一读响应消息发送给所述主机。由于诸如交织大小、交织方式等交织控制配置信息可以提前进行设置，这样，增加了交织控制的灵活性。并且在预设的低功耗计时阈值时间内如果没有任何数据或消息传输的时候，关断自身的控制时钟，如此能够降低功耗。
本发明实施例先提供一种多通道DDR的交织控制装置，基于所述交织控制装置本发明实施例又提供了一种多通道DDR的交织控制方法。
图3-1为本发明实施例三多通道DDR交织控制装置的组成结构示意图，如图3-1所示，所述装置包括：读数据、读响应控制301、读地址映射控制302、写地址映射、写数据、写反馈控制303、总线监控304和寄存器配置305，其中：
所述读数据、读响应控制301，配置为将各从机返回的读数据、读响应做判决后返回给主机。
所述读地址映射控制302，配置为按照交织配置将主机发送过来的读地址映射到相应的从机。
所述写地址映射、写数据、写反馈控制303，配置为按照交织配置将主机发送过来的写地址映射到相应的从机，并将写数据发送到对应地址的从机，且从机接收写反馈给主机。
所述总线监控304，检测读数据通路、写数据通路的带宽信息、多个读 写命令同时执行的信息(outstanding信息)，并记录读写命令的各自平均响应延时，这些信息可以存在寄存器配置105供处理器获取。
所述寄存器配置305：完成交织控制的各项配置，包括交织大小、交织方式、非交织区域、读数据通道超时阈值、忽略交织控制、低功耗计时阈值等，寄存总线监测信息。
根据以上多通道DDR控制装置的组成结构的说明可以看出，本发明实施例提供的多通道DDR控制装置，主要有以下功能：
(1)交织控制器配置：完成交织控制的各项配置，包括交织大小、交织方式、非交织区域、读数据通道超时阈值、忽略交织控制、低功耗计时阈值等。
(2)写通道控制：完成写通道地址映射，写优先级寄存，改进的微控制器总线架构(Advanced Microcontroller Bus Architecture，AMBA)，改进的高级的可扩展接口(Advanced eXtensible Interface，AXI)写标识(Identification，ID)寄存，写数据发送，写反馈接收。
(3)读通道控制：完成读通道地址映射，读优先级寄存，AMBA、AXI协议读ID寄存，读数据、读响应返回控制。
(4)读数据、读响应返回控制：根据读优先级有高到低向主机返回读数据，优先级相同则根据从机端口序号顺序有低到高返回读数据，如果某个从机占用读数据通道时间超过读数据通道超时阈值，则响应该从机以外的其他从机的读数据。
(5)低功耗控制：在一段时间没有读请求或者写请求并且没有正在进行的读写操作，则自动关断交织控制器时钟。
(6)总线监控：监控总线的带宽信息和传输延时信息。
基于所述多通道DDR交织控制装置，本发明实施例再提供一种多通道DDR交织控制方法，图3-2为本发明实施例三多通道DDR交织控制方法的 实现流程示意图，如图3-2所示，所述方法包括以下步骤：
步骤S301，处理器配置交织控制器的寄存器，如交织大小的寄存器、交织方式的寄存器、非交织地址范围的寄存器等；
步骤S302，主机发送写地址、写数据到所述交织控制器；
步骤S303，所述交织控制器根据设置好的交织大小、交织方式、非交织地址范围等将写地址映射到相应从机，并发送写数据到该从机；
步骤S304，交织控制器接收该从机返回的写反馈；
步骤S305，所述交织控制器判断写反馈接收逻辑是否正忙；
步骤S306，如果写反馈接收逻辑空闲，则所述交织控制器将写反馈返回给主机；
步骤S307，如果写反馈接收逻辑正忙，则等待空闲后再回到步骤S305；
步骤S308，主机发送读地址到所述交织控制器；
步骤S309，所述交织控制器根据设置好的交织大小、交织方式、非交织地址范围等将读地址映射到相应从机；
步骤S310，所述交织控制器接收该从机返回的读数据和读响应；
步骤S311，所述交织控制器判断同一时刻是否有其他从机返回读数据和读响应；
步骤S312，如果同一时刻有其他从机返回读数据和读响应，则所述交织控制器判断该从机等待的时间是否小于等于响应超时阈值；是则进入步骤S313，否则进入步骤S316；
步骤S313，所述交织控制器判断该从机的读优先级是否比其他从机的读优先级高；是则进入步骤S314，否则进入步骤S315；
步骤S314，所述交织控制器返回读数据和读响应到主机；
步骤S315，所述交织控制器判断该从机与其他从机是否优先级相同并且从机端口号小于其他从机；是则进入步骤S314，否则进入步骤S316；
步骤S316，所述交织控制器等待其他从机将读数据和读响应返回给主机后，再回到步骤S311。
这里，交织控制器可重复步骤S302-S307进行写操作，重复步骤S308-S316进行读操作。
在本发明实施例提供的多通道DDR交织控制方法中，处理器提前配置交织控制器的交织大小、非交织地址范围、交织方式等；交织大小可以为64字节(Byte，B)、128B、256B、512B、1千字节(Kilo Byte，KB)、2KB、4KB；非交织地址范围为一段连续地址(KB对齐)，可以约定该地址只会映射到固定的从机，不做交织访存；交织方式约定为交织地址范围内不同的交织地址映射形式，交织方式在不同应用场景下的带宽利用率不同。
写地址数据流根据交织设置发送至相应从机DDR写通道，根据写地址的映射发送写数据到从机，从机侧将写反馈发送给主机；
读地址数据流根据交织设置发送至相应从机DDR读通道，从机侧接收读数据并按照一定的次序反馈给主机，从机侧将读响应和读数据发送给主机。
其中，写通道包含：1，写地址通道：主机发送写地址到交织控制器，交织控制器根据交织配置，完成地址映射并发送映射后的写地址到相应从机；2，写数据通道：根据映射后的写地址，发送写数据到相应从机；3，写反馈通道：从机根据写地址将写反馈返回给主机。
读通道包括：1，读地址通道：主机发送读地址到交织控制器，交织控制器根据交织配置，完成地址映射并发送映射后的读地址到相应从机；2，读数据、读响应通道：从机接收读数据，并根据各个从机读数据的优先级、从机的读数据超时计时器、各个从机的轮询响应控制等情况依次返回读数据、读响应。
在本发明实施例中，交织控制器的交织大小、交织方式、非交织地址 范围等参数可以提前进行配置，增加了灵活性。完成交织配置后，主机就可以通过交织控制器完成对从机多通道DDR进行读写交织访问，读写的信息按照规则到达从机并返回相关信息到主机。本发明实施例提供的交织控制方法及控制装置具有延迟小、面积小、交织方式灵活可配置、功耗低等特点。
本发明实施例提供一种多通道DDR交织控制装置，图4为本发明实施例四多通道DDR交织控制装置的组成结构示意图，如图4所示，所述控制装置包括：第一接收模块401、第一确定模块402、第一发送模块403、第二接收模块404和第二发送模块405，其中：
所述第一接收模块401，配置为接收主机发送的写数据和第一写地址；其中，所述主机为总线互联模块；
所述第一确定模块402，配置为根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息；
这里，所述第一确定模块402包括：第一确定单元，配置为根据预先设置的交织控制器的交织大小、非交织地址范围、交织方式确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息。
所述第一发送模块403，配置为根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机；其中，所述从机为DDR控制器；
所述第二接收模块404，配置为接收所述从机发送的写反馈消息，其中，所述写反馈消息用于表征所述写数据是否写成功；
所述第二发送模块405，配置为将所述写反馈消息发送给所述主机。
这里，所述第二发送模块405包括：第一判断单元，配置为判断写反馈接收逻辑模块是否空闲；第一发送单元，配置为如果所述写反馈接收逻辑模块空闲，将所述写反馈消息发送给所述主机。第二判断单元，配置为 如果所述写反馈逻辑模块不空闲，则等待预设的时间后，判断所述写反馈接收逻辑模块是否空闲；第二发送单元，配置为如果所述写反馈接收逻辑模块空闲，将所述写反馈消息发送给所述主机。
本发明实施例提供的多通道DDR交织控制装置还包括：
第三确定模块，配置为确定写数据通路的带宽信息；
第四确定模块，配置为确定写命令的响应时延信息；其中，所述写命令的响应时延为从接收到主机发送的写数据和第一写地址到向所述主机发送写反馈消息之间的时间差；
第一存储模块，配置为存储所述写数据通路的带宽信息和所述写命令的响应时延信息。
第一启动模块，配置为如果没有接收到任一从机发送的读数据和读响应消息或写反馈信息，并且也没有接收到主机发送的读地址或写地址或写数据，则启动低功耗计时器开始计时；
第一关断模块，配置为如果当低功耗计时器的计时时间达到低功耗计时阈值时，仍没有接收到任一从机发送的读数据和读响应消息和/或写反馈消息并且也没有接收到主机发送的读地址或写地址或写数据，则关断自身的控制时钟。
这里需要指出的是：以上多通道DDR交织控制装置实施例的描述，与上述方法实施例的描述是类似的，具有同方法实施例相似的有益效果。对于本发明多通道DDR交织控制装置实施例中未披露的技术细节，请参照本发明方法实施例的描述而理解。
本发明实施例再提供一种多通道DDR交织控制装置，图5为本发明实施例五多通道DDR交织控制装置的组成结构示意图，如图5所示，所述控制装置500包括：第三接收模块501、第二确定模块502、第三发送模块503、第四接收模块504和第四发送模块505，其中：
所述第三接收模块501，配置为接收主机发送的第一读地址；
所述第二确定模块502，配置为根据预先设置的交织控制配置信息，确定所述第一读地址对应的第二读地址和所述第一读地址对应的第一从机的标识信息；
所述第三发送模块503，配置为根据所述第一从机的标识信息，将所述第二读地址发送给第一从机；
所述第四接收模块504，配置为接收所述第一从机发送的第一读数据和第一读响应消息；
所述第四发送模块505，配置为将所述第一读数据和第一读响应消息发送给所述主机。
这里，所述第四发送模块505包括：
第三判断单元，配置为判断是否接收到第二从机发送的第二读数据和第二读响应消息；
第三发送单元，配置为如果没有接收到第二从机发送的第二读数据和第二读响应消息，则将所述第一读数据和第一读响应消息发送给所述主机。
第四判断单元，配置为如果接收到第二从机发送的第二读数据和第二读响应消息，判断所述第一从机等待的时间是否小于等于预设的响应超时阈值；
第五判断单元，配置为如果所述第一从机等待的时间小于等于预设的响应超时阈值，判断所述第一从机的读优先级是否高于第二从机的读优先级；
第四发送单元，配置为如果所述第一从机的读优先级高于第二从机的读优先级，则将所述第一读数据和第一读响应消息发送给所述主机。
第六判断单元，配置为如果所述第一从机的读优先级与第二从机的读优先级相同，则判断所述第一从机的端口号是否小于所述第二从机的端口 号；
第五发送单元，配置为如果所述第一从机的端口号小于所述第二从机的端口号，则将所述第一读数据和第一读响应消息发送给所述主机。
第六发送单元，配置为如果所述第一从机的读优先级低于所述第二从机的读优先级，将所述第二读数据和第二读响应消息发送给所述主机；
第七判断单元，配置为判断是否接收到第三从机发送的第三读数据和第三读响应消息；
第七发送单元，配置为如果没有接收到第三从机发送的第三读数据和第二读响应消息，则将所述第一读数据和第一读响应消息发送给所述主机。
第八发送单元，配置为如果所述第一从机等待的时间大于预设的响应超时阈值，将所述第二读数据和第二读响应消息发送给所述主机；
第八判断单元，配置为判断是否接收到第三从机发送的第三读数据和第三读响应消息；
第九发送单元，配置为如果没有接收到第三从机发送的第三读数据和第三读响应消息，则将所述第一读数据和第一读响应消息发送给所述主机。
本发明实施例提供的多通道DDR交织控制装置还包括：
第五确定模块，配置为确定读数据通路的带宽信息；
第六确定模块，配置为确定读命令的响应时延信息；其中，所述读命令的响应时延为从接收到主机发送的第一读地址到向所述主机发送第一读数据和第一读响应消息之间的时间差；
第一存储模块，配置为存储所述读数据通路的带宽信息和所述读命令的响应时延信息。
第二启动模块，配置为如果没有接收到任一从机发送的读数据和读响应消息或写反馈信息，并且也没有接收到主机发送的读地址或写地址或写数据，则启动低功耗计时器开始计时；
第二关断模块，配置为如果当低功耗计时器的计时时间达到低功耗计时阈值时，仍没有接收到任一从机发送的读数据和读响应消息和/或写反馈消息并且也没有接收到主机发送的读地址或写地址或写数据，则关断自身的控制时钟。
这里需要指出的是：以上多通道DDR交织控制装置实施例的描述，与上述方法实施例的描述是类似的，具有同方法实施例相似的有益效果。对于本发明多通道DDR交织控制装置实施例中未披露的技术细节，请参照本发明方法实施例的描述而理解。
本发明实施例中多通道DDR交织控制装置所包括的各模块以及各模块所包括的各单元，都可以通过DDR中的处理器来实现，当然也可通过逻辑电路实现；在实施例的过程中，处理器可以为中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)或现场可编程门阵列(FPGA)等。
需要说明的是，本发明实施例中，如果以软件功能模块的形式实现上述的多通道DDR交织控制方法，并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read Only Memory)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
对应地，本发明实施例提供一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令配置为执行上述提供的多通道DDR交织控制方法。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
需要说明的是，说明书中描述的主题的实施方式和操作能够以数字电子电路或者以计算机软件、固件或硬件实现，其中包括本说明书中所公开的结构及其结构等效，或者采用这些结构及其结构等效中的一个或多个的 结合。说明书中所描述的主题的实施方式能够被实现为一个或多个计算机程序，即一个或多个计算机程序指令模块，其编码到一个或多个计算机存储介质上以由数据处理装置执行或者控制数据处理装置的操作。替选地或附加地，计算机指令能够被编码到人工生成的传播信号(例如机器生成的电信号、光信号或电磁信号)上，该信号被生成用于对信息编码以发送到合适的接收机装置由数据处理装置执行。计算机存储介质能够是或包含在计算机可读存储设备、计算机可读存储载体，随机或顺序访问存储阵列或设备、或者以上各项中的一个或多个的结合之中。而且，虽然计算机存储介质不是传播信号，但是计算机存储介质能够是被编码在人工生成的传播信号中的计算机程序指令的源或目标。计算机存储介质还能够是或者包含在一个或多个独立的组件或媒体(例如，多个CD、磁盘或其它存储设备)中。因此，计算机存储介质可以是有形的。
说明书中描述的操作能够被实现为由数据处理装置对存储在一个或多个计算机可读存储设备上或从其它源接收的数据进行的操作。
术语“客户端”或“服务器”包括用于处理数据的所有类型的装置、设备和机器，例如包括可编程处理器、计算机、片上系统或前述各项中的多个或结合。装置能够包括专用逻辑电路，例如，现场可编程门阵列(FPGA)或专用集成电路(ASIC)。除硬件之外，装置还能够包括创建用于所关注计算机程序的执行环境的代码，例如，构成处理器固件、协议栈、数据库管理系统、操作系统、跨平台运行环境、虚拟机或其一个或多个的结合。装置和执行环境能够实现各种不同的计算模型基础架构，诸如网络服务、分布式计算和网格计算基础架构。
计算机程序(也被称为程序、软件、软件应用、脚本或代码)能够以任何编程语言形式(包括汇编语言或解释语言、说明性语言或程序语言)书写，并且能够以任何形式(包括作为独立程序，或者作为模块、组件、 子程序、对象或其它适用于计算环境中的单元)部署。计算机程序可以但非必要地对应于文件系统中的文件。程序能够被存储在文件的保存其它程序或数据(例如，存储在标记语言文档中的一个或多个脚本)的部分中，在专用于所关注程序的单个文件中，或者在多个协同文件(例如，存储一个或多个模块、子模块或代码部分的文件)中。计算机程序能够被部署为在一个或多个计算机上执行，该一个或多个计算机位于一个站点处，或者分布在多个站点中且通过通信网络互连。
说明书中描述的过程和逻辑流能够由一个或多个可编程处理器执行，该一个或多个可编程处理器执行一个或多个计算机程序以通过操作输入数据和生成输出来执行动作。上述过程和逻辑流还能够由专用逻辑电路执行，并且装置还能够被实现为专用逻辑电路，例如，FPGA或ASIC。
适用于执行计算机程序的处理器例如包括通用微处理器和专用微处理器，以及任何数字计算机类型的任何一个或多个处理器。通常来说，处理器会从只读存储器或随机访问存储器或以上两者接收指令和数据。计算的主要元件是用于按照指令执行动作的处理器以及一个或多个用于存储指令和数据的存储器。通常来说，计算机还会包括一个或多个用于存储数据的大容量存储设备(例如，磁盘、磁光盘、或光盘)，或者操作地耦接以从其接收数据或向其发送数据，或者两者均是。然而，计算机不需要具有这样的设备。而且，计算机能够被嵌入在另一设备中，例如，移动电话、个人数字助手(PDA)、移动音频播放器或移动视频播放器、游戏控制台、全球定位系统(GPS)接收机或移动存储设备(例如，通用串行总线(USB)闪盘)，以上仅为举例。适用于存储计算机程序指令和数据的设备包括所有形式的非易失性存储器、媒体和存储设备，例如包括半导体存储设备(例如，EPROM、EEPROM和闪存设备)、磁盘(例如，内部硬盘或移动硬盘)、磁光盘、以及CD-ROM和DVD-ROM盘。处理器和存储器能够由专用逻辑电 路补充或者包含到专用逻辑电路中。
为了提供与用户的交互，说明书中描述的主题的实施方式能够在计算机上实现，该计算机包括显示设备、键盘、指向设备(例如，鼠标、轨迹球等，或触摸屏、触摸板等)。显示设备例如为阴极射线管(CRT)、液晶显示器(LCD)、有机发光二极管(OLED)、薄膜晶体管(TFT)、等离子、其它柔性配置、或者用于向用户显示信息的任何其它监视器。用户能够过键盘和指向设备向计算机提供输入。其它类型的设备也能够用于提供与用户的交互；例如，提供给用户的反馈能够是任何形式的感官反馈，例如，视觉反馈、听觉反馈、或触觉反馈；并且来自用户的输入能够以任何形式被接收，包括声学输入、语音输入或触摸输入。此外，计算机能够通过向用户使用的设备发送文档以及从该设备接收文档来与用户交互；例如，响应于从网页浏览器接收的请求将网页发送到用户的客户端上的网页浏览器。
说明书中描述的主题的实施方式能够以计算系统来实现。该计算系统包括后端组件(例如，数据服务器)，或者包括中间件组件(例如，应用服务器)，或者包括前端组件(例如，具有图形用户接口或网页浏览器的客户端计算机，用户通过该客户端计算机能够与本申请描述的主题的实施方式交互)，或者包括上述后端组件、中间件组件或前端组件中的一个或多个的任何结合。系统的组件能够通过任何数字数据通信形式或介质(例如，通信网络)来互连。通信网络的示例包括局域网(LAN)和广域网(WAN)、互连网络(例如，互联网)以及端对端网络(例如，自组织端对端网络)。
本申请中描述的特征在智能电视模块上(或连接电视模块、混合电视模块等)实现。智能电视模块可以包括被配置成为互联网连接性集成更多传统电视节目源(例如，经由线缆、卫星、空中或其它信号接收的节目源)的处理电路。智能电视模块可以被物理地集成到电视机中或者可以包括独 立的设备，例如，机顶盒、蓝光或其它数字媒体播放器、游戏控制台、酒店电视系统以及其它配套设备。智能电视模块可以被配置为使得观看者能够搜索并找到在网络上、当地有线电视频道上、卫星电视频道上或存储在本地硬盘上的视频、电影、图片或其它内容。机顶盒(STB)或机顶盒单元(STU)可以包括信息适用设备，信息适用设备包括调谐器并且连接到电视机和外部信号源上，从而将信号调谐成之后将被显示在电视屏幕或其它播放设备上的内容。智能电视模块可以被配置成为多种不同的应用(例如，网页浏览器和多个流媒体服务、连接线缆或卫星媒体源、其它网络“频道”等)提供家用屏幕或包括图标的顶级屏幕。智能电视模块还可以被配置成为用户提供电子节目。智能电视模块的配套应用可以在移动计算设备上运行以向用户提供与可用节目有关的附加信息，从而使得用户能够控制智能电视模块等。在替选实施例中，该特征可以被实现在便携式计算机或其它个人计算机(PC)、智能手机、其它移动电话、手持计算机、平板PC或其它计算设备上。
虽然说明书包含许多具体的实施细节，但是这些实施细节不应当被解释为对任何权利要求的范围的限定，而是对专用于特定实施方式的特征的描述。说明书中在独立实施方式前后文中描述的特定的特征同样能够以单个实施方式的结合中实现。相反地，单个实施方式的上下文中描述的各个特征同样能够在多个实施方式中单独实现或者以任何合适的子结合中实现。而且，尽管特征可以在上文中描述为在特定结合中甚至如最初所要求的作用，但是在一些情况下所要求的结合中的一个或多个特征能够从该结合中去除，并且所要求的结合可以为子结合或者子结合的变型。
类似地，虽然在附图中以特定次序描绘操作，但是这不应当被理解为要求该操作以所示的特定次序或者以相继次序来执行，或者所示的全部操作都被执行以达到期望的结果。在特定环境下，多任务处理和并行处理可 以是有利的。此外，上述实施方式中各个系统组件的分离不应当被理解为要求在全部实施方式中实现该分离，并且应当理解的是所描述的程序组件和系统通常能够被共同集成在单个软件产品中或被封装为多个软件产品。
因此，已经对主题的特定实施方式进行了描述。其它实施方式在以下权利要求的范围内。在一些情况下，权利要求中所限定的动作能够以不同的次序执行并且仍能够达到期望的结果。此外，附图中描绘的过程并不必须采用所示出的特定次序、或相继次序来达到期望的结果。在特定实施方式中，可以使用多任务处理或并行处理。
工业实用性
本发明实施例中，通过接收主机发送的写数据和第一写地址，再根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息，然后根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机，并接收所述从机发送的写反馈消息，最后将所述写反馈消息发送给所述主机。由于诸如交织大小、交织方式等交织控制配置信息可以提前进行设置，这样，增加了交织控制的灵活性。

Claims (17)

  1. 一种多通道双倍速率同步动态随机存储器DDR的交织控制方法，所述方法包括：
    接收主机发送的写数据和第一写地址；
    根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息，其中，第二写地址为将第一写地址根据所述交织控制配置信息进行映射得到的写地址；
    根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机；
    接收所述从机发送的写反馈消息，其中，所述写反馈消息用于表征所述写数据是否写成功；
    将所述写反馈消息发送给所述主机。
  2. 根据权利要求1中所述的方法，所述根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息，包括：
    根据预先设置的交织控制器的交织大小、非交织地址范围、交织方式确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息。
  3. 根据权利要求1中所述的方法，所述将所述写反馈消息发送给所述主机，包括：
    判断写反馈接收逻辑模块是否空闲；
    如果所述写反馈接收逻辑模块空闲，将所述写反馈消息发送给所述主机。
  4. 根据权利要求3中所述的方法，所述方法还包括：
    如果所述写反馈逻辑模块不空闲，则等待预设的时间后，判断所述 写反馈接收逻辑模块是否空闲；
    如果所述写反馈接收逻辑模块空闲，将所述写反馈消息发送给所述主机。
  5. 根据权利要求1中所述的方法，所述方法还包括：
    确定写数据通道的带宽信息；
    确定写命令的响应时延信息；其中，所述写命令的响应时延为从接收到主机发送的写数据和第一写地址到向所述主机发送写反馈消息之间的时间差；
    存储所述写数据通道的带宽信息和所述写命令的响应时延信息。
  6. 一种多通道双倍速率同步动态随机存储器DDR的交织控制方法，所述方法包括：
    接收主机发送的第一读地址；
    根据预先设置的交织控制配置信息，确定所述第一读地址对应的第二读地址和所述第一读地址对应的第一从机的标识信息，其中第二读地址为将第一读地址根据所述交织控制配置信息进行映射得到的读地址；
    根据所述第一从机的标识信息，将所述第二读地址发送给第一从机；
    接收所述第一从机发送的第一读数据和第一读响应消息；
    将所述第一读数据和发送给所述主机。
  7. 根据权利要求6中所述的方法，所述将所述第一读数据和第一读响应消息发送给所述主机，包括：
    判断是否接收到第二从机发送的第二读数据和第二读响应消息；其中，所述第二从机是除第一从机之外的其他从机；
    如果没有接收到第二从机发送的第二读数据和第二读响应消息，则将所述第一读数据和第一读响应消息发送给所述主机。
  8. 根据权利要求7中所述的方法，其特征在于所述方法还包括：
    如果接收到第二从机发送的第二读数据和第二读响应消息，判断所述第一从机等待的时间是否小于等于预设的响应超时阈值；
    如果所述第一从机等待的时间小于等于预设的响应超时阈值，判断所述第一从机的读优先级是否高于第二从机的读优先级；
    如果所述第一从机的读优先级高于第二从机的读优先级，则将所述第一读数据和第一读响应消息发送给所述主机。
  9. 根据权利要求8中所述的方法，所述方法还包括：
    如果所述第一从机的读优先级与第二从机的读优先级相同，则判断所述第一从机的端口号是否小于所述第二从机的端口号；
    如果所述第一从机的端口号小于所述第二从机的端口号，则将所述第一读数据和第一读响应消息发送给所述主机。
  10. 根据权利要求9中所述的方法，所述方法还包括：
    如果所述第一从机的读优先级低于所述第二从机的读优先级，将所述第二读数据和第二读响应消息发送给所述主机；
    判断是否接收到第三从机发送的第三读数据和第三读响应消息如果没有接收到第三从机发送的第三读数据和第三读响应消息，则将所述第一读数据和第一读响应消息发送给所述主机。
  11. 根据权利要求8中所述的方法，所述方法还包括：
    如果所述第一从机等待的时间大于预设的响应超时阈值，将所述第二读数据和第二读响应消息发送给所述主机；
    判断是否接收到第三从机发送的第三读数据和第三读响应消息；其中，所述第三从机是除第一从机之外的其他从机；
    如果没有接收到第三从机发送的第三读数据和第三读响应消息，则将所述第一读数据和第一读响应消息发送给所述主机。
  12. 根据权利要求6中所述的方法，所述方法还包括：
    如果没有接收到任一从机发送的读数据和读响应消息或写反馈信息，并且也没有接收到主机发送的读地址或写地址，则启动低功耗计时器开始计时；
    当低功耗计时器的计时时间达到低功耗计时阈值时，仍没有接收到任一从机发送的读数据和读响应消息和/或写反馈消息并且也没有接收到主机发送的读地址或写地址，则关断自身的控制时钟。
  13. 根据权利要求6中所述的方法，所述方法还包括：
    确定读数据通道的带宽信息；
    确定读命令的响应时延信息；其中，所述读命令的响应时延为从接收到主机发送的第一读地址到向所述主机发送完第一读数据和第一读响应消息之间的时间差；
    存储所述读数据通道的带宽信息和所述读命令的响应时延信息。
  14. 一种多通道DDR的交织控制装置，所述装置包括：
    第一接收模块，配置为接收主机发送的写数据和第一写地址；其中，所述主机为总线互联模块；
    第一确定模块，配置为根据预先设置的交织控制配置信息，确定所述第一写地址对应的第二写地址和所述第一写地址对应的从机的标识信息；
    第一发送模块，配置为根据所述从机的标识信息，将所述写数据和所述第二写地址发送给所述从机；其中，所述从机为DDR控制器；
    第二接收模块，配置为接收所述从机发送的写反馈消息，其中，所述写反馈消息配置为表征所述写数据是否写成功；
    第二发送模块，配置为将所述写反馈消息发送给所述主机。
  15. 一种多通道DDR的交织控制装置，所述装置包括：
    第三接收模块，配置为接收主机发送的第一读地址；
    第二确定模块，配置为根据预先设置的交织控制配置信息，确定所述第一读地址对应的第二读地址和所述第一读地址对应的第一从机的标识信息；
    第三发送模块，配置为根据所述第一从机的标识信息，将所述第二读地址发送给第一从机；
    第四接收模块，配置为接收所述第一从机发送的第一读数据和第一读响应消息；
    第四发送模块，配置为将所述第一读数据和第一读响应消息发送给所述主机。
  16. 一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现权利要求1至5任一项所述的方法的步骤。
  17. 一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现权利要求6至13任一项所述的方法的步骤。
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