WO2018107612A1 - 显示基板及其测试方法 - Google Patents

显示基板及其测试方法 Download PDF

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Publication number
WO2018107612A1
WO2018107612A1 PCT/CN2017/078296 CN2017078296W WO2018107612A1 WO 2018107612 A1 WO2018107612 A1 WO 2018107612A1 CN 2017078296 W CN2017078296 W CN 2017078296W WO 2018107612 A1 WO2018107612 A1 WO 2018107612A1
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Prior art keywords
connection point
gate driving
display substrate
circuit
gate
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PCT/CN2017/078296
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English (en)
French (fr)
Inventor
陈猷仁
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/545,155 priority Critical patent/US10416512B2/en
Publication of WO2018107612A1 publication Critical patent/WO2018107612A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2825—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere in household appliances or professional audio/video equipment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • Embodiments of the present disclosure relate to display technologies, and in particular, to a display substrate and a test method thereof.
  • TFT-LCD Active Thin Film Transistor-LCD
  • a liquid crystal display panel is composed of a color film substrate, an OLED substrate, a liquid crystal (LC) sandwiched between a color filter substrate and a thin film transistor substrate, and a sealant (Sealant).
  • the working principle is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the two glass substrates, and refract the light of the backlight module to generate a picture.
  • a large-sized display substrate generally adopts a dual-drive architecture, and two gate drive circuits on both sides are connected to the same gate line. When the display substrate is operating normally, the two gate drive circuits output the same signal.
  • the gate drive circuits on both sides are connected to the same High Vertical Alignment (HVA) trace.
  • HVA High Vertical Alignment
  • the gate driving circuits on both sides are simultaneously turned on, and the output gate pulse signal lights the pixels inside the display area.
  • the gate drive circuit on one side is not working properly, the gate drive circuit on the other side can still output the gate pulse signal.
  • the gate pulse signal can also cause the pixels inside the display area to work normally. This will bring the risk of missed inspections, which is very unfavorable for improving the yield of the process.
  • Embodiments of the present disclosure provide a display substrate and a test method thereof, so that when a high vertical alignment curing process is performed, two gate driving circuits of a display substrate are simultaneously turned on, and when an array test is performed on the gate driving circuit, two The gate drive circuits are tested separately.
  • an embodiment of the present disclosure provides a display substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of scan lines extending along the first direction, and respectively disposed on the a first gate driving circuit and a second gate driving circuit at the two ends of the plurality of scanning lines, the display substrate further comprising:
  • test pad disposed at at least one end of the test lead
  • a first array test pad electrically connected to the first gate driving circuit and connected to the test lead to form a first connection point
  • a switching unit formed between the first connection point and the second connection point of the test lead for controlling the test lead to be turned on or off.
  • the high vertical alignment process test pads are disposed at two ends of the test leads, and are located in the non-display area of the display area along both sides of the first direction.
  • the first array test pad and the second array test pad are located in a non-display area of one side of the display area along the second direction.
  • the switch unit is a thin film transistor
  • the display substrate further includes a switch control line
  • the switch control line is electrically connected to a gate of the thin film transistor
  • a source and a drain of the thin film transistor are The test leads are electrically connected.
  • the display substrate further includes a switch control pad, and an end of the switch control line is electrically connected to the switch control pad.
  • the switch control pad is disposed adjacent to the high vertical alignment process test pad.
  • an embodiment of the present disclosure provides a test method for a display substrate.
  • Controlling the switching unit to conduct during a high vertical alignment curing process applying a first test signal through the high vertical alignment process test pad, the first test signal driving the first gate driving circuit and the The second gate driving circuit operates simultaneously;
  • the switch unit controlling the switch unit to turn off, applying a second test signal through the first array test pad in a time division manner, and applying a third test signal through the second array test pad, the second test A signal drives the first gate drive circuit, and the third test signal drives the second gate drive circuit to operate in a time division manner.
  • the switching unit is a thin film transistor, and an opening signal is applied to a gate of the thin film transistor through the switch control line during a high vertical alignment curing process to control the thin film transistor to be turned on.
  • the display substrate further includes a switch control pad, and an end of the switch control line is electrically connected to the switch control pad, and the switch is controlled by the switch during the high vertical alignment curing process An open signal is applied to the switch control line.
  • the present disclosure provides a display substrate including a test lead electrically connected to a first gate driving circuit and a second gate driving circuit, a high vertical alignment process test pad, and a first array test soldering method.
  • a disk, a second array of test pads, and a switch unit wherein the switch unit is configured to control the conduction or disconnection of the test leads, and when the high vertical alignment curing process is performed, the control switch unit is turned on, the first gate drive circuit and the second gate
  • the pole drive circuit works at the same time; in the array test, the control switch unit is turned off, the first gate drive circuit and the second gate drive circuit work in a time-sharing manner, and the high vertical alignment curing process is realized.
  • the two gate driving circuits of the display substrate are simultaneously turned on, and when the gate driving circuit is subjected to the array test, the two gate driving circuits are respectively tested.
  • FIG. 1 is a schematic structural view of a display substrate in an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of still another display substrate in the embodiment of the present disclosure.
  • FIG. 3 is a schematic structural view of still another display substrate in the embodiment of the present disclosure.
  • FIG. 4 is a schematic structural view of still another display substrate in the embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another display substrate in an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a display area 100 and a non-display area.
  • a plurality of gate lines, a plurality of data lines, and a plurality of pixel units are disposed in the display area 100.
  • Each pixel unit includes a thin film transistor (Thin Film Transistor).
  • the channel region of the thin film transistor may be an amorphous silicon or a polysilicon, and the polysilicon film may be formed, for example, by a low temperature polysilicon technology.
  • Each thin film transistor is connected to a corresponding one of the gate lines.
  • the first gate driving circuit 31 and the second gate driving circuit 32 are disposed in the non-display area.
  • Two gate drive circuits on both sides of the display area 100 are connected to the same gate line 30.
  • the two gates drive electricity The road outputs the same signal.
  • the gate driving architecture the gate driving circuits on both sides of the display area are connected to the same High Vertical Alignment (HVA) trace 10.
  • HVA High Vertical Alignment
  • the gate driving circuits on both sides of the display area are simultaneously turned on, and the output gate pulse signal lights the pixels inside the display area.
  • the gate driving circuit on one side of the display area is not working normally, the gate driving circuit on the other side can still output a gate pulse signal.
  • the gate pulse signal can also cause the pixels inside the display area to work normally. This will bring the risk of missed inspections, which is very unfavorable for improving the yield of the process.
  • one method is to separate the gate driving circuits on both sides of the display area.
  • the gate drive circuits on both sides are tested separately when performing array test on the gate drive circuit.
  • the two gate drive circuits are respectively unidirectionally sent during the array test of the gate drive circuit.
  • FIG. 2 in which the second gate driving circuit 32 is connected to the high vertical alignment trace 10, it can be understood that the first gate driving circuit 31 can also be connected to the high vertical alignment trace 10.
  • the first gate driving circuit 31 and the second gate driving circuit 32 are respectively unidirectionally sent signals when performing array test on the gate driving circuit.
  • the single-sided gate driving circuit drives the display area to work due to the RC load. Heavier and more serious signal attenuation, which can cause problems such as screen splitting or screen gradation.
  • FIG. 3 is a schematic structural diagram of still another display substrate according to an embodiment of the present disclosure, which can solve the above problem, and realizes that at the same time, in the high vertical alignment curing process, two gate driving circuits of the display substrate are simultaneously turned on, and the gate is driven. When the circuit is tested in an array, the two gate drive circuits are tested separately.
  • the display substrate includes a display area 100 and a non-display area surrounding the display area 100.
  • the display area 100 includes a plurality of scan lines 30 extending in a first direction (the direction of a broken line in FIG.
  • the display substrate provided by the embodiment further includes a test lead 10, a high vertical alignment process test pad 11, a first array test pad 21, a second array test pad 22, and a switch unit 40.
  • the test leads 10 are electrically connected to the first gate driving circuit 31 and the second gate driving circuit 32 at the same time.
  • a high vertical alignment process test pad 11 is disposed at at least one end of the test lead 10, and a high vertical alignment process test pad is exemplarily disposed at one end of the test lead in FIG.
  • the first array test pad 21 is electrically connected to the first gate driving circuit 31 and connected to the test lead 10 to form a first connection point 210; the second array test pad 22 is electrically connected to the second gate driving circuit 32, And connected to the test lead 10 to form a second connection point 220.
  • a switching unit 40 is formed between the first connection point 210 and the second connection point 220 of the test lead 10 for controlling the test lead 10 to be turned on or off.
  • test leads are arranged in a high vertical alignment.
  • the first array test pad 21 and the second array test pad 22 are located in a non-display area on the side of the display area 100 in the second direction (perpendicular to the direction of the broken line in FIG. 3).
  • the high vertical alignment process test pads in this embodiment may also be disposed at both ends of the test leads and located in the non-display area.
  • 4 is a schematic structural diagram of still another display substrate in the embodiment of the present disclosure. As shown in FIG. 4, there are two high vertical alignment process test pads 11 respectively disposed at two ends of the test leads and located in the non-display area. Inside. In the industrial production process, there is often more than one display substrate between the upper and lower glass substrates. For example, if there are four display substrates between the upper and lower glass substrates, a high vertical alignment is arranged at both ends of the test leads. The process test pads ensure high vertical alignment process testing of multiple display substrates simultaneously prior to cutting operations on multiple display substrates.
  • the display substrate provided by the embodiment of the present disclosure includes a test lead electrically connected to the first gate driving circuit and the second gate driving circuit, a high vertical alignment process test pad, a first array test pad, and a second array test solder.
  • a disk and a switching unit for controlling conduction and disconnection of the test leads, and controlling the switching unit to be turned on during the high vertical alignment curing process, the first gate driving circuit and the second gate driving The dynamic circuit works at the same time; during the array test, the control switch unit is disconnected, and the first gate drive circuit and the second gate drive circuit work in a time-sharing manner, thereby realizing the two gates of the display substrate during the high vertical alignment curing process
  • the driving circuit is turned on at the same time, and when the gate driving circuit is array tested, the two gate driving circuits are respectively tested.
  • FIG. 5 is a schematic structural diagram of still another display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a display area 100 and a non-display area surrounding the display area 100.
  • the display area 100 includes a plurality of first directions.
  • Scan lines 30 extending in the direction of the dotted line in FIG. 5, first gate driving circuit 31 and second gate driving circuit 32 respectively disposed at both ends of the plurality of scanning lines 30, and test leads 10, high vertical alignment process test soldering
  • the switch unit 40 can be a thin film transistor, and the display substrate further includes a switch control line 50 and a switch control pad 51.
  • the switch control line 50 is electrically connected to the gate of the thin film transistor, and the source and drain of the thin film transistor are electrically connected to the test lead 10.
  • the end of the switch control line 50 is electrically connected to the switch control pad 51.
  • the thin film transistor is controlled to be turned on, for example, by applying a high level signal on the switch control line to turn on the thin film transistor, thereby turning on the test lead, the first gate driving circuit and the second The gate driving circuit operates at the same time; when performing array testing on the gate driving circuit, the thin film transistor is controlled to be turned off, for example, the voltage signal is not applied on the switching control line to turn off the thin film transistor, thereby disconnecting the test lead, the first gate The driving circuit and the second gate driving circuit work in a time-sharing manner, so that when the high vertical alignment curing process is performed, the two gate driving circuits of the display substrate are simultaneously turned on, and when the gate driving circuit is array tested, two The gate drive circuit is tested separately. It should be noted that the high vertical alignment curing process and the array test are two independent processes.
  • test panel when the test panel has multiple test pads, various tests can be performed on the display substrate, for example, the test panel includes an R test.
  • Pad, G test pad, B test pad, A-COM test pad, CF-COM test pad, switch test pad, and high vertical alignment process test pad, optionally, switch control pad and high Vertical alignment of the process test pads adjacent to each other provides the advantage of minimal distance between the switch control lines electrically connected to the switch control pads and the test leads electrically connected to the high vertical alignment process test pads, saving design space.
  • the embodiment of the present disclosure further provides a testing method for the display substrate shown in the above embodiment, which includes: controlling the switching unit to be turned on by a high vertical alignment during a high vertical alignment curing process.
  • the process test pad applies a first test signal, the first test signal drives the first gate drive circuit and the second gate drive circuit to work simultaneously; when the array test, the switch unit is disconnected, and the time division is applied through the first array test pad a second test signal, and applying a third test signal through the second array test pad, the second test signal driving the first gate drive circuit, and the third test signal driving the second gate drive circuit to work in time.
  • the switching unit is a thin film transistor, and in the high vertical alignment curing process, an opening signal is applied to the gate of the thin film transistor through the switch control line to control the conduction of the thin film transistor.
  • the display substrate further includes a switch control pad, and the end of the switch control line is electrically connected to the switch control pad.
  • an opening signal is applied to the switch control line through the switch control pad, and the control film is controlled.
  • the transistor is turned on, for example, by applying a high level signal on the switch control line to turn on the thin film transistor, thereby turning on the test lead, and the first gate driving circuit and the second gate driving circuit simultaneously operate.
  • the method for testing a display substrate controls a switching unit to be turned on during a high vertical alignment curing process, and applies a test signal to drive the first gate driving circuit and the second gate driving through a high vertical alignment process test pad.
  • the circuit works at the same time; during the array test, the control switch unit is turned off, and the first gate drive circuit and the first array drive circuit are respectively driven by the first array test pad and the second array test pad.
  • the two-gate driving circuit works to realize that the two gate driving circuits of the display substrate are simultaneously turned on during the high vertical alignment curing process, and the two gate driving circuits are respectively performed when performing array testing on the gate driving circuit. test.
  • the display substrate of the present disclosure and the testing method thereof enable simultaneous opening operation of two gate driving circuits of the display substrate in a high vertical alignment curing process, and two gate driving when performing array testing on the gate driving circuit The circuits are tested separately.

Abstract

一种显示基板及其测试方法，显示基板包括：测试引线（10），同时与第一栅极驱动电路（31）和第二栅极驱动电路（32）电连接；高垂直排列制程测试焊盘（11），设置在测试引线（10）的至少一端；第一阵列测试焊盘（21），与第一栅极驱动电路（31）电连接，且与测试引线（10）相连接形成第一连接点（210）；第二阵列测试焊盘（22），与第二栅极驱动电路（32）电连接，且与测试引线（10）相连接形成第二连接点（220）；开关单元（40），形成在测试引线（10）的第一连接点（210）和第二连接点（220）之间，用于控制测试引线（10）导通或断开。实现了在高垂直排列固化制程时，显示基板的两个栅极驱动电路（31，32）同时打开工作，在对栅极驱动电路（31，32）进行阵列测试时，对两个栅极驱动电路（31，32）分别进行测试。

Description

显示基板及其测试方法 技术领域
本公开实施例涉及显示技术，尤其涉及一种显示基板及其测试方法。
背景技术
主动式薄膜晶体管液晶显示器(Thin Film Transistor-LCD，TFT-LCD)近年来得到了飞速的发展和广泛的应用。目前市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组(Backlight module)。通常液晶显示面板由彩膜基板(Color film substrate)、薄膜晶体管基板(Array substrate)、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封框胶(Sealant)组成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
大尺寸的显示基板一般采用双驱架构，两侧的两个栅极驱动电路连接至同一条栅极线。当显示基板正常工作时，两个栅极驱动电路输出同样的信号。传统的栅极驱动架构中，两侧的栅极驱动电路都是连接至同一高垂直排列(HVA，High Vertical Alignment)走线。在栅极驱动制程阶段的测试制程中，两侧的栅极驱动电路同时打开工作，输出栅极脉冲信号将显示区内部的像素点亮。当一侧的栅极驱动电路不能正常工作时，另外一侧的栅极驱动电路仍然能够输出栅极脉冲信号。该栅极脉冲信号也可以使得显示区内部的像素正常工作。这样就会带来漏检的风险，对提升制程的良率是非常不利的。
发明内容
本公开实施例提供一种显示基板及其测试方法，以实现在高垂直排列固化制程时，显示基板的两个栅极驱动电路同时打开工作，在对栅极驱动电路进行阵列测试时，对两个栅极驱动电路分别进行测试。
一方面，本公开实施例提供了一种显示基板，包括显示区和围绕所述显示区的非显示区，所述显示区包括多条沿第一方向延伸的扫描线，以及分别设置在所述多条扫描线两端的第一栅极驱动电路和第二栅极驱动电路，所述显示基板还包括：
测试引线，同时与所述第一栅极驱动电路和所述第二栅极驱动电路电连接；
高垂直排列制程测试焊盘，设置在所述测试引线的至少一端；
第一阵列测试焊盘，与所述第一栅极驱动电路电连接，且与所述测试引线相连接形成第一连接点；
第二阵列测试焊盘，与所述第二栅极驱动电路电连接，且与所述测试引线相连接形成第二连接点；
开关单元，形成在所述测试引线的所述第一连接点和所述第二连接点之间，用于控制所述测试引线导通或断开。
可选地，所述高垂直排列制程测试焊盘设置在所述测试引线的两端，且位于所述显示区沿所述第一方向两侧的非显示区内。
可选地，所述第一阵列测试焊盘和所述第二阵列测试焊盘位于所述显示区沿第二方向一侧的非显示区内。
可选地，所述开关单元为一薄膜晶体管，所述显示基板还包括开关控制线，所述开关控制线与所述薄膜晶体管的栅极电连接，所述薄膜晶体管的源极和漏极与所述测试引线电连接。
可选地，显示基板还包括开关控制焊盘，所述开关控制线的端部与所述开关控制焊盘电连接。
可选地，所述开关控制焊盘与所述高垂直排列制程测试焊盘相邻设置。
另一方面，本公开实施例提供了一种显示基板的测试方法，
在高垂直排列固化制程时，控制所述开关单元导通，通过所述高垂直排列制程测试焊盘施加第一测试信号，所述第一测试信号驱动所述第一栅极驱动电路和所述第二栅极驱动电路同时工作；
在阵列测试时，控制所述开关单元关闭，分时通过所述第一阵列测试焊盘施加第二测试信号，以及通过所述第二阵列测试焊盘施加第三测试信号，所述第二测试信号驱动所述第一栅极驱动电路，以及所述第三测试信号驱动所述第二栅极驱动电路分时工作。
可选地，所述开关单元为一薄膜晶体管，在高垂直排列固化制程时，通过所述开关控制线向所述薄膜晶体管的栅极施加开启信号，以控制所述薄膜晶体管导通。
可选地，所述显示基板还包括开关控制焊盘，所述开关控制线的端部与所述开关控制焊盘电连接，在所述高垂直排列固化制程时，通过所述开关控制焊盘向所述开关控制线施加开启信号。
本公开提供了一种显示基板及其测试方法，该基板包括同时与第一栅极驱动电路和第二栅极驱动电路电连接的测试引线、高垂直排列制程测试焊盘、第一阵列测试焊盘、第二阵列测试焊盘以及开关单元，开关单元用于控制测试引线的导通或断开，在高垂直排列固化制程时，控制开关单元导通，第一栅极驱动电路和第二栅极驱动电路同时工作；在阵列测试时，控制开关单元关闭，第一栅极驱动电路和第二栅极驱动电路分时工作，实现了在高垂直排列固化制程 时，显示基板的两个栅极驱动电路同时打开工作，在对栅极驱动电路进行阵列测试时，对两个栅极驱动电路分别进行测试。
附图说明
图1为本公开实施例中的一种显示基板的结构示意图；
图2为本公开实施例中的又一种显示基板的结构示意图；
图3为本公开实施例中的又一种显示基板的结构示意图；
图4为本公开实施例中的又一种显示基板的结构示意图；
图5为本公开实施例中的又一种显示基板的结构示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
图1为本公开实施例中的一种显示基板的结构示意图，参考图1，显示基板包括显示区100和非显示区。在显示区100设置有多条栅极线，多条数据线以及多个像素单元。每个像素单元包括薄膜晶体管(Thin Film Transistor)。薄膜晶体管的沟道区域可以是非晶硅膜(amorphous Silicon)，也可以是多晶硅薄膜(poly Silicon)，多晶硅薄膜例如可以通过低温多晶硅(Low Temperature Poly Silicon)技术制得。每个薄膜晶体管连接对应的一条栅极线。第一栅极驱动电路31和第二栅极驱动电路32设置在非显示区。显示区100两侧的两个栅极驱动电路连接至同一条栅极线30。当显示基板中的显示区100正常工作时，两个栅极驱动电 路输出同样的信号。栅极驱动架构中，显示区两侧的栅极驱动电路都是连接至同一高垂直排列(HVA，High Vertical Alignment)走线10。在栅极驱动制程阶段的测试制程中，显示区两侧的栅极驱动电路同时打开工作，输出栅极脉冲信号将显示区内部的像素点亮。当显示区一侧的栅极驱动电路不能正常工作时，另外一侧的栅极驱动电路仍然能够输出栅极脉冲信号。该栅极脉冲信号也可以使得显示区内部的像素正常工作。这样就会带来漏检的风险，对提升制程的良率是非常不利的。
为了解决漏检的问题，一种做法是将显示区两侧的栅极驱动电路分离开来。在对栅极驱动电路进行阵列测试时对两侧的栅极驱动电路分别进行测试。在对栅极驱动电路进行阵列测试时分别对两个栅极驱动电路进行单边送信号。参考图2，其中第二栅极驱动电路32连接至高垂直排列走线10，可以理解的是，也可以是第一栅极驱动电路31连接至高垂直排列走线10。在对栅极驱动电路进行阵列测试时分别对第一栅极驱动电路31和第二栅极驱动电路32进行单边送信号。这种设计虽然可以避免对栅极驱动电路漏检的风险，但是在高垂直排列固化制程时，由于显示基板的显示区尺寸较大，单边的栅极驱动电路驱动显示区工作会因为RC负载较重而导致比较严重的信号衰减，从而会导致画面分屏或画面渐变等问题。
图3为本公开实施例中的又一种显示基板的结构示意图，可以解决上述问题，实现在高垂直排列固化制程时，显示基板的两个栅极驱动电路同时打开工作，在对栅极驱动电路进行阵列测试时，对两个栅极驱动电路分别进行测试。如图3所示，显示基板包括显示区100和围绕显示区100的非显示区，显示区100包括多条沿第一方向(图3中虚线方向)延伸的扫描线30，以及分别设置在多条扫描线30两端的第一栅极驱动电路31和第二栅极驱动电路32，本公开 实施例提供的显示基板还包括测试引线10、高垂直排列制程测试焊盘11、第一阵列测试焊盘21、第二阵列测试焊盘22和开关单元40。
其中，测试引线10同时与第一栅极驱动电路31和第二栅极驱动电路32电连接。高垂直排列制程测试焊盘11设置在测试引线10的至少一端，图3中示例性地在测试引线的一端设置了高垂直排列制程测试焊盘。第一阵列测试焊盘21与第一栅极驱动电路31电连接，且与测试引线10相连接形成第一连接点210；第二阵列测试焊盘22与第二栅极驱动电路32电连接，且与测试引线10相连接形成第二连接点220。开关单元40形成在测试引线10的第一连接点210和第二连接点220之间，用于控制测试引线10导通或断开。
可选地，测试引线为高垂直排列走线。参考图3，第一阵列测试焊盘21和第二阵列测试焊盘22位于显示区100沿第二方向(垂直于图3中虚线方向)一侧的非显示区内。
另外，本实施例中的高垂直排列制程测试焊盘也可以设置在测试引线的两端，且位于非显示区内。图4为本公开实施例中的又一种显示基板的结构示意图，如图4所示，有两个高垂直排列制程测试焊盘11，分别设置在测试引线的两端，且位于非显示区内。在工业生产过程中，往往在上下两个玻璃基板之间有不止一个显示基板，例如在上下两个玻璃基板之间存在4个上述的显示基板，则在测试引线的两端均设置高垂直排列制程测试焊盘保证了在对多个显示基板进行切割操作之前，可以同时对多个显示基板进行高垂直排列制程测试。
本公开实施例提供的显示基板包括同时与第一栅极驱动电路和第二栅极驱动电路电连接的测试引线、高垂直排列制程测试焊盘、第一阵列测试焊盘、第二阵列测试焊盘以及开关单元，开关单元用于控制测试引线的导通和断开，在高垂直排列固化制程时，控制开关单元导通，第一栅极驱动电路和第二栅极驱 动电路同时工作；在阵列测试时，控制开关单元断开，第一栅极驱动电路和第二栅极驱动电路分时工作，实现了在高垂直排列固化制程时，显示基板的两个栅极驱动电路同时打开工作，在对栅极驱动电路进行阵列测试时，对两个栅极驱动电路分别进行测试。
图5为本公开实施例中的又一种显示基板的结构示意图，如图5所示，显示基板包括显示区100和围绕显示区100的非显示区，显示区100包括多条沿第一方向(图5中虚线方向)延伸的扫描线30，分别设置在多条扫描线30两端的第一栅极驱动电路31和第二栅极驱动电路32，以及测试引线10、高垂直排列制程测试焊盘11、第一阵列测试焊盘21、第二阵列测试焊盘22和开关单元40。其中，开关单元40可以为一薄膜晶体管，显示基板还包括开关控制线50和开关控制焊盘51。开关控制线50与薄膜晶体管的栅极电连接，薄膜晶体管的源极和漏极与测试引线10电连接。开关控制线50的端部与开关控制焊盘51电连接。
在高垂直排列固化制程时，控制薄膜晶体管导通，例如可以是在开关控制线上施加一高电平信号使得薄膜晶体管导通，从而使测试引线导通，第一栅极驱动电路和第二栅极驱动电路同时工作；在对栅极驱动电路进行阵列测试时，控制薄膜晶体管关闭，例如可以是不在开关控制线上施加电压信号使得薄膜晶体管关闭，从而使测试引线断开，第一栅极驱动电路和第二栅极驱动电路分时工作，实现了在高垂直排列固化制程时，显示基板的两个栅极驱动电路同时打开工作，在对栅极驱动电路进行阵列测试时，对两个栅极驱动电路分别进行测试。需要说明的是，高垂直排列固化制程和阵列测试是两个相互独立的过程。
若将高垂直排列制程测试焊盘所在面板称为测试面板，则当测试面板上具有多个测试焊盘时，可以对显示基板进行多种测试，例如测试面板包括R测试 焊盘、G测试焊盘、B测试焊盘、A-COM测试焊盘、CF-COM测试焊盘、开关测试焊盘以及高垂直排列制程测试焊盘，可选地，开关控制焊盘与高垂直排列制程测试焊盘相邻设置，这样设置的好处是，与开关控制焊盘电连接的开关控制线和与高垂直排列制程测试焊盘电连接的测试引线之间的距离最小，节约了设计空间。
基于同样的技术构思，本公开实施例还提供了一种针对上述实施例所示的显示基板的测试方法，该方法包括：在高垂直排列固化制程时，控制开关单元导通，通过高垂直排列制程测试焊盘施加第一测试信号，第一测试信号驱动第一栅极驱动电路和第二栅极驱动电路同时工作；阵列测试时，开关单元断开，分时通过第一阵列测试焊盘施加第二测试信号，以及通过第二阵列测试焊盘施加第三测试信号，第二测试信号驱动第一栅极驱动电路，以及第三测试信号驱动第二栅极驱动电路分时工作。
可选地，开关单元为薄膜晶体管，在高垂直排列固化制程时，通过开关控制线向薄膜晶体管的栅极施加开启信号，以控制薄膜晶体管导通。
可选地，显示基板还包括开关控制焊盘，开关控制线的端部与开关控制焊盘电连接，在高垂直排列固化制程时，通过开关控制焊盘向开关控制线施加开启信号，控制薄膜晶体管导通，例如可以是在开关控制线上施加一高电平信号使得薄膜晶体管导通，从而使测试引线导通，第一栅极驱动电路和第二栅极驱动电路同时工作。
本公开实施例提供的显示基板的测试方法，在高垂直排列固化制程时，控制开关单元导通，通过高垂直排列制程测试焊盘施加测试信号驱动第一栅极驱动电路和第二栅极驱动电路同时工作；在阵列测试时，控制开关单元关闭，分时通过第一阵列测试焊盘和第二阵列测试焊盘分别驱动第一栅极驱动电路和第 二栅极驱动电路工作，实现了在高垂直排列固化制程时，显示基板的两个栅极驱动电路同时打开工作，在对栅极驱动电路进行阵列测试时，对两个栅极驱动电路分别进行测试。
注意，上述仅为本公开的实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本公开的保护范围。
本公开的显示基板及其测试方法，实现了在高垂直排列固化制程时，显示基板的两个栅极驱动电路同时打开工作，在对栅极驱动电路进行阵列测试时，对两个栅极驱动电路分别进行测试。

Claims (20)

  1. 一种显示基板，包括：
    多条扫描线，每条扫描线包括第一端和第二端；
    第一栅极驱动电路，与每条扫描线的第一端以及第一连接点电连接；
    第二栅极驱动电路，与每条扫描线的第二端以及第二连接点电连接；
    第一阵列测试焊盘，与第一连接点电连接；
    第二阵列测试焊盘，与第二连接点电连接；
    第一高垂直排列制程测试焊盘，与第一连接点电连接；以及
    开关电路设置在第一连接点和第二连接点之间，控制第一连接点和第二连接点之间导通和断开。
  2. 根据权利要求1所述的显示基板，其中，所述多条扫描线设置在显示基板的显示区，所述第一高垂直排列制程测试焊盘设置在显示基板的非显示区，所述非显示区围绕所述显示区。
  3. 根据权利要求1所述的显示基板，其中，在所述开关电路导通时，通过所述第一高垂直排列制程测试焊盘同时驱动所述第一栅极驱动电路和所述第二栅极驱动电路；
    在所述开关电路断开时，分时驱动所述第一栅极驱动电路和第二栅极驱动电路，其中，所述第一栅极驱动电路通过第一阵列测试焊盘驱动，所述第二栅极驱动电路通过第二阵列测试焊盘驱动。
  4. 根据权利要求1所述的显示基板，其中，所述开关电路为薄膜晶体管。
  5. 根据权利要求4所述的显示基板，其中，所述薄膜晶体管的栅极电连接开关控制焊盘，所述薄膜晶体管的源极电连接所述第一连接点和第二连接点中的一个，所述薄膜晶体管的漏极电连接所述第一连接点和第二连接点中的另一个。
  6. 根据权利要求5所述的显示基板，其中，所述开关控制焊盘设置在所述显示基板的非显示区。
  7. 根据权利要求1所述的显示基板，还包括与第二连接点电连接的第二高垂直排列制程测试焊盘。
  8. 根据权利要求7所述的显示基板，其中，所述多条扫描线设置在显示基板的显示区，所述第一高垂直排列制程测试焊盘和所述第二高垂直排列制程测试焊盘设置在显示基板的非显示区，所述非显示区围绕所述显示区。
  9. 根据权利要求7所述的显示基板，其中，在所述开关电路导通时，通过所述第一高垂直排列制程测试焊盘和第二高垂直排列制程测试焊盘中的至少一个同时驱动所述第一栅极驱动电路和所述第二栅极驱动电路；
    在所述开关电路断开时，分时驱动所述第一栅极驱动电路和第二栅极驱动电路，其中，所述第一栅极驱动电路通过第一阵列测试焊盘驱动，所述第二栅极驱动电路通过第二阵列测试焊盘驱动。
  10. 根据权利要求7所述的显示基板，其中，所述开关电路为薄膜晶体管。
  11. 根据权利要求10所述的显示基板，其中，所述薄膜晶体管的栅极电连接开关控制焊盘，所述薄膜晶体管的源极电连接所述第一连接点和第二连接点中的一个，所述薄膜晶体管的漏极电连接所述第一连接点和第二连接点中的另一个。
  12. 根据权利要求11所述的显示基板，其中，所述开关控制焊盘设置在所述显示基板的非显示区。
  13. 一种显示基板的测试方法，所述显示基板包括：多条扫描线，每条扫描线包括第一端和第二端；第一栅极驱动电路，与每条扫描线的第一端以及第一连接点电连接；第二栅极驱动电路，与每条扫描线的第二端以及第二连接点 电连接；第一阵列测试焊盘，与第一连接点电连接；第二阵列测试焊盘，与第二连接点电连接；第一高垂直排列制程测试焊盘，与第一连接点电连接；以及设置在第一连接点和第二连接点之间的开关电路，
    所述测试方法包括：
    控制开关电路导通，同时驱动所述第一栅极驱动电路和第二栅极驱动电路；
    控制开关电路断开，分时驱动所述第一栅极驱动电路和第二栅极驱动电路。
  14. 根据权利要求13所述的测试方法，其中，通过分时驱动所述第一栅极驱动电路和第二栅极驱动电路判断所述多条扫描线中是否存在断开的扫描线。
  15. 根据权利要求13所述的测试方法，其中，所述显示基板还包括与第二连接点电连接的第二高垂直排列制程测试焊盘。
  16. 根据权利要求15所述的测试方法，其中，通过所述第一高垂直排列制程测试焊盘和第二高垂直排列制程测试焊盘中的至少一个同时驱动所述第一栅极驱动电路和所述第二栅极驱动电路。
  17. 根据权利要求13所述的测试方法，其中，在控制开关电路断开时，第一栅极驱动电路通过第一阵列测试焊盘驱动，所述第二栅极驱动电路通过第二阵列测试焊盘驱动。
  18. 根据权利要求13所述的测试方法，其中，控制开关电路断开时，在第一时间段，驱动所述第一栅极驱动电路从而依次驱动所述多条扫描线，在第二时间段，驱动所述第二栅极驱动电路从而依次驱动所述多条扫描线。
  19. 一种显示基板的测试方法，所述显示基板包括：第一扫描线和第二扫描线，所述第一扫描线和第二扫描线均具有第一端和第二端；第一栅极驱动电路，与第一扫描线和第二扫描线的第一端以及第一连接点电连接；第二栅极驱动电路，与第一扫描线和第二扫描线的第二端以及第二连接点电连接；第一阵 列测试焊盘，与第一连接点电连接；第二阵列测试焊盘，与第二连接点电连接；第一高垂直排列制程测试焊盘，与第一连接点电连接；以及设置在第一连接点和第二连接点之间的开关电路，
    所述测试方法包括：
    控制开关电路导通，同时驱动所述第一栅极驱动电路和第二栅极驱动电路；以及
    控制开关电路断开，在第一时间段，通过第一栅极驱动电路驱动第一扫描线，在第二时间段，通过第二栅极驱动电路驱动第一扫描线；在第三时间段，通过第一栅极驱动电路驱动第二扫描线，在第四时间段，通过第二栅极驱动电路驱动第二扫描线。
  20. 根据权利要求13所述的测试方法，其中，所述开关电路为薄膜晶体管，所述薄膜晶体管的栅极电连接开关控制焊盘，所述薄膜晶体管的源极电连接所述第一连接点和第二连接点中的一个，所述薄膜晶体管的漏极电连接所述第一连接点和第二连接点中的另一个。
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11237648B2 (en) * 2013-11-08 2022-02-01 Egalax_Empia Technology Inc. Touch sensitive processing method and apparatus and touch sensitive system for reducing detection time period of tethered stylus
CN106526918B (zh) 2016-12-16 2019-05-28 惠科股份有限公司 一种显示基板及其测试方法
CN106652863B (zh) * 2017-02-22 2020-10-13 深圳市华星光电技术有限公司 一种检测电路
CN107038984B (zh) * 2017-05-19 2020-07-31 武汉华星光电技术有限公司 一种阵列基板检测线路以及检测方法和制作方法
CN107221274B (zh) * 2017-07-12 2018-03-13 深圳市华星光电半导体显示技术有限公司 Goa测试电路及goa测试方法
US10262564B2 (en) 2017-07-12 2019-04-16 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd Test circuit of gate driver on array and test method of gate driver on array
CN107463041B (zh) * 2017-08-31 2020-05-19 深圳市华星光电技术有限公司 阵列基板的外围电路结构
CN107703688B (zh) * 2017-09-28 2020-07-07 武汉天马微电子有限公司 一种阵列基板及显示装置
CN107678219A (zh) * 2017-10-23 2018-02-09 深圳市华星光电技术有限公司 液晶显示母板
CN108010475B (zh) * 2017-11-24 2021-06-22 苏州华星光电技术有限公司 一种显示面板
CN107797355A (zh) * 2017-11-27 2018-03-13 深圳市华星光电半导体显示技术有限公司 液晶显示装置及其检测方法
CN108109566A (zh) * 2017-12-26 2018-06-01 深圳市华星光电技术有限公司 一种检测电路及显示面板
CN108053788A (zh) * 2018-01-02 2018-05-18 京东方科技集团股份有限公司 一种显示面板、显示装置和测试方法
TWI650605B (zh) * 2018-01-15 2019-02-11 友達光電股份有限公司 陣列基板及陣列基板之測試方法
CN109243350B (zh) * 2018-11-09 2021-10-22 惠科股份有限公司 量测讯号电路及其量测方法
CN109637405B (zh) * 2018-12-05 2021-04-06 惠科股份有限公司 阵列基板的测试方法、装置及存储介质
CN109523943B (zh) * 2018-12-28 2023-06-20 厦门天马微电子有限公司 显示面板和显示装置
CN109727563B (zh) 2019-01-30 2021-06-25 武汉华星光电半导体显示技术有限公司 下窄边框显示面板
CN110060648A (zh) * 2019-05-17 2019-07-26 深圳市华星光电半导体显示技术有限公司 液晶显示器及驱动集成电路
CN111158177B (zh) * 2020-02-28 2022-11-22 京东方科技集团股份有限公司 检测结构、显示面板、检测装置及检测系统
CN111445798B (zh) * 2020-04-13 2022-05-31 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN111354296B (zh) * 2020-04-16 2023-01-24 京东方科技集团股份有限公司 显示面板、显示装置
CN112904632A (zh) * 2021-04-02 2021-06-04 京东方科技集团股份有限公司 显示基板、显示模组和显示装置
CN116093023B (zh) * 2023-04-03 2023-06-23 惠科股份有限公司 显示面板的制备方法、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120050633A1 (en) * 2010-08-27 2012-03-01 Au Optronics Corp. Lcd panel and fabricating method thereof
CN105096789A (zh) * 2015-09-25 2015-11-25 武汉华星光电技术有限公司 Goa测试与清除关机残影的共用电路
CN102455553B (zh) * 2010-10-22 2016-05-04 京东方科技集团股份有限公司 Tft-lcd、阵列基板及其制造方法
CN105842897A (zh) * 2016-05-30 2016-08-10 深圳市华星光电技术有限公司 液晶显示母板及其配向方法
CN106157858A (zh) * 2016-08-31 2016-11-23 深圳市华星光电技术有限公司 液晶显示面板的栅极驱动电路的测试电路及其工作方法
CN106526918A (zh) * 2016-12-16 2017-03-22 惠科股份有限公司 一种显示基板及其测试方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100964620B1 (ko) * 2003-07-14 2010-06-22 삼성전자주식회사 하부기판용 모기판, 표시패널용 기판 및 표시패널의제조방법
CN102621721B (zh) * 2012-04-10 2015-04-15 深圳市华星光电技术有限公司 液晶面板、液晶模组及厘清其画面不良的原因的方法
KR101913839B1 (ko) * 2012-04-10 2018-12-31 삼성디스플레이 주식회사 표시 장치 및 그것의 테스트 방법
CN102636928B (zh) * 2012-04-16 2015-04-15 深圳市华星光电技术有限公司 液晶显示面板配线区线路结构及液晶显示面板测试方法
US20150179666A1 (en) * 2013-12-25 2015-06-25 Shenzhen China Star Optoelectronics Technology Co., Ltd. Wiring structure of array substrate
CN106782256B (zh) * 2015-11-18 2020-11-03 上海和辉光电有限公司 一种带有面板测试电路的显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120050633A1 (en) * 2010-08-27 2012-03-01 Au Optronics Corp. Lcd panel and fabricating method thereof
CN102455553B (zh) * 2010-10-22 2016-05-04 京东方科技集团股份有限公司 Tft-lcd、阵列基板及其制造方法
CN105096789A (zh) * 2015-09-25 2015-11-25 武汉华星光电技术有限公司 Goa测试与清除关机残影的共用电路
CN105842897A (zh) * 2016-05-30 2016-08-10 深圳市华星光电技术有限公司 液晶显示母板及其配向方法
CN106157858A (zh) * 2016-08-31 2016-11-23 深圳市华星光电技术有限公司 液晶显示面板的栅极驱动电路的测试电路及其工作方法
CN106526918A (zh) * 2016-12-16 2017-03-22 惠科股份有限公司 一种显示基板及其测试方法

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