WO2018094073A2 - Methods of sub-resolution substrate patterning - Google Patents
Methods of sub-resolution substrate patterning Download PDFInfo
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- WO2018094073A2 WO2018094073A2 PCT/US2017/062053 US2017062053W WO2018094073A2 WO 2018094073 A2 WO2018094073 A2 WO 2018094073A2 US 2017062053 W US2017062053 W US 2017062053W WO 2018094073 A2 WO2018094073 A2 WO 2018094073A2
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- line layer
- etch mask
- layer
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- lines
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
- H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
- H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
- H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
- H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
- H10P76/2041—Photolithographic processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/12—Preparing bulk and homogeneous wafers
- H10P90/126—Preparing bulk and homogeneous wafers by chemical etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Definitions
- This disclosure relates to substrate processing, and, more particularly, to techniques for patterning substrates including patterning semiconductor wafers.
- creating patterned layers comprises the application of a thin layer of radiation- sensitive material, such as photoresist, to an upper surface of a substrate.
- This radiation-sensitive material is transformed into a relief pattern which can be used as an etch mask to transfer a pattern into an underlying layer on a substrate.
- Patterning of the radiation-sensitive material generally involves exposure to actinic radiation through a reticle (and associated optics) onto the radiation-sensitive material using, for example, a photo-lithography system. This exposure can then be followed by the removal of irradiated regions of the radiation-sensitive material (as in the case of positive photoresist), or non-irradiated regions (as in the case of negative resist) using a developing solvent.
- This mask layer can comprise multiple sub-layers.
- Pitch reduction techniques are termed (often somewhat erroneously yet routinely) "pitch multiplication” as exemplified by "pitch doubling" et cetera.
- Pitch reduction techniques can extend the capabilities of photolithography beyond feature size limitations (optical resolution limitations). That is, conventional multiplication of pitch (more accurately pitch reduction, or multiplication of pitch density) by a certain factor involves reducing a target pitch by a specified factor. Double patterning techniques used with 193 nm immersion lithography are conventionally considered as one of the most promising techniques to pattern 22 nm nodes and smaller.
- SADP self-aligned spacer double patterning
- Techniques disclosed herein provide a method for substrate patterning that results in lines of non-uniform pitch (mixed pitch). Techniques herein can also enable advanced patterning options by selectively replacing lines of material in a multi-line layer.
- One embodiment includes a method of patterning a substrate.
- a multiline layer is formed on an underlying layer of a substrate.
- the multi-line layer includes a region having a pattern of alternating lines of a first material, a second material, and a third material.
- Each line has a horizontal thickness, a vertical height, and extends horizontally across the underlying layer.
- Each line of the pattern of alternating lines extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer.
- a first etch mask is formed on the multi-line layer that uncovers a portion of the pattern of alternating lines. Portions of the first material of the multi-line layer that are uncovered by the first etch mask are removed.
- Removed portions of the first material are replaced with a fill material that extends vertically from a top surface of the multi-line layer to a bottom surface of the multiline layer.
- the first etch mask is removed resulting in the multi-line layer having four different materials. This process can be repeated to replace other portions of the same or different lines in the multi-line layer.
- FIG. 1 A is a cross-sectional side view
- FIG. 1 B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 2A is a cross-sectional side view
- FIG. 2B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 3A is a cross-sectional side view
- FIG. 3B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 4A is a cross-sectional side view
- FIG. 4B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 5A is a cross-sectional side view
- FIG. 5B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 6A is a cross-sectional side view
- FIG. 6B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 7A is a cross-sectional side view
- FIG. 7B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 8A is a cross-sectional side view
- FIG. 8B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 9A is a cross-sectional side view
- FIG. 9B is a top view, of an example substrate segment according to embodiments disclosed herein.
- FIG. 10A is a cross-sectional side view
- FIG. 10B is a top view, of an example substrate segment according to embodiments disclosed herein,
- FIG. 1 1 A is a cross-sectional side view
- FIG. 1 1 B is a top view, of an example substrate segment according to embodiments disclosed herein.
- Techniques disclosed herein provide a method for substrate patterning that results in lines of non-uniform pitch, sometimes referred to as mixed pitch, Techniques herein can also enable advanced patterning options by selectively replacing lines of material in a multi-line layer, A multi-line layer is formed that has alternating lines of three different materials. One or more etch masks are used to selectively remove at least one uncovered line without removing other uncovered lines. Removed material is replaced with a fill material. Selective removal is executed using an etch mask as well as differing etch resistivities of the different lines of materials.
- One embodiment includes a method of patterning a substrate.
- the method includes forming a multi-line layer on (above) an underlying layer of a substrate.
- FIGS. 1A and 1 B illustrate an example multi-line layer 150 on substrate 105.
- the multi-line layer can be formed directly on the underlying layer 107, or on any intervening layer or interfaciai films or planarization layers, such as on an anti- reflective coating (ARC) layer.
- ARC anti- reflective coating
- the multi-line layer includes a region having a pattern of alternating lines of a first material, a second material, and a third material. Each line has a horizontal thickness, a vertical height, and extends horizontally across the underlying layer.
- Each line of the pattern of alternating lines extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer 150.
- lines alternate in a horizontal direction across a working surface of the substrate and are accessible from a top surface to a bottom surface for full etch removal of the lines.
- the alternating lines can cover essentially an entire surface of a substrate, but in other alternative embodiments only particular regions have the pattern of alternating lines.
- the alternating lines can include straight lines, curved lines, race track path lines, et cetera.
- Another example of alternating lines is a set of concentric circles with each ring being a curved line.
- each line of a particular material can be anisotropicaily etched
- etch resistivities from each other means that there is at least one etchant (or etchant combination) that etches a given one material at a greater rate than the other material(s).
- Etching one material relative to another can include etching one material without substantially etching the other, or etching one material at a substantially greater rate as compared to the other material such as having an etch rate ratio of 3: 1 , 4: 1 , 10: 1 , et cetera.
- FIGS. 1A and 1 B illustrate example results of forming a particular multiline layer.
- the first material, the second material, and the third material can correspond to lines "A,” "B,” and “C.”
- bracket 151 shows a particular pattern segment of alternating lines. This pattern follows a sequence of A-B-C-B, which is then repeated. Thus, this pattern can continue with the sequence of A-B-C- B-A-B-C-B-A-B-C-B-A and so on.
- an alternating pattern of A- B-A-B is used and then one of the two materials is selectively replaced with a third material.
- multi-line layer material A can be isolated from being in contact with material C by having lines of material B on both sides of material A.
- the half pitch of a given material can be varied so that material C can be absent in some regions or larger in other regions.
- the multiline layer 150 can be formed by first forming mandrels, which can be material A.
- the sidewall spacers are formed using the mandrels as material B.
- Sidewail spacers can be formed by conformal deposition of material B followed by spacer etch back to leave deposits only on sidewalls of mandrels.
- Material C or the third material can be deposited as a spin-on material or over-coated material and then recessed to top surfaces of the mandrels by etch back, acid diffusion and development, or otherwise planarized to remove excess material.
- the underlying layer 107 can be silicon nitride. This can be a memorization layer, target layer, or temporary layer such as to help transfer into another underlying layer, such as a metal hard mask.
- the mandrels A can be a silicon material such amorphous silicon.
- Spacers B can be silicon oxide.
- Material C can be metal oxide such as titanium oxide (TiOx).
- TiOx titanium oxide
- a first etch mask is formed on the multi-line layer such as etch mask 141 .
- This first etch mask uncovers a portion of the pattern of alternating lines.
- etch mask 141 is shown directly on multi-line layer 150. Note, however, that additional layers can be used for
- FIGS. 2A and 2B show the substrate 105 with etch mask 141 and with material A having been removed, that is, uncovered portions (non-masked portions) of material A having been removed.
- Removed portions of the first material are then replaced with a fill material that extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer.
- Such removal and replacement can have two or more process steps.
- selective deposition can be executed that selectively deposits on uncovered portions of underlying layer 107 without being deposited on other materials of the multi-line layer.
- material 181 is deposited on the substrate 105 such as by spin-on deposition. Such spin-on deposition typically results in an over coat or over burden of material.
- FIGS. 3A and 3B show material 161 filling removed portions of the first material, but also covering the etch mask 141 .
- the first etch mask is then removed resulting in the multi-line layer having four different materials.
- An example result is illustrated in FIGS. 4A and 4B.
- Such removal can be executed by etch back or chemical-mechanical polishing or other pianarization technique.
- the multi-line layer 150 now can have four different materials.
- the fill material can be a different material from the other lines in the multi-line layer, or can be a same material as one of the other lines, such as a same material as lines B. Choice of material can be based on design objectives of a particular patterning flow.
- a second etch mask such as etch mask 142, is formed on the multi-line layer 150 that uncovers a second portion of the pattern of alternating lines. Portions of the third material of the multi-line layer that are uncovered by the second etch mask are then removed.
- FIGS. 5A and 5B show a portion of material C having been removed. Mask formation and material removal can be executed as previously described.
- Removed portions of the third material are then replaced with a fill material that extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer.
- a fill material that extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer.
- material 162 can be over coated on the substrate 105, and then planarized or otherwise recessed to a top surface of multiline layer 150.
- FIGS. 6A and 8B show material 162 filling removed portions of the third material, but also covering the etch mask 142.
- the second etch mask is then removed resulting in the multi-line layer having four or more different materials.
- An example result is illustrated in FIGS. 7A and 7B.
- Such removal can be executed by etch back or chemical-mechanical polishing or other pianarization technique.
- the multi-line layer 150 now can have four different materials.
- the fill material can be a different material from the other lines in the multi-line layer, or can be a same material as one of the other lines, such as a same material as lines B.
- Material 161 and 162 can be identical if desired.
- the multi-line layer itself can be used as an etch mask for transfer into an underlying layer, or additional etch masks can be formed on/above the modified multi-line layer for etching selected areas of the modified multi-line layer.
- FIGS. 8A and 8B show a modified multi-line layer after removal of lines of the first material and the third material. What remains on the substrate then is lines of the second material as well as replacement material. The remaining material of the multi-line layer can then be used to transfer into underlying layer 107, as shown in FIGS. 9A and 9B, FIGS. 10A and 10B show the multi-line layer having been removed. The result is a pattern of lines of the second material plus additional plugs. Note that entire lines or segments of lines can be replaced to create areas of mixed pitch lines. For example, in some areas all of line A can be removed and replaced with material B, resulting in mixed pitch of remaining lines of material A. Note also that the steps of removal and replacement can be executed any number of times. FIGS. 1 1 A and 1 1 B illustrate a multi-line layer with three replacement steps to create a larger blocked area that includes fill 163.
- a third etch mask can be formed on the multi-line layer that uncovers a third portion of the pattern of alternating lines. Portions of the first material (or second material or third material) of the multi-line layer that are uncovered by the third etch mask are removed. The removed portions can then be replaced. Thus, any combination of etch masks and lines of material can be selectively removed and replaced. Moreover, after forming a modified multiline layer, any number of additional etch masks can be formed thereon for combined transfer into one or more underlying layers. For example, after a modified multi-line layer is formed, an etch mask can be formed thereon that uncovers portions of the modified multi-line layer.
- One or more materials in the modified multi-line layer can then be selectively removed.
- the etch mask on the modified multi-line layer together with the modified multi-line layer itself (having one or more materials removed) then forms a combined etch mask.
- This combined etch mask can then be used to transfer into an underlying layer, such as a memorization layer, target layer, hard mask, et cetera.
- Block masks typically leave relatively small islands, mesas, or pillars on a substrate to block a relatively small portion of a relief pattern from being etch transferred into one or more underlying layers.
- cut or hole masks typically cover most of a substrate surface and have relatively small openings at specific locations to make location-precise etches such as to remove a segment of a line or make a cut in that line or make a via or contact opening.
- One challenge with using block masks or pillar masks is that of pattern collapse. With increased scaling, portions of a pattern that need to be blocked for pattern transfer become increasingly smaller in dimensions. This makes it challenging, for example, to make blocks for narrow pitch back end of line (BEOL) trench patterning, such as for metallization.
- BEOL back end of line
- Techniques herein use customized self-aligned block masks so that un-manageabie overlay requirements are traded off for etch selectivity challenges,
- a self-aligned block mask (multi-line layer) is selectively modified in lines of material as a tone reversal patterning technique instead of using a pillar mask initially.
- CDs Critical dimensions
- Techniques herein use a self-aligned block process with spin-on metal oxide (MeOx) or another material with differing etch resistivity to other patterning materials.
- a given pillar mask is thus replaced with a hole mask, which is structurally better and essentially provides higher flop-over and printabiiity margin.
- CD control is easily controlled by etch shrink for hole mask as compared with trim techniques for pillar mask shrinking. Accordingly, techniques herein can use two spin-on materials for the fourth color material and the tone reversal material, respectively.
- tone reversal material is spin-on glass (SOG).
- substrate or "target substrate” as used herein generically refers to an object being processed in accordance with the invention.
- the substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film.
- substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures.
- the description may reference particular types of substrates, but this is for illustrative purposes only.
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- Engineering & Computer Science (AREA)
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- Manufacturing Of Printed Circuit Boards (AREA)
- Chemical & Material Sciences (AREA)
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- Drying Of Semiconductors (AREA)
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Abstract
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Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020197017076A KR102230086B1 (en) | 2016-11-16 | 2017-11-16 | Sub-resolution Substrate Patterning Method |
| JP2019525945A JP6805414B2 (en) | 2016-11-16 | 2017-11-16 | Sub-resolution substrate patterning method |
| CN201780070924.0A CN109983564B (en) | 2016-11-16 | 2017-11-16 | Method for sub-resolution substrate patterning |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662422840P | 2016-11-16 | 2016-11-16 | |
| US62/422,840 | 2016-11-16 |
Publications (2)
| Publication Number | Publication Date |
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| WO2018094073A2 true WO2018094073A2 (en) | 2018-05-24 |
| WO2018094073A3 WO2018094073A3 (en) | 2018-07-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2017/062053 Ceased WO2018094073A2 (en) | 2016-11-16 | 2017-11-16 | Methods of sub-resolution substrate patterning |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10083842B2 (en) |
| JP (1) | JP6805414B2 (en) |
| KR (1) | KR102230086B1 (en) |
| CN (1) | CN109983564B (en) |
| TW (1) | TWI721231B (en) |
| WO (1) | WO2018094073A2 (en) |
Cited By (1)
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| JP2021170670A (en) * | 2016-12-23 | 2021-10-28 | インテル・コーポレーション | Advanced lithography and self-assembling device |
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| US10388644B2 (en) | 2016-11-29 | 2019-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing conductors and semiconductor device which includes conductors |
| US10867854B2 (en) | 2019-01-08 | 2020-12-15 | Tokyo Electron Limited | Double plug method for tone inversion patterning |
| US20240038547A1 (en) * | 2022-07-26 | 2024-02-01 | International Business Machines Corporation | Method and structure to form connector tabs in subtractive patterning |
| US12451354B2 (en) | 2022-09-09 | 2025-10-21 | Tokyo Electron Limited | Double patterning method of patterning a substrate |
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2017
- 2017-11-16 CN CN201780070924.0A patent/CN109983564B/en active Active
- 2017-11-16 WO PCT/US2017/062053 patent/WO2018094073A2/en not_active Ceased
- 2017-11-16 TW TW106139643A patent/TWI721231B/en active
- 2017-11-16 JP JP2019525945A patent/JP6805414B2/en active Active
- 2017-11-16 KR KR1020197017076A patent/KR102230086B1/en active Active
- 2017-11-16 US US15/815,374 patent/US10083842B2/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021170670A (en) * | 2016-12-23 | 2021-10-28 | インテル・コーポレーション | Advanced lithography and self-assembling device |
| US11854787B2 (en) | 2016-12-23 | 2023-12-26 | Intel Corporation | Advanced lithography and self-assembled devices |
| US12218052B2 (en) | 2016-12-23 | 2025-02-04 | Intel Corporation | Advanced lithography and self-assembled devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2019537266A (en) | 2019-12-19 |
| KR20190073585A (en) | 2019-06-26 |
| US20180138051A1 (en) | 2018-05-17 |
| TWI721231B (en) | 2021-03-11 |
| CN109983564B (en) | 2023-05-02 |
| CN109983564A (en) | 2019-07-05 |
| KR102230086B1 (en) | 2021-03-18 |
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| US10083842B2 (en) | 2018-09-25 |
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| WO2018094073A3 (en) | 2018-07-26 |
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