WO2018085989A1

WO2018085989A1 - Channel allocation and frame transmission controller

Info

Publication number: WO2018085989A1
Application number: PCT/CN2016/105074
Authority: WO
Inventors: 张科峰
Original assignee: 武汉芯泰科技有限公司
Priority date: 2016-11-08
Filing date: 2016-11-08
Publication date: 2018-05-17

Abstract

The present invention relates to the technical field of wireless communications. Disclosed is a channel allocation and frame transmission controller. The controller comprises a control unit (1), a counting conversion unit (2), and a setting unit (3). The counting conversion unit (2) comprises a counter (21), a channel handover setting module (22), a relative-delay setting module (23), and an independent-delay setting module (24). The control unit (1) and the setting unit (3) are separately used for providing a control signal and data to the counting conversion unit (2). The channel handover setting module (22) is used for obtaining a channel handover setting value. The relative-delay setting module (23) is used for obtaining a relative delay value. The independent-delay setting module (24) is used for obtaining an independent delay value. The counter (21) is used for obtaining a channel switching control clock signal, a relative delay control clock signal and an independent delay control clock signal. The controller supports implementation of channel handover and frame transmission control of a hybrid communication mechanism.

Description

Channel allocation and frame transmission controller

Technical field

[0001] The present invention relates to the field of wireless communications technologies, and in particular, to a channel allocation and frame transmission controller.

Background technique

[0002] Currently, a wireless communication chip for a mobile network generally uses only a TDM (Ti me Division Multiplexing) or a Statistical Time Division Multiplexing (STDM).

[0003] TDM allocates a determined channel to each user through a control center, and the channel usage order of each user is determined and does not conflict. When a channel is assigned to a user and the channel is not transmitted, the channel cannot be used by other users.

[0004] TDM includes the following features: 1) the user's use time is allocated by the control center; 2) communication use time and wait time is known; 3) order and do not interfere with each other; 4) use rate fixed; 5) Suitable for real communication. The advantages of TDM are: fixed gap distribution, easy adjustment and control, suitable for digital information transmission; its disadvantages are: low channel and equipment utilization. TDM is widely used in telecommunications telephone networks and IOTs with high requirements.

[0005] STDM is an asynchronous split-multiplexing mechanism. When a user has data to transmit and directly robs line resources, when a user suspends transmitting data, the transmission capability of the line can be used by other users. STDM includes the following features: 1) without control center, the right to grab; 2) unknown length of communication and waiting time; 3) no fixed use order; 4) uneven use rate, up to the total transmission capacity of the line; 5) Applicable to non-real communication. The advantages of STDM are: Improved channel and device utilization; The disadvantages of STDM are: Complex technology (buffered data memory that holds input queue information and more complex addressing and control techniques). STDM is mainly used in IP Internet with low requirements.

It is not difficult to see that TDM and STDM have their own characteristics. According to their respective advantages, the applicable fields are not the same. However, the inability to coexist two mechanisms in a single chip has always been a technically unsolvable problem. At present, the present applicant has invented a hybrid multiplexing and multiplexing mechanism, which is compatible with two communication mechanisms of TD M and STDM in a single wireless communication chip, thereby meeting the requirements of the user for communication reality and channel high utilization. Technical effect. In this regard, there is an urgent need for a channel allocation and frame transmission control scheme to support the normal operation of the hybrid multiplexing and multiplexing mechanism.

technical problem

[0007] There is a lack of technical problems in the prior art that there is a channel switching and frame transmission control scheme that supports a hybrid communication mechanism.

Problem solution

Technical solution

[0008] The present invention is directed to a technical problem in the prior art that lacks a channel switching and frame transmission control scheme supporting a hybrid communication mechanism, and provides a channel allocation and frame transmission controller, which can implement hybrid split multiplexing. The normal operation of the mechanism (compatible with the synchronous split multiplexing mechanism and the statistical split multiplexing mechanism).

The present invention provides a channel allocation and frame transmission controller, including: a control unit, a counter conversion unit, and a numbering unit; wherein the counting conversion unit includes: a counter, a channel switching setting module, and a relative delay setting Number module and independent delay setting module;

[0010] the control unit is configured to provide a clock signal, a clock enable signal, a channel switch enable signal, a relative delay enable signal, and an independent delay enable signal to the count conversion unit;

[0011] the setting unit is configured to provide the counter conversion unit with a counter set address set, and a set of values corresponding to each set address;

[0012] the channel switching and setting module, configured to acquire a channel switching value based on the counter set address set and the set value set under the control of the channel switching enable signal, and Channel switching values are sent to the counter;

[0013] the relative delay setting module is configured to obtain a relative delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and Relative delay value is sent to the counter;

[0014] the independent delay setting module is configured to obtain an independent delay value based on the set of counter set addresses and the set of values under the control of the independent delay enable signal, and Independent delay value is sent to the counter;

[0015] the counter is configured to be based on the cuckoo clock enable signal and the cuckoo clock signal:

[0016] performing a desk conversion on the channel switching value to obtain a channel switching control chirp signal; [0017] performing a chirp conversion on the relative delay set value to obtain a relative delay control chirp signal;

[0018] performing a chirp conversion on the independent delay value to obtain an independent delay control chirp signal;

[0019] wherein the channel switching control chirp signal is used as a channel switching control sequence, the relative delay control chirp signal is used as a frame transmission control sequence, and the independent delay control chirp signal is used as a frame reception control Order.

Advantageous effects of the invention

Beneficial effect

One or more technical solutions provided in the present invention have at least the following technical effects or advantages: Since in the present invention, the channel allocation and frame transfer controller includes a control unit, a count conversion unit, and a set number unit; The method further includes a counter, a channel switching setting module, a relative delay setting module, and an independent delay setting module; and respectively outputting, by the control unit, the channel switching module, the relative delay setting module, and the independent delay setting module, and outputting a channel switching enable signal, a relative delay enable signal, and an independent delay enable signal to respectively acquire a channel switching set value, a relative delay set value, and an independent delay set value; further, the counter is based on the clock enable signal and the a cuckoo clock signal, performing signal conversion on the channel switching value, the relative delay value, and the independent delay value to obtain a channel switching control chirp signal, a relative delay control chirp signal, and independent delay control Cuckoo clock signal to be used as channel switching control sequence, Ordering and transmission control inch inch frame receiving control sequence. The invention solves the technical problem of lacking the channel switching and frame transmission control scheme supporting the hybrid communication mechanism in the prior art, and can support the normal implementation of the hybrid split multiplexing mechanism (compatible with the synchronous split multiplexing mechanism and the statistical split multiplexing mechanism) Work runs.

Brief description of the drawing

DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings to be used in the embodiments or the prior art description will be briefly described below, and obviously, in the following description The drawings are merely examples of the invention, and those skilled in the art can obtain other drawings based on the drawings provided without any inventive effort.

1 is a structural block diagram of a first channel allocation and frame transmission controller according to an embodiment of the present invention;

2 is a structural block diagram of a second channel allocation and frame transmission controller according to an embodiment of the present invention; [0024] FIG. 3 is a schematic diagram of a correspondence between a single inter-cycle period divided into a plurality of synchronous division multiplexing sections and a statistical division multiplexing section and a MAC protocol user according to an embodiment of the present invention;

[0025] FIG. 4 is a schematic diagram of a corresponding relationship between a single inter-cycle period divided into a plurality of synchronous division multiplexing sections and a statistical division multiplexing section and an operating state according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a correspondence between a count value of a state machine counter and a channel access segment in two-dimensional coordinates according to an embodiment of the present invention; FIG.

6 is a schematic structural diagram of a linked list in which a single inter-turn period is divided into three synchronous split multiplexing sections and one statistical split multiplexing section according to an embodiment of the present invention;

7 is a structural block diagram of a counting conversion unit according to an embodiment of the present invention.

Embodiments of the invention

[0029] The embodiment of the present invention solves the technical problem of the channel switching and frame transmission control schemes existing in the prior art, which lacks a hybrid communication mechanism, by providing a channel allocation and frame transmission controller. The frame transmission controller It can support the normal working operation of the hybrid split multiplexing mechanism compatible with the synchronous split multiplexing mechanism and the statistical split multiplexing mechanism.

[0030] The technical solution of the embodiment of the present invention is to solve the above technical problem, and the general idea is as follows:

The embodiment of the present invention provides a channel allocation and frame transmission controller, including: a control unit, a count conversion unit, and a set-number unit; wherein the count conversion unit includes: a counter, a channel switching set module, and a relative a delay setting module and an independent delay setting module; the control unit is configured to provide a clock signal, a clock enable signal, a channel switching enable signal, a relative delay enable signal, and an independent delay to the counting conversion unit a set-up unit, configured to provide a counter set address set to the counter conversion unit, and a set of values corresponding to each set address; the channel switch set-up module, configured to be in the channel Controlling, by the switch enable signal, acquiring a channel switching value based on the set of counter address addresses and the set of values, and transmitting the channel switching value to the counter; the relative delay setting module And for controlling, based on the counter, a set of address sets and the set value under the control of the relative delay enable signal Collecting, obtaining a relative delay value, and transmitting the relative delay value to the counter; the independent delay setting module, configured to set the counter based on the independent delay enable signal a set of addresses and a set of said values, obtained Taking an independent delay value and transmitting the independent delay value to the counter; the counter is configured to calculate the value of the channel switching based on the clock enable signal and the chirp signal吋 converting to obtain a channel switching control chirp signal; performing a chirp conversion on the relative delay setting value to obtain a relative delay control chirp signal; performing a chirp conversion on the independent delay value to obtain an independent delay Controlling a chirp signal; wherein the channel switching control chirp signal is used as a channel switching control sequence, the relative delay control chirp signal is used as a frame transmission control sequence, and the independent delay control chirp signal is used as a frame Receive control sequence.

[0032] It can be seen that, in the solution of the present invention, the channel switching enable module, the relative delay setting module, and the independent delay setting module are respectively outputted by the control unit, and the channel switching enable signal and the relative delay enable signal are output. And an independent delay enable signal to respectively acquire a channel switching value, a relative delay value, and an independent delay value; further, the counter sets a value for the channel switching based on the clock enable signal and the chirp signal And calculating, by using the relative delay value and the independent delay value, to obtain a channel switching control chirp signal, a relative delay control chirp signal, and an independent delay control chirp signal, respectively, for channel switching control Sequence, frame transmission control sequence and frame reception control sequence. The invention solves the technical problem of lacking the channel switching and frame transmission control scheme supporting the hybrid communication mechanism in the prior art, and can support the normal implementation of the hybrid split multiplexing mechanism (compatible with the synchronous split multiplexing mechanism and the statistical split multiplexing mechanism) Work runs.

[0033] In order to better understand the above technical solutions, the above technical solutions will be described in detail in conjunction with the drawings and specific embodiments. It should be understood that the specific features of the embodiments and embodiments of the present invention are the technical solutions of the present application. The detailed description, rather than the limitation of the technical solution of the present application, can be combined with each other in the embodiments of the present invention and the technical features in the embodiments without conflict.

[0034] Embodiment 1

Referring to FIG. 1 , an embodiment of the present invention provides a channel allocation and frame transmission controller, including: a control unit 1, a count conversion unit 2, and a set number unit 3; wherein the count conversion unit 2 includes: a counter 21 a channel switching setting module 22, a relative delay setting module 23, and an independent delay setting module 24; the control unit 1 is configured to provide a clock signal, a clock enable signal, a channel switching enable signal, and a channel switching enable signal to the counting conversion unit 2, a relative delay enable signal and an independent delay enable signal; a setting unit 3, configured to provide the counter conversion unit 2 with a set of counter set addresses, and a set of values corresponding to each set address; Block 22, configured to acquire a channel switching value based on the counter set address set and the set value set under the control of the channel switch enable signal, and send the channel switch value to the counter 21 And a relative delay setting module 23, configured to obtain a relative delay value based on the set of the counter set address and the set of values under the control of the relative delay enable signal, and set the relative delay The value is sent to the counter 21; the independent delay setting module 24 is configured to obtain an independent delay value based on the counter set address set and the set of values under the control of the independent delay enable signal, and The independent delay value is sent to the counter 21; the counter 21 is configured to perform, based on the chirp enable signal and the chirp signal, a value conversion of the channel switching value to obtain a channel switching control clock a signal; performing a chirp conversion on the relative delay value to obtain a relative delay control chirp signal; performing the independent delay value The conversion is performed to obtain an independent delay control chirp signal.

[0036] Specifically, referring to FIG. 2, the counter 21 includes: a first meter conversion module 211, configured to perform a meter conversion on the channel switching value to obtain a channel switching control chirp signal;

The second meter conversion module 212 is configured to perform a program conversion on the relative delay value to obtain a relative delay control clock signal; and a third meter conversion module 213, configured to perform the independent delay value The conversion is performed to obtain an independent delay control chirp signal.

[0037] wherein the channel switching control chirp signal is used as a channel switching control sequence, the relative delay control chirp signal is used as a frame transmission control sequence, and the independent delay control chirp signal is used as a frame reception control Order.

[0038] In the specific implementation process, still referring to FIG. 2, the control unit 1 includes: a chirp signal generating module 11 for generating and outputting the chirp signal; a chirp enable signal generating module 12 for generating And outputting the clock enable signal; the channel switch enable signal generating module 13 is configured to generate and output a channel switch enable signal; the delay enable signal generating module 14 is configured to generate and output the relative delay enable A signal and the independent delay enable signal.

[0039] The counting conversion unit 2 is a core module of the channel allocation and frame transmission controller. According to the foregoing function description of the counting conversion unit 2, the channel allocation and frame transmission controller mainly includes three aspects: 1) channel switching control 2) Relative delay switching control; 3) Independent delay switching control. The following three aspects are specifically introduced: [0040] (1) Channel switching control

[0041] In a specific implementation process, the channel allocation and frame transmission controller of the present application may be disposed inside the communication chip, and a control center master is disposed inside the communication chip, and a MAC protocol user connected to the control center Master usually includes following synchronization. MAC protocol users of the TDM (Time Division Multiplexing) and the statistical division multiplexing mechanism (STDM, Statistical Time Division)

Multiplexing) MAC protocol users. The Control Center Master can estimate the length of the data frame to be sent by all MAC protocol users connected to it, and determine the length of a single inter-cycle period based on the length of the acquired data frame. ^ Further, the Control Center Master is based on the length of a single inter-turn period T and TDM. The length of the transmission data frame required by the user of the MAC protocol is determined by the Hybrid Time Division Multiplexing (HTDM) working status table corresponding to the length T of the individual inter-turn period. The status information contained in the working status table is as follows: 1 shows:

[0042] Table 1 HTDM working status table

[]

Among them, Table 1 only lists some parameter categories of the working status table, and can form a complete working status table corresponding to the setting parameter values. Synchronous split multiplexing section Ttd occupies a single inter-turn period length T proportional value (κ = Ttd/T) adjustable between 0~1.

[0044] As shown in FIG. 3, the number of MAC protocol users of the TDM is n (an integer greater than 1), and correspondingly, the synchronous split multiplexing section Ttd is divided into n synchronous split multiplexing subsections Ttdl. ~Ttdn. The n-synchronous split-multiplex sub-sections Ttdl~Ttdn can be used to correspond to n TDM MAC protocol users U1~Un. Of course, in a specific implementation process, one TDM MAC protocol user can also correspond to multiple synchronizations. The multiplex sub-section is not limited here. In addition, the length of the plurality of synchronous split multiplexing sub-frames depends on the length of the data frame to be transmitted by the corresponding M AC protocol user.

[0045] Taking a protocol type of a TDM MAC protocol user as an example, the protocol types of any two MAC protocol users of the N TDM MAC protocol users (Ul~Un) may be the same or different, for example: User U1 The corresponding protocol type is TD-SCDMA, and the protocol type corresponding to user U2 is WCDMA, user. The protocol type corresponding to U3 is 802.16, ..., and the protocol type corresponding to User Un is TD-SCDMA.

[0046] For the statistical division multiplexing section Tstd, the user access situation of the segment cannot be agreed in advance, and the user access information such as the user and the user accessing the channel can be known only after the user finishes using the channel. As shown in FIG. 3, the MAC protocol user corresponding to the statistical division multiplexing section Tstd is Ux.

[0047] In a specific implementation process, the HTDM implements the working state switching of the plurality of synchronous split multiplexing sub-sections Ttdl~Ttdn through a state machine model. HTDM realizes the switching of the working state of the synchronous division multiplexing section T td and the statistical division multiplexing section Tstd through the state machine model. Specifically, referring to FIG. 4, a single inter-turn period T is divided into a synchronous split-multiplex section Ttd and a statistical split-multiplex section Tstd, and the synchronous split-multiplex section Ttd is divided into n synchronization splits. The sub-sections Ttdl~Ttdn are used to correspond to n+1 states S1~Sn+l, wherein the states S1~Sn- one correspond to n synchronous split multiplex sub-sections Ttdl~Ttdn, and the state Sn+1 corresponds to The statistical division multiplexing section Tstd.

[0048] As can be seen from the above, each operating state of the state machine corresponds to each segment divided by a single inter-turn period. In the specific implementation process, the state machine control module is set in the control unit 1, by each segment

(ie, each working state) corresponds to the counter value of the counter, and in the process of gradually accumulating or gradually decreasing the counter value, the interrupt request is sent to the state machine controller at a specific moment to realize the switching of each working state. .

[0049] Please refer to FIG. 5 , which is a schematic diagram of the correspondence between the counter count value Count of the counter and the channel access segment t in two-dimensional coordinates, and the counter count value is gradually accumulated, and the synchronous split multiplexing section Ttd is divided into three. For example, the synchronous split multiplexing sub-section Ttdl~Ttd3, the state machine includes four working states S1~S4:

[0050] When Count is greater than or equal to 0 and less than C1吋, the state machine works in the segment Ttdl, corresponding to the working state S1;

[0051] When Count is greater than or equal to C1 and less than C2吋, the state machine works in the segment Ttd2, corresponding to the working state S2;

[0052] When Count is greater than or equal to C2 and less than C3, the state machine works in the segment Ttd3, corresponding to the working state S3;

[0053] When Count is greater than or equal to C3 and less than C4, the state machine operates in the segment Tstd, corresponding to the working state S4.

[0054] wherein, the segments Ttdl~Ttd3 together constitute a complete synchronous division multiplexing section Ttd, and the counter sends a first interrupt request to the state machine controller at the count value Count=0 (ie, starts counting 吋), Entering state S1; the counter sends a second interrupt request to the state machine controller to enter state S 2 at the count value Coimt=Cl; the counter sends a third interrupt request to the state machine controller at the count value Coimt=C2 to enter State S3; the counter sends a fourth interrupt request to the state machine controller at the count value Coimt=C3 to enter the state State S4; The counter sends a fifth interrupt request to the state machine controller at the count value Coimt=C4, indicating that the work of one day period has been completed, and the counter is zeroed for resuming counting in the next cycle. .

[0055] In a specific implementation process, the state machine can also be implemented in conjunction with a linked list, which is a common and important data structure. It is a structure for dynamically performing storage allocation. It can create memory units as needed. The linked list has a "header pointer" variable that holds an address. The address points to an element. Each element in the linked list is called a "node", and each node should consist of two parts: one for the actual data the user needs, and two for the address of the next node. Therefore, the "head pointer" variable points to the first element; the first element points to the second element; ..., until the last element, the element no longer points to other elements, it is called the "footer" ", its address part puts a "NULL" (indicating "empty address"), and the list ends here; of course, depending on the application, the last element can also point to the first element to form a circular working mode.

Referring to FIG. 6, the synchronous split multiplexing section Ttd is still divided into three synchronous split multiplexing subsections Ttdl~Ttd3, where As is the header address and LEN is the register of the existing address set. The length, Atdl is the working state parameter storage address corresponding to the synchronous split multiplexing sub-section Ttdl, Atd2 is the working state parameter storage address corresponding to the synchronous split multiplexing sub-section Ttd2, and Atd3 is the synchronous split-multiplexer The working state parameter storage address corresponding to the segment Ttd3, and Astd is the storage state parameter storage address corresponding to the statistical segmentation multiplexing segment Tstd.

[0057] After controlling the state machine, the state machine controller first acquires the header address As of the linked list corresponding to the event period (ie, the state machine pointer P first points to the header address As), and points according to the header address As The node (ie, the register), obtains the address of the next node, such as Atdl, and further, according to the node pointed to by the address Atdl (ie, the register), on the one hand, obtains the work corresponding to the synchronous split multiplexing sub-section Ttdl The parameter (including the value obtained by the corresponding setting unit) includes: the counter value of the counter corresponding to the sub-section Ttdl, the MAC protocol user name and the MAC protocol type working in the segment Ttdl, and the like, on the other hand, The address of a node, such as Atd2, and after the count value corresponding to the sub-section Ttdl ends, jumps to the next node address and enters the working state corresponding to the next segment. Other situations and so on, are not repeated here. The dotted arrow in Fig. 6 shows the sequential address pointing of the pointer P.

[0058] In order to achieve the above state transition (ie, channel switching), the control unit 1 generates a channel switch according to communication requirements. The enable signal is controlled by the control channel switching module 22 to obtain a channel switching value (usually a plurality of values) based on the counter set address set and the set of value sets (the principle is the same as the above state machine linked list), and The channel switching value is sent to the counter 21, so that the counter 21 performs a count conversion on the plurality of channel switching values based on the state switching principle shown in FIG. 5, that is, the value is switched to a set interval on a certain channel, and The enable signal is valid, generating a rising edge of the chime (as indicated by the chirp signal CLKx in Fig. 5), and jumping out of the set interval after the counter is incremented or decremented based on the channel switching value, generating a chirp Falling edge. That is to say, based on the channel switching control, the chirp signal, after its rising edge, enters a state, and after the falling edge comes, the current state ends, and after another rising edge, the next state is entered, .. . Other cases and so on, here are not repeated.

[0059] Based on the channel switching principle, in the embodiment of the present application, in order to implement switching between a TDM channel and an STDM channel and switching between TDM subchannels, refer to FIG. 2, the channel switching enable signal generating module. 13 includes: a first switching enable signal generating sub-module 131, configured to generate and output a synchronous split multiplexing channel switching enable signal; a second switching enable signal generating sub-module 132, configured to generate and output a statistical splitting The channel switching enable signal is used, wherein the synchronous split multiplexing channel switching enable signal is used to control channel switching of the synchronous split multiplexing mechanism, and the statistical split multiplexing channel switching enable signal is used for controlling statistics. Channel switching of the split multiplexing mechanism.

[0060] Further, the channel switching and setting module 22 includes: a first switching control sub-module 221, configured to set the address set based on the counter under the control of the synchronous split multiplexing channel switching enable signal And setting the set of values, obtaining a synchronous split multiplexing channel switching value, and transmitting the synchronous split multiplexing channel switching value to the counter 21, so that the counter 21 divides the synchronization into the synchronization The channel switching value is calculated and converted to obtain a synchronous split multiplexing channel switching control chirp signal; the second switching control sub-module 222 is configured to be under the control of the statistical split multiplexing channel switching enable signal. Obtaining a statistical split-multiplex channel switching value based on the counter set address set and the set value set, and sending the statistical split-multiplex channel switching value to the counter 21 to enable the counter 21 The statistical split-multiplex channel switching value is calculated and converted to obtain a statistical split-multiplex channel switching control clock signal.

[0061] (2) Relative delay switching control (ie, TDM subchannel frame transmission control)

[0062] For information transmission based on TDM, different sub-sections Ttdl~Ttdn respectively correspond to different TDM sub- The channel is used for allocation to different TDM protocol users. To adapt to each TDM protocol, the frame transmission rule may be preset, that is, the transmission delay, the frame protection period, the pre-delay, and the frame reception are set during the frame transmission process. In the meantime, according to the protocol user corresponding to the TDM sub-section that is switched in, by the control of the enable signal, the delay and frame are obtained and sent from the counter set address set and the set value set corresponding to each set address. The values corresponding to the protection period, the pre-delay and the frame reception time are further set, and further, the counters are used to perform one-to-one correspondence between the values, to obtain the delay between the transmission, the frame protection, and the delay. And control the chirp signal corresponding to the frame receiving time.

[0063] In a specific implementation process, referring also to FIG. 2, the relative delay setting module 23 includes:

[0064] a frame transmission delay number sub-module 231, configured to acquire a frame transmission delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and The frame transmission delay value is sent to the counter 21, so that the counter 21 performs a frame conversion on the frame transmission delay value to obtain a frame transmission delay control clock signal;

[0065] a frame protection delay number sub-module 232, configured to obtain a frame protection delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and The frame protection delay value is sent to the counter 21, so that the counter 21 performs a frame conversion on the frame protection delay value to obtain a frame protection delay control chirp signal;

[0066] a frame preamble number submodule 233, configured to obtain a pre-frame delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, And sending the frame pre-delay value to the counter 21, so that the counter 21 performs a delay conversion on the pre-delay value of the frame to obtain a delay control clock signal before the frame is sent;

[0067] a frame receiving delay sub-module 234, configured to obtain a frame reception delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and The frame reception delay value is sent to the counter 21 to cause the counter 21 to perform a frame conversion on the frame reception delay value to obtain a frame reception delay control chirp signal. In the specific implementation process, please refer to FIG. 2 again, the numbering unit 3 includes: a user setting module 31 and a random number module 32; wherein the user setting unit 31 is configured to acquire and store a set value set by the user, random The setting module 32 is configured to acquire and store the random value; the control unit 1 includes: a setting selection module 15 connected to the user setting module 31 and the random number module 32, for controlling the user setting module 31 and/or The random number module 32 inputs to the counter conversion unit 2 A counter set address set and a set of values corresponding to each set address are output.

[0068] In the process of implementing the channel switching control and the relative delay switching control, the selection setting module 15 of the control unit 1 controls the selection user setting module 31 to output the counter setting address set and the setting to the counting conversion unit 2. A set of values corresponding to the number address.

[0069] In addition, for the information transmission based on the STDM, the user access situation of the statistical division multiplexing section Tstd cannot be agreed in advance, and only after the user finishes using the channel, can the user who accesses the channel and the user access the user such as the length of the channel can be known. Use information. In order to be able to use the channel after a user STDM protocol user has finished using the channel, it is used for another round of competitive use by the STDM protocol user. In a specific implementation process, the selection random selection module 32 controls the selection of the counter address set and the set of values corresponding to the respective set addresses by the set selection module 15.

[0070] Still referring to FIG. 2, the count conversion unit 2 further includes: a random delay setting module 25 connected to the random number setting module 32, and a random counting unit 26 connected to the random delay setting module 25;

[0071] The random delay setting module 25 is configured to control the selection random number module 32 to output the counter set address set and the set value set corresponding to each set address to the count conversion unit 2 in the set selection module 15 based on And setting a set of counters and a set of values corresponding to each set address to obtain a random delay value, and sending the random delay value to the counter 21, so that the counter 21 performs the conversion of the random delay value. Obtaining a first trigger signal; wherein, in the generation of the first trigger signal, the statistical split-multiplex channel starts transmitting the current frame data (ie, the protocol user of the STD M that obtains the channel usage right through competition) Send frame data);

[0072] The random counting unit 26 is configured to start counting under the control of the first trigger signal, and after the current frame data is sent, stop counting, to obtain a frame transmission count value, and to the frame The count value is sent for conversion, to obtain a second trigger signal.

[0073] In a specific implementation, the frame transmission controller further includes: a first random enable signal generating unit 4 connected to the random number setting module 32 and the random delay setting module 25, and connected to the random counting unit 26 a second random enable signal generating unit 5;

The first random enable signal generating unit 4 is configured to, in the set number selection module 15 , control the selection random number module 32 to output the counter set address set and the set value corresponding to each set address to the count conversion unit 2 Collecting a first random enable signal for controlling the random delay setting module 25 based on the counter The set of address addresses and the set of values corresponding to each set address obtain a random delay value;

[0075] The second random enable signal generating unit 5 is configured to generate a second random enable signal for controlling the random counting unit 26 to stop counting after the current frame data is transmitted.

[0076] wherein, the second trigger signal determines that the current STDM protocol user uses the STDM channel, and calculates the STDM residual channel width.

(3) Independent delay switching control

[0078] In a specific implementation, at least one setting unit may be disposed in the independent delay setting module 24, for setting the address set and the set value from the counter under the control of the independent delay enable signal The set obtains at least one independent delay set value to cause the counter 21 to convert at least one independent delay set value to an independent delay control chirp signal to provide data reception sequence or for other communication needs.

[0079] In the above process of implementing the independent delay switching control, the selection user setting module 31 or the random setting module 32 may be controlled to output the counter setting address to the counting conversion unit 2 through the setting selection module 15 of the control unit 1 according to actual needs. A set and a set of values corresponding to each set address.

[0080] In a specific implementation process, the counter 21 includes a plurality of meter conversion modules; and the control unit 1 is further configured to control the plurality of meter conversion modules to work in series or in parallel. Specifically, the control unit 1 outputs an enable control signal to the plurality of meter conversion modules to control the serial operation or the parallel operation. In summary, in the solution of the present invention, the channel switching enable signal, the relative delay enable signal, and the independent delay are respectively outputted to the channel switching setting module, the relative delay setting module, and the independent delay setting module by the control unit. The enable signal is respectively configured to obtain a channel switching value, a relative delay value, and an independent delay value; further, the counter sets a value for the channel switching based on the clock enable signal and the chirp signal Calculating a relative delay set value and the independent delay value to obtain a channel switching control chirp signal, a relative delay control chirp signal, and an independent delay control chirp signal, respectively, for use as a channel switching control sequence, Frame transmission control sequence and frame reception control sequence. The invention solves the technical problem of lacking the channel switching and frame transmission control scheme supporting the hybrid communication mechanism in the prior art, and can support the normal implementation of the hybrid split multiplexing mechanism (compatible with the synchronous split multiplexing mechanism and the statistical split multiplexing mechanism) Work runs.

Embodiment 2

[0082] Based on the same inventive concept, the embodiment of the present application further provides a counting conversion unit, which is applied to implement In the channel allocation and frame transmission controller of the first embodiment, the controller further includes a control unit and a setting unit connected to the counting conversion unit, wherein the control unit is configured to control the working operation of the counting conversion unit.

Referring to FIG. 7, the counting conversion unit includes a main counter Co _Un _er _M (corresponding to the counter 21 in the first embodiment) and m+1 channel switching setting units (NTD1~NTDm, NSTD) (corresponding to The channel switching set-up module 22) and the four relative delay setting units (NTe, NTp, NTs. NTch) in the first embodiment (corresponding to the relative delay setting module 23 in the first embodiment), n independent delay sets Unit (NT1 N Tn) (corresponding to the independent delay setting module 24 in the first embodiment); wherein m and n are integers greater than or equal to 1.

[0084] In conjunction with FIG. 7, the control unit is configured to output a chirp signal CLK, a chirp enable signal CLKen, and m+1 channel switching setting units (NTD1~NTDm, NSTD) to the counting conversion unit. A corresponding channel switching enable signal (En_tdl~

En_tdm, En_std), and four relative delay set units (NTe, NTp, NTs, NTch) - corresponding relative delay enable signals (En_te, En_tp, En_ts, En_tch), and n independent delay set units ( ΝΤ1~ΝΤη) - a corresponding independent delay enable signal (Εη_1~ Εη_ _η ); the set unit is configured to provide the counter conversion address set Ato to the count conversion unit, and corresponding to each set address The set of values Dto.

(1) Channel switching control

[0086] The m+1 channel switching and setting units (NTD1~NTDm, NSTD) are respectively corresponding one-to-one under the control of the channel switching enable signal (En_tdl~En_tdm, En_std), and the counter sets the address set Ato and the set value. The set Dto obtains the corresponding set value, and performs the conversion calculation by the set value corresponding to the main counter c _oun t _er _ ^ to obtain the channel switching control chirp signal (Dtdl~Dtdm, Dstd). The channel switching principle is the same as that in the first embodiment, and details are not described herein again.

(2) Relative delay switching control

[0088] Four relative delay setting units (NTe, NTp, NTs, NTch) respectively - corresponding to the relative delay enable signals (En_te, En_tp, En_ts, En_tch), from the counter set address set At o The set value Dto is used to obtain the corresponding set value, and the corresponding set value is calculated and converted by the main counter C _OUn ter_M to obtain the channel switching control chirp signal (DTe, DTp, DTs, DTch). (3) Independent Delay Switching Control

[0090] n independent delay setting units (ΝΤ1~ΝΤη) are respectively corresponding one by one under the control of the independent delay enable signal (Εη_1 ~ Εη_η), and obtain corresponding positions from the counter set address set Ato and the set value set Dto The value is calculated and converted by the main counter Coimter-M to obtain the channel switching control chirp signal (DT1~DTn).

[0091] In the specific implementation process, still refer to FIG. 7, the setting unit includes: a user setting module Memory 1 and a random number setting module Mem _OT y2 _; wherein the user setting unit Memory1 is used to acquire and store the user. Set the set value, the random number module Mem _OT y2 is used to acquire and store the random set value; the control unit is used to control the selection of the user set module Memory1 and/or the random set module Mem _OT y2 to convert the count The unit output counter sets the address set Ato and the set value Dto corresponding to each set address.

[0092] In the process of implementing the channel switching control and the relative delay switching control, the control unit may control the selection of the user setting module Memory 1 to output the counter setting address set Ato and the respective setting addresses to the counting conversion unit. Corresponding set of values Dto.

[0093] In addition, in the specific implementation process, the counting conversion unit further includes: a random delay setting module NR connected to the random setting module Memor y2, a random counting unit Co unter_S connected to the random delay setting module NR;

[0094] a random delay setting module NR, configured to output, from the control unit control selection random number module Memory 2, the counter setting address set Ato and the set value set corresponding to each set address to the counting conversion unit Dto吋, based on the counter set address set Ato and the set value set D to corresponding to each set address, obtain a random delay set value, and send the random delay set value to the main counter Coimter_M, so that the main The counter Coimter-M performs the conversion based on the random delay value to obtain the first trigger signal En_s; wherein, after generating the first trigger signal En_^, the statistical division multiplexing channel starts transmitting the current frame Data

[0095] a random counting unit C _OU nt _er _S, used to start counting under the control of the first trigger signal En_s, and after the current frame data is transmitted, stop counting to obtain a frame transmission count value, The frame transmission count value is calculated and converted to obtain a second trigger signal Tcs.

[0096] In a specific implementation process, the counting conversion unit further includes: a first random enable signal generating unit ENS1 with a random number setting module Mem _OT y2 and a random delay setting module NR, and a random counting unit Cmmte a second random enable signal generating unit ENS2 connected to r_S;

a first random enable signal generating unit ENS1, configured to output, to the counting conversion unit, a counter set address set and a set of value values corresponding to each set address in the random number setting module Mem _OT y2 to generate a first a random enable signal En_rl for controlling the random delay setting module NR to obtain a random delay value based on the set of counter set addresses and a set of values corresponding to each set address;

[0098] The second random enable signal generating unit ENS2 is configured to generate a second random enable signal En_r2 after the current frame data is transmitted, for controlling the random counting unit Cmmter_S to stop counting.

[0099] In a specific implementation, the master counter Co _Un t _er _M inch gauge comprises a plurality of conversion modules; the control unit for controlling the plurality of further inch gauge conversion modules operating in parallel or serial work. Specifically, the control unit outputs an enable control signal to the plurality of meter conversion modules to control the serial operation or the parallel operation.

According to the above description, the counting conversion unit in the second embodiment is applied to the channel allocation and frame transmission controller of the first embodiment, so that the counting conversion unit and one or more of the above channel allocation and frame transmission controllers are used. The embodiments are identical and will not be described again here.

[0101] While the preferred embodiment of the invention has been described, it will be apparent that those skilled in the art can make further changes and modifications to the embodiments once the basic inventive concept is known. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and the modifications and

[0102] It will be apparent to those skilled in the art that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and the modifications of the invention

Claims

Claim

[Claim 1] A channel allocation and frame transmission controller, comprising: a control unit (1)

And a counting conversion unit (2) and a setting unit (3); wherein the counting conversion unit (2) comprises: a counter (21), a channel switching setting module (22), a relative delay setting module (23), and Independent delay setting module (24);

The control unit (1) is configured to provide a clock signal, a clock enable signal, a channel switch enable signal, a relative delay enable signal, and an independent delay enable signal to the count conversion unit (2);

The setting unit (3) is configured to provide a counter setting address set to the counting conversion unit (2), and a set value set corresponding to each set address; the channel switching setting module (22), And acquiring, under the control of the channel switching enable signal, a channel switching value based on the set of counter setting addresses and the set of values, and sending the channel switching value to the counter (21) The relative delay setting module (23) is configured to obtain a relative delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and The relative delay value is sent to the counter (21); the independent delay setting module (24) is configured to, based on the independent delay enable signal, set the address set based on the counter Determining a set of values, obtaining an independent delay value, and transmitting the independent delay value to the counter (21); the counter (21), for a chirp enable signal and the chirp signal: performing a desk conversion on the channel switching value to obtain a channel switching control chirp signal; performing a chirp conversion on the relative delay setting value to obtain a relative delay control Cuckoo clock signal

Performing a meter conversion on the independent delay value to obtain an independent delay control clock signal;

The channel switching control chirp signal is used as a channel switching control sequence, and the relative delay control chirp signal is used as a frame transmission control sequence, and the independent delay control chirp signal is used as a frame reception control sequence.

[Claim 2] The channel allocation and frame transmission controller according to claim 1, wherein the control Unit (1) includes:

a cuckoo clock signal generating module (11) for generating and outputting the cuckoo clock signal; a cuckoo clock enable signal generating module (12) for generating and outputting the cuckoo clock enable signal; channel switching enable signal generating a module (13) for generating and outputting a channel switching enable signal;

The delay enable signal generating module (14) is configured to generate and output the relative delay enable signal and the independent delay enable signal.

[Claim 3] The channel allocation and frame transmission controller according to claim 2, wherein the channel switching enable signal generating module (13) comprises:

a first switching enable signal generating sub-module (131) for generating and outputting a synchronous split multiplexing channel switching enable signal;

a second switch enable signal generating sub-module (132) for generating and outputting a statistical split-channel switching enable signal;

The synchronous split multiplexing channel switching enable signal is used to control channel switching of the synchronous split multiplexing mechanism, and the statistical split multiplexing channel switching enable signal is used to control a channel of the statistical split multiplexing mechanism. Switch.

[Claim 4] The channel allocation and frame transmission controller according to claim 3, wherein the channel switching and setting module (22) comprises:

a first switching control sub-module (221), configured to obtain synchronous split multiplexing based on the counter set address set and the set of values under control of the synchronous split multiplexing channel switching enable signal Channel switching sets a value, and sends the synchronous split multiplex channel switching value to the counter (21) to cause the counter (21) to calculate the value of the synchronous split multiplexing channel switching. Converting to obtain a synchronous split-multiplexed channel switching control chirp signal;

a second switching control sub-module (222), configured to obtain statistical split multiplexing based on the counter set address set and the set of values under the control of the statistical split multiplexing channel switching enable signal Channel switching sets a value, and sends the statistical split multiplex channel switching value to the counter (21) to cause the counter (21) to compare the statistics The split-multiplexed channel switching values are used for counting conversion to obtain a statistical split-multiplexed channel switching control chirp signal.

[Claim 5] The channel allocation and frame transmission controller according to claim 1, wherein the counter (21) comprises:

a first meter conversion module (211), configured to perform a clock conversion on the channel switching value to obtain a channel switching control chirp signal;

a second counting conversion module (212), configured to perform a conversion conversion on the relative delay setting value to obtain a relative delay control chirp signal;

The third meter conversion module (213) is configured to perform the conversion of the independent delay value to obtain an independent delay control chirp signal.

[Claim 6] The channel allocation and frame transmission controller according to claim 1, wherein the relative delay setting module (23) comprises:

a frame transmission delay number submodule (231), configured to acquire a frame transmission delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and Transmitting a frame transmission delay value to the counter (21), so that the counter (21) performs a frame conversion on the frame transmission delay value to obtain a frame transmission delay control chirp signal;

a frame protection delay number submodule (232), configured to obtain a frame protection delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and The frame protection delay value is sent to the counter (21), so that the counter (21) performs a frame conversion on the frame protection delay value to obtain a frame protection delay control clock signal;

a frame delay preamble submodule (233), configured to obtain a pre-frame delay value based on the counter set address set and the set value set under the control of the relative delay enable signal, and Sending the pre-frame delay value to the counter (21), so that the counter (21) performs a post-delay delay on the frame to obtain a pre-frame delay control chirp signal. ;

a frame receiving delay sub-module (234) for controlling the relative delay enable signal Forming, based on the set of counter number addresses and the set of values, obtaining a frame reception delay value, and transmitting the frame reception delay value to the counter (21), so that the counter (21) And performing a frame conversion on the frame reception delay value to obtain a frame reception delay control clock signal.

[Claim 7] The channel allocation and frame transmission controller according to claim 1, wherein the setting unit (3) comprises: a user setting module (31) and a random number setting module (32); The user setting unit (31) is configured to acquire and store a set value set by a user, and the random number setting module (32) is configured to acquire and store a random set value;

The control unit (1) comprises:

a set selection module (15) connected to the user set module (31) and the random number module (32) for controlling selection of the user set module (31) and/or random set module (32) And outputting, to the counting conversion unit (2), a set of counter set addresses and a set of set values corresponding to the respective set addresses.

[Claim 8] The channel allocation and frame transmission controller according to claim 7, wherein the counting conversion unit (2) further comprises: a random delay connected to the random numbering module (32) a number module (25), a random counting unit (26) connected to the random delay setting module (25);

The random delay setting module (25) is configured to control, by the setting selection module (15), selecting the random setting module (32) to output a counter setting address set to the counting conversion unit (2) and And setting a set of values corresponding to each set address, obtaining a random delay value based on a set of counter set addresses and a set of values corresponding to each set address, and transmitting the random delay value to the counter (21) So that the counter (21) performs the conversion conversion on the random delay value to obtain the first trigger signal; wherein, in the generation of the first trigger signal, the statistical division multiplexing channel Send the current frame data;

The random counting unit (26) is configured to start counting under the control of the first trigger signal, and after the current frame data is sent, stop counting, to obtain a frame transmission count value, and to The frame transmission count value is calculated and converted to obtain a second trigger signal.

[Claim 9] The channel allocation and frame transmission controller according to claim 8, wherein the frame transmission controller further comprises: the random number setting module (32) and the random delay setting a first random enable signal generating unit (4) connected to the module (25), and a second random enable signal generating unit (5) connected to the random counting unit (26);

The first random enable signal generating unit (4) is configured to control, in the setting selection module (15), to select the random setting module (32) to output a counter to the counting conversion unit (2) And generating a first random enable signal for controlling the random delay setting module (25) based on the set of counter address addresses and each of the set of address numbers and the set of values corresponding to each set address The set of values corresponding to the number address obtains a random delay value;

The second random enable signal generating unit (5) is configured to generate a second random enable signal for controlling the random counting unit after the current frame data is transmitted.

) Stop counting.

[Claim 10] The channel allocation and frame transmission controller according to claim 1, wherein the counter (21) includes a plurality of meter conversion modules; and the control unit (1) is further used to control the The plurality of meter conversion modules operate in series or in parallel.