WO2018047689A1 - Switching circuit - Google Patents

Switching circuit Download PDF

Info

Publication number
WO2018047689A1
WO2018047689A1 PCT/JP2017/031100 JP2017031100W WO2018047689A1 WO 2018047689 A1 WO2018047689 A1 WO 2018047689A1 JP 2017031100 W JP2017031100 W JP 2017031100W WO 2018047689 A1 WO2018047689 A1 WO 2018047689A1
Authority
WO
WIPO (PCT)
Prior art keywords
switching element
gate
capacitor
circuit
switching
Prior art date
Application number
PCT/JP2017/031100
Other languages
French (fr)
Japanese (ja)
Inventor
祐樹 石倉
植木　浩一
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2018047689A1 publication Critical patent/WO2018047689A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a switching circuit including a gate drive circuit for a switching element.
  • Error firing means that when the MOSFET of one arm of the upper and lower arms (MOSFET including silicon carbide (SiC) as a component, SiC-MOSFET) is changed from the off state to the on state, the other arm that should be in the off state. This is a phenomenon in which the gate potential of the arm rises due to rapid (dv / dt), and the MOSFET of the other arm also turns on.
  • MOSFET silicon carbide
  • Non-Patent Document 1 as a countermeasure against this false ignition, a Zener die auto is inserted between the source of the MOSFET and the ground line, and a negative voltage is applied to the gate of the MOSFET when the MOSFET is turned off.
  • a method for preventing turn-on by a feedback current flowing through the feedback capacitor is disclosed.
  • Non-Patent Document 1 since a negative voltage (-3.9 V) applied to the gate of the MOSFET is applied, the source potential of the MOSFET differs from the ground potential, making it difficult to achieve consistency with peripheral circuits. It becomes.
  • an object of the present invention is to provide a switching circuit that avoids the occurrence of false firing while keeping the source potential of the MOSFET equal to the ground potential.
  • a switching circuit includes a switching element made of SiC-MOSFET and a gate driving circuit that drives the switching element.
  • the gate driving circuit has a driver and an anode connected to the gate of the switching element.
  • a Zener diode whose cathode is connected to the driver; a first capacitor connected in parallel to the Zener diode; a diode whose anode is connected to the gate of the switching element; a cathode of the diode; and a source of the switching element.
  • a second capacitor connected to the capacitor.
  • a reverse bias voltage can be applied between the gate and source of the switching element when an L level signal is output from the driver by using the Zener voltage of the Zener diode and the charge / discharge of the first capacitor.
  • the current flowing through the body diode of the switching element can maintain the reverse bias state between the gate and the source even if the feedback current flows through the drain-gate capacitance, and the switching element is not turned on. Thereby, it is possible to avoid the occurrence of false firing while keeping the source potential of the MOSFET equal to the ground potential.
  • the capacitance of the first capacitor is preferably larger than the capacitance of the second capacitor.
  • a reverse bias voltage can be applied between the gate and the source of the switching element to avoid the occurrence of false firing.
  • FIG. 1 is a circuit diagram of a switching power supply according to the embodiment.
  • FIG. 2 is a circuit diagram of the gate driving circuit.
  • 3A is a diagram for explaining the operation of each gate drive circuit when the switching element is turned on
  • FIG. 3B is a diagram for explaining the operation of each gate driving circuit when the switching element is turned off.
  • FIG. 1 is a circuit diagram of a switching power supply 100 according to the present embodiment.
  • Switching power supply 100 transforms a DC voltage from DC power supply Vin and outputs it to a load connected to output units Out1 and Out2.
  • the switching power supply 100 includes a switching circuit 10.
  • the switching circuit 10 includes a full bridge circuit 11 and a gate drive circuit 12.
  • a series circuit of switching elements Q11 and Q12 and a series circuit of switching elements Q13 and Q14 are connected in parallel.
  • Each of the switching elements Q11, Q12, Q13, and Q14 is a SiC-MOSFET, and the switching is controlled by the gate drive circuit 12.
  • the gate drive circuit 12 alternately turns on and off the switching elements Q11 and Q14 and the switching elements Q12 and Q13, and converts the DC voltage from the DC power supply Vin into an AC voltage.
  • the full bridge circuit 11 is connected to the primary winding of the transformer T1.
  • the transformer T1 is represented as an ideal transformer.
  • An inductor L1 and a capacitor C1 are provided between the full bridge circuit 11 and the transformer T1.
  • the inductor L1 and the capacitor C1 constitute a resonance circuit with the exciting inductance of the transformer T1.
  • the switching circuit 10 outputs the resonance current of this resonance circuit.
  • the secondary winding of the transformer T1 is connected to a rectifying / smoothing circuit.
  • the rectifying / smoothing circuit includes switching elements Q21, Q22, Q23, Q24 and a smoothing capacitor Co. Switching elements Q21, Q22, Q23, and Q24 are subjected to switching control by a control circuit (not shown).
  • the switching circuit 10 alternately turns on and off the switching elements Q11 and Q14 and the switching elements Q12 and Q13. At this time, if the switching element Q11 and the switching element Q12 are simultaneously turned on, the series circuit of the switching elements Q11 and Q12 is erroneously fired to be in a short circuit state. Similarly, when switching element Q13 and switching element Q14 are turned on at the same time, a false firing occurs in which the series circuit of switching elements Q13 and Q14 is short-circuited.
  • the gate drive circuit 12 drives and controls the switching elements Q11, Q12, Q13, and Q14 so as to avoid the occurrence of this false firing.
  • FIG. 2 is a circuit diagram of the gate drive circuit 12.
  • the circuit configuration of the gate drive circuit 12 for each of the switching elements Q11, Q12, Q13, and Q14 is the same.
  • a circuit for driving the switching elements Q11 and Q12 is shown, and a circuit for driving the switching elements Q13 and Q14 is not shown.
  • a drive circuit for the switching element Q11 will be described, and a description of the drive circuit for the switching element Q12 will be given in parentheses, and a description thereof will be omitted.
  • the gate drive circuit 12 includes a driver 121 (122).
  • a DC power source E1 (E2) that outputs a DC voltage of 20 V is connected to the input terminals Vi1 and Vi2 of the driver 121 (122).
  • the driver 121 (122) outputs a pulse signal from the output terminal Vo.
  • the driver 121 (122) outputs the voltage 20V input from the input terminal Vi1 when outputting the H level signal.
  • the ground potential 0V input from the input terminal Vi2 is output.
  • the output terminal Vo of the driver 121 (122) is connected to the gate of the switching element Q11 (Q12) via the Zener diode Dz1 (Dz2) and the resistor R11 (R21).
  • the Zener diode Dz1 (Dz2) is connected such that its cathode is on the output terminal Vo side.
  • the Zener voltage of the Zener diode Dz1 (Dz2) is 2.0V.
  • a capacitor C21 (C31) is connected in parallel to the Zener diode Dz1 (Dz2).
  • the capacitor C21 (C31) is a capacitor for stabilizing the Zener voltage of the Zener diode Dz1 (Dz2), which will be described later.
  • the capacitor C21 (C31) is an example of the “first capacitor” according to the present invention.
  • a series circuit of a diode D11 (D21) and a resistor R14 (R24) is connected between the anode of the zener diode Dz1 (Dz2) and the source of the switching element Q11 (Q12).
  • the diode D11 (D21) is connected such that its anode is on the Zener diode Dz1 (Dz2) side.
  • a capacitor C22 (C32) is connected in parallel to the resistor R14 (R24).
  • the capacitor C22 (C32) is an example of the “second capacitor” according to the present invention.
  • a series circuit of a diode D12 (D22) and a resistor R12 (R22) is connected in parallel to the resistor R11 (R21). This series circuit is a circuit for discharging the charge charged in the gate capacitance of the switching element Q11 (Q12).
  • a resistor R13 (R23) is connected between the gate and source of the switching element Q11 (Q12).
  • FIG. 3A is a diagram for explaining the operation of each gate drive circuit 12 when the switching element Q11 is turned on
  • FIG. 3B is a diagram for explaining the operation of each gate drive circuit 12 when the switching element Q11 is turned off.
  • a drive circuit for the switching element Q11 will be described as an example.
  • the driver 121 When the switching element Q11 is turned on, the driver 121 outputs an H level signal (20V) from the output terminal Vo.
  • the Zener voltage of the Zener diode Dz1 is 2.0V.
  • the signal (20V) output from the driver 121 is stepped down to 18V by the Zener diode Dz1 and applied between the gate and source of the switching element Q11. Thereby, the switching element Q11 is turned on.
  • a current flows from the driver 121 through a path of the capacitor C21, the diode D11, and the capacitor C22, and the capacitors C21 and C22 are charged.
  • the capacitance of the capacitor C21 is set larger than the capacitance of the capacitor C22.
  • the capacitance of the capacitor C22 is determined according to the charging speed of the capacitor C21. More specifically, the capacitor C21 is set to be charged with a Zener voltage (2.0 V) by a single pulse signal from the driver 121.
  • the driver 121 When the switching element Q11 is turned off, the driver 121 outputs an L level signal (0 V) from the output terminal Vo. At this time, as shown by the arrow in FIG. 3B, the charged capacitor C21 starts discharging.
  • the Zener voltage of the Zener diode Dz1 is stabilized by the charging voltage of the capacitor C21. That is, the cathode side potential of the Zener diode Dz1 is 0V, and the anode side potential is ⁇ 2.0V.
  • This -2.0V is applied between the gate and source of the switching element Q11. That is, the gate of the switching element Q11 has a lower potential than the source of the switching element Q11, and the switching element Q11 is turned off.
  • the switching element Q11 when the switching element Q11 is turned off, a negative voltage is applied to the gate of the switching element Q11. Therefore, when the switching element Q12 (FIG. 1 or FIG. 2) is turned on, the current flowing through the body diode of the switching element Q11 is reversely recovered, and the drain voltage between the drain and gate of the switching element Q11 is determined by the drain voltage dV / dt. Even if a current flows through the capacitor and the gate potential rises somewhat, the switching element Q11 is not turned on. For this reason, the simultaneous ON state of the switching elements Q11 and Q12 can be avoided. The same applies to the switching elements Q13 and Q14.
  • the present embodiment it is possible to avoid the occurrence of false firing while keeping the source potential of the MOSFET equal to the ground potential. Furthermore, compared to a configuration in which a MOSFET is connected between a driver and a Zener diode, a Zener diode voltage can be generated at high speed without loss. In addition, since a transformer or the like is not used to generate a negative voltage applied to the gate of the switching element, the switching power supply 100 can be prevented from being enlarged.

Abstract

A switching circuit (10) provided with a switching element (Q11) comprising a SiC-MOSFET, and a gate drive circuit (12) for driving the switching element (Q11). The gate drive circuit (12) has: a driver (121); a Zener diode (Dz1) having an anode connected to the gate of the switching element (Q11) and a cathode connected to the driver (121); a capacitor (C21) connected in parallel to the Zener diode (Dz1); a diode (D11) having an anode connected to the gate of the switching element (Q11); and a capacitor (C22) connected between the cathode of the diode (D11) and the source of the switching element (Q11).

Description

スイッチング回路Switching circuit
　本発明は、スイッチング素子のゲート駆動回路を備えるスイッチング回路に関する。 The present invention relates to a switching circuit including a gate drive circuit for a switching element.
　一般に、ハーフブリッジ構造またはフルブリッジ構造等のスイッチング回路においては、誤点弧の問題がある。「誤点弧」は、上下アームの一方のアームのＭＯＳＦＥＴ（シリコンカーバイド（ＳｉＣ）を成分として含むＭＯＳＦＥＴ，ＳｉＣ－ＭＯＳＦＥＴ）をオフ状態からオン状態に遷移させた場合、オフ状態であるべき他方のアームのゲート電位が、急激な（ｄｖ／ｄｔ）によって上昇し、他方のアームのＭＯＳＦＥＴもオン状態になってしまう現象である。 Generally, there is a problem of false firing in a switching circuit such as a half bridge structure or a full bridge structure. “Error firing” means that when the MOSFET of one arm of the upper and lower arms (MOSFET including silicon carbide (SiC) as a component, SiC-MOSFET) is changed from the off state to the on state, the other arm that should be in the off state This is a phenomenon in which the gate potential of the arm rises due to rapid (dv / dt), and the MOSFET of the other arm also turns on.
　誤点弧の原因としては、例えば、上アームのＭＯＳＦＥＴがターンオンする際、下アームのＭＯＳＦＥＴのボディダイオードに流れていた電流が逆回復し、同時に下アームのＭＯＳＦＥＴのドレイン・ソース間電位が上昇する。このときに発生するｄＶ／ｄｔにより、下アームのＭＯＳＦＥＴのドレイン・ゲート間容量（帰還容量）に過渡的な電流が流れ、この電流がゲート抵抗に流れることで下アームのＭＯＳＦＥＴのゲート電位は上昇する。この電圧がしきい値電圧を大きく超えると、下アームのＭＯＳＦＥＴはターンオンして、上下アームが短絡状態となる。 As a cause of false firing, for example, when the upper arm MOSFET is turned on, the current flowing in the body diode of the lower arm MOSFET is reversely recovered, and at the same time, the drain-source potential of the lower arm MOSFET is increased. . Due to the dV / dt generated at this time, a transient current flows through the drain-gate capacitance (feedback capacitance) of the lower arm MOSFET, and this current flows through the gate resistance, thereby raising the gate potential of the lower arm MOSFET. To do. When this voltage greatly exceeds the threshold voltage, the lower arm MOSFET is turned on and the upper and lower arms are short-circuited.
　非特許文献１には、この誤点弧への対策として、ＭＯＳＦＥＴのソースとグランドラインの間にツェナーダイオートを挿入して、ＭＯＳＦＥＴのターンオフ時にマイナス電圧をＭＯＳＦＥＴのゲートに印加することで、ＭＯＳＦＥＴが、その帰還容量に流れる帰還電流によりターンオンすることを防止する方法が開示されている。 In Non-Patent Document 1, as a countermeasure against this false ignition, a Zener die auto is inserted between the source of the MOSFET and the ground line, and a negative voltage is applied to the gate of the MOSFET when the MOSFET is turned off. However, there is disclosed a method for preventing turn-on by a feedback current flowing through the feedback capacitor.
　非特許文献１において、ＭＯＳＦＥＴのゲートに印加するマイナス電圧（－３．９Ｖ）が印加されるため、ＭＯＳＦＥＴのソース電位とグランドの電位が異なってしまい、周辺回路との整合性をとることが困難となる。 In Non-Patent Document 1, since a negative voltage (-3.9 V) applied to the gate of the MOSFET is applied, the source potential of the MOSFET differs from the ground potential, making it difficult to achieve consistency with peripheral circuits. It becomes.
　そこで、本発明の目的は、ＭＯＳＦＥＴのソース電位とグランドの電位を等しく保ちつつ、誤点弧の発生を回避するスイッチング回路を提供することにある。 Therefore, an object of the present invention is to provide a switching circuit that avoids the occurrence of false firing while keeping the source potential of the MOSFET equal to the ground potential.
　本発明の一態様に係るスイッチング回路は、ＳｉＣ－ＭＯＳＦＥＴからなるスイッチング素子と、スイッチング素子を駆動するゲート駆動回路と、を備え、ゲート駆動回路は、ドライバと、アノードがスイッチング素子のゲートに接続され、カソードが、ドライバに接続されたツェナーダイオードと、ツェナーダイオードに並列接続された第１キャパシタと、アノードがスイッチング素子のゲートに接続されたダイオードと、ダイオードのカソードと、スイッチング素子のソースとの間に接続された第２キャパシタとを有することを特徴とする。 A switching circuit according to one embodiment of the present invention includes a switching element made of SiC-MOSFET and a gate driving circuit that drives the switching element. The gate driving circuit has a driver and an anode connected to the gate of the switching element. A Zener diode whose cathode is connected to the driver; a first capacitor connected in parallel to the Zener diode; a diode whose anode is connected to the gate of the switching element; a cathode of the diode; and a source of the switching element. And a second capacitor connected to the capacitor.
　この構成では、ツェナーダイオードのツェナー電圧と、第１キャパシタの充放電を利用することで、ドライバからＬレベルの信号を出力する際に、スイッチング素子のゲート・ソース間に逆バイアス電圧を印加できる。これにより、スイッチング素子のボディダイオードを流れる電流が、ドレイン・ゲート間容量に帰還電流が流れてもゲート・ソース間を逆バイアス状態に保つことができ、スイッチング素子はオンしない。これにより、ＭＯＳＦＥＴのソース電位とグランドの電位を等しく保ちつつ、誤点弧の発生を回避することができる。 In this configuration, a reverse bias voltage can be applied between the gate and source of the switching element when an L level signal is output from the driver by using the Zener voltage of the Zener diode and the charge / discharge of the first capacitor. As a result, the current flowing through the body diode of the switching element can maintain the reverse bias state between the gate and the source even if the feedback current flows through the drain-gate capacitance, and the switching element is not turned on. Thereby, it is possible to avoid the occurrence of false firing while keeping the source potential of the MOSFET equal to the ground potential.
　ダイオードのアノードと、スイッチング素子のゲートとの間に設けられた抵抗器をさらに備える構成としてもよい。これにより、ＭＯＳＦＥＴのオンオフ時に発生するサージ電圧を抑制することができる。 It is good also as a structure further provided with the resistor provided between the anode of the diode and the gate of the switching element. Thereby, the surge voltage generated when the MOSFET is turned on / off can be suppressed.
　第１キャパシタのキャパシタンスは、第２キャパシタのキャパシタンスよりも大きいことが好ましい。 The capacitance of the first capacitor is preferably larger than the capacitance of the second capacitor.
　本発明によれば、スイッチング素子のゲート・ソース間に逆バイアス電圧を印加して、誤点弧の発生を回避することができる。 According to the present invention, a reverse bias voltage can be applied between the gate and the source of the switching element to avoid the occurrence of false firing.
図１は、実施形態に係るスイッチング電源の回路図である。FIG. 1 is a circuit diagram of a switching power supply according to the embodiment. 図２は、ゲート駆動回路の回路図である。FIG. 2 is a circuit diagram of the gate driving circuit. 図３（Ａ）は、スイッチング素子をオンにする場合、図３（Ｂ）は、スイッチング素子をオフにする場合、それぞれのゲート駆動回路の動作を説明するための図である。3A is a diagram for explaining the operation of each gate drive circuit when the switching element is turned on, and FIG. 3B is a diagram for explaining the operation of each gate driving circuit when the switching element is turned off.
　図１は、本実施形態に係るスイッチング電源１００の回路図である。 FIG. 1 is a circuit diagram of a switching power supply 100 according to the present embodiment.
　スイッチング電源１００は、直流電源Ｖｉｎからの直流電圧を変圧し、出力部Ｏｕｔ１，Ｏｕｔ２に接続される負荷へ出力する。 Switching power supply 100 transforms a DC voltage from DC power supply Vin and outputs it to a load connected to output units Out1 and Out2.
　スイッチング電源１００はスイッチング回路１０を備える。スイッチング回路１０は、フルブリッジ回路１１と、ゲート駆動回路１２とを有する。 The switching power supply 100 includes a switching circuit 10. The switching circuit 10 includes a full bridge circuit 11 and a gate drive circuit 12.
　フルブリッジ回路１１は、スイッチング素子Ｑ１１，Ｑ１２の直列回路と、スイッチング素子Ｑ１３，Ｑ１４の直列回路とが並列接続されている。各スイッチング素子Ｑ１１，Ｑ１２，Ｑ１３，Ｑ１４はＳｉＣ－ＭＯＳＦＥＴであり、ゲート駆動回路１２によりスイッチング制御される。ゲート駆動回路１２は、スイッチング素子Ｑ１１，Ｑ１４と、スイッチング素子Ｑ１２，Ｑ１３とを交互にオンオフして、直流電源Ｖｉｎからの直流電圧を交流電圧に変換する。 In the full bridge circuit 11, a series circuit of switching elements Q11 and Q12 and a series circuit of switching elements Q13 and Q14 are connected in parallel. Each of the switching elements Q11, Q12, Q13, and Q14 is a SiC-MOSFET, and the switching is controlled by the gate drive circuit 12. The gate drive circuit 12 alternately turns on and off the switching elements Q11 and Q14 and the switching elements Q12 and Q13, and converts the DC voltage from the DC power supply Vin into an AC voltage.
　フルブリッジ回路１１はトランスＴ１の１次巻線に接続されている。図１では、トランスＴ１は理想トランスとして表している。フルブリッジ回路１１とトランスＴ１との間には、インダクタＬ１およびキャパシタＣ１が設けられている。インダクタＬ１およびキャパシタＣ１は、トランスＴ１の励磁インダクタンスとで共振回路を構成する。スイッチング回路１０からは、この共振回路の共振電流が出力される。 The full bridge circuit 11 is connected to the primary winding of the transformer T1. In FIG. 1, the transformer T1 is represented as an ideal transformer. An inductor L1 and a capacitor C1 are provided between the full bridge circuit 11 and the transformer T1. The inductor L1 and the capacitor C1 constitute a resonance circuit with the exciting inductance of the transformer T1. The switching circuit 10 outputs the resonance current of this resonance circuit.
　トランスＴ１の２次巻線は整流平滑回路に接続されている。この整流平滑回路は、スイッチング素子Ｑ２１，Ｑ２２，Ｑ２３，Ｑ２４と、平滑コンデンサＣｏとで構成されている。スイッチング素子Ｑ２１，Ｑ２２，Ｑ２３，Ｑ２４は、不図示の制御回路によりスイッチング制御される。 The secondary winding of the transformer T1 is connected to a rectifying / smoothing circuit. The rectifying / smoothing circuit includes switching elements Q21, Q22, Q23, Q24 and a smoothing capacitor Co. Switching elements Q21, Q22, Q23, and Q24 are subjected to switching control by a control circuit (not shown).
　前記のように、スイッチング回路１０は、スイッチング素子Ｑ１１，Ｑ１４と、スイッチング素子Ｑ１２、Ｑ１３とを交互にオンオフする。このとき、スイッチング素子Ｑ１１と、スイッチング素子Ｑ１２とが同時にオン状態となると、スイッチング素子Ｑ１１，Ｑ１２の直列回路は短絡状態となる誤点弧が発生する。同様に、スイッチング素子Ｑ１３と、スイッチング素子Ｑ１４とが同時にオン状態となると、スイッチング素子Ｑ１３，Ｑ１４の直列回路は短絡状態となる誤点弧が発生する。本実施形態に係るゲート駆動回路１２は、この誤点弧の発生を回避するように、スイッチング素子Ｑ１１，Ｑ１２，Ｑ１３，Ｑ１４を駆動制御する。 As described above, the switching circuit 10 alternately turns on and off the switching elements Q11 and Q14 and the switching elements Q12 and Q13. At this time, if the switching element Q11 and the switching element Q12 are simultaneously turned on, the series circuit of the switching elements Q11 and Q12 is erroneously fired to be in a short circuit state. Similarly, when switching element Q13 and switching element Q14 are turned on at the same time, a false firing occurs in which the series circuit of switching elements Q13 and Q14 is short-circuited. The gate drive circuit 12 according to the present embodiment drives and controls the switching elements Q11, Q12, Q13, and Q14 so as to avoid the occurrence of this false firing.
　図２は、ゲート駆動回路１２の回路図である。 FIG. 2 is a circuit diagram of the gate drive circuit 12.
　スイッチング素子Ｑ１１，Ｑ１２，Ｑ１３，Ｑ１４それぞれに対するゲート駆動回路１２の回路構成は同じである。図２では、スイッチング素子Ｑ１１，Ｑ１２それぞれを駆動する回路を示し、スイッチング素子Ｑ１３，Ｑ１４を駆動する回路の図示は省略する。また、以下では、スイッチング素子Ｑ１１に対する駆動回路について説明し、スイッチング素子Ｑ１２に対する駆動回路の説明については、符号を括弧書きで記し、その説明は省略する。 The circuit configuration of the gate drive circuit 12 for each of the switching elements Q11, Q12, Q13, and Q14 is the same. In FIG. 2, a circuit for driving the switching elements Q11 and Q12 is shown, and a circuit for driving the switching elements Q13 and Q14 is not shown. In the following, a drive circuit for the switching element Q11 will be described, and a description of the drive circuit for the switching element Q12 will be given in parentheses, and a description thereof will be omitted.
　ゲート駆動回路１２はドライバ１２１（１２２）を備える。ドライバ１２１（１２２）の入力端Ｖｉ１，Ｖｉ２には、２０Ｖの直流電圧を出力する直流電源Ｅ１（Ｅ２）が接続されている。ドライバ１２１（１２２）は、出力端Ｖｏからパルス信号を出力する。ドライバ１２１（１２２）は、Ｈレベルの信号を出力する場合には、入力端Ｖｉ１から入力される電圧２０Ｖを出力する。また、Ｌレベルの信号を出力する場合には、入力端Ｖｉ２から入力されるグランド電位０Ｖを出力する。 The gate drive circuit 12 includes a driver 121 (122). A DC power source E1 (E2) that outputs a DC voltage of 20 V is connected to the input terminals Vi1 and Vi2 of the driver 121 (122). The driver 121 (122) outputs a pulse signal from the output terminal Vo. The driver 121 (122) outputs the voltage 20V input from the input terminal Vi1 when outputting the H level signal. When outputting an L level signal, the ground potential 0V input from the input terminal Vi2 is output.
　ドライバ１２１（１２２）の出力端Ｖｏは、ツェナーダイオードＤｚ１（Ｄｚ２）と抵抗Ｒ１１（Ｒ２１）とを介して、スイッチング素子Ｑ１１（Ｑ１２）のゲートに接続されている。ツェナーダイオードＤｚ１（Ｄｚ２）は、そのカソードが出力端Ｖｏ側にして接続されている。この例では、ツェナーダイオードＤｚ１（Ｄｚ２）のツェナー電圧は２．０Ｖである。 The output terminal Vo of the driver 121 (122) is connected to the gate of the switching element Q11 (Q12) via the Zener diode Dz1 (Dz2) and the resistor R11 (R21). The Zener diode Dz1 (Dz2) is connected such that its cathode is on the output terminal Vo side. In this example, the Zener voltage of the Zener diode Dz1 (Dz2) is 2.0V.
　ツェナーダイオードＤｚ１（Ｄｚ２）にはキャパシタＣ２１（Ｃ３１）が並列接続されている。キャパシタＣ２１（Ｃ３１）は、後述するが、ツェナーダイオードＤｚ１（Ｄｚ２）のツェナー電圧を安定させるためのキャパシタである。キャパシタＣ２１（Ｃ３１）は、本発明に係る「第１キャパシタ」の一例である。 A capacitor C21 (C31) is connected in parallel to the Zener diode Dz1 (Dz2). The capacitor C21 (C31) is a capacitor for stabilizing the Zener voltage of the Zener diode Dz1 (Dz2), which will be described later. The capacitor C21 (C31) is an example of the “first capacitor” according to the present invention.
　ツェナーダイオードＤｚ１（Ｄｚ２）のアノードと、スイッチング素子Ｑ１１（Ｑ１２）のソースとの間には、ダイオードＤ１１（Ｄ２１）と抵抗Ｒ１４（Ｒ２４）との直列回路が接続されている。ダイオードＤ１１（Ｄ２１）は、そのアノードがツェナーダイオードＤｚ１（Ｄｚ２）側となるように接続されている。抵抗Ｒ１４（Ｒ２４）にはキャパシタＣ２２（Ｃ３２）が並列に接続されている。キャパシタＣ２２（Ｃ３２）は、本発明に係る「第２キャパシタ」の一例である。 A series circuit of a diode D11 (D21) and a resistor R14 (R24) is connected between the anode of the zener diode Dz1 (Dz2) and the source of the switching element Q11 (Q12). The diode D11 (D21) is connected such that its anode is on the Zener diode Dz1 (Dz2) side. A capacitor C22 (C32) is connected in parallel to the resistor R14 (R24). The capacitor C22 (C32) is an example of the “second capacitor” according to the present invention.
　抵抗Ｒ１１（Ｒ２１）には、ダイオードＤ１２（Ｄ２２）および抵抗Ｒ１２（Ｒ２２）の直列回路が、並列に接続されている。この直列回路は、スイッチング素子Ｑ１１（Ｑ１２）のゲート容量に充電された電荷を放電するための回路である。スイッチング素子Ｑ１１（Ｑ１２）のゲート・ソース間には、抵抗Ｒ１３（Ｒ２３）が接続されている。 A series circuit of a diode D12 (D22) and a resistor R12 (R22) is connected in parallel to the resistor R11 (R21). This series circuit is a circuit for discharging the charge charged in the gate capacitance of the switching element Q11 (Q12). A resistor R13 (R23) is connected between the gate and source of the switching element Q11 (Q12).
　図３（Ａ）は、スイッチング素子Ｑ１１をオンにする場合、図３（Ｂ）は、スイッチング素子Ｑ１１をオフにする場合、それぞれのゲート駆動回路１２の動作を説明するための図である。以下、スイッチング素子Ｑ１１に対する駆動回路を例に挙げて説明する。 3A is a diagram for explaining the operation of each gate drive circuit 12 when the switching element Q11 is turned on, and FIG. 3B is a diagram for explaining the operation of each gate drive circuit 12 when the switching element Q11 is turned off. Hereinafter, a drive circuit for the switching element Q11 will be described as an example.
　スイッチング素子Ｑ１１をオンにする場合、ドライバ１２１は、Ｈレベルの信号（２０Ｖ）を出力端Ｖｏから出力する。ツェナーダイオードＤｚ１のツェナー電圧は２．０Ｖである。このため、ドライバ１２１から出力された信号（２０Ｖ）は、ツェナーダイオードＤｚ１で１８Ｖに降圧され、それがスイッチング素子Ｑ１１のゲート・ソース間に印加される。これにより、スイッチング素子Ｑ１１がオンする。 When the switching element Q11 is turned on, the driver 121 outputs an H level signal (20V) from the output terminal Vo. The Zener voltage of the Zener diode Dz1 is 2.0V. For this reason, the signal (20V) output from the driver 121 is stepped down to 18V by the Zener diode Dz1 and applied between the gate and source of the switching element Q11. Thereby, the switching element Q11 is turned on.
　このとき、図３（Ａ）に示すように、ドライバ１２１から、キャパシタＣ２１、ダイオードＤ１１、キャパシタＣ２２の経路で電流が流れ、キャパシタＣ２１、Ｃ２２が充電される。キャパシタＣ２１のキャパシタンスは、キャパシタＣ２２のキャパシタンスよりも大きく設定される。キャパシタＣ２２のキャパシタンスは、キャパシタＣ２１の充電速度に応じて決定される。より詳しくは、ドライバ１２１からの一発のパルス信号で、キャパシタＣ２１にツェナー電圧（２．０Ｖ）が充電されるように設定されている。 At this time, as shown in FIG. 3A, a current flows from the driver 121 through a path of the capacitor C21, the diode D11, and the capacitor C22, and the capacitors C21 and C22 are charged. The capacitance of the capacitor C21 is set larger than the capacitance of the capacitor C22. The capacitance of the capacitor C22 is determined according to the charging speed of the capacitor C21. More specifically, the capacitor C21 is set to be charged with a Zener voltage (2.0 V) by a single pulse signal from the driver 121.
　スイッチング素子Ｑ１１をオフにする場合、ドライバ１２１は、Ｌレベルの信号（０Ｖ）を出力端Ｖｏから出力する。このとき、図３（Ｂ）の矢印に示すように、充電されたキャパシタＣ２１が放電を開始する。キャパシタＣ２１の充電電圧により、ツェナーダイオードＤｚ１のツェナー電圧は安定する。つまり、ツェナーダイオードＤｚ１のカソード側の電位は０Ｖ、アノード側の電位は－２．０Ｖとなる。この－２．０Ｖが、スイッチング素子Ｑ１１のゲート・ソース間に印加される。つまり、スイッチング素子Ｑ１１のゲートには、スイッチング素子Ｑ１１のソースよりも電位が低く、スイッチング素子Ｑ１１はオフする。 When the switching element Q11 is turned off, the driver 121 outputs an L level signal (0 V) from the output terminal Vo. At this time, as shown by the arrow in FIG. 3B, the charged capacitor C21 starts discharging. The Zener voltage of the Zener diode Dz1 is stabilized by the charging voltage of the capacitor C21. That is, the cathode side potential of the Zener diode Dz1 is 0V, and the anode side potential is −2.0V. This -2.0V is applied between the gate and source of the switching element Q11. That is, the gate of the switching element Q11 has a lower potential than the source of the switching element Q11, and the switching element Q11 is turned off.
　このとき、ダイオードＤ１１により、充電されたキャパシタＣ２２から、スイッチング素子Ｑ１１のゲート側に電流が流れることはない。このため、スイッチング素子Ｑ１１がオンすることはない。また、スイッチング電源１００がオフ状態のときには、キャパシタＣ２２の充電電圧は、抵抗Ｒ１４により放電される。 At this time, no current flows from the charged capacitor C22 to the gate side of the switching element Q11 by the diode D11. For this reason, the switching element Q11 is not turned on. Further, when the switching power supply 100 is in the off state, the charging voltage of the capacitor C22 is discharged by the resistor R14.
　このように、スイッチング素子Ｑ１１をオフする場合には、スイッチング素子Ｑ１１のゲートにはマイナス電圧が印加される。このため、スイッチング素子Ｑ１２（図１または図２）がターンオンするときに、スイッチング素子Ｑ１１のボディダイオードに流れていた電流が逆回復し、ドレイン電圧のｄＶ/ｄｔによってスイッチング素子Ｑ１１のドレイン・ゲート間容量に電流が流れ、ゲート電位が多少上昇しても、スイッチング素子Ｑ１１はオンしない。このため、スイッチング素子Ｑ１１，Ｑ１２の同時オン状態を回避できる。スイッチング素子Ｑ１３，Ｑ１４についても同様である。 Thus, when the switching element Q11 is turned off, a negative voltage is applied to the gate of the switching element Q11. Therefore, when the switching element Q12 (FIG. 1 or FIG. 2) is turned on, the current flowing through the body diode of the switching element Q11 is reversely recovered, and the drain voltage between the drain and gate of the switching element Q11 is determined by the drain voltage dV / dt. Even if a current flows through the capacitor and the gate potential rises somewhat, the switching element Q11 is not turned on. For this reason, the simultaneous ON state of the switching elements Q11 and Q12 can be avoided. The same applies to the switching elements Q13 and Q14.
　以上説明したように、本実施形態では、ＭＯＳＦＥＴのソース電位とグランドの電位を等しく保ちつつ、誤点弧の発生を回避することができる。さらに、ドライバとツェナーダイオードの間にＭＯＳＦＥＴを接続する構成と比べて、損失なく高速にツェナーダイオード電圧を生成することができる。また、スイッチング素子のゲートに印加するマイナス電圧を生成するために、トランス等を用いることがないため、スイッチング電源１００の大型化を抑制できる。 As described above, in the present embodiment, it is possible to avoid the occurrence of false firing while keeping the source potential of the MOSFET equal to the ground potential. Furthermore, compared to a configuration in which a MOSFET is connected between a driver and a Zener diode, a Zener diode voltage can be generated at high speed without loss. In addition, since a transformer or the like is not used to generate a negative voltage applied to the gate of the switching element, the switching power supply 100 can be prevented from being enlarged.
Ｃ１，Ｃ２１，Ｃ２２…キャパシタ
Ｃｏ…平滑コンデンサ
Ｄ１１，Ｄ１２…ダイオード
Ｄｚ１…ツェナーダイオード
Ｅ１…直流電源
Ｌ１…インダクタ
Ｏｕｔ１，Ｏｕｔ２…出力部
Ｑ１１，Ｑ１２，Ｑ１３，Ｑ１４…スイッチング素子
Ｑ２１，Ｑ２２，Ｑ２３，Ｑ２４…スイッチング素子
Ｒ１１，Ｒ１２，Ｒ１３，Ｒ１４…抵抗
Ｔ１…トランス
Ｖｉ１，Ｖｉ２…入力端
Ｖｉｎ…直流電源
Ｖｏ…出力端
１０…スイッチング回路
１１…フルブリッジ回路
１２…ゲート駆動回路
１００…スイッチング電源
１２１…ドライバ C1, C21, C22 ... Capacitor Co ... Smoothing capacitors D11, D12 ... Diode Dz1 ... Zener diode E1 ... DC power supply L1 ... Inductor Out1, Out2 ... Outputs Q11, Q12, Q13, Q14 ... Switching elements Q21, Q22, Q23, Q24 ... switching elements R11, R12, R13, R14 ... resistor T1 ... transformers Vi1 and Vi2 ... input terminal Vin ... DC power supply Vo ... output terminal 10 ... switching circuit 11 ... full bridge circuit 12 ... gate drive circuit 100 ... switching power supply 121 ... driver

Claims (3)

  1. 　ＳｉＣ－ＭＯＳＦＥＴからなるスイッチング素子と、
    　前記スイッチング素子を駆動するゲート駆動回路と、
    　を備え、
    　前記ゲート駆動回路は、
    　ドライバと、
    　アノードが前記スイッチング素子のゲートに接続され、カソードが前記ドライバに接続されたツェナーダイオードと、
    　前記ツェナーダイオードに並列接続された第１キャパシタと、
    　アノードが前記スイッチング素子のゲートに接続されたダイオードと、
    　前記ダイオードのカソードと、前記スイッチング素子のソースとの間に接続された第２キャパシタと、
    　を有する、スイッチング回路。     A switching element made of SiC-MOSFET,
    A gate driving circuit for driving the switching element;
    With
    The gate driving circuit includes:
    A driver,
    A Zener diode having an anode connected to the gate of the switching element and a cathode connected to the driver;
    A first capacitor connected in parallel to the Zener diode;
    A diode having an anode connected to the gate of the switching element;
    A second capacitor connected between the cathode of the diode and the source of the switching element;
    A switching circuit.
  2. 　前記ダイオードの前記アノードと前記スイッチング素子の前記ゲートとの間に設けられた抵抗器をさらに備える、
    　請求項１に記載のスイッチング回路。     A resistor provided between the anode of the diode and the gate of the switching element;
    The switching circuit according to claim 1.
  3. 　前記第１キャパシタのキャパシタンスは、前記第２キャパシタのキャパシタンスよりも大きい、
    　請求項１または２に記載のスイッチング回路。     The capacitance of the first capacitor is greater than the capacitance of the second capacitor;
    The switching circuit according to claim 1 or 2.
PCT/JP2017/031100 2016-09-08 2017-08-30 Switching circuit WO2018047689A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-175159 2016-09-08
JP2016175159 2016-09-08

Publications (1)

Publication Number Publication Date
WO2018047689A1 true WO2018047689A1 (en) 2018-03-15

Family

ID=61562485

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/031100 WO2018047689A1 (en) 2016-09-08 2017-08-30 Switching circuit

Country Status (1)

Country Link
WO (1) WO2018047689A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020005179A (en) * 2018-06-29 2020-01-09 富士電機株式会社 Semiconductor device
EP3751736A1 (en) * 2019-06-12 2020-12-16 Nabtesco Corporation Switching device, driving circuit device for actuators, actuator system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013026924A (en) * 2011-07-22 2013-02-04 Sanken Electric Co Ltd Gate drive circuit
JP2014171276A (en) * 2013-03-01 2014-09-18 Tabuchi Electric Co Ltd Switching power circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013026924A (en) * 2011-07-22 2013-02-04 Sanken Electric Co Ltd Gate drive circuit
JP2014171276A (en) * 2013-03-01 2014-09-18 Tabuchi Electric Co Ltd Switching power circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020005179A (en) * 2018-06-29 2020-01-09 富士電機株式会社 Semiconductor device
EP3751736A1 (en) * 2019-06-12 2020-12-16 Nabtesco Corporation Switching device, driving circuit device for actuators, actuator system
JP2020202517A (en) * 2019-06-12 2020-12-17 ナブテスコ株式会社 Switching device, actuator drive circuit device, and actuator system
US11277126B2 (en) 2019-06-12 2022-03-15 Nabtesco Corporation Switching device, driving circuit device for actuators, actuator system

Similar Documents

Publication Publication Date Title
TWI434165B (en) Power converting circuit and feedback control circuit
US20160126718A1 (en) Semiconductor device
CN107302351B (en) Driving device and inductive load driving device
JP6639103B2 (en) Switching unit and power supply circuit
JP6477442B2 (en) Switching circuit and power conversion circuit
JP5991939B2 (en) Semiconductor device driving circuit and semiconductor device driving apparatus
TW201630322A (en) Dc-dc converter
EP3038223A1 (en) Load driving circuit
JP7309987B2 (en) Driver circuits for output transistors, semiconductor devices, automobiles
WO2018047689A1 (en) Switching circuit
US20190260373A1 (en) Driving circuit and a desaturation circuit of a power circuit
US20170104412A1 (en) Control circuit of power converter and related method
US9900009B2 (en) Level shift circuit
JP2020202669A (en) Integrated circuit and power source circuit
US10958065B2 (en) Switching circuit
JP6942269B2 (en) Power converter
WO2020021757A1 (en) Switch circuit and power conversion device
JP6156073B2 (en) Semiconductor switching element protection circuit and power conversion device
JP5145142B2 (en) Half bridge circuit
JP5471862B2 (en) Level shift circuit and switching power supply device
CN111884489B (en) Power circuit and drive circuit
TW201806322A (en) Level shift circuit
JP2006187101A (en) Method of driving voltage driver element
JP6848345B2 (en) Switching power supply
JP7338139B2 (en) Switching control circuit, power supply circuit

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17848629

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17848629

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP