WO2018032713A1 - 包含沟道高级寄生元件的场效应晶体管小信号等效电路模型 - Google Patents

包含沟道高级寄生元件的场效应晶体管小信号等效电路模型 Download PDF

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WO2018032713A1
WO2018032713A1 PCT/CN2017/000528 CN2017000528W WO2018032713A1 WO 2018032713 A1 WO2018032713 A1 WO 2018032713A1 CN 2017000528 W CN2017000528 W CN 2017000528W WO 2018032713 A1 WO2018032713 A1 WO 2018032713A1
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intrinsic
channel
parameter
resistance
series
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PCT/CN2017/000528
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English (en)
French (fr)
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黄风义
张有明
姜楠
唐旭升
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南京展芯通讯科技有限公司
爱斯泰克（上海）高频通讯技术有限公司
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Publication of WO2018032713A1 publication Critical patent/WO2018032713A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

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  • the invention relates to a device model of a transistor, in particular to a small signal equivalent circuit model and a parameter extraction method of a field effect transistor.
  • Transistors are one of the most important components in microelectronic devices and integrated circuit chips. They are widely used in various fields. Transistor models are an indispensable tool in the design of electronic devices and integrated circuits. The digital model of transistors in the world is relatively mature and can provide high-precision model simulation. However, the current RF model of the transistor is not perfect, and it has become a major difficulty in the design and implementation of the RF circuit chip.
  • the transistor model mainly includes two types, a physical model and an equivalent circuit model. Among them, the design of the circuit chip is mainly based on the frequency-independent equivalent circuit model. High-precision equivalent circuit model is the core factor to improve circuit performance, shorten development cycle, improve design success rate and yield, and reduce development cost.
  • the present invention is primarily directed to a small signal equivalent circuit model for a field effect transistor.
  • the current field effect transistor model commonly used in the world is based on papers (Gilles Dambrine, Alain Cappy, Frkdderic Heliodore, and Edouard Playez, "A New Method for Determining the FET Small-Signal Equivalent Circuit", Microwave Theory and Techniques, IEEE Transactions on , 36 (7): 1151-1159, 1988, reference 1) proposed model structure, combined with some additional components for correction.
  • a common feature of all these traditional models is that only one level effect is considered in the intrinsic part, where the channel portion contains only one channel resistance and one channel capacitance, but does not consider the advanced parasitic effects caused by the channel current. .
  • the present invention proposes a novel model structure for this defect of the conventional model, thereby including a channel advanced parasitic element in the intrinsic portion, thereby realizing high-precision simulation of the field effect transistor.
  • the traditional small-signal equivalent circuit model of a field effect transistor is based on the 14-element model of Reference 1.
  • the invention patent proposes a semi-physical modeling method for small-signal equivalent circuit model of high mobility field effect transistor (HEMT).
  • the circuit model includes a parasitic portion including a gate parasitic inductance, a gate parasitic resistance, a drain parasitic inductance, a drain parasitic resistance, a source parasitic inductance, a source parasitic resistance, and an intrinsic portion.
  • Another transistor small-signal equivalent circuit model contains 22 components, please refer to the paper (A.Jarndal A, G.. Kompa, "A new small-signal Approach applied to GaN devices”, Microwave Theory and Techniques, IEEE Transactions on, 53(11): 3440-3448, 2005, reference 3).
  • the paper is based on the idea of a distributed model compared to references
  • the equivalent circuit model additionally considers the parasitic capacitance between the gate, the drain and the source, mainly considering the parasitic overlap capacitance between the gate and the source, the parasitic overlap capacitance between the gate and the drain, and the source and drain. Inter-parasitic overlap capacitance.
  • the advanced parasitic effects of the intrinsic channel are still not considered.
  • the channel's advanced parasitic effects in the intrinsic part reflect the advanced parasitic effects generated by the internal current of the transistor, and pass through the channel advanced parasitic elements including any one or combination of the intrinsic resistance, the intrinsic capacitance, and the intrinsic inductance. The form is reflected.
  • the high-precision fitting between the equivalent circuit model and the test results cannot be achieved only by the existing field effect transistor equivalent circuit model technique considering the first-order effect.
  • the advanced parasitic effects that have been considered in the small-signal equivalent circuit model of the existing field effect transistor are only reflected in the parasitic part, but the current flow inside the transistor also produces high-level parasitic effects, and the advanced parasitic effect of the channel is not small by the existing transistor.
  • the signal equivalent circuit model is considered. More importantly, as the transistor feature size and channel length decrease, the effect of the channel advanced parasitic components on the transistor performance is more significant, and the value of the channel advanced parasitic components varies with the bias, which will It cannot be realized by adjusting the component parameters in the existing transistor small-signal equivalent circuit model. Therefore, the existing transistor small-signal equivalent circuit model cannot achieve high-precision simulation of the transistor.
  • the existing small-signal equivalent circuit model of the field effect transistor does not consider the channel advanced parasitic components existing in the intrinsic part, so the existing transistor small-signal equivalent circuit model cannot achieve the same test result. High precision fitting.
  • a small-signal equivalent circuit model of a field effect transistor comprising a channel advanced parasitic element, characterized in that the intrinsic part of the field effect transistor small signal equivalent circuit model comprises a channel advanced parasitic element,
  • the channel advanced parasitic element includes any one or combination of three elements of an intrinsic resistance, an intrinsic capacitance, and an intrinsic inductance.
  • FIG. 1 A schematic diagram of a small-signal equivalent circuit model of a field effect transistor including a channel advanced parasitic element proposed by the present invention is shown in FIG.
  • the field effect transistor small signal equivalent circuit model includes a parasitic portion (100) and an intrinsic portion (200), wherein the parasitic portion includes a gate parasitic unit (110), a drain parasitic unit (120), and a source parasitic unit (130)
  • the intrinsic portion includes a gate-source intrinsic unit (210), a gate-drain intrinsic unit (220), and an inter-source-drain intrinsic unit (230).
  • the channel advanced parasitic element includes an intrinsic resistance that is included in the source-drain between the intrinsic unit (230).
  • the gate parasitic unit (110) is located between the gate outer node (G) and the gate inner node (G'), and is connected to the gate outer node (G) and the gate inner node (G');
  • the drain parasitic unit (120) is located between the drain outer node (D) and the drain inner node (D'), and is connected to the drain outer node (D) and the drain inner node (D');
  • the source parasitic unit (130) is located between the source outer node (S) and the source inner node (S'), and is connected to the source outer node (S) and the source inner node (S'). And connected between the gate parasitic cell and the drain parasitic cell, and connected to the gate parasitic cell and the drain parasitic cell.
  • the gate-source eigencell (210) is located between the gate inner node (G') and the source inner node (S'), and is connected to the gate inner node (G') and the source inner node (S). ') phase connection;
  • the inter-gate inter-drain eigencell (220) is located between the gate inner node (G'), the drain inner node (D'), and the gate inner node (G'), the drain The in-pole node (D') is connected;
  • the source-drain eigencell (230) is located between the drain inner node (D') and the source inner node (S'), and is connected to the drain inner node ( D'), the source node (S') is connected.
  • a novel small field equivalent circuit model of the field effect transistor proposed by the present invention is applicable to all field effect transistors, including but not limited to metal-oxide-semiconductor crystal (MOSFET), metal-semiconductor transistor (MESFET).
  • MOSFET metal-oxide-semiconductor crystal
  • MESFET metal-semiconductor transistor
  • HEMT High electron mobility transistor
  • PHEMT high electron mobility transistor
  • field effect transistor consists of silicon (Si), germanium silicon (SiGe), gallium arsenide (GaAs), indium phosphide (InP), carbonization Preparation of silicon (SiC) or gallium nitride (GaN) materials.
  • FIG. 1 is a schematic diagram of a small-signal equivalent circuit model of a field effect transistor including a channel advanced parasitic element (Exemplary Embodiment 1).
  • FIG. 2 is a schematic diagram of a small-signal equivalent circuit model of a field effect transistor including a channel advanced parasitic element (Exemplary Embodiment 2).
  • FIG. 3 is a schematic diagram of a small-signal equivalent circuit model of a field effect transistor including a channel advanced parasitic element (Exemplary Embodiment 3).
  • Figure 4 is a comparison of the measured values of the field effect transistor S parameter measurements with a conventional transistor small signal equivalent circuit model that does not include channel advanced parasitic elements.
  • 100-field effect transistor small signal equivalent circuit model parasitic part including 110, 120, 130
  • the field effect transistor small signal equivalent circuit model includes a parasitic portion (100) and an intrinsic portion (200), wherein the parasitic portion includes a gate parasitic unit (110), a drain parasitic unit (120), A source parasitic unit (130), the intrinsic portion includes a gate-source intrinsic unit (210), a gate-drain intrinsic unit (220), and an inter-source-drain intrinsic unit (230).
  • the channel advanced parasitic element includes an intrinsic resistance that is included in the source-drain between the intrinsic unit (230).
  • the gate parasitic unit (110) is located between the gate outer node (G) and the gate inner node (G'), and is connected to the gate outer node (G) and the gate inner node (G');
  • the drain parasitic unit (120) is located between the drain outer node (D) and the drain inner node (D'), and is connected to the drain outer node (D) and the drain inner node (D');
  • the source parasitic unit (130) is located between the source outer node (S) and the source inner node (S'), and is connected to the source outer node (S) and the source inner node (S'). And located between the gate parasitic unit and the drain parasitic unit, and connected to the gate parasitic unit and the drain parasitic unit.
  • the gate-source eigencell (210) is located between the gate inner node (G') and the source inner node (S'), and is connected to the gate inner node (G') and the source inner node (S). ') phase connection;
  • the inter-gate inter-drain eigencell (220) is located between the gate inner node (G'), the drain inner node (D'), and the gate inner node (G'), the drain The in-pole node (D') is connected;
  • the source-drain eigencell (230) is located between the drain inner node (D') and the source inner node (S'), and is connected to the drain inner node ( D'), the source node (S') is connected.
  • the gate parasitic portion (110) includes a gate parasitic inductance (111), a gate parasitic resistance (112), and a gate-to-ground parasitic capacitance (113).
  • the drain parasitic portion (120) includes a drain parasitic inductance (121), a drain parasitic resistance (122), and a drain-to-ground parasitic capacitance (123).
  • the source parasitic portion (130) includes a source parasitic inductance (131) and a source parasitic resistance (132).
  • the gate-source intrinsic unit (210) includes a gate-source capacitor (211), a gate-source resistor (212), and a gate-source leakage resistor (213).
  • the inter-gate drain eigencell (220) includes a gate-drain capacitance (221), a gate-drain resistance (222), and a gate leakage leakage resistance (223).
  • the source-drain eigencell (230) includes a voltage control current source (231), a channel resistance (232), a channel capacitance (233), and an intrinsic resistance (234).
  • the gate parasitic inductance (111) and the gate parasitic resistance (112) are connected in series between the gate outer node (G) and the gate inner node (G'), and the gate-to-ground parasitic capacitance (113) is external to the gate
  • the nodes (G) are connected, and the other end is connected to the source outer node (S).
  • the drain parasitic inductance (121) and the drain parasitic resistance (122) are connected in series between the drain outer node (D) and the drain inner node (D'), and the drain-to-ground parasitic capacitance (123) is external to one end and the drain.
  • the node (D) is connected and the other end is connected to the source external node (S).
  • the source parasitic inductance (131) and the source parasitic resistance (132) are connected in series between the source outer node (S) and the source inner node (S').
  • the gate source capacitor (211) and the gate source resistor (212) are connected in series between the gate inner node (G') and the source inner node (S'), and one end of the gate source leakage resistor (213) and the gate inner node (G) ') is connected, and the other end is connected to the source node (S').
  • the gate-drain capacitance (222) and the gate-drain resistance (221) are connected in series between the gate inner node (G') and the drain inner node (D'), and one end of the gate leakage leakage resistor (223) and the gate inner node (G) ') is connected, and the other end is connected to the node (D') in the drain.
  • An integral end of the channel capacitor (233) in parallel with the channel resistance (232) is connected to the drain internal node (D'), and the other end is connected to the intrinsic resistor (234), and the intrinsic resistance (234)
  • the other end is connected to the source internal node (S'), and one end of the voltage control current source (231) is connected to the drain inner node (D'), and the other end is connected to the source inner node (S').
  • the field effect transistor small signal equivalent circuit model includes a parasitic portion (100) and an intrinsic portion (200), wherein the parasitic portion includes a gate parasitic unit (110), a drain parasitic unit (120), A source parasitic unit (130), the intrinsic portion includes a gate-source intrinsic unit (210), a gate-drain intrinsic unit (220), and an inter-source-drain intrinsic unit (230).
  • the intrinsic advanced parasitic element includes an intrinsic resistance (234), an intrinsic capacitance (235), and an intrinsic inductance (236), the channel advanced parasitic element being included in the source-drain between the intrinsic unit (230).
  • the gate parasitic unit (110) is located between the gate outer node (G) and the gate inner node (G'), and is connected to the gate outer node (G) and the gate inner node (G');
  • the drain parasitic unit (120) is located between the drain outer node (D) and the drain inner node (D'), and is connected to the drain outer node (D) and the drain inner node (D');
  • the source parasitic unit (130) is located between the source outer node (S) and the source inner node (S'), and is connected to the source outer node (S) and the source inner node (S'). And located between the gate parasitic unit and the drain parasitic unit, and connected to the gate parasitic unit and the drain parasitic unit.
  • the gate-source eigencell (210) is located between the gate inner node (G') and the source inner node (S'), and is connected to the gate inner node (G') and the source inner node (S). ') phase connection;
  • the inter-gate inter-drain eigencell (220) is located between the gate inner node (G'), the drain inner node (D'), and the gate inner node (G'), the drain The in-pole node (D') is connected;
  • the source-drain eigencell (230) is located between the drain inner node (D') and the source inner node (S'), and is connected to the drain inner node ( D'), the source node (S') is connected.
  • Gate parasitic part (110) including gate parasitic inductance (111), gate parasitic resistance (112), gate-to-ground parasitic capacitance (113).
  • the drain parasitic portion (120) includes a drain parasitic inductance (121), a drain parasitic resistance (122), and a drain-to-ground parasitic capacitance (123).
  • the source parasitic portion (130) includes a source parasitic inductance (131) and a source parasitic resistance (132).
  • the gate-source intrinsic unit (210) includes a gate-source capacitor (211), a gate-source resistor (212), and a gate-source leakage resistor (213).
  • the inter-gate drain eigencell (220) includes a gate-drain capacitance (221), a gate-drain resistance (222), and a gate leakage leakage resistance (223).
  • Source-drain eigencell (230) including voltage control current source (231), channel resistance (232), channel capacitance (233), intrinsic resistance (234), intrinsic capacitance (235), intrinsic Inductance (236).
  • the gate parasitic inductance (111) and the gate parasitic resistance (112) are connected in series between the gate outer node (G) and the gate inner node (G'), and the gate-to-ground parasitic capacitance (113) is external to the gate Node (G) is connected, the other end is connected to the source (S) Connected.
  • the drain parasitic inductance (121) and the drain parasitic resistance (122) are connected in series between the drain outer node (D) and the drain inner node (D'), and the drain-to-ground parasitic capacitance (123) is external to one end and the drain.
  • the nodes (D) are connected and the other end is connected to the source outer node (S).
  • the source parasitic inductance (131) and the source parasitic resistance (132) are connected in series between the source outer node (S) and the source inner node (S').
  • the gate source capacitor (211) and the gate source resistor (212) are connected in series between the gate inner node (G') and the source inner node (S'), and one end of the gate source leakage resistor (213) and the gate inner node (G) ') is connected, and the other end is connected to the source node (S').
  • the gate-drain capacitance (222) and the gate-drain resistance (221) are connected in series between the gate inner node (G') and the drain inner node (D'), and one end of the gate leakage leakage resistor (223) and the gate inner node (G) ') is connected, and the other end is connected to the node (D') in the drain.
  • the channel capacitor (233) is connected in parallel with the channel resistance (232), the intrinsic resistor (234) is connected in parallel with the intrinsic capacitor (235), and the channel capacitor (233) is connected in parallel with the channel resistor (232).
  • the inner node (D') is connected, the other end is connected to one end of the intrinsic resistor (234) and the intrinsic capacitor (235) in parallel, and the other end of the intrinsic resistor (234) and the intrinsic capacitor (235) are connected in parallel.
  • the other end of the intrinsic inductor (236) is connected to the source node (S'), and one end of the voltage control current source (231) is connected to the drain internal node (D'). One end is connected to the source node (S').
  • the field effect transistor small signal equivalent circuit model includes a parasitic portion (100) and an intrinsic portion (200), wherein the parasitic portion includes a gate parasitic unit (110), a drain parasitic unit (120), A source parasitic unit (130), the intrinsic portion includes a gate-source intrinsic unit (210), a gate-drain intrinsic unit (220), and an inter-source-drain intrinsic unit (230).
  • the channel advanced parasitic element includes an intrinsic resistor (234), an intrinsic capacitor (235), an intrinsic inductor (236), and an intrinsic advanced inductor (237), and the channel advanced parasitic element is included between the source and the drain.
  • the eigen unit (230) In the eigen unit (230).
  • the gate parasitic unit (110) is located between the gate outer node (G) and the gate inner node (G'), and is connected to the gate outer node (G) and the gate inner node (G');
  • the drain parasitic unit (120) is located between the drain outer node (D) and the drain inner node (D'), and is connected to the drain outer node (D) and the drain inner node (D');
  • the source parasitic unit (130) is located between the source outer node (S) and the source inner node (S'), and is connected to the source outer node (S) and the source inner node (S'). And located between the gate parasitic unit and the drain parasitic unit, and connected to the gate parasitic unit and the drain parasitic unit.
  • the gate-source eigencell (210) is located between the gate inner node (G') and the source inner node (S'), and is connected to the gate inner node (G') and the source inner node (S). ') phase connection;
  • the inter-gate inter-drain eigencell (220) is located between the gate inner node (G'), the drain inner node (D'), and the gate inner node (G'), the drain The in-pole node (D') is connected;
  • the source-drain eigencell (230) is located between the drain inner node (D') and the source inner node (S'), and is connected to the drain inner node ( D'), the source node (S') is connected.
  • the gate parasitic portion (110) includes a gate parasitic inductance (111), a gate parasitic resistance (112), and a gate-to-ground parasitic capacitance (113).
  • the drain parasitic portion (120) includes a drain parasitic inductance (121), a drain parasitic resistance (122), and a drain-to-ground parasitic capacitance (123).
  • the source parasitic portion (130) includes a source parasitic inductance (131) and a source parasitic resistance (132).
  • the gate-source intrinsic unit (210) includes a gate-source capacitor (211), a gate-source resistor (212), and a gate-source leakage resistor (213).
  • the inter-gate drain eigencell (220) includes a gate-drain capacitance (221), a gate-drain resistance (222), and a gate leakage leakage resistance (223).
  • Source-drain eigencell including voltage control current source (231), channel resistance (232), channel capacitance (233), intrinsic resistance (234), intrinsic capacitance (235), intrinsic Inductance (236), intrinsic advanced inductance (237).
  • the gate parasitic inductance (111) and the gate parasitic resistance (112) are connected in series between the gate outer node (G) and the gate inner node (G'), and the gate-to-ground parasitic capacitance (113) is external to the gate
  • the nodes (G) are connected, and the other end is connected to the source outer node (S).
  • the drain parasitic inductance (121) and the drain parasitic resistance (122) are connected in series to the drain outer node (D) and the drain inner node (D') Between the drain-to-ground parasitic capacitance (123), one end is connected to the drain outer node (D), and the other end is connected to the source outer node (S).
  • the source parasitic inductance (131) and the source parasitic resistance (132) are connected in series between the source outer node (S) and the source inner node (S').
  • the gate source capacitor (211) and the gate source resistor (212) are connected in series between the gate inner node (G') and the source inner node (S'), and one end of the gate source leakage resistor (213) and the gate inner node (G) ') is connected, and the other end is connected to the source node (S').
  • the gate-drain capacitance (222) and the gate-drain resistance (221) are connected in series between the gate inner node (G') and the drain inner node (D'), and one end of the gate leakage leakage resistor (223) and the gate inner node (G) ') is connected, and the other end is connected to the node (D') in the drain.
  • the channel resistance (232) is connected in series with the intrinsic higher order inductor (237), one end of which is connected to the in-drain node (D') and the other end in series with the intrinsic inductor (236) and the intrinsic resistor (234).
  • the whole end is connected, the other end of the intrinsic inductor (236) and the intrinsic resistor (234) are connected in series with the source node (S'), and the intrinsic inductor (236) is connected in series with the intrinsic resistor (234).
  • the whole is connected in parallel with the intrinsic capacitor (235), the channel capacitor (233) is connected in parallel with the voltage control current source (231), and the channel capacitor (233) is connected in parallel with the voltage control current source (231). (D'), the other end is connected to the source node (S').
  • Step one determine the small-signal equivalent circuit model of the field effect transistor.
  • Step 2 The gate external node of the small-effect circuit equivalent circuit model of the field effect transistor determined above is used as an input terminal, the external node of the drain is used as an output terminal, and the outer node of the source is grounded for simulation.
  • step 3 the field effect transistor is tested, the gate is used as an input terminal, the drain is used as an output terminal, the source is grounded, and a set of frequencies is scanned, thereby obtaining two-port RF scattering parameters (S parameters) at different frequency points, and RF impedance.
  • S parameters two-port RF scattering parameters
  • Z parameters RF admittance parameters
  • Y parameters RF admittance parameters
  • the small-signal equivalent circuit model of the field effect transistor including the channel advanced parasitic element proposed by the present invention has been subjected to transistor testing to obtain two-port RF scattering parameters (S parameters) and RF impedance parameters (Z parameters) at different frequency points. After the RF admittance parameter (Y parameter), the component parameter extraction of the small-signal equivalent circuit model of the field effect transistor is performed.
  • the model parameter extraction method of the channel advanced parasitic element is:
  • the initial value of the channel advanced parasitic element is solved by the derivation of the Z parameter or the Y parameter.
  • the channel advanced parasitic element of the field effect transistor small signal equivalent circuit model proposed by the present invention is included in the source-drain eigencell, and the channel advanced parasitic element includes the intrinsic element.
  • the resistance parameter (234), the model parameter extraction method of the intrinsic resistance (234) is:
  • the intrinsic part of the transistor small-signal equivalent circuit circuit model is divided into four paths: gate source path, gate leak path, controlled source path, source-drain path, wherein source-drain path includes channel capacitance (233), channel resistance (232), the intrinsic resistance (234), set the channel capacitance (233) parameter value to C ds , the channel resistance (232) parameter value to R ds , and the intrinsic resistance ( 234 ) parameter value to R 1 .
  • the field effect transistor is tested, the gate is used as an input terminal, the drain is used as an output terminal, the source is grounded, and a set of frequencies is scanned, thereby obtaining two-port RF scattering parameters (S parameters) at different frequency points, and RF impedance parameters (Z Parameter), RF admittance parameter (Y parameter), the Z parameter and the Y parameter are respectively stripped off the parasitic part of the model to obtain the Z parameter or the Y parameter of the intrinsic part, the channel capacitance (233), the channel resistance (232), the source-drain path Y parameter (Y ds ) formed by the intrinsic resistance (234) can be obtained by adding Y 12 and Y 22 of the intrinsic part Y parameter, as shown in the following formula.
  • the source and drain Z parameters (Z ds ) are as follows.
  • the parameter value R ds of the channel resistance (232) can be calculated by the following formula.
  • the initial value of the parameter of the intrinsic resistance ( 234 ) is calculated, and then the numerical value between the source and the leakage path Y parameter test curve and the source and the leakage path Y parameter simulation result is calculated.
  • a field effect transistor small signal equivalent circuit model including a channel advanced parasitic element is implemented, the intrinsic advanced parasitic element comprising an intrinsic resistor (234) and an intrinsic inductor (236),
  • the channel advanced parasitic element is included in the source-drain eigen unit (230), the channel capacitance (233) is connected in parallel with the channel resistance (232), and the parallel whole end is connected to the drain internal node (D').
  • the other end is connected in series with the intrinsic resistor (234) and the intrinsic inductor (236). Connected, the other end of the series is connected to the source node (S'), one end of the voltage control current source (231) is connected to the drain inner node (D'), and the other end is connected to the source node (S' ).
  • the model parameter extraction methods of the intrinsic resistance (234) and the intrinsic inductance (236) are:
  • the intrinsic part of the transistor small-signal equivalent circuit circuit model is divided into four paths: gate source path, gate leak path, controlled source path, source-drain path, wherein source-drain path includes channel capacitance (233), channel resistance (232), intrinsic resistance (234), intrinsic inductance (236), set channel capacitance (233) parameter value C ds , channel resistance (232) parameter value R ds , intrinsic resistance (234) parameter
  • source-drain path includes channel capacitance (233), channel resistance (232), intrinsic resistance (234), intrinsic inductance (236), set channel capacitance (233) parameter value C ds , channel resistance (232) parameter value R ds , intrinsic resistance (234) parameter
  • the value is R 1 and the intrinsic inductance (236) parameter value is L 1 .
  • the field effect transistor is tested, the gate is used as an input terminal, the drain is used as an output terminal, the source is grounded, and a set of frequencies is scanned, thereby obtaining two-port RF scattering parameters (S parameters) at different frequency points, and RF impedance parameters (Z Parameter), RF admittance parameter (Y parameter), the Z parameter and the Y parameter are respectively stripped off the parasitic part of the model to obtain the Z parameter or the Y parameter of the intrinsic part, the channel capacitance (233), the channel resistance (232), the source-drain path Y parameter (Y ds ) formed by the intrinsic resistance (234) and the intrinsic inductance (236) can be obtained by adding Y 12 and Y 22 of the intrinsic part Y parameter, as shown in the following formula.
  • the source and drain Z parameters (Z ds ) are as follows.
  • the initial values of the parameters of the channel capacitance (233), the channel resistance (232), and the intrinsic resistance (234) are calculated by fitting the characteristic function f 1 ( ⁇ ). From the fitting of f 2 ( ⁇ ), the initial value of the parameter of the intrinsic inductance (236) is calculated, and then the method of numerical fitting between the source-leakage Y-parameter test curve and the source-drain Y-parameter simulation result is used to iterate.
  • the parameter values of the intrinsic resistance (234) and the intrinsic inductance (236) are optimized.

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  • Junction Field-Effect Transistors (AREA)

Abstract

本发明公开了一种场效应晶体管小信号等效电路模型，其特征在于，所述场效应晶体管小信号等效电路模型的本征部分包含沟道高级寄生元件，所述沟道高级寄生元件包括本征电阻、本征电容、本征电感这三种元件中的任意一种或者组合，从而实现在高频、大电流下，对晶体管的高精度仿真，本发明进一步公开了包含沟道高级寄生元件的特征函数，以及利用测量的S参数提取所述沟道高级寄生元件参数值的方法。本发明提出的包含沟道高级寄生元件的场效应晶体管小信号等效电路模型可以提高仿真同测试结果的拟合精度。

Description

包含沟道高级寄生元件的场效应晶体管小信号等效电路模型 所属技术领域
本发明涉及晶体管的器件模型，特别是场效应晶体管的小信号等效电路模型及参数提取方法。
背景技术
晶体管是微电子器件、集成电路芯片中一个最重要的元件，在各种不同领域具有广泛应用.在电子器件、集成电路的设计过程中，晶体管模型是一个不可缺少的工具。国际上晶体管的数字模型已经比较成熟，可以提供高精度的模型仿真。然而，目前晶体管的射频模型还不是很完善，成为射频电路芯片设计和实现的一个主要难点。
晶体管模型主要包括两大类型，物理模型和等效电路模型。其中，电路芯片的设计，主要是基于和频率无关的等效电路模型。高精度的等效电路模型是提高电路性能、缩短研制周期、提高设计成功率和成品率、降低研制成本的核心因素。
本发明主要是针对场效应晶体管的小信号等效电路模型。目前国际上通用的场效应晶体管模型，是基于论文(Gilles Dambrine，Alain Cappy，Frkdderic Heliodore，and Edouard Playez，“A New Method for Determining the FET Small-Signal Equivalent Circuit”，Microwave Theory and Techniques，IEEE Transactions on，36(7)：1151-1159，1988，参考文献1)提出的模型结构，再结合某些额外的元件进行修正。所有这些传统模型的一个共同点，是在本征部分只考虑了一级效应，其中沟道部分只包含了一个沟道电阻和一个沟道电容，但没有考虑沟道电流所导致的高级寄生效应。本发明针对传统模型的这个缺陷，提出一种新型的模型结构，从而在本征部分包含沟道高级寄生元件，从而实现对场效应晶体管的高精度仿真。
以下，我们通过对场效应晶体管传统模型技术的分析，介绍传统场效应晶体管小信号等效电路模型的缺陷，并说明本发明思想的新颖性。
场效应晶体管的传统小信号等效电路模型是基于参考文献1的14元件模型。在此基础上，发明专利(Roger S.Tsal，
Figure PCTCN2017000528-appb-000001
MODELING OF HEMT HIGH FREQUENCY SMALL SIGNAL 
Figure PCTCN2017000528-appb-000002
CIRCUTT MODELS”，US200200077258A1，Jan.17，2002，参考专利1)提出了一种针对高迁移率场效应晶体管(HEMT)小信号等效电路模型半物理建模方法。该发明专利中采用的等效电路模型包括寄生部分和本征部分两部分，其中，寄生部分包括栅极寄生电感、栅极寄生电阻、漏极寄生电感、漏极寄生电阻、源极寄生电感、源极寄生电阻；本征部分包括栅漏电容、栅源电容、电压控制电流源、沟道电阻、沟道电容、栅源电阻、栅漏电阻、栅源泄露电阻以及栅漏泄露电阻。该发明专利考虑的高阶寄生效应体现在寄生部分，包括栅极寄生电感，漏极寄生电感以及源极寄生电感。但该专利中对本征部分的沟道高级寄生效应却没有考虑。
论文(Fan Qian，Jacoi_H.Leach，and Hadis Morkoc，“Small signal equivalent circuit modeling for AlGaN/GaN 
Figure PCTCN2017000528-appb-000003
Hybrid extraction method for determining circuit elements of AlGaN/GaN HFET”，
Figure PCTCN2017000528-appb-000004
of the IEEE，98(7)：1140-1150，2010，参考文献2)介绍了氮化镓(GaN)场效应管关键元件的混合提取方法，该论文采用了一种包含18个元件的等效电路模型，同参考专利1采用的等效电路模型相比，增加考虑了栅极寄生电容、漏极寄生电容。相比于参考专利1，该论文的模型精度虽然有了改善，但仍没有包括本征部分的沟道高级寄生元件。
另外一种晶体管小信号等效电路模型包含22个元件，请参照论文(A.Jarndal A，G..Kompa，“A new small-signal 
Figure PCTCN2017000528-appb-000005
approach applied to GaN devices”，Microwave Theory and Techniques，IEEE Transactions on，53(11)：3440-3448，2005，参考文献3)。该论文基于分布式模型的思想，相比于参考文献
Figure PCTCN2017000528-appb-000006
中的等效电路模型，额外考虑了栅极、漏极以及源极的极间寄 生电容，主要体现在考虑了栅源极间寄生交叠电容、栅漏极间寄生交叠电容、源漏极间寄生交叠电容。但本征部分的沟道高级寄生效应仍然没有被考虑。
在参考文献3的基础上，论文(R.James Shealy，Jiali Wang，and Richard Brown，“Methodology for small-signal model extraction of AlGaN HEMTs”，Electron Devices，IEEE Transactions on，55(7)：1603-1613，2008，参考文献4)，认为极间寄生交叠电容可以被相应端口上的对地寄生电容所吸收，近似地将极间寄生交叠电容移到相应端口寄生电阻内侧，这样等效电路模型就可以拆分成多个相对独立的部分，从而简化参数提取过程。该论文的等效电路模型结构同参考文献3相比，虽然拓扑上有所不同，但所考虑的物理效应类似，虽然可比较精确地仿真低频下的晶体管模型，但却没有考虑高频下的沟道高级寄生效应。
论文(Andreas R.Alt，Marti Diego，and C.R.Bolognesi，“Transistor Modeling：Robust Small-Signal Equivalent Circuit Extraction in Various HEMT Technologies”，Microwave Magazine，IEEE，14(4)：83-101，2013，参考文献5)提出了一种HEMT晶体管的小信号等效电路模型。该模型在寄生部分考虑了栅极、漏极衬底损耗电阻以表征栅极、漏极衬底损耗，寄生部分同参考文献3一样包括了分布式电容效应.同参考文献3相比该论文模型精度有所提高，但也也同样没有包括高频下具有重要影响的沟道高级寄生效应。
本征部分的沟道高级寄生效应反映了晶体管内部电流产生的高级寄生效应，通过包括本征电阻、本征电容、本征电感这三种元件中的任意一种或者组合的沟道高级寄生元件的形式体现出来。我们在随后的测试结果与仿真结果的比较中，说明仅仅通过考虑了一级效应的现有场效应晶体管等效电路模型技术，无法实现等效电路模型和测试结果之间的高精度拟合。
现有场效应晶体管小信号等效电路模型已经考虑的高级寄生效应只体现在寄生部分，但是晶体管内部电流流动也同样会产生高级寄生效应，这种沟道高级寄生效应却没有被现有晶体管小信号等效电路模型所考虑。更重要的，随着晶体管特征尺寸以及沟道长度的减小，沟道高级寄生元件对晶体管性能的影响更加显著，且沟道高级寄生元件的值随偏置的变化而变化，这种特性将无法通过调节现有晶体管小信号等效电路模型中的元件参数来体现，从而，现有晶体管小信号等效电路模型无法实现对晶体管的高精度仿真。
综上所述，目前国际上现有的场效应晶体管小信号等效电路模型均没有考虑本征部分存在的沟道高级寄生元件，因此现有晶体管小信号等效电路模型无法实现同测试结果的高精度拟合。
发明内容
有鉴于上述现有技术之缺失，本发明提出的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型将解决存在于现有技术中的该些缺失。
本发明所提出的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述场效应晶体管小信号等效电路模型的本征部分包含沟道高级寄生元件，所述沟道高级寄生元件包括本征电阻、本征电容、本征电感这三种元件中的任意一种或者组合。
本发明所提出的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型的示意图，如图1所示，
场效应晶体管小信号等效电路模型包括寄生部分(100)和本征部分(200)，其中，寄生部分包括栅极寄生单元(110)、漏极寄生单元(120)、源极寄生单元(130)，本征部分包括栅源极间本征单元(210)、栅漏极间本征单元(220)、源漏极间本征单元(230)。
所述沟道高级寄生元件包括本征电阻，所述本征电阻包含于源漏极间本征单元(230)中。
所述栅极寄生单元(110)位于栅极外节点(G)、栅极内节点(G′)之间，并与栅极外节点(G)、栅极内节点(G′)相连接；所述漏极寄生单元(120)位于漏极外节点(D)、漏极内节点(D′)之间，并与漏极外节点(D)、漏极内节点(D′)相连接；所述源极寄生单元(130)位于源极外节点(S)、源极内节点(S′)之间，并与源极外节点(S)、源极内节点(S′)相连 接，且位于于栅极寄生单元与漏极寄生单元之间，并与栅极寄生单元与漏极寄生单元相连接。
所述栅源极间本征单元(210)位于栅极内节点(G′)、源极内节点(S′)之间，并与栅极内节点(G′)、源极内节点(S′)相连接；所述栅漏极间本征单元(220)位于栅极内节点(G′)、漏极内节点(D′)之间，并与栅极内节点(G′)、漏极内节点(D′)相连接；所述源漏极间本征单元(230)位于漏极内节点(D′)、源极内节点(S′)之间，并与漏极内节点(D′)、源极内节点(S′)相连接。
较佳地，本发明所提出的一种新型场效应晶体管小信号等效电路模型适用于所有场效应晶体管，包括但不限于金属-氧化物-半导体晶体(MOSFET)、金属-半导体晶体管(MESFET)、高电子迁移率晶体管(HEMT)和赝高电子迁移率晶体管(PHEMT)；场效应晶体管由硅(Si)、锗硅(SiGe)、砷化镓(GaAs)、磷化铟(InP)、碳化硅(SiC)或氮化镓(GaN)材料制备。
附图说明
下面结合附图和实施例对本发明做进一步说明。
图1是包含沟道高级寄生元件的场效应晶体管小信号等效电路模型示意图(示例性实施例一)。
图2是包含沟道高级寄生元件的场效应晶体管小信号等效电路模型示意图(示例性实施例二)。
图3是包含沟道高级寄生元件的场效应晶体管小信号等效电路模型示意图(示例性实施例三)。
图4是场效应晶体管S参数测量值与采用不包含沟道高级寄生元件的传统晶体管小信号等效电路模型时仿真值的比较。
图5是场效应晶体管S参数测量值与采用本发明的包含沟道高级寄生元件的场效应晶体管小信号等效电路模型时仿真值的比较。
其中
100-场效应晶体管小信号等效电路模型寄生部分(包括110、120、130)
200-场效应晶体管小信号等效电路模型本征部分(包括210、220、230)
110-栅极寄生单元
120-漏极寄生单元
130-源极寄生单元
210-栅源极间本征单元
220-栅漏极间本征单元
230-源漏极间本征单元
G-栅极外节点
D-漏极外节点
S-源极外节点
G′-栅极内节点
D′-漏极内节点
S′-源极内节点
111-栅极寄生电感
112-栅极寄生电阻
113-栅极对地寄生电容
121-漏极寄生电感
122-漏极寄生电阻
123-漏极对地寄生电容
131-源极寄生电感
132-源极寄生电阻
211-栅源电容
212-栅源电阻
213-栅源泄露电阻
221-栅漏电容
222-栅漏电阻
223-栅漏泄露电阻
231-电压控制电流源
232-沟道电阻
233-沟道电容
234-本征电阻
235-本征电容
236-本征电感
237-本征高级电感
61-场效应晶体管S参数测量值
62-采用不包含沟道高级寄生元件的传统晶体管小信号等效电路模型时S参数仿真值
63-采用本发明的包含沟道高级寄生元件的场效应晶体管小信号等效电路模型时S参数仿真值
具体实施方式
下面结合具体实施例，进一步阐明本发明，应理解实施例仅用于说明本发明而不用于限制本发明的范围，在阅读了本发明之后，本领域技术人员对本发明的各种等价形式的修改均落于本申请所附权利要求项要求所限定的范围。
本发明的示例性实施例一
本发明的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型的实施方式：
如图1所示，场效应晶体管小信号等效电路模型包括寄生部分(100)和本征部分(200)，其中，寄生部分包括栅极寄生单元(110)、漏极寄生单元(120)、源极寄生单元(130)，本征部分包括栅源极间本征单元(210)、栅漏极间本征单元(220)、源漏极间本征单元(230)。
所述沟道高级寄生元件包括本征电阻，所述本征电阻包含于源漏极间本征单元(230)中。
所述栅极寄生单元(110)位于栅极外节点(G)、栅极内节点(G′)之间，并与栅极外节点(G)、栅极内节点(G′)相连接；所述漏极寄生单元(120)位于漏极外节点(D)、漏极内节点(D′)之间，并与漏极外节点(D)、漏极内节点(D′)相连接；所述源极寄生单元(130)位于源极外节点(S)、源极内节点(S′)之间，并与源极外节点(S)、源极内节点(S′)相连接，且位于于栅极寄生单元与漏极寄生单元之间，并与栅极寄生单元与漏极寄生单元相连接。
所述栅源极间本征单元(210)位于栅极内节点(G′)、源极内节点(S′)之间，并与栅极内节点(G′)、源极内节点(S′)相连接；所述栅漏极间本征单元(220)位于栅极内节点(G′)、漏极内节点(D′)之间，并与栅极内节点(G′)、漏极内节点(D′)相连接；所述源漏极间本征单元(230)位于漏极内节点(D′)、源极内节点(S′)之间，并与漏极内节点(D′)、源极内节点(S′)相连接.
栅极寄生部分(110)：包括栅极寄生电感(111)、栅极寄生电阻(112)、栅极对地寄生电容(113)。
漏极寄生部分(120)：包括漏极寄生电感(121)、漏极寄生电阻(122)、漏极对地寄生电容(123)。
源极寄生部分(130)：包括源极寄生电感(131)、源极寄生电阻(132)。
栅源极间本征单元(210)：包括栅源电容(211)、栅源电阻(212)、栅源泄露电阻(213)。
栅漏极间本征单元(220)：包括栅漏电容(221)、栅漏电阻(222)、栅漏泄露电阻(223)。
源漏极间本征单元(230)：包括电压控制电流源(231)、沟道电阻(232)、沟道电容(233)、本征电阻(234)。
栅极寄生电感(111)与栅极寄生电阻(112)串联于栅极外节点(G)和栅极内节点(G′)之间，栅极对地寄生电容(113)一端与栅极外节点(G)相连接，另一端与源极外节点(S)相连接.
漏极寄生电感(121)与漏极寄生电阻(122)串联于漏极外节点(D)和漏极内节点(D′)之间，漏极对地寄生电容(123)一端与漏极外节点(D)相连接，另一端与源极外节点(S)相连接.
源极寄生电感(131)与源极寄生电阻(132)串联于源极外节点(S)和源极内节点(S′)之间。
栅源电容(211)与栅源电阻(212)串联于栅极内节点(G′)和源极内节点(S′)之间，栅源泄漏电阻(213)一端与栅极内节点(G′)相连接，另一端与源极内节点(S′)相连接。
栅漏电容(222)与栅漏电阻(221)串联于栅极内节点(G′)和漏极内节点(D′)之间，栅漏泄漏电阻(223)一端与栅极内节点(G′)相连接，另一端与漏极内节点(D′)相连接。
沟道电容(233)与沟道电阻(232)并联的整体的一端与漏极内节点(D′)相连接，另一端与所述本征电阻(234)相连，所述本征电阻(234)的另一端与源极内节点(S′)相连接，电压控制电流源(231)的一端连接漏极内节点(D′)，另一端连接源极内节点(S′)。
本发明的示例性实施例二
本发明的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型的实施方式：
如图2所示，场效应晶体管小信号等效电路模型包括寄生部分(100)和本征部分(200)，其中，寄生部分包括栅极寄生单元(110)、漏极寄生单元(120)、源极寄生单元(130)，本征部分包括栅源极间本征单元(210)、栅漏极间本征单元(220)、源漏极间本征单元(230)。
所述本征高级寄生元件包括本征电阻(234)、本征电容(235)，本征电感(236)，所述沟道高级寄生元件包含于源漏极间本征单元(230)中。
所述栅极寄生单元(110)位于栅极外节点(G)、栅极内节点(G′)之间，并与栅极外节点(G)、栅极内节点(G′)相连接；所述漏极寄生单元(120)位于漏极外节点(D)、漏极内节点(D′)之间，并与漏极外节点(D)、漏极内节点(D′)相连接；所述源极寄生单元(130)位于源极外节点(S)、源极内节点(S′)之间，并与源极外节点(S)、源极内节点(S′)相连接，且位于于栅极寄生单元与漏极寄生单元之间，并与栅极寄生单元与漏极寄生单元相连接。
所述栅源极间本征单元(210)位于栅极内节点(G′)、源极内节点(S′)之间，并与栅极内节点(G′)、源极内节点(S′)相连接；所述栅漏极间本征单元(220)位于栅极内节点(G′)、漏极内节点(D′)之间，并与栅极内节点(G′)、漏极内节点(D′)相连接；所述源漏极间本征单元(230)位于漏极内节点(D′)、源极内节点(S′)之间，并与漏极内节点(D′)、源极内节点(S′)相连接。
栅极寄生部分(110)：包括栅极寄生电感(111)、栅极寄生电阻(112)、栅极对地寄生电容(113).
漏极寄生部分(120)：包括漏极寄生电感(121)、漏极寄生电阻(122)、漏极对地寄生电容(123)。
源极寄生部分(130)：包括源极寄生电感(131)、源极寄生电阻(132)。
栅源极间本征单元(210)：包括栅源电容(211)、栅源电阻(212)、栅源泄露电阻(213)。
栅漏极间本征单元(220)：包括栅漏电容(221)、栅漏电阻(222)、栅漏泄露电阻(223)。
源漏极间本征单元(230)：包括电压控制电流源(231)、沟道电阻(232)、沟道电容(233)、本征电阻(234)、本征电容(235)、本征电感(236).
栅极寄生电感(111)与栅极寄生电阻(112)串联于栅极外节点(G)和栅极内节点(G′)之间，栅极对地寄生电容(113)一端与栅极外节点(G)相连接，另一端与源极外节点(S) 相连接。
漏极寄生电感(121)与漏极寄生电阻(122)串联于漏极外节点(D)和漏极内节点(D′)之间，漏极对地寄生电容(123)一端与漏极外节点(D)相连接，另一端与源极外节点(S)相连接。
源极寄生电感(131)与源极寄生电阻(132)串联于源极外节点(S)和源极内节点(S′)之间.
栅源电容(211)与栅源电阻(212)串联于栅极内节点(G′)和源极内节点(S′)之间，栅源泄漏电阻(213)一端与栅极内节点(G′)相连接，另一端与源极内节点(S′)相连接。
栅漏电容(222)与栅漏电阻(221)串联于栅极内节点(G′)和漏极内节点(D′)之间，栅漏泄漏电阻(223)一端与栅极内节点(G′)相连接，另一端与漏极内节点(D′)相连接。
沟道电容(233)与沟道电阻(232)并联，本征电阻(234)与本征电容(235)并联，沟道电容(233)与沟道电阻(232)并联整体的一端与漏极内节点(D′)相连接，另一端与本征电阻(234)和本征电容(235)并联整体的一端相连接，本征电阻(234)与本征电容(235)并联整体的另一端与本征电感(236)连接，本征电感(236)的另一端与源极内节点(S′)相连接，电压控制电流源(231)的一端连接漏极内节点(D′)，另一端连接源极内节点(S′)。
本发明的示例性实施例三
本发明的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型的实施方式：
如图3所示，场效应晶体管小信号等效电路模型包括寄生部分(100)和本征部分(200)，其中，寄生部分包括栅极寄生单元(110)、漏极寄生单元(120)、源极寄生单元(130)，本征部分包括栅源极间本征单元(210)、栅漏极间本征单元(220)、源漏极间本征单元(230)。
所述沟道高级寄生元件包括本征电阻(234)、本征电容(235)、本征电感(236)、本征高级电感(237)，所述沟道高级寄生元件包含于源漏极间本征单元(230)中。
所述栅极寄生单元(110)位于栅极外节点(G)、栅极内节点(G′)之间，并与栅极外节点(G)、栅极内节点(G′)相连接；所述漏极寄生单元(120)位于漏极外节点(D)、漏极内节点(D′)之间，并与漏极外节点(D)、漏极内节点(D′)相连接；所述源极寄生单元(130)位于源极外节点(S)、源极内节点(S′)之间，并与源极外节点(S)、源极内节点(S′)相连接，且位于于栅极寄生单元与漏极寄生单元之间，并与栅极寄生单元与漏极寄生单元相连接。
所述栅源极间本征单元(210)位于栅极内节点(G′)、源极内节点(S′)之间，并与栅极内节点(G′)、源极内节点(S′)相连接；所述栅漏极间本征单元(220)位于栅极内节点(G′)、漏极内节点(D′)之间，并与栅极内节点(G′)、漏极内节点(D′)相连接；所述源漏极间本征单元(230)位于漏极内节点(D′)、源极内节点(S′)之间，并与漏极内节点(D′)、源极内节点(S′)相连接。
栅极寄生部分(110)：包括栅极寄生电感(111)、栅极寄生电阻(112)、栅极对地寄生电容(113)。
漏极寄生部分(120)：包括漏极寄生电感(121)、漏极寄生电阻(122)、漏极对地寄生电容(123)。
源极寄生部分(130)：包括源极寄生电感(131)、源极寄生电阻(132)。
栅源极间本征单元(210)：包括栅源电容(211)、栅源电阻(212)、栅源泄露电阻(213)。
栅漏极间本征单元(220)：包括栅漏电容(221)、栅漏电阻(222)、栅漏泄露电阻(223)。
源漏极间本征单元(230)：包括电压控制电流源(231)、沟道电阻(232)、沟道电容(233)、本征电阻(234)、本征电容(235)、本征电感(236)、本征高级电感(237)。
栅极寄生电感(111)与栅极寄生电阻(112)串联于栅极外节点(G)和栅极内节点(G′)之间，栅极对地寄生电容(113)一端与栅极外节点(G)相连接，另一端与源极外节点(S)相连接.
漏极寄生电感(121)与漏极寄生电阻(122)串联于漏极外节点(D)和漏极内节点(D′) 之间，漏极对地寄生电容(123)一端与漏极外节点(D)相连接，另一端与源极外节点(S)相连接。
源极寄生电感(131)与源极寄生电阻(132)串联于源极外节点(S)和源极内节点(S′)之间。
栅源电容(211)与栅源电阻(212)串联于栅极内节点(G′)和源极内节点(S′)之间，栅源泄漏电阻(213)一端与栅极内节点(G′)相连接，另一端与源极内节点(S′)相连接。
栅漏电容(222)与栅漏电阻(221)串联于栅极内节点(G′)和漏极内节点(D′)之间，栅漏泄漏电阻(223)一端与栅极内节点(G′)相连接，另一端与漏极内节点(D′)相连接。
沟道电阻(232)与本征高阶电感(237)串联，该串联整体一端与漏极内节点(D′)相连接，另一端与本征电感(236)和本征电阻(234)串联整体的一端相连接，本征电感(236)与本征电阻(234)串联整体的另一端与源极内节点(S′)相连接，本征电感(236)与本征电阻(234)串联的整体与本征电容(235)并联，沟道电容(233)与电压控制电流源(231)并联，沟道电容(233)与电压控制电流源(231)并联整体的一端连接漏极内节点(D′)，另一端连接源极内节点(S′)。
本发明的其他特征和方面
本发明的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型建模具体包括以下步骤：
步骤一，确定场效应晶体管小信号等效电路模型.
步骤二，以上确定的场效应晶体管小信号等效电路模型的栅极外节点作为输入端，漏极外节点作为输出端，源极外节点接地，进行仿真.
步骤三，对场效应晶体管进行测试，栅极作为输入端，漏极作为输出端，源极接地，扫描一组频率，从而得到不同频率点上的两端口射频散射参数(S参数)，射频阻抗参数(Z参数)，射频导纳参数(Y参数)。
本发明所提出的包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，在已进行晶体管测试得到不同频率点上的两端口射频散射参数(S参数)、射频阻抗参数(Z参数)、射频导纳参数(Y参数)后，进行场效应晶体管小信号等效电路模型的元件参数提取，
所述沟道高级寄生元件的模型参数提取方法是：
剥离掉寄生部分，得到本征部分的Z参数或者Y参数，
通过Z参数或者Y参数的推导求解出沟道高级寄生元件的初始值，
利用测试曲线与仿真结果之间曲线拟合的方法，迭代优化得到沟道高级寄生元件的值。
具体地，针对示例性实施例一，本发明所提出的场效应晶体管小信号等效电路模型的沟道高级寄生元件包含于源漏极间本征单元，所述沟道高级寄生元件包括本征电阻(234)，所述本征电阻(234)的模型参数提取方法是：
将晶体管小信号等效电路电路模型的本征部分分为四路：栅源路、栅漏路、受控源路、源漏路，其中源漏路包括沟道电容(233)、沟道电阻(232)、本征电阻(234)，设沟道电容(233)参数值为Cds、沟道电阻(232)参数值为Rds、本征电阻(234)参数值为R1.
对场效应晶体管进行测试，栅极作为输入端，漏极作为输出端，源极接地，扫描一组频率，从而得到不同频率点上的两端口射频散射参数(S参数)，射频阻抗参数(Z参数)，射频导纳参数(Y参数)，上述Z参数与Y参数分别剥离掉所述模型寄生部分后得到本征部分的Z参数或者Y参数，所述沟道电容(233)、沟道电阻(232)、本征电阻(234)构成的源漏路Y参数(Yds)可以通过本征部分Y参数的Y12与Y22相加得到，见下式，
Yds＝Y12+Y22         (1)
源漏路Z参数(Zds)见下式，
Figure PCTCN2017000528-appb-000007
根据所述模型本征部分源漏路的电路结构推导出包含所述沟道高级寄生元件的特征函数表达式，设特征函数f1(ω)＝Re[Zds]，其表达式如下式，
Figure PCTCN2017000528-appb-000008
设特征函数f2(ω)＝-ω/Im[Zds]，其表达式如下式，
Figure PCTCN2017000528-appb-000009
设特征函数f0(ω)＝Re[Yds]＝Re[Y22+Y12]，其表达式如下式，
Figure PCTCN2017000528-appb-000010
利用上述源漏路Y参数的测试数据，通过特征函数f2(ω)对ω2的线性拟合得到斜率(k1＝Cds)和截距
Figure PCTCN2017000528-appb-000011
沟道电阻(232)的参数值Rds可以通过下式计算得到，
Figure PCTCN2017000528-appb-000012
通过特征函数f1(ω)对ω2的拟合，计算出本征电阻(234)的参数初始值，然后再利用源漏路Y参数测试曲线与源漏路Y参数仿真结果之间数值拟合的方法，迭代优化得到所述本征电阻(234)的参数值。
以下是场效应晶体管S参数测量值与晶体管小信号等效电路模型的仿真值比较：
在图4中可以看出，当采用不包含沟道高级寄生元件的现有晶体管小信号等效电路模型，对测试S参数四个分量S11、S12、S21、S22进行仿真时，即使调节模型的元件参数以实现S11和S12同测试结果的高精度拟合，但却无法同时实现S21和S22同测试结果的高精度拟合。
当采用本发明的包含沟道高级寄生元件的场效应晶体管小信号等效电路模型以及沟道高级寄生元件的模型参数提取方法后，由图5中可以看出，可以同时实现S11、S22、S21、S22四个分量的同时高精度拟合。可以看出，利用本发明的包含沟道高级寄生元件的场效应晶体管小信号等效电路模型以及沟道高级寄生元件的模型参数提取方法可以实现同测试结果更高精度的拟合。
具体地，实施本发明的一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，所述本征高级寄生元件包括本征电阻(234)、本征电感(236)，所述沟道高级寄生元件包含于源漏极间本征单元(230)中，沟道电容(233)与沟道电阻(232)并联，该并联整体一端与漏极内节点(D′)相连接，另一端与本征电阻(234)与本征电感(236)串联整体的一端 相连接，该串联整体的另一端与源极内节点(S′)相连接，电压控制电流源(231)的一端连接漏极内节点(D′)，另一端连接源极内节点(S′)。
所述本征电阻(234)、本征电感(236)的模型参数提取方法是：
将晶体管小信号等效电路电路模型的本征部分分为四路：栅源路、栅漏路、受控源路、源漏路，其中源漏路包括沟道电容(233)、沟道电阻(232)、本征电阻(234)、本征电感(236)，设沟道电容(233)参数值为Cds、沟道电阻(232)参数值为Rds、本征电阻(234)参数值为R1、本征电感(236)参数值为L1。
对场效应晶体管进行测试，栅极作为输入端，漏极作为输出端，源极接地，扫描一组频率，从而得到不同频率点上的两端口射频散射参数(S参数)，射频阻抗参数(Z参数)，射频导纳参数(Y参数)，上述Z参数与Y参数分别剥离掉所述模型寄生部分后得到本征部分的Z参数或者Y参数，所述沟道电容(233)、沟道电阻(232)、本征电阻(234)、本征电感(236)构成的源漏路Y参数(Yds)可以通过本征部分Y参数的Y12与Y22相加得到，见下式，
Yds＝Y12+Y22          (1)
源漏路Z参数(Zds)见下式，
Figure PCTCN2017000528-appb-000013
根据所述模型本征部分源漏路的电路结构推导出包含所述沟道高级寄生元件的特征函数表达式，设特征函数f1(ω)＝1/Re[Zds]，其表达式如下式，
Figure PCTCN2017000528-appb-000014
设特征函数f2(ω)＝Im[Yds]＝Im[Y22+Y12]，其表达式如下式，
Figure PCTCN2017000528-appb-000015
设特征函数f0(ω)＝Re[Yds]＝Re[Y22+Y12]，其表达式如下式，
Figure PCTCN2017000528-appb-000016
利用上述源漏路Y参数的测试数据，通过特征函数f1(ω)的拟合，计算出沟道电容(233)、沟道电阻(232)、本征电阻(234)的参数初始值，从f2(ω)的拟合，计算出本征电感(236)的参数初始值，然后再利用源漏路Y参数测试曲线与源漏路Y参数仿真结果之间数值拟合的方法，迭代优化得到所述本征电阻(234)、本征电感(236)的参数值。

Claims (11)

  1. 一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，所述模型本征部分包含沟道电阻Rds及沟道电容Cds，其特征在于，所述场效应晶体管小信号等效电路模型的本征部分包含沟道高级寄生元件，所述沟道高级寄生元件包括本征电阻R1、本征电容C1、本征电感L1这三种元件中的任意一种或者组合.
  2. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述沟道高级寄生元件包括本征电阻R1，沟道电阻Rds及沟道电容Cds并联的整体再与所述本征电阻R1串联；或者沟道电容Cds与所述本征电阻R1串联的整体再与沟道电阻Rds并联。
  3. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述沟道高级寄生元件包括本征电感L1，沟道电阻Rds及沟道电容Cds并联的整体再与所述本征电感L1串联；或者沟道电阻Rds与所述本征电感L1串联的整体再与沟道电容Cds并联.
  4. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述沟道高级寄生元件包括本征电阻R1、本征电容C1，所述本征电阻R1与本征电容C1并联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联。
  5. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述沟道高级寄生元件包括本征电阻R1、本征电感L1，所述本征电阻R1与本征电感L1并联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联；或者所述本征电阻R1与本征电感L1串联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联；或者所述本征电阻R1与沟道电容Cds串联，该串联与沟道电阻Rds并联后，再与本征电感L1串联；或者所述本征电阻R1与沟道电容Cds串联的整体，再与所述本征电感L1与沟道电阻Rds串联的整体并联；或者所述本征电感L1与沟道电阻Rds串联的整体与沟道电容Cds并联，该并联整体再与所述本征电阻R1串联。
  6. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述沟道高级寄生元件包括本征电容C1、本征电感L1，所述本征电容C1与本征电感L1并联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联；或者所述本征电感L1与沟道电阻Rds及沟道电容Cds并联的整体串联，该串联整体再与本征电容C1并联。
  7. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述沟道高级寄生元件包括本征电阻R1、本征电容C1、本征电感L1，所述本征电阻R1与本征电感L1串联的整体与本征电容C1并联，该并联整体再与沟道电阻Rds及沟道电容Cds并联的整体串联；或者所述本征电阻R1与本征电容C1并联的整体、沟道电阻Rds及沟道电容Cds并联的整体、本征电感L1三者串联；或者所述本征电阻R1与本征电感L1串联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联，该串联整体再与本征电容C1并联；或者所述本征电阻R1与本征电感L1串联的整体再与本征电容C1并联，该并联整体再与沟道电阻Rds串联，该串联整体再与沟道电容Cds并联；所述本征电容C1与本征电感L1并联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联，该串联整体再与所述本征电阻R1并联；或者所述本征电感L1与沟道电阻Rds串联的整体与沟道电容Cds并联，该并联整体再与所述本征电阻R1及所述本征电容C1并联的整体串联；所述本征电阻R1、本征电容C1与本征电感L1三者并联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联；所述本征电阻R1与本征电容C1并联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联，该串联再与所述本征电感L1并联.
  8. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述沟道高级寄生元件包括本征电阻R1、本征电容C1、本征电感L1、本征高阶电感L2，所述本征电阻R1与本征电感L1串联的整体再与本征电容C1并联，该并联与沟道电阻Rds、本征高阶电感L2三者串联，该串联整体再与沟道电容Cds并联。
  9. 根据权利要求1所述一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，其特征在于，所述的沟道高级寄生元件参数的提取方法是：对场效应晶体管进行测试，栅极作为输入端，漏极作为输出端，源极接地，扫描一组频率，从而得到不同频率点上的两端口射频散射参数(S参数)，射频阻抗参数(Z参数)，射频导纳参数(Y参数)，确定场效应晶体管小信号等效电路模型的等效电路结构，根据上述确定的模型等效电路结构推导出包含所述沟道高级寄生元件的特征函数表达式，利用上述包括射频阻抗参数(Z参数)、射频导纳参数(Y参数)的测试数据拟合出所述沟道高级寄生元件的初始值，上述确定的场效应晶体管小信号等效电路模型的栅极外节点作为输入端，漏极外节点作为输出端，源极外节点接地，进行仿真，利用测试曲线与仿真结果之间数值拟合的方法，迭代优化得到所述沟道高级寄生元件的参数值。
  10. 根据权利要求2所述，一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，沟道电阻Rds及沟道电容Cds并联的整体再与所述本征电阻R1串联，其特征在于，所述本征电阻R1参数的提取方法是：
    对场效应晶体管进行测试，栅极作为输入端，漏极作为输出端，源极接地，扫描一组频率，从而得到不同频率点上的两端口射频散射参数(S参数)，射频阻抗参数(Z参数)，射频导纳参数(Y参数)，上述Z参数与Y参数分别剥离掉所述模型寄生部分后得到本征部分的Z参数或者Y参数，所述本征电阻R1、沟道电阻Rds及沟道电容Cds构成的源漏路Y参数(Yds)可以通过本征部分Y参数的Y12与Y22相加得到，见下式，
    Yds＝Y12+Y22         (1)
    源漏路Z参数(Zds)见下式，
    Figure PCTCN2017000528-appb-100001
    根据所述模型本征部分源漏路的电路结构推导出包含所述沟道高级寄生元件的特征函数表达式，设特征函数f1(ω)＝Re[Zds]，其表达式如下式，
    Figure PCTCN2017000528-appb-100002
    设特征函数f2(ω)＝-ω/Im[Zds]，其表达式如下式，
    Figure PCTCN2017000528-appb-100003
    设特征函数f0(ω)＝Re[Yds]＝Re[Y22+Y12]，其表达式如下式，
    Figure PCTCN2017000528-appb-100004
    利用上述源漏路Y参数的测试数据，通过特征函数f2(ω)对ω2的线性拟合得到斜率(k1＝Cds)和截距
    Figure PCTCN2017000528-appb-100005
    沟道电阻Rds可以通过下式计算得到，
    Figure PCTCN2017000528-appb-100006
    通过特征函数f1(ω)对ω2的拟合，计算出R1的参数初始值，然后再利用源漏路Y参数测试曲线与源漏路Y参数仿真结果之间数值拟合的方法，迭代优化得到所述本征电阻R1的参数值.
  11. 根据权利要求5所述，一种包含沟道高级寄生元件的场效应晶体管小信号等效电路模型，所述本征电阻R1与本征电感L1串联的整体再与沟道电阻Rds及沟道电容Cds并联的整体串联，其特征在于，所述所述本征电阻R1与本征电感L1参数的提取方法是：
    对场效应晶体管进行测试，栅极作为输入端，漏极作为输出端，源极接地，扫描一组频率，从而得到不同频率点上的两端口射频散射参数(S参数)，射频阻抗参数(Z参数)，射频导纳参数(Y参数)，上述Z参数与Y参数分别剥离掉所述模型寄生部分后得到本征部分的Z参数或者Y参数，所述本征电阻R1、沟道电阻Rds及沟道电容Cds构成的源漏路Y参数(Yds)可以通过本征部分Y参数的Y12与Y22相加得到，见下式，
    Yds＝Y12+Y22          (1)
    源漏路Z参数(Zds)见下式，
    Figure PCTCN2017000528-appb-100007
    根据所述模型本征部分源漏路的电路结构推导出包含所述沟道高级寄生元件的特征函数表达式，设特征函数f1(ω)＝1/Re[Zds]，其表达式如下式，
    Figure PCTCN2017000528-appb-100008
    设特征函数f2(ω)＝Im[Yds]＝Im[Y22+Y12]，其表达式如下式，
    Figure PCTCN2017000528-appb-100009
    设特征函数f0(ω)＝Re[Yds]＝Re[Y22+Y12]，其表达式如下式，
    Figure PCTCN2017000528-appb-100010
    利用上述源漏路Y参数的测试数据，通过特征函数f1(ω)的拟合，计算出R1、Rds，Cds的参数初始值，从f2(ω)的拟合，计算出L1的参数初始值，然后再利用源漏路Y参数测试曲线与源漏路Y参数仿真结果之间数值拟合的方法，迭代优化得到所述本征电阻R1与本征电感L1的参数值。
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