WO2018015839A3 - A cam memory - Google Patents

A cam memory Download PDF

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Publication number
WO2018015839A3
WO2018015839A3 PCT/IB2017/054171 IB2017054171W WO2018015839A3 WO 2018015839 A3 WO2018015839 A3 WO 2018015839A3 IB 2017054171 W IB2017054171 W IB 2017054171W WO 2018015839 A3 WO2018015839 A3 WO 2018015839A3
Authority
WO
WIPO (PCT)
Prior art keywords
plurality
bits
lines
memory cells
memory
Prior art date
Application number
PCT/IB2017/054171
Other languages
French (fr)
Other versions
WO2018015839A2 (en
Inventor
Alberto Stabile
Alberto Annovi
Luca FRONTINI
Valentino Liberali
Original Assignee
Istituto Nazionale Di Fisica Nucleare
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to IT102016000077445 priority Critical
Priority to IT102016000077445A priority patent/IT201600077445A1/en
Application filed by Istituto Nazionale Di Fisica Nucleare filed Critical Istituto Nazionale Di Fisica Nucleare
Publication of WO2018015839A2 publication Critical patent/WO2018015839A2/en
Publication of WO2018015839A3 publication Critical patent/WO2018015839A3/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/14Word line organisation; Word line lay-out

Abstract

A CAM memory (Content Addressable Memory) is described, comprising a plurality of memory cells (2), organized in rows and columns, adapted to store a plurality of data words, a plurality of bit lines (BL, BLN) for receiving the bits of a word to be stored, a plurality of write lines (WL, WLN) to enable writing of a sequence of memory cells, so as to store the bits present on the bit lines (BL, BLN), a plurality of search lines (SL, SLN) arranged in the column direction to transmit a word to be searched in the memory cells, a matching circuit to compare bits of the word to be searched with bits of the words stored in the memory cells. At least two of the write lines (WL0, WL1) are intertwined, so that on a same row of the CAM memory (10) are stored alternately bits of at least two different words. In this way, the length of the search lines and/ or of the bit lines can be reduced.
PCT/IB2017/054171 2016-07-22 2017-07-11 A cam memory WO2018015839A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT102016000077445 2016-07-22
IT102016000077445A IT201600077445A1 (en) 2016-07-22 2016-07-22 Memory cam

Publications (2)

Publication Number Publication Date
WO2018015839A2 WO2018015839A2 (en) 2018-01-25
WO2018015839A3 true WO2018015839A3 (en) 2018-04-12

Family

ID=58159177

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2017/054171 WO2018015839A2 (en) 2016-07-22 2017-07-11 A cam memory

Country Status (2)

Country Link
IT (1) IT201600077445A1 (en)
WO (1) WO2018015839A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040100830A1 (en) * 2002-11-22 2004-05-27 International Business Machines Corporation Cam cell with interdigitated search and bit lines
US7286379B1 (en) * 2005-09-08 2007-10-23 Lsi Corporation Content addressable memory (CAM) architecture and method of operating the same
US20090175064A1 (en) * 2007-12-25 2009-07-09 Elpida Memory, Inc. Semiconductor memory device with reduced coupling noise
US20130170273A1 (en) * 2011-12-29 2013-07-04 Lsi Corporation Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers
US8493763B1 (en) * 2011-10-27 2013-07-23 Netlogic Microsystems, Inc. Self-timed match line cascading in a partitioned content addressable memory array

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040100830A1 (en) * 2002-11-22 2004-05-27 International Business Machines Corporation Cam cell with interdigitated search and bit lines
US7286379B1 (en) * 2005-09-08 2007-10-23 Lsi Corporation Content addressable memory (CAM) architecture and method of operating the same
US20090175064A1 (en) * 2007-12-25 2009-07-09 Elpida Memory, Inc. Semiconductor memory device with reduced coupling noise
US8493763B1 (en) * 2011-10-27 2013-07-23 Netlogic Microsystems, Inc. Self-timed match line cascading in a partitioned content addressable memory array
US20130170273A1 (en) * 2011-12-29 2013-07-04 Lsi Corporation Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ANNOVI ALBERTO ET AL: "A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications", 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS), IEEE, 6 December 2015 (2015-12-06), pages 392 - 395, XP032884812, DOI: 10.1109/ICECS.2015.7440331 *
PAGIAMTZIS K ET AL: "A Low-Power Content-Addressable Memory (CAM) Using Pipelined Hierarchical Search Scheme", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 39, no. 9, 30 August 2004 (2004-08-30), pages 1512 - 1519, XP011117971, ISSN: 0018-9200, DOI: 10.1109/JSSC.2004.831433 *

Also Published As

Publication number Publication date
IT201600077445A1 (en) 2018-01-22
WO2018015839A2 (en) 2018-01-25

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