WO2018009154A1

WO2018009154A1 - Rram devices with extended switching layer and methods of fabrication

Info

Publication number: WO2018009154A1
Application number: PCT/US2016/040887
Authority: WO
Inventors: Ravi Pillarisetty; Elijah V. KARPOV; Uday Shah; Niloy Mukherjee; Prashant Majhi; Tejaswi K. Indukuri; James S. Clarke
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2016-07-02
Filing date: 2016-07-02
Publication date: 2018-01-11
Anticipated expiration: 2019-01-02

Abstract

Approaches for integrating a switching layer that is continuous across an array of RRAM (RRAM) cells and the resulting structures, are described. In an example, a RRAM (RRAM) cell includes an RRAM device coupled to a conductive interconnect disposed in a dielectric layer above the substrate. An RRAM device includes a bottom electrode coupled to an oxygen exchange layer and a top electrode through a switching layer. The switching layer physically extends over the dielectric layer and the bottom electrodes associated with all RRAM devices in a given array. A dielectric spacer film is disposed on the sidewalls of the memory device extending from a lowermost portion of the oxygen exchange layer to the uppermost portion of the top electrode.

Description

RRAM DEVICES WITH EXTENDED SWITCHING LAYER AND METHODS OF FABRICATION

TECHNICAL FIELD

Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, RRAM devices with extended switching layer and their methods of fabrication.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Non-volatile embedded memory with RRAM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of creating an appropriate stack for fabrication of RRAM devices that exhibit high device endurance, high retention and operability at low voltages and currents presents formidable roadblocks to commercialization of this technology today. Specifically, the objective of memory technology to control tail bit data in a large array of memory bits necessitates tighter control of the variations in metal oxide break down and switching events in individual bits. Furthermore, in filamentary RRAM systems, the latter is dictated by fine tuning oxygen vacancy concentration, which is widely understood to drive filament formation and dissolution in metal oxide films. As such, significant improvements are still needed in the area of metal oxide stack engineering, which rely on material advancements, deposition techniques or a combination of both. This area of process development is an integral part of the non-volatile memory roadmap.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell where a metal oxide switching layer is on a bottom electrode and on a portion of a dielectric layer surrounding the bottom electrode, in accordance with an embodiment of the present invention.

Figure IB illustrates a cross-sectional view of a pair of resistive random access memory (RRAM) cells where a metal oxide switching layer is continuous between the two RRAM cells, in accordance with an embodiment of the present invention.

Figure 1C illustrates a plan view of an array of RRAM cells of the type illustrated in Figure IB, in accordance with an embodiment of the present invention.

Figure ID illustrates a partial cross-sectional view of the array of RRAM cells illustrated in

Figure 1C, depicting an extended metal oxide switching layer across adjacent RRAM cells, in accordance with an embodiment of the present invention.

Figure 2A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell where an oxygen exchange layer and a top electrode are formed in an opening in a dielectric layer formed above an extended metal oxide switching layer disposed above a substrate, in accordance with an embodiment of the present invention.

Figure 2B illustrates a plan view of an array of RRAM cells of the type illustrated in Figure 2A, in accordance with an embodiment of the present invention.

Figure 2C illustrates a partial cross-sectional view of the array of RRAM cells illustrated in Figure 2B, depicting an extended metal oxide switching layer across adjacent RRAM cells, in accordance with an embodiment of the present invention.

Figures 3A-3M illustrate cross sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, in accordance with an embodiment of the present invention.

Figure 3A illustrates a conductive interconnect formed in a first dielectric layer above a substrate.

Figure 3B illustrates the structure of Figure 3 A following recessing of the conductive interconnect to a level below an uppermost surface of the first dielectric layer.

Figure 3C illustrates the structure of Figure 3B following formation of a bottom electrode layer on the recessed conductive interconnect and on the uppermost surface of the first dielectric layer.

Figure 3D illustrates the structure of Figure 3C following planarization of the bottom electrode layer and the first dielectric layer to form a bottom electrode.

Figure 3E illustrates the structure of Figure 3D following formation of a metal oxide switching layer, an oxygen exchange layer, and a top electrode layer for a resistive random access memory device formed on a conductive interconnect.

Figure 3F illustrates the structure of Figure 3E following formation of a dielectric hardmask layer on the material layer stack followed by formation of a resist pattern formed on the dielectric hardmask layer. Figure 3G illustrates the structure of Figure 3F following an etch process used to transfer the resist pattern into the dielectric hardmask layer to form a pattemed dielectric hardmask layer.

Figure 3H illustrates the structure of Figure 3G following the removal of the resist partem.

Figure 31 illustrates the structure of Figure 3H following an etch process used to transfer the pattern of the dielectric hardmask layer into the top electrode layer and subsequently into the oxygen exchange material to form a material layer stack above an extended metal oxide switching layer.

Figure 3 J illustrates the structure of Figure 31 following the formation of a dielectric spacer layer covering the dielectric hardmask layer, the material layer stack and the extended metal oxide switching layer.

Figure 3K illustrates the structure of Figure 3 J following an anisotropic plasma etch of the dielectric spacer layer to form a dielectric spacer.

Figure 3L illustrates the structure of Figure 3K following formation of a second dielectric material covering the dielectric hardmask layer, the dielectric spacer and the extended metal oxide switching layer.

Figure 3M illustrates the structure of Figure 3L following planarization of the second dielectric layer, the dielectric spacer, and a top portion of the top electrode.

Figures 4A-4H illustrate cross-sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, in accordance with an embodiment of the present invention.

Figure 4A illustrates a bottom electrode formed above a conductive interconnect formed in a first dielectric layer.

Figure 4B illustrates the structure of Figure 4A following formation an extended metal oxide switching layer formed on the uppermost surface of the bottom electrode and on the uppermost surface of the first dielectric layer.

Figure 4C illustrates the structure of Figure 4B following formation of a second dielectric layer formed above the extended metal oxide switching layer and a dielectric hardmask layer formed on the second dielectric layer.

Figure 4D illustrates the structure of Figure 4C following patterning of a photoresist material to form a mask to define a via location.

Figure 4E illustrates the structure of Figure 4D following patterning of the dielectric hardmask layer to form a dielectric hardmask layer, followed by removal of the mask.

Figure 4F illustrates the structure of Figure 4E following formation of a via in the second dielectric layer to expose the extended metal oxide switching layer. Figure 4G illustrates the structure of Figure 4F following formation of an oxygen exchange material in the via, on the extended metal oxide switching layer and along the sidewalls of the via, followed by a formation of a top electrode layer in the via and on the oxygen exchange material.

Figure 4H illustrates the structure of Figure 4G following a planarization process to form a top electrode and an oxygen exchange layer.

Figure 5A-5E illustrate cross-sectional views representing various operations in a method of fabricating a bottom electrode integrated on a conductive interconnect, in accordance with an embodiment of the present invention.

Figure 5A illustrates a conductive interconnect formed in an opening in a first dielectric layer above a substrate.

Figure 5B illustrates the structure of Figure 5 A following the formation of a bottom electrode layer on the uppermost surface of the conductive interconnect and on the uppermost surface of the first dielectric layer, followed by formation of a dielectric hardmask layer on the bottom electrode layer, and formation of a resist pattern on the dielectric hardmask layer.

Figure 5C illustrates the structure of Figure 5B following patterning of the dielectric hardmask layer to form a dielectric hardmask layer, followed by removal of the mask.

Figure 5D illustrates the structure of Figure 5C following an etch process used to transfer a partem of the dielectric hardmask layer into the bottom electrode layer to form a bottom electrode, followed by formation of a second dielectric layer over the dielectric hardmask layer.

Figure 5E illustrates the structure of Figure 5D following planarization of dielectric hardmask layer, a top portion of the bottom electrode and portions of the second dielectric layer.

Figure 6A illustrates an RRAM device formed above a conductive interconnect where a width of the conductive interconnect, a width of the bottom electrode and a width of the oxygen exchange layer are different from one another, in accordance with an embodiment of the present invention.

Figure 6B illustrates an RRAM device formed above a conductive interconnect where the center of the conductive interconnect, the center of the bottom electrode layer and the center of the oxygen exchange layer are not aligned vertically, in accordance with an embodiment of the present invention.

Figure 7A illustrates formation of a conductive filament in an extended metal oxide switching layer, near an edge of an oxygen exchange layer in accordance with an embodiment of the present invention.

Figure 7B illustrates formation of a conductive filament in an extended metal oxide switching layer, at or near the middle of the oxygen exchange layer in accordance with an embodiment of the present invention.

Figure 8 illustrates a cross-sectional view of a conventional RRAM device.

Figure 9 illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, in accordance with embodiments of the present invention.

Figure 10 illustrates a cross-sectional view of an RRAM element coupled to a drain side of a select transistor, in accordance with an embodiment of the present invention.

Figures 11 A-l IE illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention.

Figure 12 illustrates a schematic of a memory bit cell, which includes a metal-conductive oxide-metal RRAM device, in accordance with embodiments of the present invention.

Figure 13 illustrates a block diagram of an electronic system, in accordance with embodiments of the present invention.

Figure 14 illustrates a computing device in accordance with embodiments of the present invention.

Figure 15 illustrates an interposer in accordance with embodiments of the present invention. DESCRIPTION OF THE EMBODIMENTS

RRAM devices with extended switching layers and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

To provide context, integrating a memory array with low voltage logic circuitry, such as logic circuitry operational at a voltage less than or equal to 1 Volt, may be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Additionally, approaches to integrating an RRAM device onto a transistor to create embedded memory presents material challenges that have become far more formidable with scaling. As transistor operating voltages are scaled down in an effort to become energy efficient, RRAM memory devices that are connected in series with such transistors are also required to function at lower voltages and currents.

Figure 8 illustrates a cross-sectional view of a conventional RRAM device 800. The RRAM device 800 includes a top electrode 812, an oxygen exchange layer 810, a metal oxide switching layer 808, and a bottom electrode 806. The RRAM device 800 is above an interconnect 804 formed in a dielectric layer 802 above a substrate 800.

The metal oxide switching layer 810 of RRAM device 800 is a region where conductive filaments are formed in filamentary RRAM devices. The metal oxide switching layer may be subjected to etch degradation during the fabrication process. Specifically, edge regions of the metal oxide switching layer 810 may be vulnerable to etch damage. A high level of variability in the size, shape and location of the filament may result when the edges of the metal oxide switching layer are damaged, leading to variability in device performance. Such operational variability manifests in write voltage and write current variability leading to erroneous programming states of a device. In accordance with an embodiment of the present invention, a patterned metal oxide switching layer is replaced by an extended metal oxide switching layer connecting adjacent RRAM devices in an array. By forming an extended (e.g., non-patterned) metal oxide switching layer, device variability associated with etch damage at the edges of a metal oxide switching layer may be avoided.

In accordance with embodiments of the present invention, various examples of RRAM devices including an extended metal oxide switching layer are described in association with Figures 1A-1D and Figures 2A-2C.

In a first example, Figure 1 A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell where a metal oxide switching layer 108 is on a bottom electrode 106 and on a portion of a dielectric layer 102 surrounding the bottom electrode 106. The RRAM device 100 includes the bottom electrode 106 disposed above a conductive interconnect 104. The conductive interconnect 104 is recessed to provide a recess 107, and the bottom electrode 106 of the RRAM device 100 is included in the recess 107. The conductive interconnect 104 is disposed above a substrate 101. The metal oxide switching layer 108 is extended beyond an overlying oxygen exchange layer 110 and beyond a top electrode 1 12 disposed above the oxygen exchange layer 110. In an embodiment, the top electrode 1 12 and the oxygen exchange layer 1 10 have sidewalls. In one such embodiment, the width of the oxygen exchange layer 110, Woe, is greater than the width of the bottom electrode 106, Wbe. In an embodiment, the width of the oxygen exchange layer 110, Woe, is less than the width of the bottom electrode 106, Wbe.

A dielectric spacer 114 is disposed adjacent to the sidewalls of the oxygen exchange layer 1 10 and sidewalls of the top electrode 1 12, and on the metal oxide switching layer 108. The dielectric spacer 114 extends from the uppermost surface of the extended metal oxide switching layer 108 to an uppermost portion of the top electrode 112 and may be any suitable dielectric material such as but not limited to carbon doped silicon nitride or silicon nitride. In an embodiment, the dielectric material of the dielectric spacer 114 is a non-oxygen-containing material. In an embodiment, the dielectric spacer 1 14 has a thickness that ranges from 30-60nm. In an embodiment, the metal oxide switching layer 108 extends to an outermost perimeter of the dielectric spacer 1 14, as is shown in Figure 1 A. In other embodiments, the metal oxide switching layer 108 extends beyond the outermost perimeter of the dielectric spacer 114.

In an embodiment, the extended metal oxide switching layer 108 is a continuous metal oxide switching layer. For example, Figure IB illustrates a cross-sectional view of a pair of resistive random access memory (RRAM) cells where a metal oxide switching layer 108 is continuous between the RRAM cells. The metal oxide switching layer 108 is formed above a bottom electrode 106 of each of the RRAM cells and above a dielectric layer 102 separating the RRAM cells. A second dielectric layer 1 16 is disposed on the continuous metal oxide switching layer 108.

In an embodiment, the bottom electrode 106 includes a material such as but not limited to titanium nitride, tantalum, tantalum nitride, tungsten or ruthenium. In an embodiment, the bottom electrode 106 has a thickness in the range of 40 to 60 nanometers (nm). In an embodiment, the composition and thickness of the bottom electrode 106 are tuned to meet specific device attributes such as series resistance, programming voltage and current. In an embodiment, a portion of the bottom electrode 106 at an interface between the bottom electrode 106 and the metal oxide switching layer 108 is oxidized. In one such embodiment, the bottom electrode 106 includes tungsten or ruthenium and the oxidized portion of the bottom electrode 106 remains conductive. In an embodiment, the bottom electrode 106 has a width, Wbe, approximately equal to a width, Wd, of the conductive interconnect 104. In an embodiment, an uppermost surface of the bottom electrode 106 is coplanar or substantially coplanar with the uppermost surface of the dielectric layer 102.

In an embodiment, the metal oxide switching layer 108 is composed of a metal (M), such as but not limited to, hafnium, tantalum or titanium. In the case of titanium or hafnium, or tantalum with an oxidation state +4, the metal oxide switching layer 108 has a chemical composition, MOx, where O is oxygen and X is or is substantially close to 2. In the case of tantalum with an oxidation state +5, the metal oxide switching layer 108 has a chemical composition, IVhOx, where O is oxygen and X is or is substantially close to 5. In an embodiment, the metal oxide switching layer 108 has a thickness approximately in the range of 1 -5 nm. In an embodiment, metal oxide switching layer 108, is an example of a switching layer that includes a metal oxide.

In an embodiment, the oxygen exchange layer 110 acts as a source of oxygen vacancy or as a sink for O^2". In an embodiment the oxygen exchange layer 1 10 is composed of a metal such as but not limited to, hafnium, tantalum or titanium. In an embodiment, oxygen exchange layer 1 10 has a thickness in the range of 5-20nm. In an embodiment, the thickness of the oxygen exchange layer 110 is at least twice the thickness of the metal oxide switching layer 108. In another embodiment, the thickness of the oxygen exchange layer 1 10 is at least twice the thickness of the metal oxide switching layer 108.

In an embodiment, the top electrode 112 is composed of a material such as, but not limited to, titanium nitride, tantalum nitride, tungsten and ruthenium. In an embodiment, the bottom electrode 106 and the top electrode 112 are composed of the same material. In an embodiment, the top electrode 112 has a thickness approximately in the range of 30 to 100 nm. In an embodiment, the composition and thickness of the top electrode 112 are tuned to meet specific device attributes such as series resistance, programming voltage and current.

Figure 1C illustrates a plan view of an array of RRAM cells of the type illustrated in Figure IB, in accordance with an embodiment of the present invention. In an embodiment, an RRAM array may include 10³— 10^s RRAM cells. In an embodiment, electrical contact is made to the top electrode 1 12 of each RRAM device 100 through subsequent formation of conductive interconnects.

Figure ID illustrates a section of the array of RRAM cells illustrated in Figure 1 C, depicting a continuous metal oxide switching layer 108 across adjacent RRAM cells, in accordance with an embodiment of the present invention. In an embodiment, the metal oxide switching layer 108 is patterned near the boundary of the array during the fabrication process, yet is still referred to as a continuous layer.

Figure 2A illustrates a cross-sectional view of a resistive random access memory (RRAM) cell where an oxygen exchange layer 210 and a top electrode 212 are formed in an opening in a second dielectric layer 216. The second dielectric layer 216 is formed above a metal oxide switching layer 208 that is continuous, in accordance with an embodiment of the present invention. The RRAM cell includes an RRAM device 200 disposed on a conductive

interconnect 204, such as a conductive line or via, disposed in a first dielectric layer 202. The conductive interconnect 204 is recessed to provide a recess 207, and the bottom electrode 206 of the RRAM device 200 is included in the recess 207. The oxygen exchange layer 210 is disposed on the bottom electrode 206. The metal oxide switching layer 208 is disposed on the uppermost surface of the bottom electrode 206 and on the uppermost surface of the first dielectric layer 202.

In an embodiment, the bottom electrode 206 has a width, Wbe, approximately equal to a width, Woe, of the oxygen exchange layer 204. In an embodiment, an uppermost surface of the bottom electrode 206 is coplanar or substantially coplanar with the uppermost surface of the first dielectric layer 202. In an embodiment, the uppermost portion of the second dielectric layer 216, the oxygen exchange layer 210 and the top electrode 212 are coplanar or substantially coplanar with one another.

In an embodiment, the second dielectric layer 216 is a material that is is devoid of oxygen and serves to prevent oxygen diffusion into the laterally adjacent oxygen exchange layer 210. In an embodiment, the second dielectric layer 216 is composed of a material such as, but not limited to silicon nitride, carbon doped silicon nitride and silicon carbide. In an embodiment the width, Wto, of the top of the opening in the second dielectric layer 216 is greater than the width, Wbo, of the base of the opening. In an embodiment, the sidewalls of the opening are slanted by an angle of approximately 45 degrees with respect to a vertical axis of the opening. The width, Wbo, of the base of the opening may be larger or smaller than the width of the bottom electrode 106, Wbe. It is to be appreciated that, in an embodiment, the portion of the oxygen exchange layer 208 that is in contact with the bottom electrode 206 determines an effective device size. In an embodiment, the portion of the oxygen exchange layer 208 that is in contact with the uppermost surface of the bottom electrode 206 has a thickness that is greater than a thickness of portions of the oxygen exchange layer 208 disposed along the sidewalls of the second dielectric layer 216. In an embodiment, the width of the oxygen exchange layer, Woe, may not be identical to the width, Wbo, of the base of the opening.

Figure 2B illustrates a plan view of a sub-section of an array of RRAM cells of the type illustrated in Figure 2A, in accordance with an embodiment of the present invention. In an embodiment, an array of RRAM cells includes 10³— 10^s RRAM cells. In an embodiment, contact is made to the top electrode 212 of each RRAM device 200, subsequently through formation of interconnects. Each each RRAM device 200 is disposed in a dielectric 216 above a substrate 201. In contrast to the RRAM devices in the array illustrated in Figure 1C, RRAM devices 200 depicted in the array in Figure 2B expose an uppermost surface of both the top electrode 212 and the oxygen exchange layer 210. In contrast, only the top electrode component of the RRAM device 100 is exposed in the array depicted in Figure IB. In an embodiment, the uppermost portion of the oxygen exchange layer 210 adjacent to the dielectric layer 216 is oxidized during subsequent fabrication of the device. In one such embodiment, a portion of the oxygen exchange layer 210 that is in direct contact with the metal oxide switching layer 208 remains protected from any potential oxidation effects and, ultimately, dictates the functionality of the RRAM device.

Figure 2C illustrates a section of the array of RRAM cells illustrated in Figure 2B, depicting a continuous metal oxide switching layer 208 across adjacent RRAM cells, in accordance with an embodiment of the present invention. In an embodiment, the metal oxide switching layer 208 is patterned near the boundary of the array during a fabrication process, yet is still referred to as a continuous layer.

Figures 3A-3M illustrate cross sectional views representing various operations in a method of fabricating a resistive random access memory device integrated on a conductive interconnect, which may be used to fabricate a device of the type described in association with Figure 1A or Figure IB, in accordance with an embodiment of the present invention.

Figure 3A illustrates a cross-sectional view of a bottom electrode formed above a conductive interconnect, surrounded by a first dielectric layer 302 formed above a substrate 300. In an embodiment, one or more dielectric layers are included. First dielectric layer 302 may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiC ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The first dielectric layer 302 may include pores or air gaps to further reduce their dielectric constant. In an embodiment, the total thickness of first dielectric layer 302 may be in the range of 2000A - 3000A. The conductive interconnect 304 may be fabricated using dual damascene processing or subtractive etching. The first dielectric layer 302 has an uppermost surface substantially co- planar with an uppermost surface of the conductive interconnect 304. Figure 3B illustrates the structure of Figure 3 A following recessing of the conductive interconnect 304 to a level below an uppermost portion of the first dielectric layer 302 to form a recess 303.

In an embodiment, the recessing is performed by a combination of a dry and a wet etch processing. In an embodiment, the recess 303 has a depth approximately in the range of 30nm- 60nm. The recessing process may or may not recess all components of the conductive interconnect 304. For example, in an embodiment, a conductive fill material is recessed and a diffusion barrier layer is not recessed and extends above the recessed conductive fill material. In another embodiment, both a conductive fill material and a diffusion barrier layer are recessed.

Figure 3C illustrates the structure of Figure 3B following formation of a bottom electrode layer 305 on the recessed conductive interconnect 304 and on the uppermost surface of the first dielectric layer 302. In an embodiment the bottom electrode layer 305 includes a material deposited by a physical vapor deposition (PVD) process. In an embodiment, the bottom electrode layer 305 is a material having a composition and a thickness such as described above in association with the bottom electrode layer 305. The process of depositing the bottom electrode metal material 305 using PVD may include an in-situ sputter cleans to first remove any oxide residue from an uppermost surface of the conductive interconnect 304. In an embodiment, a gas containing Ar is used to energetically bombard the upper most surface of the conductive interconnect 304 to remove any native oxide.

Figure 3D illustrates the structure of Figure 3C following planarization of the bottom electrode layer 305 and the first dielectric layer 302 to form a bottom electrode 306. In an embodiment, the resulting uppermost surface of first dielectric layer 302 and bottom electrode 306 are coplanar or substantially coplanar. In an embodiment, the planarization is performed using a chemical mechanical process (CMP). To avoid dishing between adj acent bottom electrodes 306, the CMP process may include multiple processing operations. In an

embodiment, a first processing operation includes planarizing with a first slurry to remove bottom electrode layer 305. A subsequent, second process includes planarizing with a different, second slurry to polish a portion of the bottom electrode layer 305 and a portion of the first dielectric layer 302. In an embodiment, the bottom electrode 306 formed by a PVD process and subsequently polished, achieves a surface roughness of 1 nm or less. Reducing surface roughness of the bottom electrode 306 using a polishing process may offer advantages during cycling of an RRAM device as it may serve to reduce abrupt filament nucleation and hence lessen variation in cycling voltage in a large device array.

Figure 3E illustrates a sequential formation of a material layer stack including a metal oxide switching layer 308, an oxygen exchange layer 310 and a top electrode layer 312, on the uppermost surface of the bottom electrode 306 and on the uppermost surface of the first dielectric layer 302.

Referring again to Figure 3E, the metal oxide switching layer 308 is formed on the bottom electrode 306. In an embodiment, the metal oxide switching layer 308 is composed of a material having a composition and a thickness such as described above in association with the metal oxide switching material 108. In an embodiment, the metal oxide switching layer 308 is formed using an ALD process. The ALD process may be characterized by a slow and a highly controlled metal oxide deposition rate. The ALD process may also be highly uniform (e.g., approximately 0. lnm level variation). In an embodiment, a pre-clean of the surface of the bottom electrode 306 is performed immediately prior to deposition of the metal oxide switching layer 308. In another embodiment, the metal oxide switching layer 308 is formed using a PVD process. In an embodiment, a pre-clean of the surface of the bottom electrode 306 is performed using an Ar sputter clean immediately prior to deposition of the metal oxide switching layer 308.

Referring again to Figure 3E, the oxygen exchange layer 310 is formed on the metal oxide switching layer 308. In an embodiment, the oxygen exchange layer 310 is a material having a composition and a thickness such as described above in association with the oxygen exchange material 1 10. In an embodiment, the oxygen exchange layer 310 is formed using a PVD process. In one such embodiment, the metal oxide switching layer 308 and the oxygen exchange layer 310 are deposited sequentially in a same chamber or in a same tool without breaking vacuum.

Referring again to Figure 3E, the top electrode layer 312 is formed on the oxygen exchange material 310 . In an embodiment, the top electrode layer 312 is a material having a composition and a thickness such as described above in association with the top electrode 112. In an embodiment, the top electrode layer 312 is formed using a PVD process. In an

embodiment, the top electrode layer 312 and the oxygen exchange layer 310 are deposited sequentially in a same chamber or in a same tool without breaking vacuum. By doing so, the oxygen exchange layer 310 does not become oxidized. In an embodiment the top electrode layer 312 has a same composition as the bottom electrode 306.

Figure 3F illustrates a resist pattern 317 formed on a dielectric hardmask layer 314 formed on the structure of Figure 3E. In an embodiment, the dielectric hardmask layer 314 is devoid of oxygen to prevent oxidation of the oxygen exchange material 310 . In one embodiment, the dielectric hardmask layer 314 is a material such as, but not limited to, silicon nitride, silicon carbide or carbon-doped silicon nitride. In one embodiment, the dielectric hardmask layer 314 has a thickness approximately in the range of 50-100nm. The thickness of the dielectric hardmask layer 314 may be determined by patterning fidelity and subsequent processing tolerances, as will be discussed further below.

In an embodiment, the resist partem 317 has a shape that ultimately defines a shape of the top electrode layer 312 and the oxygen exchange layer 310 . In one embodiment, the resist partem 317 has rectangular shape or a circular shape. In one embodiment, the resist pattern 317 has a shortest width in the range of 20-100nm. resist pattern 317 may include one or more materials such as an anti-reflective coating (ARC), gap-fill and planarizing material in addition to or in place of a photoresist material. In one embodiment, the resist partem 317 is formed to a thickness sufficient to retain its profile during subsequent patterning of the dielectric hardmask layer 314 but not so thick as to prevent lithographic patterning into the smallest dimensions (e.g., critical dimensions) possible with photolithography processing.

Figure 3G illustrates the structure of Figure 3F following an etch process used to transfer the pattern of resist partem 317 into the dielectric hardmask layer 314. In an embodiment, an anisotropic plasma etch process is used to pattern dielectric hardmask layer 314 with selectivity to the resist pattern 317. In an embodiment, a selectivity of greater than 3 to 1 between photoresist material and dielectric hardmask layer 314 is achieved. It is to be appreciated that chemical etchants utilized in the plasma etch process may depend on the dielectric material being etched, and may include one or more of CH_xF_y, C , Ar, N2 and CF4. Sidewall angles of the patterned dielectric hardmask layer 314 may be tailored to vary from 85-90 degrees depending on the type of etch conditions employed.

Figure 3H illustrates the structure of Figure 31 following removal of the resist pattern 317 selectively to the dielectric hardmask layer 314. In an embodiment, the resist pattern 317 is removed using an ash process. The ash process may include use of a gas containing O2, H2/N2, etc. It is to be appreciated that polymeric films, which may result from the interaction between a photoresist material and etch byproducts during memory device etch, may adhere to the sidewall portions of an etched RRAM material stack. If portions of such polymeric layers have metallic components, device performance may be significantly degraded. As such, in one embodiment, the resist pattern 317 is removed prior to etching the top electrode layer 312 and the oxygen exchange layer 310 .

Figure 31 illustrates the structure of Figure 3H following an etch process used to transfer the dielectric hardmask pattern into the top electrode layer 312 and the oxygen exchange layer 310 . In one embodiment, etching of the top electrode layer 312 and the the oxygen exchange layer 310 is performed in a single introduction in an etch tool. However, different chemistries may be utilized in the etch recipes. In an embodiment, a TiN top electrode layer 312 is etched using a reactive ion etch with chemistry including Ar, CF4 and C12. In an embodiment, a hafnium-based oxygen exchange layer 310 is etched using BC13, C12, and Ar. In an

embodiment, where the oxygen exchange layer 310 and the metal oxide switching layer 308 include a same metal, such as Hf, a portion of the uppermost surface of the metal oxide switching layer 308 is removed while etching the oxygen exchange material 310 . In another embodiment, a Ta-based oxygen exchange layer 310 is patterned using a mixture of CHF_X, Ar, Ch containing chemistry. In an embodiment, a combination of high etch selectivity to an underlying metal oxide switching layer and a non-uniform etch leads to notching 307 in the oxygen exchange layer during the etching process (indicated by the dotted line shown in Figure 31).

Figure 3 J illustrates the structure of Figure 31 following the formation of a dielectric spacer layer 315 covering the dielectric hardmask layer 314, the material layer stack 320 and the extended metal oxide switching layer 308. In an embodiment, deposition of the dielectric spacer layer 315 is performed immediately post RRAM device etch, prior to breaking vacuum in the same tool or chamber used for the etch process. Such a procedure, known in the art as in-situ deposition, may hermetically seal the device and potentially decrease oxidation of the perimeter of the sensitive metal oxide switching layer 308. In an embodiment, the dielectric spacer layer 315 is a material such as, but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non-oxygen containing material. In an embodiment, the dielectric spacer layer 315 has a thickness approximately in the range of 20-50nm. In another embodiment, the RRAM device and the dielectric hardmask layer 314 have angled sidewalls between 80-90 degrees, and the dielectric spacer layer 315 is deposited to a thickness greater than 50nm.

Figure 3K illustrates the structure of Figure 3 J following an anisotropic plasma etch of the dielectric spacer layer 315 to form a dielectric spacer 316. In an embodiment, a silicon nitride or silicon oxynitride dielectric spacer 316 is reactive-ion etched utilizing a chemistry including Ar, O2, and a fluorocarbon such as but not limited to CHF3, CH2F2, or C4F8. In an embodiment, the resulting structure as depicted in Figure 3K has a vertical dielectric spacer 316 that extends from the top of the metal oxide switching layer 308 to the top of the dielectric hardmask layer 314. In an embodiment, the metal oxide switching layer 308 is preserved after etching of the dielectric spacer layer as depicted in Figure 3 J. The structure shown in connection with Figure IB illustrates the extended metal oxide switching layer 308 over the first dielectric layer 302. In an embodiment, by tuning the 02 content to approximately 10% of the total gas flow and controlling the ion energy of the spacer etch by reducing a substrate bias power to below 600W in a reactive ion etch chamber, the metal oxide switching layer 308 can be preserved. Enhanced 02 gas flow of greater than 5% of total gas mixture, serves to increase etch rate of the dielectric spacer relative to the metal oxide switching layer 308.

In another embodiment, the underlying metal oxide switching layer 308 over the first dielectric layer 302 is etched, but a portion of the metal oxide switching layer 308 under the dielectric spacer 316 and the oxygen exchange layer 310 is retained, and may result in a structure such as is depicted in Figure 1A. In an embodiment, a reduction in the C content in the etch, an increased etch bias power and a longer over etch time yields a vertical dielectric spacer 316 profile. In one such etch, any uncovered metal oxide switching layer is also effectively removed.

In a further embodiment, the underlying metal oxide switching layer 308 may extend outside of the perimeter of the dielectric spacer 316, but not be continuous between adjacent RRAM devices. In one such embodiment, a photresist is formed over the metal oxide switching layer 308, the dielectric spacer 316, the dielectric hardmask 314, followed by an etch of the oxide switching layer 308.

In an embodiment when the first dielectric layer 302 is exposed post etch of the metal oxide switching layer 308, a small but noticeable amount of recess 303 in the first dielectric layer 302 (indicated by the dotted line in Figure 3K) depending on the etch selectivity to the first dielectric layer 302,

Figure 3L illustrates the structure of Figure 3K following formation of a second dielectric layer 318 covering the dielectric hardmask layer 316, the dielectric spacer 316, the layer layer stack and the extended metal oxide switching layer. In an embodiment, the total thickness of dielectric layer 318 is in the range of 250-350 nm. Suitable materials for the second dielectric layer 318 may be the same as those described in association with the first dielectric layer 302. In an embodiment, a total thickness of the second dielectric layer 318 is approximately 2 to 2.5 times the combined height of the material layer stack 320 and the dielectric hardmask layer 314. In an embodiment, when the metal oxide switching material 108 extends approximately to the same lateral extent as the dielectric spacer 114 as depicted in Figure 1A, the second dielectric layer covers the material layer stack 120, the metal oxide switching layer 108 and the first dielectric layer 102.

Figure 3M illustrates the structure of Figure 3L following planarization of the second dielectric layer 318, the dielectric spacer 316, and an upper portion of the top electrode 312. In an embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. To avoid localized dishing between RRAM devices the CMP process may include multiple processes. In one embodiment, a first processing operation includes use of a first slurry to planarize the second dielectric layer 218, the dielectric hardmask layer 214 and a portion of the dielectric spacer layer 216. A second, different, slurry is used to polish a portion of the top electrode 212. The resulting structure may include uppermost portions of the second dielectric layer 218, the dielectric spacer layer 216 and the top electrode 212 that are co-planar with one another.

Figure 4A illustrates a bottom electrode formed above a conductive interconnect formed in a first dielectric layer 402 above a substrate 400. Bottom electrode may be fabricated in a manner similar to the conductive interconnect 204 described in association with Figure 3D.

Figure 4B illustrates the structure of Figure 4A following formation an extended metal oxide switching layer formed on the uppermost surface of the bottom electrode and on the uppermost surface of the first dielectric layer. Exemplary materials and deposition processes for the metal oxide switching layer are as described above in association with Figure 3E.

Figure 4C illustrates the structure of Figure 4B following formation of a second dielectric layer formed above the extended metal oxide switching layer 408 and a dielectric hardmask layer 412 formed on the second dielectric layer 410. In an embodiment, the second dielectric layer 410 is a material such as, but not limited to, silicon nitride, carbon doped nitride and silicon carbide. In an embodiment, the second dielectric layer 410 is devoid of oxygen. In an embodiment, the thickness of the second dielectric layer 410 is selected based on the width and height of the RRAM device to be fabricated. The thickness may be selected to account for an amount to be sacrificed during a CMP operation used at the end of an RRAM device structure fabrication process. Referring again to Figure 4C, in an embodiment, the dielectric hardmask layer 412 is devoid of oxygen. In one embodiment, the dielectric hardmask layer 412 is a material such as, but not limited to, silicon nitride, silicon carbide or carbon-doped silicon nitride. In one embodiment, the dielectric hardmask layer 412 has a thickness approximately in the range of 30-50nm. The thickness of the dielectric hardmask layer 412 may be determined by patterning fidelity and subsequent processing tolerances, as will be discussed further below. In an embodiment, the combination of material choices between the dielectric hardmask 412 and the underlying second dielectric layer 410 is such that the underlying second dielectric layer 410 acts as an etch stop.

Figure 4D illustrates the structure of Figure 4C following patterning of a photoresist material 414 to form a mask to define a via location. In an embodiment, the via 413 location is selected to ultimately overlap with least a portion of the bottom electrode.

Figure 4E illustrates the structure of Figure 4D following patterning of the dielectric hardmask layer 412 to form a dielectric hardmask layer 412, followed by removal of the mask 414. In an embodiment, the width of the top of the via 413 is wider than the bottom of the via. In one such embodiment, the via 413 has sloped sidewalls. In an embodiment, the sloped sidewalls have an angle between 45-60 degrees with respect to a vertical axis of the via 413. In one embodiment, the via 413 has a vertical profile. In an embodiment, the mask 414 is removed using a resist strip and cleans process. In one such embodiment, the resist strip is carried out before continuing the via formation into the second dielectric layer 410 to avoid exposing the metal oxide switching layer 408 to elements of the resist strip process.

Figure 4F illustrates the structure of Figure 4E following formation of a via in the second dielectric layer 410 to expose the extended metal oxide switching layer 408. In an embodiment, the width of the top of the via 413 is wider than the bottom of the via. In one such embodiment the via 413 has sloped sidewalls. In an embodiment, the sloped sidewalls have an angle between 45-60 degrees with respect to a vertical axis of the via 413. In an embodiment, the width, Wbo, of the bottom of the via 413 is approximately the same size as the width, Wbe, of the bottom electrode 406, under the metal oxide switching layer 408. In one embodiment, a central vertical axis of the via 413 is centered with a center of the bottom electrode 406. In another

embodiment, the central vertical axis of the via 413 is off-set with the center of the bottom electrode 406.

Figure 4G illustrates the structure of Figure 4F following formation of an oxygen exchange layer 411 in the via 413, on the extended metal oxide switching layer 408 and along the sidewalls of the via 413, followed by a formation of a top electrode layer 415 in the via 413 and on the oxygen exchange layer 411. It is to be appreciated that the RRAM device size may be determined by the overlap between the oxygen exchange layer 411 and the bottom electrode 406. In an embodiment, the oxygen exchange layer 411 is formed at the bottom of the via 413 on the extended metal oxide switching layer 408, along the sidewalls of the via 413, and on the uppermost surface of the second dielectric layer 410. In an embodiment, the oxygen exchange layer 411 has a thickness on the sidewalls that is less that the thickness on the bottom of the opening. Exemplary material compositions and deposition techniques for forming the extended oxygen exchange layer 411 may be as described above for the extended oxygen exchange layer 310 . In an embodiment, the top electrode layer 415 is formed on the oxygen exchange layer 411. In an embodiment, the top electrode layer 415 completely fills the via 413 and extends over the uppermost surface of the second dielectric layer 410. Exemplary material compositions and deposition techniques for forming the top electrode layer 415 may be as described above for the top electrode layer 312.

Figure 4H illustrates the structure of Figure 4G following a planarization process to form a top electrode 416 and an oxygen exchange layer 414. In an embodiment, the planarization process is a CMP process. In one such embodiment, the CMP process provides the top electrode 416 and the oxygen exchange layer 414 with uppermost surfaces co-planar with the uppermost surface of the second dielectric layer 410.

Figures 5A-5E illustrates cross-sectional views representing various operations in a method of fabricating a bottom electrode integrated on a conductive interconnect 504, in accordance with an embodiment of the present invention. In this way, a bottom electrode 506 may be fabricated to have a width, Wbe, independent of the size of an underlying conductive interconnect 504.

Figures 5A illustrates a conductive interconnect 504 formed in an opening in a first dielectric layer 502 above a substrate 500.

Figure 5B illustrates the structure of Figure 5A following the formation of a material layer stack including of a resist pattem 510, a dielectric hardmask layer 507 and a bottom electrode layer 506 formed on the conductive interconnect 504 and on the first dielectric layer 502. In an embodiment, the bottom electrode layer 506, the dielectric hardmask layer 507 and resist pattern 510 have compositions and thicknesses such as described above in association with the bottom electrode 306, the dielectric hardmask layer 308 and resist pattern 317, respectively. In an embodiment, the resist pattem 510 has a width, Wr, that is greater than the width, Wd, of the conductive interconnect 504. In another embodiment, the resist pattem 510 has a width, Wr, that is less than the width, Wd, of the conductive interconnect 504.

Figure 5C illustrates the structure of Figure 5B following an etch process used to transfer the resist pattern 510 into the dielectric hardmask layer 508 to form a dielectric hardmask layer 508. In an embodiment, the resist pattem 510 is subsequently removed by a resist strip process.

Figure 5D illustrates the structure of Figure 5C following an etch process used to transfer the pattern of the dielectric hardmask layer 508 into the bottom electrode layer 506 to form a bottom electrode 506. Subsequently, a second dielectric layer 510 is formed and covers the top and the sidewalls of the dielectric hardmask layer 508, the sidewalls of the bottom electrode 506 and an uppermost surface of the first dielectric layer 502.

Figure 5E illustrates the structure of Figure 5D following planarization of dielectric hardmask layer 508, a top portion of the bottom electrode 506 and the second dielectric layer 510. In an embodiment, an uppermost surface of the bottom electrode 506 and the second dielectric layer 510 are coplanar or substantially coplanar subsequent to planarization. Figures 6A illustrates an RRAM device formed on the structure of Figure 5E, in accordance with an embodiment of the present invention. In an embodiment, the width of an oxygen exchange layer 310 , Woe, is larger than the width of the bottom electrode 506, Wbe.

Figures 6B illustrates an RRAM device formed on the structure of Figure 5E, in accordance with an embodiment of the present invention. In an embodiment, the material layer stack 320 including the oxygen exchange layer 310 and the top electrode 312 has a center that is misaligned with a center of the bottom electrode 506.

Figure 7A illustrates a device of Figure IB following formation of a conductive filament 704 in an extended metal oxide switching layer 108, near an edge of an oxygen exchange layer 110, in accordance with an embodiment of the present invention. Figure 7B illustrates a device of Figure IB following formation of a conductive filament 704 in an extended metal oxide switching layer 108, approximately central to the oxygen exchange layer 110, in accordance with another embodiment of the present invention. In an embodiment, the filament is 2-5nm wide at its widest point and tapers to several monolayers wide at the tip. In an embodiment the filament is between 4-15% of the width of the RRAM device. Referring to both Figures 7 A and 7B, since the metal oxide switching layer 108 is extended or is continuous, the RRAM devices of Figures 7A and 7B can have the same or substantially the same switching behavior as one another regardless of the filament location. Methods of forming a filament 704 can be as described below in association with Figure 9.

In an embodiment, prior to filament formation the RRAM device depicted in Figures IB is annealed in a high temperature furnace at the end of the RRAM device fabrication process. In an embodiment, the anneal temperatures reach 400°C and lasts for a time period of 60 minutes. Annealing is a thermal phenomenon that serves to drive the O^2" from the extended metal oxide switching layer 108 in to the oxygen exchange layer 110 thus creating oxygen vacancies, V₀ in the extended metal oxide switching layer 108. In an embodiment, a conductive filament 704, composed of the oxygen vacancies, V₀, is formed in the metal oxide switching layer 108 during an application of a one-time high break down voltage applied between the top electrode 112 and bottom electrode 106. In embodiments of the present invention, an extended metal oxide switching layer 108 offers a non-degraded layer for a filament to form within the vicinity of the oxygen exchange layer 110 and the bottom electrode 106.

Figures 9 illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, depicted in Figure IB, in accordance with embodiments of the present invention. The initial operation of an RRAM device begins by gradually applying a voltage that is increasing in magnitude, between the top electrode 112 and the bottom electrode 106. In an "intentional" one-time breakdown process, known as forming, oxygen vacancies, V₀, are pumped in from the oxygen exchange layer 110 into the extended metal oxide switching layer 108 to augment the vacancies created during the anneal process described above. This leads to a formation of a "conductive" V₀ filament in the extended metal oxide switching layer 108 (point B). With a conductive filament bridging the top electrode 112 and the bottom electrode 106, the RRAM device is said to be almost immediately conductive and thus, in a low resistance state (point C). By sweeping the voltage between the top and bottom electrodes in a reversed direction (point C to D and then to F), causing a reversal of the electric field direction, the oxygen vacancies (technically positively charged ions) are now directed towards oxygen exchange layer 110 leading to a dissolution of the conductive filament in the extended metal oxide switching layer 108. Filament dissolution takes place at some critical voltage (point F), termed VReset, and the device returns to a high resistance state (point G). It is to be appreciated that the high resistance level of the RRAM device, point G, is different and lower in magnitude compared to the resistance level of the device before the onset of the forming process. By once again "sweeping" the voltage in the opposite direction, traversing from point G to H and then to point I in the I-V plot, the momentarily dissolved filament begins to manifests again under the action of vacancy migration. At some critical voltage, Vset, the filament completely bridges the top electrode 112 and the bottom electrode 106 and the device is once again said to be in a conductive mode or a low resistance state, point J. The cycling of the RRAM device in this manner, where the resistance levels remain unchanged about the 0 voltage point, leads to the effect of non-volatile memory. In other words, even with the voltage turned off, the resistance of the RRAM device is maintained to within a certain range. In an embodiment, when a device undergoes a read operation where a voltage, less than the switching voltage (Vset or VReset) is applied, the device exhibits a numerical resistance value approximately similar in value before the voltage is turned off. It is to be appreciated that the values Vset and VReset, generally refer to a portion of a voltage that is applied to a transistor in series with the RRAM element. The RRAM coupled with a transistor in this manner is given the term embedded memory.

Figure 10 illustrates a RRAM device 1004, formed on a conductive interconnect 1002 disposed in a via formed in a dielectric 1007 and integrated with a logic transistor 1030 disposed above a substrate 1005. RRAM device 1004 includes a bottom electrode 1006, a fully stoichiometric metal oxide switching layer 1008, a sub-stoichiometric metal oxide switching layer 1010 and a top electrode 1021. In one such embodiment, the RRAM device 1004 is a device such as described in association with Figure 1A. In one such embodiment, the RRAM device is disposed directly on a conductive interconnect coupled to a contact structure 1012 connected to the drain end 1020 of the transistor. In other embodiments, the RRAM device 1004 is a device such as described in association with Figure IB.

In an embodiment, the underlying semiconductor substrate 1005 represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, poly crystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other

semiconductor materials. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, transistors associated with substrate 1005 are metal-oxide- semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 1005. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include Fin- FET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, each MOS transistor 1030 of substrate 1005 includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer of each MOS transistor of substrate 1005 is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers 1040 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source 1050 and drain 1020 regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxial deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

To provide further context, integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Unfortunately, traditional charge-based memory technologies such as DRAM and NAND Flash are now facing severe scalability issues related to increasingly precise charge placement and sensing requirements. As such, embedding charge-based memory directly onto a high performance logic chip is not very attractive for future technology nodes. However, a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories is resistive random access memory (RRAM), since it relies on resistivity rather than charge as the information carrier. However, in order to exploit the potential benefits of a high performance logic chip with embedded RRAM memory, an appropriate integrated logic plus RRAM structure and fabrication method is needed.

Embodiments of the present invention include such structures and fabrication processes.

Relating to one or more embodiments described herein, it is to be appreciated that traditional DRAM memory is facing severe scaling issues and, so, other types of memory devices are being actively explored in the electronics industry. One future contender is RRAM devices. Embodiments described herein include a fabrication method for embedding RRAM bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.

In an aspect, an RRAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit. As examples, Figures 11 A-l IE illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention.

Referring to all Figures 11 A-l IE, in each case, a memory region 1100 and a logic region 1102 of an integrated circuit are depicted schematically. Each memory region 1100 includes a select transistor 1104 and overlying alternating metal lines and vias. Each logic region includes a plurality of transistors 1106 and overlying alternating metal lines and vias which can be used to connect the plurality of transistors 1106 into functional circuits, as is well known in the art.

Referring to Figure 11 A, an RRAM device 1120 is disposed between a lower conductive via 1122 and an upper conductive line 1124. In one embodiment, the lower conductive via 1122 is in electrical contact with a bottom electrode of the RRAM device 1120, and the upper conductive line 1124 is in electrical contact with a top electrode of the RRAM device 1120. In a specific embodiment, the lower conductive via 1122 is in direct contact with a bottom electrode of the RRAM device 1120, and the upper conductive line 1124 is in direct contact with a top electrode of the RRAM device 1120.

Referring to Figure 11B, an RRAM device 1130 is disposed between a lower conductive line 1132 and an upper conductive via 1134. In one embodiment, the lower conductive line 1132 is in electrical contact with a bottom electrode of the RRAM device 1130, and the upper conductive via 1134 is in electrical contact with a top electrode of the RRAM device 1130. In a specific embodiment, the lower conductive line 1132 is in direct contact with a bottom electrode of the RRAM device 1130, and the upper conductive via 1134 is in direct contact with a top electrode of the RRAM device 1130.

Referring to Figure 11C, an RRAM device 1140 is disposed between a lower conductive line 1142 and an upper conductive line 1144 without an intervening conductive via. In one embodiment, the lower conductive line 1142 is in electrical contact with a bottom electrode of the RRAM device 1140, and the upper conductive line 1144 is in electrical contact with a top electrode of the RRAM device 1140. In a specific embodiment, the lower conductive line 1142 is in direct contact with a bottom electrode of the RRAM device 1140, and the upper conductive line 1144 is in direct contact with a top electrode of the RRAM device 1140.

Referring to Figure 11D, an RRAM device 1150 is disposed between a lower conductive via 1152 and an upper conductive via 1154 without an intervening conductive line. In one embodiment, the lower conductive via 1152 is in electrical contact with a bottom electrode of the RRAM device 1150, and the upper conductive via 1154 is in electrical contact with a top electrode of the RRAM device 1150. In a specific embodiment, the lower conductive via 1152 is in direct contact with a bottom electrode of the RRAM device 1150, and the upper conductive via 1154 is in direct contact with a top electrode of the RRAM device 1150.

Referring to Figure 1 IE, an RRAM device 1160 is disposed between a lower conductive line 1162 and an upper conductive via 1164 in place of an intervening conductive line and conductive via pairing. In one embodiment, the lower conductive line 1162 is in electrical contact with a bottom electrode of the RRAM device 1160, and the upper conductive via 1164 is in electrical contact with a top electrode of the RRAM device 1160. In a specific embodiment, the lower conductive line 1162 is in direct contact with a bottom electrode of the RRAM device 1160, and the upper conductive via 1164 is in direct contact with a top electrode of the RRAM device 1160.

Referring to Figure 12, the RRAM memory device 1210 may include a bottom electrode 1212 with an extended metal oxide switching layer 1213 formed on the bottom electrode 1212. An oxygen exchange layer 1214 is formed on the extended metal oxide switching layer 1213. A top electrode 1216 is formed on the oxygen exchange layer 1214. The top electrode 1216 may be electrically connected to a bit line 1232. The bottom electrode 1212 may be coupled with a transistor 1234. The transistor 1234 may be coupled with a wordline 1236 and a source line 1238 in a manner that will be understood to those skilled in the art. The RRAM cell 1200 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the RRAM cell 1200. It is to be appreciated that a plurality of the RRAM cells 1200 may be operably connected to one another to form a memory array, wherein the memory array can be incorporated into a non-volatile memory region of a substrate in common with a logic region. It is to be appreciated that the nomenclature top and bottom refer to relative positioning of the metal electrodes with respect to the metal oxide switching layer. The transistor 1234 may be connected to top electrode 1216 although only connection to bottom electrode 1212 is shown.

Figure 13 illustrates a block diagram of an electronic system 1300, in accordance with an embodiment of the present invention. The electronic system 1300 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 1300 may include a microprocessor 1302 (having a processor 1304 and control unit 1306), a memory device 1308, and an input/output device 1310 (it is to be appreciated that the electronic system 1300 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 1300 has a set of instructions that define operations, which are to be performed on data by the processor 1304, as well as, other transactions between the processor 1304, the memory device 1308, and the input/output device 1310 . The control unit 1306 coordinates the operations of the processor 1304, the memory device 1308 and the input/output device 1310 by cycling through a set of operations that cause instructions to be retrieved from the memory device 1308 and executed. The memory device 1308 can include a memory element having a conductive oxide and electrode stack as described in the present description. In an embodiment, the memory device 1308 is embedded in the microprocessor 1302, as depicted in Figure 13. In an embodiment, the processor 1304, or another component of electronic system 1300, includes an array of RRAM devices.

Figure 14 illustrates a computing device 1400 in accordance with one embodiment of the invention. The computing device 1400 houses a motherboard 1402. The motherboard 1402 may include a number of components, including but not limited to a processor 1404 and at least one communication chip 1406. The processor 1404 is physically and electrically coupled to the motherboard 1402. In some implementations the at least one communication chip 1406 is also physically and electrically coupled to the motherboard 1402. In further implementations, the communication chip 1406 is part of the processsor 1404.

Depending on its applications, computing device 1400 may include other components that may or may not be physically and electrically coupled to the motherboard 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1406 enables wireless communications for the transfer of data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1406 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1406 also includes an integrated circuit die packaged within the communication chip 1406. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.

In further implementations, another component housed within the computing device 1400 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with

embodiments of the present invention.

In various implementations, the computing device 1400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1400 may be any other electronic device that processes data.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of RRAM memory arrays integrated into a logic processor. Such arrays may be used in an embedded non-volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memory (eDRAM). For example, such an array may be used for 1T-1R memory or 2T-1R memory (R = resistor) at competitive cell sizes within a given technology node.

Figure 15 illustrates an interposer 1500 that includes one or more embodiments of the invention. The interposer 1500 is an intervening substrate used to bridge a first substrate 1502 to a second substrate 1504. The first substrate 1502 may be, for instance, an integrated circuit die. The second substrate 1504 may be, for instance, a memory module, a computer

mothermotherboard, or another integrated circuit die. Generally, the purpose of an interposer 1500 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1500 may couple an integrated circuit die to a ball grid array (BGA) 1506 that can subsequently be coupled to the second substrate 1504. In some embodiments, the first and second substrates 1502/1504 are attached to opposing sides of the interposer 1500. In other embodiments, the first and second substrates 1502/1504 are attached to the same side of the interposer 1500. And in further embodiments, three or more substrates are interconnected by way of the interposer 1500.

The interposer 1500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 1508 and vias 1510, including but not limited to through-silicon vias (TSVs) 1510. The interposer 1500 may further include embedded devices 1514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1500. In accordance with

embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1500.

Thus, embodiments of the present invention include approaches for fabricating RRAM devices with extended switching layer and their methods of fabrication.

In an embodiment, a resistive random access (RRAM) memory cell includes a conductive interconnect disposed in an opening in a dielectric layer above the substrate and an RRAM device coupled to the conductive interconnect. The RRAM device includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. The bottom electrode has a sidewall and an upper portion coplanar with the dielectric layer. An extended metal oxide switching layer is disposed on the uppermost surface of the bottom electrode and on the dielectric layer. An oxygen exchange layer disposed on the extended metal oxide switching layer and a portion of the dielectric layer and a top electrode disposed on the oxygen exchange layer. The electrode and the oxygen exchange layer have sidewalls.

In one embodiment, the RRAM device includes a dielectric spacer film surrounding the sidewalls of the oxygen exchange layer and the top electrode. The dielectric film extends from a lowermost portion of the oxygen exchange layer to the uppermost portion of the top electrode In one embodiment, the metal oxide switching layer has a chemical composition, MC -x, where M is a metal and O is an oxide, where X is approximately in the range from 0 to 0.05. The metal oxide switching layer is a material selected from the group consisting of Hf02 and Zr02.

In one embodiment, the metal oxide switching layer is a continuous layer over the dielectric layer.

In one embodiment, the metal oxide switching layer extends over the dielectric layer and onto an upper most surface of a bottom electrode of an adjacent second RRAM device.

In one embodiment, the metal oxide switching layer has a thickness approximately in the range of 1-5 nanometers (nm) and the oxygen exchange layer has a thickness approximately in the range of 5-20 nm.

In one embodiment, the bottom electrode and the top electrode include a selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

In one embodiment, the bottom electrode and the top electrode are a same material, the material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

In an embodiment, a resistive random access memory cell includes a conductive interconnect disposed in a dielectric layer above the above the substrate and a resistive random access memory device coupled to the conductive interconnect. The RRAM device includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. The bottom electrode has a sidewall and an upper portion coplanar with the dielectric layer. A metal oxide switching layer is disposed on the uppermost surface of the bottom electrode and on the dielectric layer. An insulator is disposed on the metal oxide switching layer. The insulator has an opening with sidewalls and a bottom. An oxygen exchange layer is disposed in the opening on the metal oxide switching layer and along the sidewalls of the insulator and a top electrode is disposed in the opening on the metal oxide switching layer.

In one embodiment, the metal oxide switching layer has a chemical composition M02-X, where M is a metal and O is an oxide, where X is approximately in the range from 0 to 0.05.

In one embodiment, the metal oxides switching layer extends over the dielectric layer onto an uppermost surface of the bottom electrode middle layer of an adjacent second RRAM device.

In one embodiment, the metal oxide switching layer has a thickness approximately in the range of 1-5 nm and the oxygen exchange layer has a thickness approximately in the range of 5- 20 nm.

In one embodiment, the bottom electrode and the top electrode comprises a material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

In an embodiment, a method of fabricating resistive random access memory (RRAM) device, the method includes forming a conductive interconnect formed in an opening of dielectric layer above a substrate, forming a bottom electrode in the opening and on the conductive interconnect, forming a metal oxide switching layer on the bottom electrode and on the dielectric layer, forming an oxygen exchange layer on the metal oxide switching layer and forming a top electrode layer on the oxygen exchange layer.

In one embodiment, forming the RRAM device further include forming a dielectric hardmask layer on the top electrode, patterning the dielectric hardmask layer and using the dielectric hardmask layer as a mask to etch the top electrode and the oxygen exchange layer to form a patterned material layer stack having sidewalls.

In one embodiment, forming the RRAM device further includes forming a dielectric spacer surrounding the patterned material layer stack extends from the bottom electrode to the top of the dielectric hardmask layer.

In one embodiment, forming the RRAM device further includes forming an insulating dielectric layer on the the patterned material layer stack and on and along the sidewall of the dielectric spacer layer, and planarizing the insulating layer stack to form a coplanar upper most surface of the insulating dielectric layer, the dielectric spacer layer and the top electrode.

In one embodiment, forming the metal oxide switching layer includes depositing a metal film using an atomic layer deposition process or a physical vapor deposition process.

In one embodiment, the top electrode layer is formed on the oxygen exchange layer without an air break post deposition of the oxygen exchange layer.

In one embodiment, forming the RRAM device further includes forming a bottom electrode on the conductive interconnect. The bottom electrode has sidewalls adjacent to the dielectric layer and an uppermost surface coplanar with the uppermost surface of the dielectric layer. An insulating layer is formed above the bottom electrode and the dielectric layer, the insulating layer having an opening and sidewalls. A metal oxide switching layer is formed on the bottom electrode and on the dielectric layer. An oxygen exchange layer is formed in the opening, on the metal oxide switching layer and along the sidewalls of the insulating layer. Atop electrode is formed in the opening, on the metal oxide switching layer and planarized to expose coplanar insulating layer, the oxygen exchange layer and the top electrode surfaces.

Claims

CLAIMS What is claimed is:

1. An apparatus comprising:

a conductive interconnect disposed in a dielectric layer above the above the substrate; a resistive random access memory (RRAM) device coupled to the conductive interconnect, the resistive random access memory comprising:

a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer, the bottom electrode having a sidewall and an upper portion coplanar with the dielectric layer;

a switching layer including a metal oxide and disposed on an uppermost surface of the bottom electrode and on the dielectric layer;

an oxygen exchange layer disposed on the metal oxide switching layer and a portion of the dielectric layer; and

a top electrode disposed on the oxygen exchange layer, the top electrode and the oxygen exchange layer having sidewalls.

2. The apparatus of claim 1, wherein the RRAM device comprises a dielectric spacer film surrounding the sidewalls of the oxygen exchange layer and the top electrode, extending from a lowermost portion of the oxygen exchange layer to the uppermost portion of the top electrode.

3. The apparatus of claim 1, wherein the metal oxide switching layer has a chemical composition, MC -x, where M is a metal and O is an oxide, where X is approximately in the range from 0 to 0.05, further wherein the metal oxide switching layer comprises a material selected from the group consisting of HfC and ZrC .

4. The RRAM device of claim 1, wherein the metal oxide switching layer is a continuous layer over the dielectric layer.

5. The apparatus of claim 1, wherein the metal oxide switching layer extends over the dielectric layer onto an upper most surface of a bottom electrode of an adjacent second RRAM device.

6. The apparatus of claim 1, wherein the switching layer has a thickness approximately in the range of 1-5 nanometers and the oxygen exchange layer has a thickness approximately in the range of 5-20 nanometers.

7. The apparatus of claim 1, wherein the bottom electrode and the top electrode comprises a material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

8. The apparatus of claim 1, wherein the bottom electrode and the top electrode are a same material, the material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

9. A RRAM cell, comprising: a conductive interconnect disposed in a dielectric layer above the above the substrate; a RRAM device coupled to the conductive interconnect, the RRAM comprising:

a switching layer disposed on the uppermost surface of the bottom electrode and on the dielectric layer;

an insulator disposed on the switching layer; the insulator having an opening with sidewalls and a bottom;

an oxygen exchange layer disposed in the opening, on the switching layer and along the sidewalls of the insulator; and

a top electrode disposed in the opening on the switching layer.

10. The RRAM cell of claim 9, wherein the switching layer has a chemical composition, MO2- x, where M is a metal and O is an oxide, where X is approximately in the range from 0 to 0.05.

11. The RRAM cell of claim 9, wherein the switching layer is a continuous layer over the dielectric layer.

12. The RRAM cell of claim 9, wherein the switching layer extends over the dielectric layer onto an upper most surface of a bottom electrode of an adjacent second RRAM device.

13. The RRAM cell of claim 9, wherein the switching layer has a thickness approximately in the range of 1-5 nanometers and the oxygen exchange layer has a thickness approximately in the range of 5-20 nanometers.

14. The RRAM cell of claim 9, wherein the bottom electrode and the top electrode comprises a material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

15. The RRAM device of claim 9, wherein the bottom electrode and the top electrode are a same material, the material selected from the group consisting of titanium nitride, tantalum nitride, tungsten and ruthenium.

16. A method of fabricating RRAM device, the method comprising:

forming a conductive interconnect in an opening of dielectric layer above a substrate; forming a bottom electrode in the opening and on the conductive interconnect;

forming a switching layer on the bottom electrode and on the dielectric layer;

forming an oxygen exchange layer on the switching layer; and

forming a top electrode layer on the oxygen exchange layer.

17. The method of claim 16, wherein, forming the RRAM device further comprises:

forming a dielectric hardmask layer on the top electrode;

patterning the dielectric hardmask layer; and

using the dielectric hardmask layer as a mask to etch the top electrode and the oxygen exchange layer to form a patterned material layer stack having sidewalls.

18. The method of claim 17, wherein forming the RRAM device further comprises forming a dielectric spacer surrounding the patterned material layer stack, wherein the dielectric spacer extends from the bottom electrode to the top of the dielectric hardmask layer.

19. The method of claim 18, wherein forming the RRAM device further comprises forming an insulating dielectric layer on the the patterned material layer stack and on and along the sidewall of the dielectric spacer layer, and planarizing the insulating layer stack to form a coplanar upper most surface comprising of the insulating dielectric layer, the dielectric spacer layer and the top electrode.

20. The method of claim 16, wherein forming the switching layer comprises depositing a metal film using an atomic layer deposition process or a physical vapor deposition process.

21. The method of claim 16, wherein the top electrode layer is formed on the oxygen exchange layer without an air break post deposition of the oxygen exchange layer.

22. The method of claim 16, wherein forming the RRAM device further comprises:

forming a bottom electrode on the conductive interconnect, the bottom electrode having sidewalls adjacent to the dielectric layer and an uppermost surface coplanar with the uppermost surface of the dielectric layer;

forming an insulating layer above the bottom electrode and the dielectric layer, the insulating layer having an opening and sidewalls;

Forming a switching layer on the bottom electrode and on the dielectric layer;

forming an oxygen exchange layer in the opening, on the switching layer and along the sidewalls of the insulating layer;

forming a top electrode in the opening, on the switching layer; and

planarizing to expose a coplanar surface comprising of the insulating layer, the oxygen exchange layer and the top electrode.