WO2017222918A1

WO2017222918A1 - Chip package assembly having conformal lid

Info

Publication number: WO2017222918A1
Application number: PCT/US2017/037784
Authority: WO
Inventors: Jaspreet Singh Gandhi
Original assignee: Xilinx Inc
Current assignee: Xilinx Inc
Priority date: 2016-06-24
Filing date: 2017-06-15
Publication date: 2017-12-28
Anticipated expiration: 2018-12-24
Also published as: US10236229B2; US20170372979A1

Abstract

A chip package assembly and method for fabricating the same are provided which utilize a conformal lid (150, 450) to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid (250, 450). The packaging substrate has a die receiving area (120) that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate (150). The lid (150, 450) a surface that includes a first region (254) and a second region. The first region (254) is disposed over the first IC die (110) while the second region (258) of the lid (150, 450) extends below the second surface the first IC die (110) and is spaced above the packaging substrate (150). At least a portion of the second region (258) of the lid (150, 450) is overlapped with the die receiving area (120).

Description

CHIP PACKAGE ASSEMBLY HAVING CONFORMAL LID

TECHNICAL FIELD

Embodiments of the present invention generally relate to a chip package assembly, and in particular, to chip package assembly comprising at least integrated circuit (IC) die disposed on a package substrate or interposer, and a conformal lid.

BACKGROUND

Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. Conventional chip packaging schemes often utilize a package substrate, often in conjunction with a through-silicon-via (TSV) interposer, to enable a plurality of integrated circuit (IC) dies to be mounted to a single package substrate. The IC dies may include memory, logic or other IC devices.

Out of plane deformation of the package substrate, i.e., warpage, can be problematic to conventional chip packaging schemes. Warpage is particularly problematic in conventional chip packaging schemes that have an asymmetrical die distribution about at least one of the horizontal axes. Such warpage or bending of the package substrate can lead to solder connection failure or other damage to the components and devices of the chip package assembly, which may detrimentally effect device performance and reliability.

In many instances, dummy dies are utilized to stiffen the package substrate against out of plane deformation. The use of dummy dies is particularly common on chip packages that integrate high band-width memory (HBM) with field programmable gate arrays (FPGA). However, dummy dies undesirably increase the cost of the chip package. Additionally, die attach films often utilized to attach the dummy dies to an underlying substrate typically have high coefficients of thermal expansion (CTE), which undesirably contributes to delamination and crack initiation.

Therefore, a need exists for an improved chip package assembly, and in particular, to a chip package assembly having a conformal lid. SUMMARY

A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes a first and second integrated circuit (IC) dies, a packaging substrate, and a lid. Each IC die has a first surface and a second surface that faces way from the first surface. The packaging substrate has a first surface having a die receiving area surrounded by a ring shaped border. The die receiving area is defined by the laterally outermost extents of the IC dies mounted to the first surface of the packaging substrate. The lid has a first surface and a second surface that faces away from the first surface. The second surface of the lid has a first region and a second region. The first region is disposed over the first IC die, while the second region of the lid extends below the first surface the first IC die and is spaced above the first surface of the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area.

Optionally, the second surface of the lid further may further include a mounting region circumscribing the first and second regions. The mounting region may be disposed farther from the first surface of the lid than the second region and the mounting region may be bonded to the first surface of the packaging substrate.

Optionally, the chip package assembly may further include a ring shaped stiffener having a first side bonded to the second surface of the packaging substrate and a second side coupled the second surface of the lid.

Optionally, the chip package assembly may further include a thermal interface material conductively coupling the first region of the lid to the first surface of the first IC die.

Optionally, the chip package assembly may further include a thermal interface material conductively coupling the second region of the lid to the first surface of the packaging substrate within the die receiving area.

Optionally, the packaging substrate may be a package substrate adapted for coupling to a printed circuit board (PCB).

Optionally, the packaging substrate may be an interposer mounted to a package substrate. Optionally, the second surface of the lid may further include a third region separated from the second region by the first region. The third region of the lid may extend below the first surface the first IC die and may be spaced above the first surface of the packaging substrate. At least a portion of the third region of the lid may be overlapped with the die receiving area.

Optionally, the second surface of the lid may further include a mounting region circumscribing the first, second and third regions. The mounting region may be disposed farther from the first surface of the lid than the second region and the mounting region may be connected to the first surface of the packaging substrate.

Optionally, the chip package assembly may further include a ring shaped stiffener connecting the second surface of the packaging substrate to the mounting region of the lid.

Optionally, the chip package assembly may further include a package substrate having first side and a second side. The package substrate may have the packaging substrate mounted to first side of the package substrate. The second side of the package substrate may be configured for coupling to a printed circuit board thereto and the lid may be coupled to the package substrate outward of the packaging substrate.

In another example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a second IC die, a package substrate, an interposer and a lid. Each of the first and second IC dies has a first surface and a second surface that faces way from the first surface. The interposer has a first surface and a second surface. The second surface of the interposer is coupled to the package substrate. The first surface of the interposer has the first IC die and second IC die mounted thereto. The first surface of the interposer has a die receiving area surrounded by a ring shaped border, wherein the die receiving area is defined by the laterally outermost extents of the IC dies mounted to the first surface of the interposer. The lid has a first surface and a second surface that faces away from the first surface. The second surface of the lid has a first region, a second region and a mounting region. The first region is disposed over the first IC die. The second region of the lid extends below the first surface the first IC die and is spaced above the first surface of the packaging substrate. At least a portion of the second region of the lid is overlapped with the die receiving area. The mounting region circumscribes the first and second regions, and is structurally connected to the first surface of the package substrate.

Optionally, the chip package assembly may further include a ring shaped stiffener structurally connecting the mounting region of the lid to the package substrate.

Optionally, the chip package assembly may further include a thermal interface material conductively coupling the second region of the lid to the first surface of the interposer within the die receiving area.

Optionally, the second surface of the lid may further include a third region separated from the second region by the first region. The third region of the lid may extend below the first surface the first IC die and may be spaced above the first surface of the interposer. At least a portion of the third region of the lid may overlapped with the die receiving area.

In another example, a chip package assembly is provided that includes a plurality of integrated circuit (IC) dies, a package substrate, an interposer and a lid. Each of the IC dies has a first surface and a second surface that faces way from the first surface. The interposer has a first surface and a second surface. The second surface of the interposer is coupled to the package substrate. The first surface of the interposer has at least a first IC die and a second IC die of the plurality of IC dies mounted thereon. The lid includes first surface and a second surface that faces away from the first surface. The second surface of the lid has a first region, a second region, a third region and a mounting region. The first region is disposed vertically above at least the first IC die and separates the second region from the third region. The second and third regions of the lid extend below the first surface the first IC die and are spaced vertically above the first surface of the interposer. At least a portion of the second and third regions of the lid laterally overlap the interposer. The mounting region circumscribes the first, second and third regions laterally outward of the interposer. The mounting region is structurally connected to the package substrate. Optionally, the chip package assembly may further include a ring shaped stiffener structurally connecting the mounting region of the lid to the package substrate.

Optionally, the chip package assembly may further include a first thermal interface material conductively coupling the first region of the lid to the first surface of the first IC die and a second thermal interface material conductively coupling the second region of the lid to the first surface of the interposer.

Optionally, the mounting region of the lid may be spaced further from the first surface of the lid than the first, second and third regions. The mounting region may bound the interposer and may be bonded to the package substrate.

In another example, a method for fabricating a chip package assembly is provided that includes attaching a lid to a packaging substrate, wherein at least a first region of the lid is thermally connected directly to one or more IC dies by thermal interface material and at least a second region of the lid is thermally connected directly to an interposer by thermal interface material.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

Figure 1 is a schematic top view of a chip package assembly having a conformal lid removed to revile an exemplary geometric arrangement of integrated circuit (IC) dies.

Figure 2 is a schematic sectional view of the chip package assembly of

Figure 1 taken along section line 2- -2 and passing through the conformal lid.

Figure 3 is a schematic sectional view of the chip package assembly of

Figure 1 taken along section line 3- -3 and passing through the conformal lid.

Figure 4 is a schematic sectional view of another chip package assembly having a conformal lid. Figure 5 is an operation diagram of one example of a method for forming a chip package assembly having a conformal lid.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments.

DETAILED DESCRIPTION

A chip package assembly and method for fabricating the same are provided which utilize a conformal lid. The chip package assembly described herein includes at least one integrated circuit (IC) die and conformal lid disposed on a packaging substrate. The surface of the lid facing the packaging substrate is "conformal" to the topography of the dies across a die receiving area of the packaging substrate, thereby substantially eliminating the need and associated cost for dummy dies within the die receiving area to reduce susceptibility of the chip package assembly to out of plane deformation during the fabrication and use of the chip package assembly. Advantageously, the enhanced stiffness of the chip package assembly improves reliability and performance. Furthermore, the conformal lid enhances heat transfer across the entire the die receiving area of the packaging substrate, thereby reducing hot spots directly over IC dies which could induce warpage or provide insufficient temperature control of the IC dies.

Turning now to Figure 1 , a schematic top view of an exemplary chip package assembly 100 having a conformal lid removed to revile an exemplary geometric arrangement of integrated circuit (IC) dies is schematically illustrated. The conformal lid (250) is illustrated in Figures 2-3, and is described in detail below. Although two IC dies 1 14 and three IC dies 1 10 are shown in Figure 1 , the total number of IC dies may range from two to as many as can be fit within the chip package assembly 100. Examples of IC dies 1 10, 1 14 that may be utilized in the chip package assembly 100 include, but are not limited to, programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, such as high band-width memory (HBM), optical devices, processors or other IC logic structures. One or more of the IC dies 1 10, 1 14 may optionally include optical devices such as photo-detectors, lasers, optical sources, and the like. In the example depicted in Figure 1 , the IC dies 1 10 are field programmable gate arrays (FPGA) while the IC dies 1 14 are high bandwidth memory (HBM) dies. It is contemplated that the IC dies comprising the chip package assembly 100 may be the same or different types, including types other than HBM and FPGA dies.

In the top view of Figure 1 , the IC dies 1 10, 1 14 are oriented in an arrangement that is asymmetrical about at least one direction or axis in the horizontal plane. For example, as all the IC dies 1 10 are positioned to the right of the IC dies 1 14, the arrangement of dies is asymmetrical about a vertical axis while being symmetrical about a horizontal axis, the vertical extending between the top and bottom of the illustration of Figure 1 . In alternative embodiments, the arrangement of IC dies 1 10, 1 14 may be asymmetrical or symmetrical about both axes, or have another arrangement.

The chip package assembly 100 includes a packaging substrate 150 on which the IC dies 1 10, 1 14 are mounted. The packaging substrate 150 is generically utilized to mean either: (1 ) a package substrate 122 when the IC dies are directly coupled thereto without an intervening substrate (i.e., an interposer); or (2) an interposer 1 12 disposed on a first surface 102 of a package substrate 122 when the IC dies are directly coupled to the interposer 1 12. The interposer 1 12, when utilized, may include a substrate having through-substrate vias (TSV) supporting a metalization interconnect layer, or a substrate-less interposer having only a metalization interconnect layer without the use of TSVs. Although in the embodiment depicted in Figure 1 the packaging substrate 150 is depicted as the interposer 1 12, the associated description of the dies and lid interfacing with the interposer 1 12 is substantially identical for the dies and lid interfacing with the package substrate 122 when the packaging substrate 150 is solely the package substrate 122 without use of an intervening interposer.

Referring additionally to sectional view of Figure 2, the interposer 1 12 includes a first surface 106 and a second surface 290 connected by a sidewall such that the first and second surfaces 106, 290 face opposite directions. A first surface 220 of the IC dies 1 10, 1 14 faces away from the interposer 1 12, while a second surface 222 of the IC dies 1 10, 1 14 faces and is mounted to the first surface 106 of the interposer 1 12. The first surface 106 of the interposer 1 12 facing the second surface 222 of the IC dies 1 10, 1 14 has an IC die receiving area 120 that is optionally circumscribed by a boundary area 126. The boundary area 126 may be ring shaped, such as a rectangular or square ring. The die receiving area 120 is defined by outermost edges (108_L, 108_R, 108_T, 108_B) the IC dies 1 10, 1 14 (when considered as a single group of dies) mounted to the first surface 106 of the packaging substrate 150 extended to intersect at right angles, as illustrated by a dashed imaginary line 108. A portion of the dashed imaginary line 108 is hidden by the die edges 108_L, 108_R, 108_T, 108_B in the illustration of Figure 1 as they are linearly aligned.

The die receiving area 120 generally has regions covered by the IC dies 1 10, 1 14 and regions that are not covered by the IC dies 1 10, 1 14. The regions that are not covered by the IC dies 1 10, 1 14 are referred to as free regions 124. The free regions 124 may be large enough to mount a die thereto. In

conventional chip package assemblies, at least a portion of the free regions would be utilized to mount dummy dies. The number of free regions 124 may vary with specific packaging schemes, for example from 1 to many. In the example depicted in Figure 1 , the first surface 106 of the interposer 1 12 includes multiple free regions 124 that are separated by at least one IC die, such as both IC dies 1 10.

Referring now primarily to Figures 2 and 3, interposer 1 12 includes circuitry for electrically connecting the IC dies 1 10, 1 14 to circuitry of the package substrate 122. The circuitry of the interposer 1 12 may optionally include transistors and/or other circuit elements. Package bumps 214, also known as "C4 bumps," are utilized to provide an electrical connection between the circuitry of the interposer 1 12 and the circuitry of the package substrate 122. A second surface 204 of the package substrate 122 may be mounted and connected to a first surface 206 of a printed circuit board (PCB) 202, utilizing solder balls 208, wire bonding or other suitable technique.

As discussed above, the IC dies 1 10, 1 14 are mounted to the first surface 106 of the interposer 1 12, or alternatively in implementations wherein an interposer is not utilized, to the first surface 102 of the package substrate 122. In the example depicted in Figures 2-3, the IC dies 1 10, 1 14 are mounted to the first surface 106 of the interposer 1 12 by a plurality of micro-bumps 218. The micro-bumps 218 electrically connect the circuitry of each IC die 1 10, 1 14 to circuitry of the interposer 1 12. The circuitry of the interposer 1 12 connects the micro-bumps 218 to selective package bumps 214, and hence, connects selective circuitry of each IC die 1 10, 1 14 to the package substrate 122, to enable communication of the IC dies 1 10, 1 14 with the PCB 202 after the chip package assembly 100 is mounted within an electronic device (not shown). When the optional interposer 1 12 is not present, the micro-bumps 218 connects selective circuitry of each IC die 1 10, 1 14 to the package substrate 122 to enable communication of the IC dies 1 10, 1 14 with the PCB 202. An undermolding 212 may be utilized to fill the space not taken by the micro-bumps 218 between the IC dies 1 10, 1 14 and interposer 1 12. An undermolding 210 may be utilized to fill the space not taken by the package bumps 214 between the package substrate 122 and interposer 1 12.

The conformal lid 250 is disposed over the IC dies 1 10, 1 14. In some implementations, the lid 250 may be fabricated from a plastic material or other suitable material. In other implementations particularly where it is desirable to utilize the lid 250 to receive heat from the IC dies 1 10, 1 14, the lid 250 may be fabricated from a thermally conductive material, such as stainless steel, copper, nickel-plated copper or aluminum, among other suitable materials. In the region of the lid 250 directly over the IC dies 1 10, 1 14, the lid 250 may have a thickness of between about 0.5 mm and about 3.0 mm, although other thicknesses may be utilized. A heat sink, not shown, may optionally be mounted to a first surface 252 of the lid 250.

The lid 250 may be structurally coupled to the package substrate 122 to increase the rigidity of the chip package assembly 100. For example, a second surface 248 of the lid 250 that faces way from the first surface 252 may be coupled to the first surface 102 of the package substrate 122 by an adhesive (not shown), such as an epoxy. Optionally, a separate stiffener, shown in phantom by reference numeral 262, may be utilized to structurally couple the lid 250 to the package substrate 122. When used, the stiffener 262 may be made of ceramic, metal or other various inorganic materials, such as aluminum oxide (Al₂0₃), aluminum nitride (AIN), silicon nitride (SiN), silicon (Si), copper (Cu), aluminum (Al), and stainless steel, among other materials. The stiffener 262 can also be made of organic materials such as copper-clad laminate.

The second surface 248 of the lid 250 includes at least three discreet regions. A first region 254 is generally configured to align over the IC dies 1 10, 1 14 mounted in the die receiving area 120 of the first surface 106 of the interposer 1 12. The lid 250 is generally thinnest at the first region 254. A second region 258 is disposed immediately adjacent the first region 254. The second region 258 is generally configured to align over at least a portion of the free region 124 of the die receiving area 120. The surface of the second region 258 generally extends further away from the first surface 252 of the lid 250 than the first region 254. In one example, the second region 258 extends far enough from the first surface 252 of the lid 250 to overlap the IC dies 1 10, 1 14 when the lid 250 is mounted to the package substrate 122. Stated differently, the second region 258 of the lid 250 extends below the first surface 220 the IC dies 1 10, 1 14. As such, the lid 250 is thicker at the second region 258 relative a thickness of the lid 250 at the first region 254. A mounting region 260 of the lid 250 is disposed outward of, and circumscribes the first and second regions 254, 258. The mounting region 260 is also generally outward of the interposer 1 12. The mounting region 260 generally extends further away from the first surface 252 of the lid 250 than the second region 258 to enable the lid 250 to be mounted over the interposer 1 12 and structurally couple to the package substrate 122. As such, the lid 250 is thicker at the mounting region 260 relative a thickness of the lid 250 at the second region 258. In embodiments wherein a stiffener is utilized, the mounting region 260 may be simply configured to effectively couple to the stiffener in a position laterally outward of the interposer 1 12.

The stepped second surface 248 of the lid 250 created by the regions 254, 258, 260 significantly increases the resistance of the lid 250 to out of plane deformation. Consequently, the chip package assembly 100 is also significantly stiffer and resistant to warpage compared to conventional flat lids, making for more robust and dependable solder connections, along with enhancing performance and reliability of the IC dies 1 10, 1 14 comprising the chip package assembly 100.

A thermal interface material (TIM) 256 may be utilized to couple the first region 254 of the lid 250 to the IC dies 1 10, 1 14. The TIM 256 may be selected to provide a thermally conductive path between the lid 250 to the IC dies 1 10, 1 14 so that heat generated by the IC dies 1 10, 1 14 may be efficiently dissipated through the lid 250. The TI M 256 may be a soft or compliant adhesive to allow compensation between mismatched heights of neighboring IC dies 1 14 within the chip package assembly 100. In one example, the TIM 256 may be a thermal gel or thermal epoxy, such as for example, packaging component attach adhesives available from Al Technology, Inc. , located in Princeton Junction, New Jersey.

Advantageously, the thicker second region 258 of the lid 250 also functions as a heat sink for the adjacent thinner first region 254 of the lid 250. Thus, heat transferring from the IC dies 1 10, 1 14 to the first region 254 of the lid 250 is effectively and rapidly spread outward into the thicker second region 258, thereby reducing the potential of unwanted hot spots on the lid 250, which further enhances the performance and reliability of function the IC dies 1 10, 1 14 comprising the chip package assembly 100.

Additionally, as the second region 258 of the lid 250 extends beyond the IC dies 1 10, 1 14 to a position closely spaced from the interposer 1 12, a thermal interface material (TIM) 264 may be utilized to couple the second region 258 of the lid 250 to the free region 124 of the die receiving area 120 defined on the first surface 106 of the interposer 1 12. The TIM 264 may be selected to provide a thermally conductive path between the lid 250 to the interposer 1 12, so that heat generated by the IC dies 1 10, 1 14 and transferred to the adjoining regions of the interposer 1 12 may be advantageously dissipated through the lid 250. The TIM 264 may be the same or substantially equivalent material to the TIM 256 described above.

Figure 4 is a schematic sectional view of another chip package assembly 400 having a conformal lid 450. The chip package assembly 400 is substantially identical to the chip package assembly 100 described above except wherein the middle IC die 1 10 is removed so that the first surface 106 of the interposer 1 12 includes at least one free region 124 that separates at least two IC dies, such as the IC dies 1 10. The first surface 106 of the interposer 1 12 may also include multiple free regions 124. For example portions of the lid 450 may be configured similar to the lid 250 as shown in Figure 2, wherein the first surface 106 of the interposer 1 12 includes free regions 124 separated by at least one IC die.

In the configuration illustrated in Figure 4, the lid 450 includes multiple second regions 258 that at least partially align with the free region 124 of the die receiving area 120. The lid 450 may including one first region 254 disposed between at least two second regions 258. The first and second regions 254, 258 are utilized to stiffen the lid and enhance heat transfer using TIMs 256, 264 as described above.

Figure 5 is an operation diagram of one example of a method 500 for forming a chip package assembly 100 having conformal lid. The method 500 begins at operation 502 by connecting a plurality of IC dies to a packaging substrate 150, such as the package substrate 122 or the interposer 1 12 described above. In embodiments wherein an interposer 1 12 is utilized, the interposer 1 12 is coupled to the package substrate 122 using conventional or other suitable techniques.

At operation 504, a thermal interface material (TIM) 256 is applied to either the first surface of the IC dies 1 10, 1 14 or the region(s) 254 of the lid that will be disposed directly above the IC dies 1 10, 1 14 once the lid is mounted to the chip package assembly 100.

At operation 506, TIM 264 is applied to either the free region 124 of die receiving area 120 of the packaging substrate not having an IC die mounted thereto or the region(s) of the lid that will be disposed directly above the free region 124 of the packaging substrate once the lid is mounted to the chip package assembly.

At operation 508, a lid 250, such as the lid 250, 450 among others, is structurally connected to the chip package assembly such that the TIM 256 provides a direct conductive path between the IC dies 1 10, 1 14 and the lid. Once the lid is mounted, the TIM 264 also provides a direct conductive path between the free region 124 of the packaging substrate and the lid. In one example, the lid is structurally connected to the package substrate using an epoxy or other suitable adhesive.

Thus, a chip package assembly and method for fabricating the same have been provided which utilize a conformal lid to improve the resistance of a package substrate to out of plane deformation. The conformal lid substantially eliminates the need for dummy dies to fill surface area within a die receiving area of the surface of the packaging substrate to which the dies are mounted.

Compared with chip package assemblies utilizing dummy dies, the chip package assemblies described herein utilizing a conformal lid are less expense to produce due to reduced raw material requirements and vastly simplified manufacturing techniques. Accordingly, the implementations described above advantageously provide enhanced warpage control while maintaining lower package profile and lower unit costs, among other benefits.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

CLAIMS What is claimed is:

1 . A chip package assembly comprising:

a first integrated circuit (IC) die;

a second IC die, each of the first and second IC die has a first surface and a second surface that faces way from the first surface;

a packaging substrate having a first surface and a second surface, the first surface of the packaging substrate facing the second surface of the IC dies and having a die receiving area surrounded by a ring shaped boundary area, the die receiving area defined by the laterally outermost extents of the IC dies mounted to the first surface of the packaging substrate; and

a lid having a first surface and a second surface facing away from the first surface, the second surface of the lid having a first region and a second region, the first region disposed over the first IC die, the second region of the lid extending below the first surface the first IC die and spaced above the first surface of the packaging substrate, wherein at least a portion of the second region of the lid is overlapped with the die receiving area.

2. The chip package assembly of claim 1 , wherein the second surface of the lid further comprises:

a mounting region circumscribing the first and second regions, the mounting region disposed farther from the first surface of the lid than the second region, the mounting region bonded to the first surface of the packaging substrate.

3. The chip package assembly of claim 1 further comprising:

a ring shaped stiffener having a first side bonded to the second surface of the packaging substrate and a second side coupled the second surface of the lid.

4. The chip package assembly of claim 1 further comprising:

a first thermal interface material conductively coupling the first region of the lid to the first surface of the first IC die; and a second thermal interface material conductively coupling the second region of the lid to the first surface of the packaging substrate within the die receiving area.

5. The chip package assembly of claim 1 , wherein the packaging substrate is a package substrate adapted for coupling to a printed circuit board (PCB) or an interposer mounted to the package substrate.

6. The chip package assembly of claim 1 , wherein the second surface of the lid further comprises:

a third region separated from the second region by the first region, the third region of the lid extending below the first surface the first IC die and spaced above the first surface of the packaging substrate, wherein at least a portion of the third region of the lid is overlapped with the die receiving area.

7. The chip package assembly of claim 6, wherein the second surface of the lid further comprises:

a mounting region circumscribing the first, second and third regions, the mounting region disposed farther from the first surface of the lid than the second region, the mounting region connected to the first surface of the packaging substrate.

8. The chip package assembly of claim 6 further comprising:

a package substrate having first side and a second side, the package substrate having the packaging substrate mounted to first side of the package substrate, the second side of the package substrate configured for coupling to a printed circuit board thereto, the lid coupled to the package substrate outward of the packaging substrate.

9. A chip package assembly comprising:

a first integrated circuit (IC) die;

a second IC die, each of the first and second IC dies having a first surface and a second surface that faces way from the first surface;

a package substrate; an interposer having a first surface and a second surface, the second surface of the interposer coupled to the package substrate, the first surface of the interposer having the first IC die and second IC die mounted thereto, the first surface of the interposer having a die receiving area surrounded by a ring shaped border, the die receiving area defined by the laterally outermost extents of the IC dies mounted to the first surface of the interposer; and

a lid having a first surface and a second surface facing away from the first surface, the second surface of the lid having a first region, a second region and a mounting region, the first region disposed over the first IC die, the second region of the lid extending below the first surface the first IC die and spaced above the first surface of the interposer, at least a portion of the second region of the lid overlapped with the die receiving area, the mounting region circumscribing the first and second regions and structurally connected to the first surface of the package substrate.

10. The chip package assembly of claim 9 further comprising:

a ring shaped stiffener structurally connecting the mounting region of the lid to the package substrate.

1 1 . The chip package assembly of claim 9 further comprising:

a first thermal interface material conductively coupling the first region of the lid to the first surface of the first IC die; and

a second thermal interface material conductively coupling the second region of the lid to the first surface of the interposer within the die receiving area.

12. The chip package assembly of claim 9, wherein the second surface of the lid further comprises:

a third region separated from the second region by the first region, the third region of the lid extending below the first surface the first IC die and spaced above the first surface of the interposer, wherein at least a portion of the third region of the lid is overlapped with the die receiving area.

13. A chip package assembly comprising: a plurality of integrated circuit (IC) dies each having a first surface and a second surface that faces way from the first surface;

a package substrate;

an interposer having a first surface and a second surface, the second surface of the interposer coupled to the package substrate, the first surface of the interposer having at least a first IC die and a second IC die of the plurality of IC dies mounted thereon; and

a lid comprising:

a first surface; and

a second surface facing away from the first surface, the second surface of the lid having a first region, a second region, a third region and a mounting region, the first region disposed vertically above at least the first IC die and separating the second region from the third region, the second and third regions of the lid extending below the first surface the first IC die and spaced vertically above the first surface of the interposer, at least a portion of the second and third regions of the lid laterally overlapped with the interposer, the mounting region circumscribing first, second and third regions laterally outward of the interposer, the mounting region structurally connected to the package substrate.

14. The chip package assembly of claim 13 further comprising:

a second thermal interface material conductively coupling the second region of the lid to the first surface of the interposer.

15. The chip package assembly of claim 13, wherein the mounting region of the lid is spaced further from the first surface of the lid than the first, second and third regions, the mounting region bounding the interposer and bonded to the package substrate.