WO2017209724A1 - Microelectronic device stacks having interior window wirebonding - Google Patents

Microelectronic device stacks having interior window wirebonding Download PDF

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Publication number
WO2017209724A1
WO2017209724A1 PCT/US2016/034955 US2016034955W WO2017209724A1 WO 2017209724 A1 WO2017209724 A1 WO 2017209724A1 US 2016034955 W US2016034955 W US 2016034955W WO 2017209724 A1 WO2017209724 A1 WO 2017209724A1
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WO
WIPO (PCT)
Prior art keywords
microelectronic
microelectronic device
bond
opening
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2016/034955
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French (fr)
Inventor
Min-Tih LAI
Cory A. Runyan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to PCT/US2016/034955 priority Critical patent/WO2017209724A1/en
Priority to US16/096,392 priority patent/US10770429B2/en
Priority to TW106113780A priority patent/TWI744317B/en
Publication of WO2017209724A1 publication Critical patent/WO2017209724A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • Embodiments of the present description generally relate to the field of microelectronic packaging, and, more particularly, to a microelectronic packages having at least one
  • microelectronic device stack wherein a first microelectronic device within the microelectronic device stack is in electronic communication with a second microelectronic device within microelectronic device stack and/or in electrical communication with a microelectronic substrate upon which the first microelectronic device is stacked with a bond wire which extends through an opening or "window" formed through the first microelectronic device.
  • microelectronic industry is continually striving to produce ever faster, smaller, and thinner microelectronic packages for use in various electronic products, including, but not limited to, computer server products and portable products, such as wearable microelectronic systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like.
  • One way to achieve these goals is by increasing integration density, such as by stacking components within the microelectronic package.
  • One stacking method may comprise a method typically used in NAND memory die stacking, wherein a plurality of wirebond pads are formed along one edge of each of the NAND memory dice.
  • the NAND memory dice are stacked on a microelectronic substrate in a staggered or zig-zag configuration to allow access to the wirebond pads.
  • Bond wires are then used to form electrical connections between the wirebond pads on various NAND memory dice and/or between the NAND memory dice and the microelectronic substrate.
  • this stacking method allows for flexibility and choice in wirebond pad location, the longest distance for a transmission line to a corresponding wirebond pad location within each NAND memory die may be the entire length of the NAND memory die. This may result in signal degradation due to impedance.
  • Another stacking method may comprise the use of through-silicon vias wherein signal lines are formed in and through the stacked NAND memory dice to form connections therebetween, as will be understood to those skilled in the art.
  • Through-silicon vias allow for very short conductor paths between the NAND memory dice and the microelectronic substrate, and longest distance for a transmission line to a corresponding wirebond pad location within each NAND memory die may be a fraction of the length of the NAND memory die.
  • the use of through-silicon vias requires an increased number of expensive wafer level processing steps, and may cause reliability issues from copper processing temperature, volume expansion during annealing, and ion migration.
  • the use of through-silicon vias does not allow for flexibility in the positioning of the through-silicon vias within the individual microelectronic dice, as the connection must be made straight down through the microelectronic die stack.
  • FIG. 1 illustrates a top plan view of a microelectronic die having at least one opening defined therethrough, according to an embodiment of the present description.
  • FIG. 2 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 1, according to one embodiment of the present description.
  • FIG. 3 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 1, according to another embodiment of the present description.
  • FIGs. 4 and 5 illustrate top plan views of microelectronic dice having openings defined therethrough, according to still another embodiment of the present description.
  • FIG. 6 illustrates a side cross-sectional view of a microelectronic package including the microelectronic dice of FIGs. 4 and 5, according to one embodiment of the present description.
  • FIG. 7 illustrates a top plan view of a microelectronic die having at least one opening defined therethrough, according to an embodiment of the present description.
  • FIG. 8 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 7, according to one embodiment of the present description.
  • FIG. 9 illustrates a top plan view of a microelectronic die having at least one opening defined therethrough, according to an embodiment of the present description.
  • FIG. 10 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 9, according to one embodiment of the present description.
  • FIG. 11 illustrates a top plan view of a microelectronic die having an opening defined therethrough, according to an embodiment of the present description.
  • FIG. 12 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 11, according to one embodiment of the present description.
  • FIG. 13 illustrates a top plan view of a microelectronic wafer having at least one microelectronic die area and at least one opening defined therethrough, according to an embodiment of the present description.
  • FIG. 14 illustrates an oblique view of a wafer level microelectronic package including the microelectronic wafer of FIG. 13, according to one embodiment of the present description.
  • FIG. 15 is a flow diagram of a process of fabricating a microelectronic package, according to an embodiment of the present description.
  • FIG. 16 illustrates a computing device in accordance with one implementation of the present description.
  • over may refer to a relative position of one layer with respect to other layers.
  • One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more
  • One layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.
  • Embodiments of the present description may include a microelectronic package having a microelectronic die stack attached to a microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening or "window" formed therethrough.
  • the first microelectronic die may be in electronic communication with a second microelectronic die within microelectronic die stack and/or in electrical communication with a microelectronic substrate upon which the microelectronic die stack may be attached, wherein the electronic communication may be created with a bond wire which extends through the opening or
  • microelectronic device may include microelectronic dice, microelectronic substrates, and microelectronic wafers, as will be discussed.
  • FIG. 1 illustrates a first microelectronic die 110i having a first surface 112 1 with at least one bond pad 122 1 formed in or on the first microelectronic die first surface 112 1 .
  • the first microelectronic die 110i may also include at least one opening or window 124 1 formed through the first microelectronic die 110 1 . It is understood that the openings 124 1 do not include notches, as they are defined within the first microelectronic die 110 1 and do not extend from a side 116 1 of the first microelectronic die 110 1 .
  • FIG. 2 illustrates the first microelectronic die 110 1 of FIG. 1 attached to a microelectronic substrate 150 to form a microelectronic package 100.
  • the first microelectronic die 110 1 may be attached to the microelectronic substrate 150 with a first die attach adhesive layer 132 1 disposed between a second surface 114 1 of the first microelectronic die 110 1 and a first surface 152 of the microelectronic substrate 150.
  • the microelectronic substrate 150 may include at least one bond pad 162 formed in or one the microelectronic structure first surface 152 and at least one interconnect bond pad 164 formed in or on a second surface 154 of the microelectronic substrate 150, wherein interconnects 166, such as solder balls, may be attached to each microelectronic substrate interconnect bond pad 164.
  • the first microelectronic die openings 124 1 may extend through the first microelectronic die 110 1 from the first microelectronic die first surface 112 1 to the first microelectronic die second surface 114 1 .
  • the first microelectronic die bond pads 122 1 may be electrically connected to corresponding microelectronic substrate bond pads 162 with first bond wires 142 1 extending through corresponding first microelectronic die openings 124 1 .
  • the microelectronic substrate 150 may comprise any appropriate dielectric material, including, but not limited to, liquid crystal polymer, epoxy resin, bismaleimide triazine resin, FR4, polyimide materials, and the like, and may include conductive routes (not shown) formed therein and/or thereon to form any desired electrical route within the microelectronic
  • Additional microelectronic dice may be stacked on the first microelectronic die 110i to form a microelectronic package 170.
  • a second microelectronic die 110 2 may be attached to the first microelectronic die 110i with a second die attach adhesive layer 132 2 disposed between a second surface 114 2 of the second microelectronic die 110 2 and the first microelectronic die first surface 112 1 .
  • the second microelectronic die 110 2 may have a first surface 112 2 with at least one bond pad 122 2 formed in or on the second microelectronic die first surface 112 2 .
  • the second microelectronic die 110 2 may also include at least one opening or window 124 2 formed through the second microelectronic die 110 2 .
  • the second microelectronic die bond pads 122 2 may be electrically connected to corresponding first microelectronic die bond pads 122 1 with second bond wires 142 2 extending through corresponding second microelectronic die openings 124 2 .
  • a third microelectronic die 110 3 may be attached to the second microelectronic die 110 2 with a third die attach adhesive layer 132 3 disposed between a second surface 114 3 of the third microelectronic die 110 3 and the second microelectronic die first surface 112 2 .
  • the third microelectronic die 110 3 may have a first surface 112 3 with at least one bond pad 122 3 formed in or on the third microelectronic die first surface 112 3 .
  • the third microelectronic die 110 3 may also include at least one opening or window 124 3 formed through the third microelectronic die 110 3 .
  • the third microelectronic die bond pads 122 3 may be electrically connected to corresponding second microelectronic die bond pads 122 2 with third bond wires 142 3 extending through corresponding third microelectronic die openings 124 3 .
  • the first microelectronic die 110i, the second microelectronic die 110 2 , and/or the third microelectronic die 110 3 may be any appropriate microelectronic device, including, but not limited to, microprocessors, chipsets, graphics devices, wireless devices, memory devices, application specific integrated circuit devices, and the like.
  • the first microelectronic die 110i, the second microelectronic die 110 2 , and/or the third microelectronic die 110 3 may be non-volatile memory devices.
  • one microelectronic die 110a may be formed in the manner described with regard to the first microelectronic die 110 1 in FIG. 2.
  • another microelectronic die 110b may also be formed in the manner described with regard to first microelectronic die 110i in FIG. 2, but in a substantially mirror-image
  • microelectronic die 110a configuration to the microelectronic die 110a. It is understood that, if the bond pads 122 1 and the openings 124 1 of FIG. 4 are appropriately positioned, the mirror-image configuration of microelectronic die 110b of FIG. 5 may be achieved by rotating the microelectronic die 110a of FIG. 4 by 180 degrees.
  • microelectronic die 110b of FIG. 5 may be stacked in an alternating fashion, wherein the first microelectronic die 110i and the third microelectronic die 110 3 corresponds to the one microelectronic die 110a of FIG. 4 and wherein the second microelectronic die 110 2 corresponds to the other microelectronic die 110b of FIG. 5 to from a microelectronic package 175.
  • the components of the microelectronic package 175 of FIG. 6 may be assembled in the manner discussed with regard to the microelectronic package 170 of FIG. 3. As will be understood to those skilled in the art, the stacking configuration of FIG. 6 will result in a small footprint than that of FIG. 3.
  • the first microelectronic die 110i may be formed with a pair of bond pads 122 la and 122 ⁇ which are positioned on opposing sides of an associated opening 124i, wherein the first bond pad 122 la and the second bond pad 122 ⁇ of each pair of pads are shorted together with a conductive trace 128.
  • microelectronic die 110i, the second microelectronic die 110 2 , the third microelectronic die 110 3 , and a fourth microelectronic die 110 4 are assembled in the manner discussed with regard to the microelectronic package 170 of FIG. 3 to form a microelectronic package 180, there is a choice of which bond pad 122 la , 122 lb to use to minimize the footprint of the microelectronic package 180, as will be understood to those skilled in the art.
  • the first microelectronic die 110 1 may be formed with a pair of openings 124 la and 124r b which are positioned on opposing sides of an associated bond pad 122 1 .
  • the first microelectronic die 110i, the second microelectronic die 110 2 , the third microelectronic die 110 3 , and the fourth microelectronic die 110 4 are assembled in the manner discussed with regard to the
  • microelectronic package 170 of FIG. 3 to form a microelectronic package 185, there is a choice of which opening 124 la , 124r b to use to minimize the footprint of the microelectronic
  • FIGs. 1-10 require that the attachment of the wire bonds (elements 142i, 142 2 , 142 3 , etc.) be completed after that attachment of each microelectronic die (elements 110i, 110 2 , 110 3 , etc.) in sequence, respectively.
  • at least one large opening 124 L1 may be formed in the microelectronic dice, such as the first
  • microelectronic die 110i of FIG. 11 The microelectronic dice, such as the first microelectronic die 110i, the second microelectronic die 110 2 , and the third microelectronic die 110 3 shown in FIG. 12, may be stacked on the microelectronic substrate 150, such that the large openings, such openings 124 L i, 124 L2 , and 124 L3 , respectively, allow access to all of the bond pads, such bond pads 162, 122i, 122 2 , and 122 4 , for the attachment of the wire bonds, such as bond wires 142i, 142 2 , and 142 3 , after the stacking of the microelectronic dice, to form a microelectronic package 190.
  • the large openings such openings 124 L i, 124 L2 , and 124 L3 , respectively, allow access to all of the bond pads, such bond pads 162, 122i, 122 2 , and 122 4 , for the attachment of the wire
  • the subject matter can be applied on a wafer level.
  • a plurality of microelectronic die areas 210 la , 210i b , 210 lc , and 21 O ld may be formed in a first microelectronic wafer 2051, wherein each of the
  • microelectronic die areas include at least one bond pad, e.g. elements 222i a , 222i b , 222 ic , and 222i d , respectively.
  • At least one opening 224 a , 224 b , 224 c , and 224 d may be formed adjacent each of the microelectronic die areas 210 la , 210i b , 210 lc , and 210i d , respectively. As shown in FIG.
  • the first microelectronic wafer 2051 may be stacked on a second microelectronic wafer 205 2 in a manner previously discuss, and at least one bond wire 242 a , 242 b , 242 c , and 242 d may extend through their respective openings 224 a , 224 b , 224 c , and 224 d to connect the bond pads 222i a , 222 i b , 222 ic , and 222i d on the first microelectronic wafer 2051 to corresponding bond pads 222 2a , 222 3 ⁇ 4 , 222 2c , and 222 2d on the second microelectronic wafer 205 2 to form a wafer level microelectronic package 200.
  • the openings 224 a , 224 b , 224 c , and 224 d need not be within the microelectronic die areas 210 la , 210i b , 210 lc , and 210i d .
  • FIG. 15 is a flow chart of a process 300 of fabricating a microelectronic package according to an embodiment of the present description.
  • a microelectronic substrate having a first surface and an opposing second surface may be formed, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface.
  • a second microelectronic device having a first surface and an opposing second surface may be formed, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the first microelectronic device from the second
  • At least one bond wire may be electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
  • FIG. 16 illustrates a computing device 400 in accordance with one implementation of the present description.
  • the computing device 400 houses a board 402.
  • the board may include a number of microelectronic components, including but not limited to a processor 404, at least one communication chip 406A, 406B, volatile memory 408, (e.g., DRAM), non-volatile memory 410 (e.g., ROM), flash memory 412, a graphics processor or CPU 414, a digital signal processor (not shown), a crypto processor (not shown), a chipset 416, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (
  • microelectronic components may be a part of the processor 404.
  • the communication chip enables wireless communications for the transfer of data to and from the computing device.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device may include a plurality of communication chips.
  • a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • any of the microelectronic components within the computing device 400 may include a microelectronic package having a microelectronic die stack attached to microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening, wherein the first microelectronic die electrically connected with a second microelectronic die within microelectronic die stack and/or with a microelectronic substrate upon which the microelectronic die stack may be attached with a bond wire extending through the opening in the first microelectronic die.
  • the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device may be any other electronic device that processes data.
  • Example 1 is a microelectronic package, comprising a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface; a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface , wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein
  • Example 2 the subject matter of Example 1 can optionally include the at least one bond pad in or on the second microelectronic device first surface comprising a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.
  • Example 3 the subject matter of Example 1 can optionally include the at least one opening through the second microelectronic device comprises a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein the at least one bond wire extends through one opening of the pair of openings.
  • Example 4 the subject matter of Example 1 can optionally include the at least one bond pad in or on the first microelectronic device first surface comprising a plurality of bond pads; the at least one bond pad of the second microelectronic device comprising a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening; and the at least one bond wire comprising a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.
  • Example 5 the subject matter of any of Examples 1 to 4 can optionally include the first microelectronic device comprising a first microelectronic die and wherein the second
  • microelectronic device comprises a second microelectronic die.
  • Example 6 the subject matter of any of Examples 1 to 4 can optionally include the first microelectronic device comprising a microelectronic substrate and wherein the second microelectronic device comprises a microelectronic die.
  • Example 7 the subject matter of any of Examples 1 to 4 can optionally include the first microelectronic device comprising a first microelectronic wafer and wherein the second microelectronic device comprises a second microelectronic wafer.
  • Example 8 the subject matter of Example 7 can optionally include the at least one opening being outside a microelectronic die area on the second microelectronic wafer.
  • a method of fabricating a microelectronic package may comprise forming a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface; forming a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device
  • Example 10 the subject matter of Example 9 can optionally include forming the second microelectronic device with the at least one bond pad in or on the second microelectronic device first surface comprising forming the second microelectronic device having a pair of bond pads on opposing sides of the at least one opening, and forming a short with a conductive trace extending between the pair of bond pads.
  • Example 11 the subject matter of Example 9 can optionally include forming the second microelectronic device with the at least one opening through the second microelectronic device comprising forming the second microelectronic device with a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein electrically attaching the at least one bond wire comprises electrically attaching the at least one bond wire through one opening of the pair of openings.
  • Example 12 the subject matter of Example 9 can optionally include forming the first microelectronic device with the at least one bond pad in or on the first microelectronic device first surface comprising forming the first microelectronic device with a plurality of bond pads in or on the first microelectronic device first surface; forming the second microelectronic device with the at least one bond pad in or on the second microelectronic device first surface comprising forming the second microelectronic device with a plurality of bond pads in or on the second microelectronic device first surface, and wherein the opening through the second microelectronic device comprises a single opening; and electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device comprising electrically attaching a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device
  • Example 13 the subject matter of any of Examples 9 to 12 can optionally include forming the first microelectronic device comprising forming a first microelectronic die and wherein forming the second microelectronic device comprises forming a second microelectronic die.
  • Example 14 the subject matter of any of Examples 9 to 12 can optionally include forming the first microelectronic device comprising forming a microelectronic substrate and wherein forming the second microelectronic device comprises forming a microelectronic die.
  • Example 15 the subject matter of any of Example 9 to 12 can optionally include forming the first microelectronic device comprising forming a first microelectronic wafer, and wherein forming the second microelectronic device comprises forming a second microelectronic wafer.
  • Example 16 the subject matter of Example 15 can optionally include the at least one opening being formed outside a microelectronic die area on the second microelectronic wafer.
  • an electronic system may comprise a board; and a microelectronic package attached to the board, wherein the microelectronic package includes a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface; a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface , wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and at least one bond wire electrically
  • Example 18 the subject matter of Example 17 can optionally include the at least one bond pad in or on the second microelectronic device first surface comprising a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.
  • Example 19 the subject matter of Example 17 can optionally include the at least one opening through the second microelectronic device comprises a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein the at least one bond wire extends through one opening of the pair of openings.
  • Example 20 the subject matter of Example 17 can optionally include the at least one bond pad in or on the first microelectronic device first surface comprising a plurality of bond pads; the at least one bond pad of the second microelectronic device comprising a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening; and the at least one bond wire comprising a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and
  • Example 21 the subject matter of any of Examples 17 to 20 can optionally include the first microelectronic device comprising a first microelectronic die and wherein the second microelectronic device comprises a second microelectronic die.
  • Example 22 the subject matter of any of Examples 17 to 20 can optionally include the first microelectronic device comprising a microelectronic substrate and wherein the second microelectronic device comprises a microelectronic die.
  • Example 23 the subject matter of any of Examples 17 to 20 can optionally include the first microelectronic device comprising a first microelectronic wafer and wherein the second microelectronic device comprises a second microelectronic wafer.
  • Example 24 the subject matter of Example 23 can optionally include the at least one opening being outside a microelectronic die area on the second microelectronic wafer.

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Abstract

A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening or "window" formed therethrough. The first microelectronic die may be in electronic communication with a second microelectronic die within microelectronic die stack and/or in electrical communication with a microelectronic substrate upon which the microelectronic die stack may be attached, wherein the electronic communication may be created with a bond wire which extends through the opening or "window" in the first microelectronic die.

Description

MICROELECTRONIC DEVICE STACKS HAVING
INTERIOR WINDOW WIREBONDING
TECHNICAL FIELD
Embodiments of the present description generally relate to the field of microelectronic packaging, and, more particularly, to a microelectronic packages having at least one
microelectronic device stack, wherein a first microelectronic device within the microelectronic device stack is in electronic communication with a second microelectronic device within microelectronic device stack and/or in electrical communication with a microelectronic substrate upon which the first microelectronic device is stacked with a bond wire which extends through an opening or "window" formed through the first microelectronic device.
BACKGROUND
The microelectronic industry is continually striving to produce ever faster, smaller, and thinner microelectronic packages for use in various electronic products, including, but not limited to, computer server products and portable products, such as wearable microelectronic systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like.
One way to achieve these goals is by increasing integration density, such as by stacking components within the microelectronic package. One stacking method may comprise a method typically used in NAND memory die stacking, wherein a plurality of wirebond pads are formed along one edge of each of the NAND memory dice. The NAND memory dice are stacked on a microelectronic substrate in a staggered or zig-zag configuration to allow access to the wirebond pads. Bond wires are then used to form electrical connections between the wirebond pads on various NAND memory dice and/or between the NAND memory dice and the microelectronic substrate. Although this stacking method allows for flexibility and choice in wirebond pad location, the longest distance for a transmission line to a corresponding wirebond pad location within each NAND memory die may be the entire length of the NAND memory die. This may result in signal degradation due to impedance.
Another stacking method may comprise the use of through-silicon vias wherein signal lines are formed in and through the stacked NAND memory dice to form connections therebetween, as will be understood to those skilled in the art. Through-silicon vias allow for very short conductor paths between the NAND memory dice and the microelectronic substrate, and longest distance for a transmission line to a corresponding wirebond pad location within each NAND memory die may be a fraction of the length of the NAND memory die. However, the use of through-silicon vias requires an increased number of expensive wafer level processing steps, and may cause reliability issues from copper processing temperature, volume expansion during annealing, and ion migration. Further, the use of through-silicon vias does not allow for flexibility in the positioning of the through-silicon vias within the individual microelectronic dice, as the connection must be made straight down through the microelectronic die stack.
Therefore, there is a need to develop novel microelectronic die stacking configurations and designs to reduce signal transmission lengths, minimize costs, and improve reliability.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
FIG. 1 illustrates a top plan view of a microelectronic die having at least one opening defined therethrough, according to an embodiment of the present description.
FIG. 2 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 1, according to one embodiment of the present description.
FIG. 3 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 1, according to another embodiment of the present description.
FIGs. 4 and 5 illustrate top plan views of microelectronic dice having openings defined therethrough, according to still another embodiment of the present description.
FIG. 6 illustrates a side cross-sectional view of a microelectronic package including the microelectronic dice of FIGs. 4 and 5, according to one embodiment of the present description.
FIG. 7 illustrates a top plan view of a microelectronic die having at least one opening defined therethrough, according to an embodiment of the present description.
FIG. 8 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 7, according to one embodiment of the present description.
FIG. 9 illustrates a top plan view of a microelectronic die having at least one opening defined therethrough, according to an embodiment of the present description.
FIG. 10 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 9, according to one embodiment of the present description. FIG. 11 illustrates a top plan view of a microelectronic die having an opening defined therethrough, according to an embodiment of the present description.
FIG. 12 illustrates a side cross-sectional view of a microelectronic package including the microelectronic die of FIG. 11, according to one embodiment of the present description.
FIG. 13 illustrates a top plan view of a microelectronic wafer having at least one microelectronic die area and at least one opening defined therethrough, according to an embodiment of the present description.
FIG. 14 illustrates an oblique view of a wafer level microelectronic package including the microelectronic wafer of FIG. 13, according to one embodiment of the present description.
FIG. 15 is a flow diagram of a process of fabricating a microelectronic package, according to an embodiment of the present description.
FIG. 16 illustrates a computing device in accordance with one implementation of the present description.
DESCRIPTION OF EMBODIMENTS
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description. The terms "over", "to", "between" and "on" as used herein may refer to a relative position of one layer with respect to other layers. One layer "over" or "on" another layer or bonded "to" another layer may be directly in contact with the other layer or may have one or more
intervening layers. One layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.
Embodiments of the present description may include a microelectronic package having a microelectronic die stack attached to a microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening or "window" formed therethrough. The first microelectronic die may be in electronic communication with a second microelectronic die within microelectronic die stack and/or in electrical communication with a microelectronic substrate upon which the microelectronic die stack may be attached, wherein the electronic communication may be created with a bond wire which extends through the opening or
"window" in the first microelectronic die.
For the purposes of the present invention the term "microelectronic device" may include microelectronic dice, microelectronic substrates, and microelectronic wafers, as will be discussed.
FIG. 1 illustrates a first microelectronic die 110i having a first surface 1121 with at least one bond pad 1221 formed in or on the first microelectronic die first surface 1121. The first microelectronic die 110i may also include at least one opening or window 1241 formed through the first microelectronic die 1101. It is understood that the openings 1241 do not include notches, as they are defined within the first microelectronic die 1101 and do not extend from a side 1161 of the first microelectronic die 1101.
FIG. 2 illustrates the first microelectronic die 1101 of FIG. 1 attached to a microelectronic substrate 150 to form a microelectronic package 100. The first microelectronic die 1101 may be attached to the microelectronic substrate 150 with a first die attach adhesive layer 1321 disposed between a second surface 1141 of the first microelectronic die 1101 and a first surface 152 of the microelectronic substrate 150. The microelectronic substrate 150 may include at least one bond pad 162 formed in or one the microelectronic structure first surface 152 and at least one interconnect bond pad 164 formed in or on a second surface 154 of the microelectronic substrate 150, wherein interconnects 166, such as solder balls, may be attached to each microelectronic substrate interconnect bond pad 164.
As further illustrated in FIG. 2, the first microelectronic die openings 1241 may extend through the first microelectronic die 1101 from the first microelectronic die first surface 1121 to the first microelectronic die second surface 1141. The first microelectronic die bond pads 1221 may be electrically connected to corresponding microelectronic substrate bond pads 162 with first bond wires 1421 extending through corresponding first microelectronic die openings 1241.
The microelectronic substrate 150 may comprise any appropriate dielectric material, including, but not limited to, liquid crystal polymer, epoxy resin, bismaleimide triazine resin, FR4, polyimide materials, and the like, and may include conductive routes (not shown) formed therein and/or thereon to form any desired electrical route within the microelectronic
substrate 150.
Additional microelectronic dice may be stacked on the first microelectronic die 110i to form a microelectronic package 170. As shown in FIG. 3, a second microelectronic die 1102 may be attached to the first microelectronic die 110i with a second die attach adhesive layer 1322 disposed between a second surface 1142 of the second microelectronic die 1102 and the first microelectronic die first surface 1121. The second microelectronic die 1102 may have a first surface 1122 with at least one bond pad 1222 formed in or on the second microelectronic die first surface 1122. The second microelectronic die 1102 may also include at least one opening or window 1242 formed through the second microelectronic die 1102. The second microelectronic die bond pads 1222 may be electrically connected to corresponding first microelectronic die bond pads 1221 with second bond wires 1422 extending through corresponding second microelectronic die openings 1242.
As further shown in FIG. 3, a third microelectronic die 1103 may be attached to the second microelectronic die 1102 with a third die attach adhesive layer 1323 disposed between a second surface 1143 of the third microelectronic die 1103 and the second microelectronic die first surface 1122. The third microelectronic die 1103 may have a first surface 1123 with at least one bond pad 1223 formed in or on the third microelectronic die first surface 1123. The third microelectronic die 1103 may also include at least one opening or window 1243 formed through the third microelectronic die 1103. The third microelectronic die bond pads 1223 may be electrically connected to corresponding second microelectronic die bond pads 1222 with third bond wires 1423 extending through corresponding third microelectronic die openings 1243.
The first microelectronic die 110i, the second microelectronic die 1102, and/or the third microelectronic die 1103, may be any appropriate microelectronic device, including, but not limited to, microprocessors, chipsets, graphics devices, wireless devices, memory devices, application specific integrated circuit devices, and the like. In a specific embodiment, the first microelectronic die 110i, the second microelectronic die 1102, and/or the third microelectronic die 1103, may be non-volatile memory devices.
In another embodiment, as shown in FIG. 4, one microelectronic die 110a may be formed in the manner described with regard to the first microelectronic die 1101 in FIG. 2. As shown in FIG. 5, another microelectronic die 110b may also be formed in the manner described with regard to first microelectronic die 110i in FIG. 2, but in a substantially mirror-image
configuration to the microelectronic die 110a. It is understood that, if the bond pads 1221 and the openings 1241 of FIG. 4 are appropriately positioned, the mirror-image configuration of microelectronic die 110b of FIG. 5 may be achieved by rotating the microelectronic die 110a of FIG. 4 by 180 degrees.
As shown in FIG. 6, the one microelectronic die 110a of FIG. 4 and the other
microelectronic die 110b of FIG. 5 may be stacked in an alternating fashion, wherein the first microelectronic die 110i and the third microelectronic die 1103 corresponds to the one microelectronic die 110a of FIG. 4 and wherein the second microelectronic die 1102 corresponds to the other microelectronic die 110b of FIG. 5 to from a microelectronic package 175. The components of the microelectronic package 175 of FIG. 6 may be assembled in the manner discussed with regard to the microelectronic package 170 of FIG. 3. As will be understood to those skilled in the art, the stacking configuration of FIG. 6 will result in a small footprint than that of FIG. 3.
In a further embodiment, as shown in FIGs. 7 and 8, the first microelectronic die 110i may be formed with a pair of bond pads 122la and 122^ which are positioned on opposing sides of an associated opening 124i, wherein the first bond pad 122la and the second bond pad 122^ of each pair of pads are shorted together with a conductive trace 128. Thus, when the first
microelectronic die 110i, the second microelectronic die 1102, the third microelectronic die 1103, and a fourth microelectronic die 1104 are assembled in the manner discussed with regard to the microelectronic package 170 of FIG. 3 to form a microelectronic package 180, there is a choice of which bond pad 122la, 122lb to use to minimize the footprint of the microelectronic package 180, as will be understood to those skilled in the art.
In still a further embodiment, as shown in FIGs. 9 and 10, the first microelectronic die 1101 may be formed with a pair of openings 124la and 124rb which are positioned on opposing sides of an associated bond pad 1221. Thus, as shown in FIG. 10, when the first microelectronic die 110i, the second microelectronic die 1102, the third microelectronic die 1103, and the fourth microelectronic die 1104 are assembled in the manner discussed with regard to the
microelectronic package 170 of FIG. 3 to form a microelectronic package 185, there is a choice of which opening 124la, 124rb to use to minimize the footprint of the microelectronic
package 185.
As will understood to those skilled in the art, the embodiment of FIGs. 1-10 require that the attachment of the wire bonds (elements 142i, 1422, 1423, etc.) be completed after that attachment of each microelectronic die (elements 110i, 1102, 1103, etc.) in sequence, respectively. In an embodiment of the present description, as shown in FIGs. 11, and 12, at least one large opening 124L1 may be formed in the microelectronic dice, such as the first
microelectronic die 110i of FIG. 11. The microelectronic dice, such as the first microelectronic die 110i, the second microelectronic die 1102, and the third microelectronic die 1103 shown in FIG. 12, may be stacked on the microelectronic substrate 150, such that the large openings, such openings 124Li, 124L2, and 124L3, respectively, allow access to all of the bond pads, such bond pads 162, 122i, 1222, and 1224, for the attachment of the wire bonds, such as bond wires 142i, 1422, and 1423, after the stacking of the microelectronic dice, to form a microelectronic package 190.
In another embodiment of the present description, the subject matter can be applied on a wafer level. As shown in FIG. 13, a plurality of microelectronic die areas 210la, 210ib, 210lc, and 21 Old may be formed in a first microelectronic wafer 2051, wherein each of the
microelectronic die areas include at least one bond pad, e.g. elements 222ia, 222ib, 222ic, and 222id, respectively. At least one opening 224a, 224b, 224c, and 224d may be formed adjacent each of the microelectronic die areas 210la, 210ib, 210lc, and 210id, respectively. As shown in FIG. 14, the first microelectronic wafer 2051 may be stacked on a second microelectronic wafer 2052 in a manner previously discuss, and at least one bond wire 242a, 242b, 242c, and 242d may extend through their respective openings 224a, 224b, 224c, and 224d to connect the bond pads 222ia, 222 ib, 222ic, and 222id on the first microelectronic wafer 2051 to corresponding bond pads 2222a, 222¾, 2222c, and 2222d on the second microelectronic wafer 2052 to form a wafer level microelectronic package 200. As shown in FIGs. 13 and 14, the openings 224a, 224b, 224c, and 224d need not be within the microelectronic die areas 210la, 210ib, 210lc, and 210id.
FIG. 15 is a flow chart of a process 300 of fabricating a microelectronic package according to an embodiment of the present description. As set forth in block 302, a microelectronic substrate having a first surface and an opposing second surface may be formed, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface. A second microelectronic device having a first surface and an opposing second surface may be formed, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the first microelectronic device from the second
microelectronic device first surface to the first microelectronic device second surface, as set forth in block 304. As set forth in block 306, at least one bond wire may be electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
FIG. 16 illustrates a computing device 400 in accordance with one implementation of the present description. The computing device 400 houses a board 402. The board may include a number of microelectronic components, including but not limited to a processor 404, at least one communication chip 406A, 406B, volatile memory 408, (e.g., DRAM), non-volatile memory 410 (e.g., ROM), flash memory 412, a graphics processor or CPU 414, a digital signal processor (not shown), a crypto processor (not shown), a chipset 416, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the microelectronic components may be physically and electrically coupled to the board 402. In some implementations, at least one of the
microelectronic components may be a part of the processor 404.
The communication chip enables wireless communications for the transfer of data to and from the computing device. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
Any of the microelectronic components within the computing device 400 may include a microelectronic package having a microelectronic die stack attached to microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening, wherein the first microelectronic die electrically connected with a second microelectronic die within microelectronic die stack and/or with a microelectronic substrate upon which the microelectronic die stack may be attached with a bond wire extending through the opening in the first microelectronic die.
In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1-16. The subject matter may be applied to other microelectronic devices and assembly applications, as well as any appropriate electronic application, as will be understood to those skilled in the art.
The follow examples pertain to further embodiments and specifics in the examples may be used anywhere in one or more embodiments, wherein Example 1 is a microelectronic package, comprising a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface; a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface , wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
In Example 2, the subject matter of Example 1 can optionally include the at least one bond pad in or on the second microelectronic device first surface comprising a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.
In Example 3, the subject matter of Example 1 can optionally include the at least one opening through the second microelectronic device comprises a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein the at least one bond wire extends through one opening of the pair of openings. In Example 4, the subject matter of Example 1 can optionally include the at least one bond pad in or on the first microelectronic device first surface comprising a plurality of bond pads; the at least one bond pad of the second microelectronic device comprising a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening; and the at least one bond wire comprising a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.
In Example 5, the subject matter of any of Examples 1 to 4 can optionally include the first microelectronic device comprising a first microelectronic die and wherein the second
microelectronic device comprises a second microelectronic die.
In Example 6, the subject matter of any of Examples 1 to 4 can optionally include the first microelectronic device comprising a microelectronic substrate and wherein the second microelectronic device comprises a microelectronic die.
In Example 7, the subject matter of any of Examples 1 to 4 can optionally include the first microelectronic device comprising a first microelectronic wafer and wherein the second microelectronic device comprises a second microelectronic wafer.
In Example 8, the subject matter of Example 7 can optionally include the at least one opening being outside a microelectronic die area on the second microelectronic wafer.
In Example 9, a method of fabricating a microelectronic package may comprise forming a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface; forming a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
In Example 10, the subject matter of Example 9 can optionally include forming the second microelectronic device with the at least one bond pad in or on the second microelectronic device first surface comprising forming the second microelectronic device having a pair of bond pads on opposing sides of the at least one opening, and forming a short with a conductive trace extending between the pair of bond pads.
In Example 11, the subject matter of Example 9 can optionally include forming the second microelectronic device with the at least one opening through the second microelectronic device comprising forming the second microelectronic device with a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein electrically attaching the at least one bond wire comprises electrically attaching the at least one bond wire through one opening of the pair of openings.
In Example 12, the subject matter of Example 9 can optionally include forming the first microelectronic device with the at least one bond pad in or on the first microelectronic device first surface comprising forming the first microelectronic device with a plurality of bond pads in or on the first microelectronic device first surface; forming the second microelectronic device with the at least one bond pad in or on the second microelectronic device first surface comprising forming the second microelectronic device with a plurality of bond pads in or on the second microelectronic device first surface, and wherein the opening through the second microelectronic device comprises a single opening; and electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device comprising electrically attaching a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and
corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.
In Example 13, the subject matter of any of Examples 9 to 12 can optionally include forming the first microelectronic device comprising forming a first microelectronic die and wherein forming the second microelectronic device comprises forming a second microelectronic die.
In Example 14, the subject matter of any of Examples 9 to 12 can optionally include forming the first microelectronic device comprising forming a microelectronic substrate and wherein forming the second microelectronic device comprises forming a microelectronic die.
In Example 15, the subject matter of any of Example 9 to 12 can optionally include forming the first microelectronic device comprising forming a first microelectronic wafer, and wherein forming the second microelectronic device comprises forming a second microelectronic wafer.
In Example 16, the subject matter of Example 15 can optionally include the at least one opening being formed outside a microelectronic die area on the second microelectronic wafer. In Example 17, an electronic system may comprise a board; and a microelectronic package attached to the board, wherein the microelectronic package includes a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface; a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface , wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
In Example 18, the subject matter of Example 17 can optionally include the at least one bond pad in or on the second microelectronic device first surface comprising a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.
In Example 19, the subject matter of Example 17 can optionally include the at least one opening through the second microelectronic device comprises a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein the at least one bond wire extends through one opening of the pair of openings.
In Example 20, the subject matter of Example 17 can optionally include the at least one bond pad in or on the first microelectronic device first surface comprising a plurality of bond pads; the at least one bond pad of the second microelectronic device comprising a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening; and the at least one bond wire comprising a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and
corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.
In Example 21, the subject matter of any of Examples 17 to 20 can optionally include the first microelectronic device comprising a first microelectronic die and wherein the second microelectronic device comprises a second microelectronic die. In Example 22, the subject matter of any of Examples 17 to 20 can optionally include the first microelectronic device comprising a microelectronic substrate and wherein the second microelectronic device comprises a microelectronic die.
In Example 23, the subject matter of any of Examples 17 to 20 can optionally include the first microelectronic device comprising a first microelectronic wafer and wherein the second microelectronic device comprises a second microelectronic wafer.
In Example 24, the subject matter of Example 23 can optionally include the at least one opening being outside a microelectronic die area on the second microelectronic wafer.
Having thus described in detail embodiments of the present description, it is understood that the present description defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims

CLAIMS What is claimed is:
1. A microelectronic package, comprising:
a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface , wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extends through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and
at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
2. The microelectronic package of claim 1, wherein the at least one bond pad in or on the second microelectronic device first surface comprises a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.
3. The microelectronic package of claim 1, wherein the at least one opening through the second microelectronic device comprises a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein the at least one bond wire extends through one opening of the pair of openings.
4. The microelectronic package of claim 1,
wherein the at least one bond pad in or on the first microelectronic device first surface comprises a plurality of bond pads;
wherein the at least one bond pad of the second microelectronic device comprises a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening; and
wherein the at least one bond wire comprising a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and corresponding bonds pad of the plurality bond pads in or on the second microelectronic device first surface.
5. The microelectronic package of any of claims 1 to 4, wherein the first microelectronic device comprises a first microelectronic die and wherein the second microelectronic device comprises a second microelectronic die.
6. The microelectronic package of any of claims 1 to 4, wherein the first microelectronic device comprises a microelectronic substrate and wherein the second microelectronic device comprises a microelectronic die.
7. The microelectronic package of any of claims 1 to 4, wherein the first microelectronic device comprises a first microelectronic wafer and wherein the second microelectronic device comprises a second microelectronic wafer.
8. The microelectronic package of claim 7, wherein the at least one opening is outside a microelectronic die area on the second microelectronic wafer.
9. A method of forming a microelectronic package, comprising:
forming a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
forming a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface, wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and
electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
10. The method of claim 9, wherein forming the second microelectronic device with the at least one bond pad in or on the second microelectronic device first surface comprises forming the second microelectronic device having a pair of bond pads on opposing sides of the at least one opening, and forming a short with a conductive trace extending between the pair of bond pads.
11. The method of claim 9, wherein forming the second microelectronic device with the at least one opening through the second microelectronic device comprises forming the second microelectronic device with a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein electrically attaching the at least one bond wire comprises electrically attaching the at least one bond wire through one opening of the pair of openings.
12. The method of claim 9,
wherein forming the first microelectronic device with the at least one bond pad in or on the first microelectronic device first surface comprises forming the first microelectronic device with a plurality of bond pads in or on the first microelectronic device first surface;
wherein forming the second microelectronic device with the at least one bond pad in or on the second microelectronic device first surface comprises forming the second microelectronic device with a plurality of bond pads in or on the second microelectronic device first surface, and wherein the opening through the second microelectronic device comprises a single opening; and wherein electrically attaching at least one bond wire to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device comprising electrically attaching a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.
13. The method of any of claims 9 to 12, wherein forming the first microelectronic device comprises forming a first microelectronic die and wherein forming the second microelectronic device comprises forming a second microelectronic die.
14. The method of any of claims 9 to 12, wherein forming the first microelectronic device comprises forming a microelectronic substrate and wherein forming the second microelectronic device comprises forming a microelectronic die.
15. The method of any of claims 9 to 12, wherein forming the first microelectronic device comprises forming a first microelectronic wafer, and wherein forming the second
microelectronic device comprises forming a second microelectronic wafer.
16. The method of claim 15, wherein the at least one opening is formed outside a
microelectronic die area on the second microelectronic wafer.
17. An electronic system, comprising:
a board; and
a microelectronic package attached to the board, wherein the microelectronic package includes:
a first microelectronic device having a first surface and an opposing second surface, wherein the first microelectronic device includes at least one bond pad in or on the first microelectronic device first surface;
a second microelectronic device having a first surface and an opposing second surface, wherein the second microelectronic device second surface is attached to the first microelectronic device first surface , wherein the second microelectronic device includes at least one bond pad in or on the second microelectronic device first surface, and wherein at least one opening extending through the second microelectronic device from the second microelectronic device first surface to the second microelectronic device second surface; and
at least one bond wire electrically attached to the at least one bond pad on the first microelectronic device and to the at least one bond pad on the second microelectronic device, wherein the bond wire extends through the at least one second microelectronic device opening.
18. The electronic system of claim 17, wherein the at least one bond pad in or on the second microelectronic device first surface comprises a pair of bond pads on opposing sides of the at least one opening, and wherein the pair of bond pads are shorted with a conductive trace extending between the pair of bond pads.
19. The electronic system of claim 17, wherein the at least one opening through the second microelectronic device comprises a pair of openings on opposing sides of the at least one bond pad of the second microelectronic device, and wherein the at least one bond wire extends through one opening of the pair of openings.
20. The electronic system of claim 17,
wherein the at least one bond pad in or on the first microelectronic device first surface comprises a plurality of bond pads;
wherein the at least one bond pad of the second microelectronic device comprises a plurality of bond pads and wherein the opening through the second microelectronic device comprises a single opening; and
wherein the at least one bond wire comprising a plurality of bond wires, wherein the plurality of bond wires extend through the single opening to form electrical connections between the plurality of bond pads in or on the first microelectronic device first surface and
corresponding bond pads of the plurality bond pads in or on the second microelectronic device first surface.
21. The electronic system of any of claims 17 to 20, wherein the first microelectronic device comprises a first microelectronic die and wherein the second microelectronic device comprises a second microelectronic die.
22. The electronic system of any of claims 17 to 20, wherein the first microelectronic device comprises a microelectronic substrate and wherein the second microelectronic device comprises a microelectronic die.
23. The electronic system of any of claims 17 to 20, wherein the first microelectronic device comprises a first microelectronic wafer and wherein the second microelectronic device comprises a second microelectronic wafer.
24. The electronic system of claim 23, wherein the at least one opening is outside a microelectronic die area on the second microelectronic wafer.
PCT/US2016/034955 2016-05-31 2016-05-31 Microelectronic device stacks having interior window wirebonding Ceased WO2017209724A1 (en)

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US16/096,392 US10770429B2 (en) 2016-05-31 2016-05-31 Microelectronic device stacks having interior window wirebonding
TW106113780A TWI744317B (en) 2016-05-31 2017-04-25 Microelectronic device stacks having interior window wirebonding

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US10770429B2 (en) 2020-09-08
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TW201807792A (en) 2018-03-01

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