WO2017202749A1

WO2017202749A1 - Converter arrangement

Info

Publication number: WO2017202749A1
Application number: PCT/EP2017/062222
Authority: WO
Inventors: Henning STRÖBEL-MAIER; Kevin Lenz
Original assignee: Danfoss Silicon Power Gmbh
Priority date: 2016-05-23
Filing date: 2017-05-22
Publication date: 2017-11-30
Also published as: DE202016102722U1

Abstract

Converter arrangement (1) comprising an upper bridge branch, which is arranged between a positive input connection (+) and a centre tap (0), and a lower bridge branch, which is arranged between a negative input connection (-) and the centre tap (0), wherein the upper bridge branch has at least two controlled upper semiconductor elements (T1, T2) and the lower bridge branch has at least two controlled lower semiconductor elements (T3, T4), characterized in that, in each of the two bridge branches, the controlled semiconductor elements (T1, T2; T3, T4) are arranged parallel next to one another with a maximum overlap (z).

Description

Converter arrangement

The present invention relates to a converter arrangement comprising an upper bridge branch, which is arranged between a positive input connection and a centre tap, and a lower bridge branch, which is arranged between a negative input connection and the centre tap, wherein the upper bridge branch has at least two controlled upper semiconductor elements and the lower bridge branch has at least two controlled lower semiconductor elements.

Such a converter arrangement is known for example from DE 10 2010 008 426 B4.

Such a converter arrangement generates, for example, an AC voltage from a DC voltage. In this case, three voltage levels are available, namely the positive input voltage, the negative input voltage and a voltage at the centre tap or zero point. The AC voltage is then generated by controlled switching of the controlled semiconductor elements.

Known converter topologies for such three-stage inverters are known as NPC1 and NPC2.

A converter arrangement is usually provided for one phase. If a polyphase system is intended to be fed, more converter arrangements of this type are required. For example, for a three-phase system three converter arrangements would be required.

The current changes as a result of the controlled switching of the respective semiconductor elements. A current which changes with time, when coupled to an inductive circuit, will lead to an induced voltage which may in turn lead to losses.

The invention is based on the object of specifying an inverter having a low- inductance configuration. This object is achieved in the case of a converter arrangement of the type mentioned in the introduction by virtue of the fact that, in each of the two bridge branches, the controlled semiconductor elements are arranged parallel next to one another with a maximum overlap.

A current change in a conductor generates an electric field. Said field induces a current in a conductor running parallel. Said current brings about a reduction of the inductance of the entire conductor loop. The semiconductor elements are then arranged such that they form a conductor loop of this type in a bridge branch. The inductance can be kept low as a result. The larger the overlap between the semiconductors, the smaller, too, the area within the conductor loop. The smaller said area can be kept, the lower the induced inductance can be kept. Thus the inductance of the entire circuit arrangement can then be kept low. The distance between the controlled semiconductor elements depends on the conditions. In particular, in the case of relatively high currents of tens of Amps or even above 100 Amps, a distance that allows sufficient heat dissipation may become necessary. In this case, a minimum distance is of the order of magnitude of 10 mm, for example. In this case, the overlap is implemented so as to result in an overlap region as viewed in the direction of the current flow. The two controlled semiconductor elements thus overlap perpendicularly to the direction of the current flow. Preferably, the two controlled semiconductor elements have a total extent, and a ratio between the overlap and the total extent is > 0.1 , in particular > 0.6. In this case, the "total extent" should be measured in the direction of the current flow, from the end of one controlled semiconductor element to the opposite end of the other controlled semiconductor element. Preferably, a maximum of one uncontrolled semiconductor element is arranged between the controlled semiconductor elements of a bridge branch. Provision can therefore be made for arranging a diode, used as a freewheeling diode, between the controlled semiconductor elements, without the inductance being appreciably increased in this case. Said diode serves to accept current during the commutation and thus provides a path through which the inducing current or the induced current can flow.

Preferably, in each bridge branch the controlled semiconductor elements are arranged with the same forward direction. During the commutation, in a simplified explanation, one semiconductor element then accepts the current from the other semiconductor element, such that the current decreases through one semiconductor element and increases through the other semiconductor element. The currents induced as a result mutually influence one another positively.

Preferably, the controlled upper semiconductor elements are arranged on a common first substrate and the controlled lower semiconductor elements are arranged on a common second substrate and the first substrate and the second substrate are separated from one another. The switching functions of the converter arrangement are thus split into two subfunctions and these subfunctions are also arranged in a manner spatially separated from one another. In other words, therefore, the upper bridge branch is arranged on a first substrate and the lower bridge branch is arranged on a second substrate. A spatial separation of the two switching functions can thus be achieved in a simple manner, such that a mutual influencing of the upper bridge branch and of the lower bridge branch does not negatively influence the inductance of the converter arrangement. In this case, it is preferred for the first substrate and the second substrate to be arranged on a common carrier. The respective connections necessary for feeding and dissipating the electrical energy and for connecting control lines can then be provided on a single carrier.

Preferably, the upper bridge branch has at least two parallel-connected groups of controlled upper semiconductor elements and the lower bridge branch has at least two parallel-connected groups of controlled lower semiconductor elements. Thus the performance of the converter arrangement can be dimensioned practically arbitrarily according to stipulations, without the need to use in each case semiconductor elements which are designed for correspondingly high currents. Rather, a plurality of semiconductor element groups can be connected in parallel, each of which then need only carry part of the current.

Preferably, at least two groups of each bridge branch are arranged on substrates separated from one another. This facilitates production. In this case there are then a corresponding number of first substrates and a corresponding number of second substrates.

Preferably, controlled semiconductor elements which are arranged on the same substrate are at a distance from one another which is less than a distance between controlled semiconductor elements which are arranged on different substrates. The substrates can be formed by DCBs, for example. Said substrates are then arranged relative to one another such that the coupling-in of one substrate has an effect on the neighbouring substrate of the same type. A corresponding influencing of first substrates and second substrates, that is to say substrates of the upper bridge branch and substrates of the lower bridge branch, is avoided by this arrangement, however. Preferably, the carrier has upper control connections for the controlled upper semiconductor elements and lower control connections for the controlled lower semiconductor elements, wherein connections of the controlled upper semiconductor elements to the upper control connections run in a crossover-free manner with respect to connections of the controlled lower semiconductor elements to the lower control connections. It is thus possible to use topologies for the upper bridge branch and the lower bridge branch in which a plurality of semiconductor elements are connected in parallel, without the drive signals, to put it more precisely the lines for the drive signals, crossing one another. The crossing of such lines could have the effect that parallel switching functions could be driven differently and uncontrolled states or oscillations could arise. This is prevented by the crossover-free routing of the connections.

Preferably, the controlled upper semiconductor elements comprise a first controlled upper semiconductor element and a second controlled upper semiconductor element and the upper control connections comprise a first upper control connection and a second control connection, wherein a connection between the first controlled upper semiconductor element and the first upper control connection runs in a crossover-free manner with respect to a connection between the second controlled upper

semiconductor element and the second upper control connection. In this case, too, disturbances as a result of a mutual inductance can be avoided by virtue of the crossover-free routing of the connections.

It is also preferred for the controlled lower semiconductor elements to comprise a controlled first lower semiconductor element and a second controlled lower semiconductor element and the lower control connections to comprise a first lower control connection and a second lower control connection, wherein a connection between the first controlled lower semiconductor element and the first lower control connection runs in a crossover-free manner with respect to a connection between the second controlled lower semiconductor element and the second lower control connection. With regard to the driving, the same substantive matter as for the upper bridge branch holds true for the lower bridge branch.

Preferably, an imaginary line between the individual controlled

semiconductor elements forms a comb-shaped structure. This holds true primarily if a plurality of groups of controlled upper semiconductor elements and/or of controlled lower semiconductor elements are used.

Preferably, the controlled semiconductor elements are embodied as transistor, IGBT or MOSFET. The semiconductor elements can thus be embodied as switches which can be driven by control signals.

Preferably, diodes are respectively assigned to the controlled

semiconductor elements. The diodes can then accept the respective current for example after the switching-off of the controlled semiconductor elements.

The invention is described below on the basis of preferred exemplary embodiments in conjunction with the drawing, in which: Figure 1 shows a circuit arrangement of a first embodiment of a

converter arrangement,

Figure 2 shows a second embodiment of a circuit arrangement of a converter arrangement, Figure 3 shows a schematic illustration of the arrangement of elements of the converter arrangement according to Figure

1 , Figure 4 shows a schematic illustration of the arrangement of

elements of the converter arrangement according to Figure

2,

Figure 5 shows a schematic illustration of the arrangement of

elements of the converter arrangement according to Figure 2 in a modified embodiment, and

Figure 6 shows a schematic illustration for elucidating the overlap. Figure 1 schematically shows a circuit arrangement of a first embodiment of a converter arrangement 1 comprising an upper bridge branch, which is arranged between a positive input connection + and a centre tap 0, and a lower bridge branch, which is arranged between a negative input connection - and the centre tap.

The upper bridge branch has a first controlled upper semiconductor element T1 and a second controlled upper semiconductor element T2. The lower bridge branch has a first controlled lower semiconductor element T4 and a second controlled lower semiconductor element T3. The controlled semiconductor elements T1 -T4 can be embodied as transistors, as IGBTs, as MOSFETs or the like. The controlled semiconductor elements should be able to handle currents having an order of magnitude of 100 A or more.

A diode D1 is arranged in an antiparallel configuration with the first controlled upper semiconductor element and a diode D2 is arranged in an antiparallel configuration with the second controlled upper semiconductor element. A diode D5 is arranged between the centre tap 0 and a point 2 between the two upper controlled semiconductor elements T1 , T2, the forward direction of said diode pointing away from the centre tap 0. In the lower bridge branch, a first controlled lower semiconductor element T4 and a second controlled lower semiconductor element T3 are arranged between the AC output AC and the negative input connection. A diode D4 is connected in a parallel configuration with the first lower controlled semiconductor element T4 and a diode D3 is connected in an antiparallel configuration with the second lower controlled semiconductor element T3. A diode D6 is arranged between a point 3 between the two controlled lower semiconductor elements T3, T4 and the centre tap 0, the forward direction of said diode being directed towards the centre tap 0. The controlled semiconductor elements T1 -T4 are operated as electronic switches. The converter arrangement illustrated in Figure 1 is also described as "NPC1 " topology. Other designations are "l-Type" or "NPC". A three-level inverter is involved which is known per se. Figure 1 a shows here the complete topology of the converter arrangement 1 .

In this embodiment, provision is made for separating the upper bridge branch and the lower bridge branch from one another and for also arranging the respective semiconductor elements of the two bridge branches physically on different substrates, as will be described further below. This division is illustrated in Figures 1 b and 1 c.

Figure 2 shows a different topology of a converter arrangement 1 , which is referred to as "NPC2" topology. Other designations are T-Type, MPC, "mixed voltage NPC" or "bi-directional switch NPC". This converter arrangement 1 also comprises an upper bridge branch, in which a first upper controlled semiconductor element T1 and a second controlled semiconductor element T2 are connected in series between a positive input connection + and an AC output AC.

In the upper bridge branch, a diode D1 is arranged in an antiparallel configuration with the first controlled upper semiconductor element T1 . A diode D2 is arranged in series with the second controlled lower

semiconductor element T2. In a similar manner, in the lower bridge branch, a diode D4 is arranged in an antiparallel configuration with the first controlled lower semiconductor element T4 and a diode D3 is arranged in series with the second lower controlled semiconductor element T3. Here, too, as is illustrated in Figures 2b and 2c, a division into the lower bridge branch (Figure 2b) and into the upper bridge branch (Figure 2c) can be performed and the two bridge branches can also be physically separated from one another. Figure 3 shows the physical arrangement of the individual semiconductor elements of the converter arrangement 1 according to Figure 1 . Elements identical to those in Figure 1 are provided with the same reference signs.

The upper controlled semiconductor elements T1 , T2 are arranged on a first substrate 4. The lower controlled semiconductor elements T3, T4 are arranged on a second substrate 5.

In the present exemplary embodiment, each bridge branch has three parallel-connected groups of controlled semiconductor elements T1 , T2; T3, T4. It can be discerned that the substrates 4, 5 are separated from one another, such that the two different bridge branches can also be arranged in a manner physically separated from one another.

On each substrate 4, 5 the controlled semiconductor elements T1 , T2; T4, T3 are arranged parallel next to one another with a minimum spacing, which will be explained in greater detail further below. A maximum of one uncontrolled semiconductor element, namely the diode D1 , D4 is arranged between the controlled semiconductor elements T1 , T2; T4, T3. An imaginary line that is illustrated in a dashed manner and runs between the individual controlled semiconductor elements T1 -T4 forms a comb- shaped structure.

The substrates 4, 5 are arranged on a common carrier 6.

Figure 4 shows a corresponding arrangement of the semiconductor elements in the configuration of the circuit arrangement according to Figure 2. The NPC2 topology requires two diodes fewer than the NPC1 topology according to Figure 1 .

Here, too, the semiconductor elements T1 , T2, D1 , D2 of the upper bridge branch are arranged on a first substrate 4 and the semiconductor elements T3, T4, D3, D4 of the lower bridge branch are arranged on a second substrate 5. Here, too, there are again in each case three parallel- connected groups of semiconductor elements T1 , T2, D1 , D2; T3, T4, D3, D4 for the upper and the lower bridge branch, respectively, such that the individual semiconductor elements have to be designed in each case only for one third of the maximum current. Furthermore, control connections are illustrated on the carrier 6, namely a first upper control connection G1 for the first controlled upper

semiconductor elements T1 , a second control connection G2 for the second controlled upper semiconductor elements T2, a control connection G4 for the first controlled lower semiconductor elements T4 and a fourth control connection G3 for the second controlled lower semiconductor elements T3.

It can be discerned that firstly the connections of the controlled upper semiconductor elements T1 , T2 to the upper control connections G1 , G2 run in a crossover-free manner with respect to the connections of the controlled lower semiconductor elements T4, T3 to the lower control connections G4, G3. Furthermore, it can be discerned that in each bridge branch, too, the connections between the control connections and the controlled semiconductor elements run in a crossover-free manner with respect to one another. The connection between the first upper control connection G1 and the first controlled upper semiconductor elements T1 runs in a crossover-free manner with respect to the connection between the second upper control connection G2 and the second controlled upper semiconductor elements T2. Correspondingly, a connection between the first lower control connection G4 and the first controlled lower

semiconductor elements T4 runs in a crossover-free manner with respect to connections between the second lower control connection G3 and the second controlled lower semiconductor elements T3.

Here, too, an imaginary line depicted in a dashed fashion between the individual controlled semiconductors forms a comb-shaped structure.

In the arrangement according to Figure 4, too, the controlled

semiconductor elements T1 , T2; T3, T4 in each of the two bridge branches are arranged parallel next to one another with a minimum spacing. At most one diode D1 ; D4, that is to say one uncontrolled semiconductor element, is provided between the two controlled semiconductor elements T1 , T2;

T3, T4.

In the arrangement according to Figure 4, the semiconductor elements T1 , T2 arranged on the same substrate 4 are at a distance from one another which is smaller than a distance between semiconductor elements T3, T4 arranged on the other substrate 5.

The distance between controlled semiconductor elements T1 , T2; T3, T4 on one substrate can be of the order of magnitude of 10 mm, for example, while a distance between semiconductor elements T1 , T4, arranged on different substrates 4, 5 can be of the order of magnitude of 15 mm.

Figure 5 shows a modified configuration of the semiconductor elements according to the circuit arrangement from Figure 2. Here the controlled semiconductor elements T1 , T2; T3, T4 are even more closely adjacent than in the configuration from Figure 4. The connections between control connections and the controlled semiconductor elements T1 -T4 are omitted for reasons of clarity. By contrast, the imaginary line between the semiconductor elements T1 -T4 is depicted in a dashed fashion, said imaginary line once again forming a comb-like structure. The function will be explained on the basis of the substrate illustrated on the far left in Figure 5.

It shall be assumed that the first controlled lower semiconductor element T4 is turned on at a specific point in time, such that a current flows from the AC output AC to the negative input connection. At a later point in time, the first controlled lower semiconductor element T4 is turned off and the second lower controlled semiconductor element T3 is turned on, such that the current flows from the AC output AC to the centre tap 0. Between these two points in time, the current through the first controlled lower semiconductor element T4 decreases and the current through the second controlled semiconductor element T3 increases. Both semiconductor elements T3, T4 are arranged with identical forward directions.

The current change over time (di/dt) and the area in the loop between the first controlled lower semiconductor element T4 and the second controlled lower semiconductor element T3 are crucial for the inductance of the arrangement. The smaller said area, the lower the inductance of the circuit is also kept.

A current change in a conductor generates an electric field. Said field induces a current in a conductor running parallel. Said current brings about a reduction of the inductance of the entire conductor loop formed by a connection of the two controlled lower semiconductor elements T3, T4 via the AC output AC.

The same effect also acts across substrates, i.e. the current change in the second controlled lower semiconductor element T3 has a corresponding effect on the first controlled lower semiconductor element T4 of the neighbouring substrate 5. Accordingly, the inductance of the circuit arrangement can also be kept low by this cross-substrate effect. Figure 6 shows a schematic illustration for elucidating the overlap of the controlled semiconductor elements. Elements identical to those in the preceding drawings are provided with the same reference signs. The illustration shows the semiconductor elements T3, T4 arranged between the AC output AC and the negative input connection minus and, respectively, the centre tap 0. The "conduction loop" which is "spanned^" by the controlled semiconductor elements T3, T4 is illustrated in a hatched manner 10.

The maximum extent of the controlled semiconductor elements T3, T4 is designated by "y". The maximum extent is the distance between the end of one controlled semiconductor element T3 and the opposite end of the other controlled semiconductor element T4.

Furthermore, the overlap is depicted by "z^". The overlap is the distance between the two other ends of the controlled semiconductor elements T3, T4, in other words the overlap between the controlled semiconductor elements T3, T4, when looking perpendicularly to the direction of the current flow. The current flow is always between the AC output AC and the negative input connection or the centre tap 0.

An optimum size of the conduction loop illustrated in a hatched manner can be influenced in two different ways. Firstly, it is possible to minimize the distance "x" perpendicularly to the direction of the current flow.

Secondly, it is also possible to minimize the extent of the controlled semiconductor elements T3, T4. Said extent can be prevented by making the overlap small. Therefore, the overlap is chosen such that z > 0.1 ^* y and the overlap z is preferably chosen such that z > 0.6 ^* y.

The overlap is therefore at least 10%, preferably at least 60%, of the distance y. In this way, the size of the conduction loop, said size being crucial for the inductance of the circuit arrangement, can be kept small.

Claims

Converter arrangement (1 ) comprising an upper bridge branch, which is arranged between a positive input connection (+) and a centre tap (0), and a lower bridge branch, which is arranged between a negative input connection (-) and the centre tap (0), wherein the upper bridge branch has at least two controlled upper semiconductor elements (T1 , T2) and the lower bridge branch has at least two controlled lower semiconductor elements (T3, T4), characterized in that, in each of the two bridge branches, the controlled semiconductor elements (T1 , T2; T3, T4) are arranged parallel next to one another with a maximum overlap (z).

Converter arrangement according to Claim 1 , characterized in that the two controlled semiconductor elements have a total extent (y) and where a ratio between the overlap (z) and the total extent y > 0.1 , in particular > 0.6.

Converter arrangement according to Claim 1 or 2, characterized in that a maximum of one uncontrolled semiconductor element (D1 , D4) is arranged between the controlled semiconductor elements (T1 , T2; T3, T4) of a bridge branch.

Converter arrangement according to any of Claims 1 to 3,

characterized in that in each bridge branch the controlled

semiconductor elements (T1 , T2; T3, T4) are arranged with the same forward direction.

Converter arrangement according to any of Claims 1 to 4,

characterized in that the controlled upper semiconductor elements (T1 , T2) are arranged on a common first substrate (4) and the -2 - controlled lower semiconductor elements (T3, T4) are arranged on a common second substrate (5) and the first substrate (4) and the second substrate (5) are separated from one another.

Converter arrangement according to Claim 5, characterized in that the first substrate (4) and the second substrate (5) are arranged on a common carrier (6).

Converter arrangement according to any of Claims 1 to 6,

characterized in that the upper bridge branch has at least two parallel-connected groups of controlled upper semiconductor elements (T1 , T2) and the lower bridge branch has at least two parallel-connected groups of controlled lower semiconductor elements (T3, T4).

Converter arrangement according to Claim 7, characterized in that at least two groups of each bridge branch are arranged on substrates (4, 5) separated from one another.

Converter arrangement according to Claim 7 or 8, characterized in that the controlled semiconductor elements arranged on the same substrates are at a distance from one another which is smaller than a distance between controlled semiconductor elements arranged on different substrates.

Converter arrangement according to any of Claims 6 to 9,

characterized in that the carrier (6) has upper control connections (G1 , G2) for the controlled upper semiconductor elements (T1 , T2) and lower control connections (G3, G4) for the controlled lower semiconductor elements (T3, T4), wherein connections of the - 3 - controlled upper semiconductor elements (T1 , T2) to the upper control connections (G1 , G3) run in a crossover-free manner with respect to connections of the controlled lower semiconductor elements (T3, T4) to the lower control connections (G3, G4).

1 1 . Converter arrangement according to Claim 10, characterized in that the controlled upper semiconductor elements (T1 , T2) comprise a first controlled upper semiconductor element (T1 ) and a second controlled upper semiconductor element (T2) and the upper control connections (G1 , G2) comprise a first upper control connection (G1 ) and a second upper control connection (G2), wherein a connection between the first controlled upper semiconductor element (T1 ) and the first upper control connection (G1 ) runs in a crossover-free manner with respect to a connection between the second controlled upper semiconductor element (T2) and the second upper control connection (G2).

12. Converter arrangement according to Claim 10 or 1 1 , characterized in that the controlled lower semiconductor elements (T3, T4) comprise a first controlled lower semiconductor element (T4) and a second controlled lower semiconductor element (T3) and the lower control connections (G3, G4) comprise a first lower control connection (G4) and a second lower control connection (G3), wherein a connection between the first controlled lower semiconductor element (T4) and the first lower control connection (G4) runs in a crossover-free manner with respect to a connection between the second controlled lower semiconductor element (T3) and the second lower control connection (G3). - 4 -

13. Converter arrangement according to any of Claims 1 to 12,

characterized in that an imaginary line between the individual controlled semiconductors (T1 -T4) forms a comb-shaped structure.

14. Converter arrangement according to any of Claims 1 to 13,

characterized in that the controlled semiconductor elements (T1 -T4) are embodied as transistor, IGBT or MOSFET.

15. Converter arrangement according to any of Claims 1 to 14,

characterized in that diodes (D1 -D4) are respectively assigned controlled semiconductor elements (T1 -T4).