WO2017197958A1 - 阵列基板及其制备方法、触摸屏 - Google Patents

阵列基板及其制备方法、触摸屏 Download PDF

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Publication number
WO2017197958A1
WO2017197958A1 PCT/CN2017/075549 CN2017075549W WO2017197958A1 WO 2017197958 A1 WO2017197958 A1 WO 2017197958A1 CN 2017075549 W CN2017075549 W CN 2017075549W WO 2017197958 A1 WO2017197958 A1 WO 2017197958A1
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WIPO (PCT)
Prior art keywords
touch
connection
array substrate
layer
insulating layer
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PCT/CN2017/075549
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English (en)
French (fr)
Inventor
史大为
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US15/574,115 priority Critical patent/US10133409B2/en
Publication of WO2017197958A1 publication Critical patent/WO2017197958A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present disclosure belongs to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a touch screen.
  • Touch screens also known as touch panels
  • touch panels have been widely used in various electronic products and widely accepted by consumers. Therefore, the industry has been working to improve touch screen display technology to bring a better user experience to consumers.
  • the touch screen can be divided into an On-Cell touch screen and an In-Cell touch screen.
  • the In-Cell touch screen can be further divided into a composite in-cell (Hybrid In-Cell, HIC for short) capacitive touch screen and a fully in-cell (Full In-Cell, FIC) capacitive touch screen.
  • the present disclosure provides an array substrate including a thin film transistor, a common electrode layer, a touch line, a touch connection end, and a connection electrode, wherein the touch connection end and the touch line are disposed in different layers, wherein the connection electrode The first connecting electrode disposed in the same layer as the touch line and the second connecting electrode disposed in the same layer as the common electrode layer, and wherein the touch line passes through the first connecting electrode and the touch The connection ends are connected, and the common electrode layer is connected to the touch connection terminal through the second connection electrode.
  • the array substrate further includes an auxiliary connection end extending from one side of the touch line, wherein the auxiliary connection end is disposed in the same layer as the touch control line, and the auxiliary connection end passes the first
  • the connection electrode is connected to the touch connection end, and the auxiliary connection end and the touch connection end at least partially overlap.
  • the array substrate further includes a first insulating layer disposed between the common electrode layer and the touch connection terminal and a second insulating layer disposed on the first insulating layer, wherein the touch line And the auxiliary connection end is disposed at the first insulation layer and the second insulation
  • the first insulating layer is provided with a first via hole in a region corresponding to the auxiliary connecting end and the touch connecting end
  • the first connecting electrode is disposed in the first via hole
  • the first insulating layer is provided with a second via hole in a region corresponding to the non-overlapping end of the touch connection end and the auxiliary connection end
  • the second insulating layer is provided with a third via hole
  • the first The second via hole at least partially overlaps the third via hole
  • the second connection electrode is disposed in the second via hole and the third via hole.
  • the second via and the third via are concentrically arranged.
  • the first via hole, the second via hole and the third via hole are both tapered holes, and an aperture of the tapered hole is gradually reduced in a direction away from the touch connection terminal.
  • the second via has a maximum aperture that is less than or equal to a minimum aperture of the third via.
  • a portion of the touch connection terminal does not overlap the touch line.
  • the touch connection terminal and the touch control line do not overlap each other.
  • the array substrate further includes a data line, and the data line is disposed in the same layer as the touch line and is disposed in parallel and spaced apart from the touch line.
  • the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, and a source and a drain, which are sequentially stacked, and the touch line is disposed in the same layer as the source and drain.
  • the touch connection terminal is disposed in the same layer as the gate.
  • the touch line and the source and drain electrodes adopt a three-layer structure, which is sequentially prepared by using titanium, aluminum, or titanium.
  • the gate and the touch connection are prepared using molybdenum.
  • the present disclosure also provides a touch screen including the above array substrate.
  • the present disclosure also provides a method for preparing an array substrate, comprising:
  • the second connection electrode is disposed in the second via hole and the third via hole, and the second connection electrode is connected to the common electrode layer and the touch connection terminal.
  • the step of forming a pattern including the touch line and the first connection electrode on the first insulating layer further includes: forming an auxiliary connection end extending from one side of the touch line, wherein the auxiliary connection end The orthographic projection at least partially overlaps the first via, the auxiliary connection forming a first connection electrode in the first via, and the auxiliary connection is connected to the touch through the first connection electrode Control the connection.
  • the step of forming a pattern including the touch connection terminal includes forming a pattern including the touch connection terminal and the gate layer in the same layer by the same patterning process.
  • the step of forming a pattern including the touch line and the first connection electrode on the first insulating layer includes forming a pattern including a touch line, a first connection electrode, and a source and drain using the same patterning process.
  • the first via hole, the second via hole, and the third via hole are both tapered holes, and the aperture of the tapered hole is gradually reduced in a direction away from the touch connection terminal, and The maximum aperture of the second via is less than or equal to the minimum aperture of the third via.
  • the touch line and the source drain adopt a three-layer structure
  • the three-layer structure is sequentially prepared by using titanium, aluminum, and titanium
  • the touch connection end is prepared by using molybdenum.
  • the touch screen of the present disclosure and the method of fabricating the array substrate have embodiments similar or identical to those of the above array substrate, and accordingly have similar or identical advantages and advantageous technical effects.
  • 1 is a partial cross-sectional view of a conventional array substrate
  • FIG. 2 is a perspective view showing a partial structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a partial cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • 5A, 5B, 5C, and 5D are partial cross-sectional views corresponding to a preparation flow of the array substrate shown in FIG. 3;
  • FIG. 6 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • the structure in which the common electrode layer in the array substrate is connected to the touch line is as shown in FIG.
  • An insulating layer 3 is disposed between the common electrode layer 1 and the connection layer 2 of the touch line.
  • the insulating layer 3 is provided with a via hole.
  • the common electrode layer 1 is overlapped with the connection layer 2 through via holes to realize connection of the common electrode layer 1 to the touch line.
  • the connection layer 2 is disposed in the same layer as the source and drain electrodes in the thin film transistor, and is formed by a Ti/Al/Ti three-layer metal structure having a low resistivity.
  • connection layer 2 of the touch line is formed by a Ti/Al/Ti three-layer metal structure.
  • Ti will be oxidized to form titanium oxide in an environment containing plasma or from a high temperature environment to a low temperature environment.
  • the adhesion of the titanium oxide to the surface of the connection layer 2 greatly increases the contact resistance of the common electrode layer 1 and the connection layer 2, resulting in poor touch and display. Further, the titanium oxide adhering to the surface of the connection layer 2 is not water-soluble and is difficult to remove.
  • FIG. 2 is a partial perspective view of the array substrate of the present embodiment
  • FIG. 3 is a partial cross-sectional view of the array substrate taken along line A-A' of FIG. 2.
  • the array substrate includes a thin film transistor and a common electrode layer 1 on the thin film transistor, and a touch line 4.
  • the array substrate further includes a touch connection terminal 7.
  • the touch connection terminal 7 and the touch control line 4 are disposed in different layers.
  • the touch line 4 and the common electrode layer 1 are connected by a connection electrode.
  • the connection electrode includes a first connection electrode 5 and a second connection electrode 6.
  • the touch line 4 is connected to the touch connection terminal 7 through the first connection electrode 5.
  • the common electrode layer 1 is connected to the touch connection terminal 7 via the second connection electrode 6.
  • At least a portion of the touch connection terminal 7 does not overlap the touch line 4.
  • a portion of the touch connection terminal 7 does not overlap the touch line 4.
  • a portion of the touch connection end 7 does not overlap the touch line 4, and the remaining portion of the touch connection end 7 overlaps with the touch line 4.
  • overlapping refers to The overlap of the projections in the direction perpendicular to the plane of the board.
  • the touch connection terminal 7 and the touch control line 4 do not overlap each other. That is to say, the projections of the touch connection end 7 and the touch line 4 in a direction perpendicular to the plane of the array substrate do not overlap each other. This is advantageous because in this case, when the touch connection terminal 7 is provided and the electrical connection of the touch connection terminal 7 to the touch line 4 is implemented, no modification is required and the existing touch line 4 is not affected. In turn, the process complexity is controlled and the touch performance of the touch line is ensured.
  • a first insulating layer 8 and a second insulating layer 9 on the first insulating layer 8 are disposed between the common electrode layer 1 and the touch connection terminal 7.
  • the touch line 4 is located between the first insulating layer 8 and the second insulating layer 9.
  • the touch wire 4 extends on one side to form the auxiliary connection end 10.
  • the auxiliary connecting end 10 and the touch connecting end 7 at least partially overlap, that is, the two at least partially overlap in the forward projection direction (in a direction perpendicular to the plane of the array substrate).
  • the first insulating layer 8 is provided with a first via hole 11 (as shown in FIG.
  • the first insulating layer 8 is provided with a second via hole 12 (as shown in FIG. 5A ) in a region where the corresponding touch connection end 7 and the auxiliary connection end 10 do not overlap, and the second insulating layer 9 is opened and the second via hole 12 is opened.
  • a concentric third via 13 (as shown in FIG. 5C) and a second connection electrode 6 are disposed in the second via 12 and the third via 13.
  • the common electrode layer 1 is connected to the touch connection terminal 7 through the second connection electrode 6, and the auxiliary connection terminal 10 is also connected to the touch connection terminal 7 through the first connection electrode 5, thereby realizing the common electrode layer 1 and the auxiliary connection.
  • Terminal 10 is indirectly connected.
  • the auxiliary connection terminal 10 is connected to the touch line 4 such that the contact resistance between the common electrode layer 1 and the touch line 4 is significantly reduced as a whole.
  • the first via 11, the second via 12, and the third via 13 are both tapered holes.
  • the maximum aperture of the second via 12 is less than or equal to the minimum aperture of the third via 13.
  • the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, and a source and drain electrode which are sequentially stacked.
  • the touch line 4 is disposed in the same layer as the source and drain electrodes, and the touch connection terminal 7 is disposed on the same layer as the gate Set. In this way, the pattern of the touch line 4 and the source and drain electrodes can be formed by the same patterning process, and the pattern of the touch connection terminal 7 and the gate electrode can be formed by the same patterning process. There is no increase in the number of patterning processes compared to existing array substrates.
  • the array substrate of this embodiment further includes a data line 14.
  • the data lines 14 are disposed in the same layer as the touch lines 4 and are disposed in parallel and spaced apart from the touch lines 4. In this way, the data line 14 and the touch line 4 can be formed by the same patterning process without increasing the number of patterning processes.
  • the touch line 4, the auxiliary connection terminal 10, and the source and drain electrodes have a three-layer structure.
  • the three-layer structure is prepared by using titanium, aluminum, and titanium in sequence.
  • the gate and touch connection terminals 7 are prepared using molybdenum. Since the touch connection terminal 7 is made of molybdenum, the contact resistance between the touch connection terminal 7 and the first connection electrode 5 and the second connection electrode 6 is kept at a low level. Compared with the connection layer 2 of the common electrode layer 1 and the touch line in the existing array substrate, the resistance between the common electrode layer 1 and the touch line 4 can be significantly reduced, and the touch and display defects are avoided.
  • the auxiliary connection end 10 of the touch line 4 and the common electrode layer 1 are indirectly connected through the first connection electrode 5, the touch connection end 7 and the second connection electrode 6. Therefore, the resistance between the touch line 4 and the common electrode layer 1 is reduced, thereby avoiding touch and display defects.
  • the touch connection terminal 7 is disposed in the same layer as the gate, and the touch line 4 is disposed in the same layer as the source and drain electrodes. Therefore, the array substrate of the present embodiment does not increase the number of patterning processes compared to the existing array substrate, and does not increase the manufacturing cost.
  • An embodiment of the present disclosure provides a method of fabricating an array substrate for forming the array substrate described above.
  • 4 is a flow chart of a method of fabricating an array substrate of the embodiment. As shown in FIG. 4, the method includes the following steps:
  • S1 forms a graphic including a touch connection end
  • Steps S1-S5 are described in detail below in conjunction with Figures 5A-5D.
  • Step S1 forming a pattern including the touch connection terminal 7.
  • this step also includes forming a pattern including the gate in the same layer using the same patterning process. That is to say, the pattern of the gate of the thin film transistor and the pattern of the touch connection terminal 7 are formed in the same layer by the same patterning process. Compared with the existing preparation process of the array substrate, although the touch connection terminal 7 is added in this step, the number of patterning processes is not increased.
  • the shape of the touch connection end 7 may be rectangular, circular, elliptical or the like. As long as the touch connection end 7 is of sufficient size, it can be simultaneously contacted with the first connection electrode and the second connection electrode formed subsequently.
  • gate and touch connection terminals 7 are made of molybdenum and have a small electrical resistance.
  • Step S2 forming a first insulating layer 8 on the touch connection end 7, and a first via hole and a second via hole are formed in the first insulating layer 8.
  • the first via hole 11 and the second via hole 12 are both tapered holes and the aperture near the opening (bottom opening) of the touch connection terminal 7 is smaller than the opening away from the touch connection terminal 7 (top opening).
  • the aperture As shown in FIG. 5A, in an example, the apertures of the first via hole 11 and the second via hole 12 are gradually reduced in a direction away from the touch connection terminal 7. Thus, it is advantageous to form electrodes in the first via hole 11 and the second via hole 12.
  • Step S3 forming a pattern on the first insulating layer 8 including the touch line 4 and the auxiliary connection end 10 extending toward one side of the touch line 4, and the orthographic projection of the auxiliary connection end 10 and the first via hole 11 are at least partially
  • the first connection electrode 5 is formed in the first via hole 11 , and the first connection electrode 5 is connected to the auxiliary connection terminal 10 and the touch connection terminal 7 .
  • the pattern of the touch line 4, the auxiliary connection terminal 10, and the first connection electrode 5 is formed by the same patterning process, and a pattern including the source and the drain is formed at the same time.
  • the auxiliary connection end 10 of the touch line 4 and the touch connection end 7 are connected through the first connection electrode 5, and the above structure is formed by the same patterning process, which simplifies the preparation process.
  • the touch wire 4 and the auxiliary connection terminal 10 have a three-layer structure.
  • the three layer structure comprises a stack of titanium, aluminum, titanium. This three-layer structure is not only mature but also low in cost.
  • Step S4 forming a second insulating layer 9 on the touch line 4, and a third via 13 concentric with the second via 12 is formed in the second insulating layer.
  • the third via 13 is a tapered hole and the second via 12
  • the maximum aperture is less than or equal to the minimum aperture of the third via 13.
  • FIG. 5C shows a case where the second via hole 12 and the third via hole 13 are concentrically arranged.
  • the present disclosure is not limited thereto as long as the top opening of the second via hole 12 and the bottom opening of the third via hole 13 at least partially overlap to form a conductive path at a subsequent stage.
  • the top opening of the second via 12 is not covered by the second insulating layer 9 such that the top opening of the second via 12 completely falls within the bottom opening of the third via 12. In another embodiment, the top opening of the second via 12 just overlaps the bottom opening of the third via 12.
  • Step S5 forming a pattern including the common electrode layer 1 on the second insulating layer 9, and forming a second connection electrode 6 in the second via hole 12 and the third via hole 13, and connecting the second connection electrode 6 to the common electrode layer 1 And the touch connection terminal 7.
  • the second connection electrode 6 is formed in the second via hole 12 and the third via hole 13 so as to pass through the second connection electrode. 6 The connection between the common electrode layer 1 and the touch connection terminal 7 is achieved.
  • the auxiliary connection end 10 of the touch line 4 is indirectly connected to the common electrode layer 1 through the first connection electrode 5, the touch connection terminal 7 and the second connection electrode 6. Since the touch connection terminal 7 is prepared by using molybdenum, the resistance between the touch line and the common electrode layer 1 can be reduced, and the touch and display defects are avoided. In addition, the touch connection terminal 7 is disposed in the same layer as the gate, and the touch line 4 is disposed in the same layer as the source and drain electrodes. Therefore, the preparation method of the present embodiment does not increase the number of patterning processes compared to the existing preparation method, and does not increase the preparation cost.
  • FIG. 6 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure.
  • the right side of FIG. 6 is the same as FIG. 5D, and the thin film transistor region of the array substrate is shown on the left side.
  • the touch connection terminal 7 is disposed in the same layer as the gate 7' of the thin film transistor
  • the auxiliary connection terminal 10 (and the touch line 4) is disposed in the same layer as the source and drain electrodes 10'.
  • FIG. 6 merely illustrates layers and/or components related to the inventive concepts of the present disclosure. For example, in FIG. 6, only the source drain and the gate of the thin film transistor are shown in the thin film transistor region, and the active layer is not shown.
  • An embodiment of the present disclosure provides a touch screen including the array substrate described above.
  • the touch screen can be specifically a FIC capacitive touch screen, and is applied to any display function and touch function of a liquid crystal display panel, a mobile phone, a tablet computer, a digital camera, a navigation device, and the like.
  • the product or component not only avoids the phenomenon of poor touch and display, but also does not increase the number of patterning processes or increase the manufacturing cost compared to the existing touch screen.
  • the touch line in the array substrate and the common electrode layer are connected through the first connection electrode and the second connection electrode, and the first connection electrode is connected to the touch connection end, and the second connection electrode
  • the first connecting electrode and the second connecting electrode are indirectly connected through the touch connecting end, so that the structure is directly contacted and connected with the auxiliary connecting end of the common electrode layer and the touch line.
  • the touch panel of the present disclosure includes the array substrate, which can significantly reduce the contact resistance between the common electrode layer and the touch line, thereby effectively avoiding touch and display defects of the touch screen.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种阵列基板及其制备方法、触摸屏。该阵列基板包括薄膜晶体管、公共电极层（1）、触控线（4）、触控连接端（7）和连接电极（5、6）。所述触控连接端（7）与所述触控线（4）异层设置。所述连接电极（5、6）包括与所述触控线（4）同层设置的第一连接电极（5）和与所述公共电极层（1）同层设置的第二连接电极（6）。所述触控线（4）通过所述第一连接电极（5）与所述触控连接端（7）连接，并且所述公共电极层（1）通过所述第二连接电极（6）与所述触控连接端（7）连接。公共电极层（1）与触控线（4）通过触控连接端（7）间接连接，减小公共电极层（1）与触控线（4）之间的电阻，避免显示和触控不良。

Description

阵列基板及其制备方法、触摸屏
相关专利申请
本申请主张于2016年5月20日提交的中国专利申请No.201610342304.5的优先权，其全部内容通过引用结合于此。
技术领域
本公开属于显示技术领域，并且具体涉及一种阵列基板及其制备方法、触摸屏。
背景技术
触摸屏又称为触摸面板，其己经在各种电子产品中广泛应用并被消费者广泛接受，因此，业界一直致力于提高触摸屏显示技术以给消费者带来更好的用户体验。
在现有的内嵌式电容触摸屏中，触摸屏可分为On-Cell触摸屏和In-Cell触控屏。In-Cell触控屏又可分为复合内嵌式(Hybrid In-Cell，简称HIC)电容触摸屏和完全内嵌式(Full In-Cell，简称FIC)电容触摸屏。
发明内容
本公开提供一种阵列基板，包括薄膜晶体管、公共电极层、触控线、触控连接端和连接电极，其中所述触控连接端与所述触控线异层设置，其中所述连接电极包括与所述触控线同层设置的第一连接电极和与所述公共电极层同层设置的第二连接电极，以及其中所述触控线通过所述第一连接电极与所述触控连接端连接，并且所述公共电极层通过所述第二连接电极与所述触控连接端连接。
例如，所述阵列基板还包括从所述触控线的一侧延伸出的辅助连接端，其中所述辅助连接端与所述触控线同层设置，所述辅助连接端通过所述第一连接电极与所述触控连接端连接，并且所述辅助连接端与所述触控连接端至少部分重叠。
例如，所述阵列基板还包括设置在所述公共电极层和所述触控连接端之间的第一绝缘层和位于所述第一绝缘层上的第二绝缘层，其中所述触控线和所述辅助连接端设置在所述第一绝缘层与所述第二绝缘 层之间，其中所述第一绝缘层在对应所述辅助连接端与所述触控连接端重叠的区域开设有第一过孔，所述第一连接电极设置于所述第一过孔中，以及其中所述第一绝缘层在对应所述触控连接端与所述辅助连接端未重叠的区域开设有第二过孔，所述第二绝缘层开设有第三过孔，所述第二过孔与所述第三过孔至少部分重叠，并且所述第二连接电极设置于所述第二过孔和所述第三过孔中。
例如，所述第二过孔和所述第三过孔同心设置。
例如，所述第一过孔、所述第二过孔和所述第三过孔均为锥形孔，并且所述锥形孔的孔径在远离所述触控连接端的方向上逐渐缩小。
例如，所述第二过孔的最大孔径小于或等于所述第三过孔的最小孔径。
例如，所述触控连接端的一部分与所述触控线不重叠。
例如，所述触控连接端与所述触控线不相互重叠。
例如，所述阵列基板还包括数据线，所述数据线与所述触控线同层设置且与所述触控线平行、间隔设置。
例如，所述薄膜晶体管包括依次层叠设置的栅极、栅绝缘层、有源层以及源漏极，并且所述触控线与所述源漏极同层设置。
例如，所述触控连接端与所述栅极同层设置。
例如，所述触控线和所述源漏极采用三层结构，所述三层结构依次采用钛、铝、钛制备。
例如，所述栅极和所述触控连接端采用钼制备。
本公开还提供一种触摸屏，包括上述阵列基板。
本公开还提供一种阵列基板的制备方法，包括：
形成包括触控连接端的图形；
在所述触控连接端上沉积第一绝缘层，并且在所述第一绝缘层中形成第一过孔和第二过孔；
在所述第一绝缘层上形成包括触控线和第一连接电极的图形，其中所述第一连接电极设置于所述第一过孔中；
在形成有所述触控线和所述第一连接电极的图形的所述第一绝缘层上沉积第二绝缘层，并且在所述第二绝缘层中形成第三过孔，其中所述第三过孔与所述第二过孔至少部分重叠；以及
在所述第二绝缘层上形成包括公共电极层和第二连接电极的图形， 其中所述第二连接电极设置于所述第二过孔和所述第三过孔中，并且所述第二连接电极连接所述公共电极层和所述触控连接端。
例如，在所述第一绝缘层上形成包括触控线和第一连接电极的图形的步骤还包括：形成从所述触控线的一侧延伸出的辅助连接端，其中所述辅助连接端的正投影与所述第一过孔至少部分重叠，所述辅助连接端在所述第一过孔中形成第一连接电极，并且所述辅助连接端通过所述第一连接电极连接到所述触控连接端。
例如，形成包括触控连接端的图形的步骤包括：采用同一构图工艺同层形成包括触控连接端和栅极的图形。
例如，在所述第一绝缘层上形成包括触控线和第一连接电极的图形的步骤包括：采用同一构图工艺，形成包括触控线、第一连接电极和源漏极的图形。
例如，所述第一过孔、所述第二过孔和所述第三过孔均为锥形孔，所述锥形孔的孔径在远离所述触控连接端的方向上逐渐缩小，并且所述第二过孔的最大孔径小于或等于所述第三过孔的最小孔径。
例如，所述触控线和所述源漏极采用三层结构，所述三层结构依次采用钛、铝、钛制备，并且所述触控连接端采用钼制备。
本公开的触摸屏以及阵列基板的制备方法具有与上述阵列基板相似或相同的实施例，并且相应地具有相似或相同的优点和有益技术效果。
附图说明
图1为现有的阵列基板的局部剖视图；
图2为本公开一实施例的阵列基板的局部结构透视图；
图3为本公开一实施例的阵列基板的局部剖视图；
图4为本公开一实施例的阵列基板的制备方法的流程框图；
图5A、图5B、图5C和图5D为对应图3所示阵列基板的制备流程的局部剖视图；以及
图6为本公开一实施例的阵列基板的剖视图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附 图和具体实施方式对本公开作进一步详细描述。
附图标记：01、公共电极层；02、连接层；03、绝缘层；1、公共电极层；4、触控线；5、第一连接电极；6、第二连接电极；7、触控连接端；7′、栅极；8、第一绝缘层；9、第二绝缘层；10、辅助连接端；10′、源漏极；11、第一过孔；12、第二过孔；13、第三过孔；14、数据线。
在FIC电容触摸屏中，阵列基板中的公共电极层与触控线连接的结构如图1所示。公共电极层1与触控线的连接层2之间设置有绝缘层3。绝缘层3开设有过孔。公共电极层1通过过孔与连接层2搭接，以实现公共电极层1与触控线连接。在低温多晶硅技术工艺中，连接层2与薄膜晶体管中的源漏极同层设置，并采用电阻率较低的Ti/Al/Ti三层金属结构形成。
发明人发现上述电容触摸屏中至少存在如下问题。触控线的连接层2采用Ti/Al/Ti三层金属结构形成。Ti在包含等离子体的环境中或者从高温环境转换到低温环境将被氧化，形成氧化钛。氧化钛附着在连接层2的表面将极大地增加公共电极层1与连接层2的接触电阻，导致触控和显示不良。并且，附着在连接层2表面的氧化钛为非水溶性，难以去除。
本公开一实施例提供一种阵列基板。图2为本实施例的阵列基板的局部结构透视图，并且图3为沿图2的A-A′线的阵列基板的局部剖视图。如图2和图3所示，阵列基板包括薄膜晶体管和位于薄膜晶体管上的公共电极层1、触控线4。阵列基板还包括触控连接端7。触控连接端7与触控线4异层设置。触控线4与公共电极层1通过连接电极连接。连接电极包括第一连接电极5和第二连接电极6。触控线4通过第一连接电极5与触控连接端7连接。公共电极层1通过第二连接电极6与触控连接端7连接。这样，公共电极层1与触控线4通过触控连接端7间接连接，能够显著减小公共电极层1与触控线4之间的接触电阻。
触控连接端7的至少一部分与触控线4不重叠。
在一实施例中，触控连接端7的一部分与触控线4不重叠。在这种情况下，触控连接端7的一部分与触控线4不重叠，而触控连接端7的其余部分与触控线4重叠。应指出，术语“重叠”是指在与阵列基 板所在平面垂直的方向的投影的重叠。
在一实施例中，触控连接端7与触控线4不相互重叠。也就是说，触控连接端7与触控线4在与阵列基板所在平面垂直的方向的投影不相互重叠。这是有利的，因为在这种情况下，在设置触控连接端7以及实现触控连接端7与触控线4的电连接时，无需改动并且不会影响已有的触控线4，进而控制工艺复杂度并且保证触控线的触控性能。
在一示例中，公共电极层1和触控连接端7之间设置有第一绝缘层8和位于第一绝缘层8上的第二绝缘层9。触控线4位于第一绝缘层8与第二绝缘层9之间。触控线4在一侧延伸形成辅助连接端10。辅助连接端10与触控连接端7至少部分重叠，即，二者在正投影方向上(在垂直于阵列基板所在平面的方向上)至少部分重叠。第一绝缘层8在对应辅助连接端10与触控连接端7重叠的区域开设有第一过孔11(如图5A中所示)，并且第一连接电极5设置于第一过孔11中。第一绝缘层8在对应触控连接端7与辅助连接端10未重叠的区域开设有第二过孔12(如图5A中所示)，第二绝缘层9开设有与第二过孔12同心的第三过孔13(如图5C中所示)，并且第二连接电极6设置于第二过孔12和第三过孔13中。这样，公共电极层1通过第二连接电极6与触控连接端7连接，并且辅助连接端10通过第一连接电极5也与触控连接端7连接，从而实现了公共电极层1与辅助连接端10间接连接。此外，辅助连接端10连接在触控线4上，使得公共电极层1与触控线4之间的接触电阻整体上显著减小。
在示例性实施例中，为了第一连接电极5和第二连接电极6便于形成且结构稳定，第一过孔11、第二过孔12和第三过孔13均为锥形孔。第二过孔12的最大孔径小于或等于第三过孔13的最小孔径。这样，在形成触控线4和辅助连接端10的图形的同时，形成结构稳定的第一连接电极5。相比现有的阵列基板，不仅没有增加构图工艺的次数，而且使辅助连接端10与触控连接端7形成了可靠的搭接。同理，在形成公共电极层1的图形的同时，能够一并形成结构稳定的第二连接电极6。相比现有的阵列基板，不仅没有增加构图工艺的次数，而且使公共电极层1与触控连接端7形成了可靠的搭接。
薄膜晶体管包括依次层叠设置的栅极、栅绝缘层、有源层以及源漏极。触控线4与源漏极同层设置，并且触控连接端7与栅极同层设 置。这样，能够采用同一构图工艺形成触控线4与源漏极的图形，以及采用同一构图工艺形成触控连接端7与栅极的图形。相比现有的阵列基板，没有增加构图工艺的次数。
本实施例的阵列基板还包括数据线14。数据线14与触控线4同层设置且与触控线4平行、间隔设置。这样，能够采用同一构图工艺形成数据线14与触控线4，不会增加构图工艺的次数。
此外，触控线4、辅助连接端10以及源漏极采用三层结构。三层结构依次采用钛、铝、钛制备。栅极和触控连接端7采用钼制备。由于触控连接端7采用钼制备，触控连接端7与第一连接电极5和第二连接电极6之间的接触电阻保持在较低的水平。相比现有的阵列基板中公共电极层1与触控线的连接层2直接接触，能够显著减小公共电极层1与触控线4之间的电阻，避免了触控和显示不良。
本实施例的阵列基板中，触控线4的辅助连接端10与公共电极层1之间依次通过第一连接电极5、触控连接端7和第二连接电极6间接连接。因此，触控线4与公共电极层1之间的电阻减小，避免了触控和显示不良。另外，触控连接端7与栅极同层设置，且触控线4与源漏极同层设置。因此，本实施例的阵列基板相比现有的阵列基板并没有增加构图工艺的次数，也没有增加制备成本。
本公开一实施例提供一种阵列基板的制备方法，该方法用于形成上文所描述的阵列基板。图4为本实施例的阵列基板的制备方法的流程框图。如图4所示，该方法包括以下步骤：
S1形成包括触控连接端的图形；
S2在所述触控连接端上沉积第一绝缘层，并且在所述第一绝缘层中形成第一过孔和第二过孔；
S3在所述第一绝缘层上形成包括触控线和第一连接电极的图形，其中所述第一连接电极设置于所述第一过孔中；
S4在形成有所述触控线和所述第一连接电极的图形的所述第一绝缘层上沉积第二绝缘层，并且在所述第二绝缘层中形成第三过孔，其中所述第三过孔与所述第二过孔至少部分重叠；以及
S5在所述第二绝缘层上形成包括公共电极层和第二连接电极的图形，其中所述第二连接电极设置于所述第二过孔和所述第三过孔中，并且所述第二连接电极连接所述公共电极层和所述触控连接端
在下文中结合图5A-5D详细描述步骤S1-S5。
步骤S1：形成包括触控连接端7的图形。
例如，此步骤还包括采用同一构图工艺同层形成包括栅极的图形。也就是说，薄膜晶体管的栅极的图形与触控连接端7的图形采用同一构图工艺同层形成。相比现有的阵列基板的制备工艺，本步骤中虽然增设了触控连接端7，但并没有增加构图工艺的次数。触控连接端7的形状可以为矩形、圆形、椭圆形等，只要保证触控连接端7具有足够的尺寸，能够与后续形成的第一连接电极和第二连接电极同时接触即可。
此外，栅极和触控连接端7采用钼制备，其电阻较小。
步骤S2：在触控连接端7上形成第一绝缘层8，第一绝缘层8中开设有第一过孔和第二过孔。
如图5A所示，第一过孔11和第二过孔12均为锥形孔且靠近触控连接端7的开口(底部开口)的孔径小于远离触控连接端7的开口(顶部开口)的孔径。如图5A所示，在一示例中，第一过孔11和第二过孔12的孔径在远离触控连接端7的方向上逐渐缩小。这样，有利于在第一过孔11和第二过孔12内形成电极。
步骤S3：在第一绝缘层8上形成包括触控线4以及向触控线4的一侧延伸形成的辅助连接端10的图形，辅助连接端10的正投影与第一过孔11至少部分重叠，并在第一过孔11内形成第一连接电极5，第一连接电极5连接辅助连接端10和触控连接端7。
如图5B所示，在此步骤中，采用同一构图工艺形成触控线4、辅助连接端10、第一连接电极5的图形，同时一并形成包括源漏极的图形。这样，实现了触控线4的辅助连接端10与触控连接端7通过第一连接电极5连接，并采用同一构图工艺形成上述结构，能够简化制备流程。
此外，触控线4和辅助连接端10采用三层结构。在一示例中，该三层结构包含钛、铝、钛的叠层。这种三层结构不仅工艺成熟，而且成本较低。
步骤S4：在触控线4上形成第二绝缘层9，第二绝缘层中开设有与第二过孔12同心的第三过孔13。
如图5C所示，在此步骤中，第三过孔13为锥形孔且第二过孔12 的最大孔径小于或等于第三过孔13的最小孔径。这样，有利于在后续工艺步骤中在第二过孔12和第三过孔13内形成连接电极。
图5C示出了第二过孔12和第三过孔13同心设置的情形。然而本公开不限于此，只要第二过孔12顶部开口和第三过孔13的底部开口至少部分重叠以便在后续阶段形成导电通路即可。
在一实施例中，第二过孔12的顶部开口不被第二绝缘层9覆盖，使得第二过孔12的顶部开口完全落在第三过孔12的底部开口之内。在另一实施例中，第二过孔12的顶部开口与第三过孔12的底部开口恰好重叠。
步骤S5：在第二绝缘层9上形成包括公共电极层1的图形，并在第二过孔12和第三过孔13内形成第二连接电极6，第二连接电极6连接公共电极层1和触控连接端7。
如图5D所示，在此步骤中，采用构图工艺形成公共电极层1的图形的同时，在第二过孔12和第三过孔13内形成第二连接电极6，从而通过第二连接电极6实现公共电极层1与触控连接端7的连接。
在本实施例的阵列基板的制备方法中，触控线4的辅助连接端10依次通过第一连接电极5、触控连接端7和第二连接电极6间接连接到公共电极层1。由于触控连接端7采用钼制备，能够减小触控线与公共电极层1之间的电阻，避免了触控和显示不良。另外，触控连接端7与栅极同层设置，且触控线4与源漏极同层设置。因此，本实施例的制备方法相比现有的制备方法并没有增加构图工艺的次数，也没有增加制备成本。
图6为本公开一实施例的阵列基板的剖视图。图6的右侧与图5D相同，并且在左侧示出了该阵列基板的薄膜晶体管区域。如所示，触控连接端7与薄膜晶体管的栅极7′同层设置，并且辅助连接端10(以及触控线4)与源漏极10′同层设置。应指出，图6仅仅图示与本公开的发明构思相关的层和/或部件。例如，图6中在薄膜晶体管区域仅仅示出了薄膜晶体管的源漏极和栅极，而没有示出有源层。
本公开一实施例提供一种触摸屏，该触摸屏包括上文所述的阵列基板。
该触摸屏可具体为FIC电容触摸屏，并运用于液晶显示面板、手机、平板电脑、数码相机、导航仪等任何具有显示功能和触控功能的 产品或部件，不仅能够避免触控和显示不良的现象出现，而且相比现有的触摸屏并没有增加构图工艺的次数，也没有增加制备成本。
本公开的阵列基板及其制备方法，将阵列基板中的触控线与公共电极层通过第一连接电极、第二连接电极连接，并且第一连接电极与触控连接端连接，第二连接电极与触控连接端连接，从而实现第一连接电极与第二连接电极通过触控连接端间接连接，这样相比现有的公共电极层与触控线的辅助连接端直接接触连接的结构，能够显著减小公共电极层与触控线之间的接触电阻，有效避免了触控和显示不良。
本公开的触控屏包括上述阵列基板，能够显著减小公共电极层与触控线之间的接触电阻，有效避免了触控屏的触控和显示不良。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，本公开并不局限于此。对于本领域的普通技术人员而言，在不脱离本公开的实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种阵列基板，包括薄膜晶体管、公共电极层、触控线、触控连接端和连接电极，
    其中所述触控连接端与所述触控线异层设置，
    其中所述连接电极包括与所述触控线同层设置的第一连接电极和与所述公共电极层同层设置的第二连接电极，以及
    其中所述触控线通过所述第一连接电极与所述触控连接端连接，并且所述公共电极层通过所述第二连接电极与所述触控连接端连接。
  2. 根据权利要求1所述的阵列基板，还包括从所述触控线的一侧延伸出的辅助连接端，
    其中所述辅助连接端与所述触控线同层设置，所述辅助连接端通过所述第一连接电极与所述触控连接端连接，并且所述辅助连接端与所述触控连接端至少部分重叠。
  3. 根据权利要求2所述的阵列基板，还包括设置在所述公共电极层和所述触控连接端之间的第一绝缘层和位于所述第一绝缘层上的第二绝缘层，
    其中所述触控线和所述辅助连接端设置在所述第一绝缘层与所述第二绝缘层之间，
    其中所述第一绝缘层在对应所述辅助连接端与所述触控连接端重叠的区域开设有第一过孔，所述第一连接电极设置于所述第一过孔中，以及
    其中所述第一绝缘层在对应所述触控连接端与所述辅助连接端未重叠的区域开设有第二过孔，所述第二绝缘层开设有第三过孔，所述第二过孔与所述第三过孔至少部分重叠，并且所述第二连接电极设置于所述第二过孔和所述第三过孔中。
  4. 根据权利要求3所述的阵列基板，其中所述第二过孔和所述第三过孔同心设置。
  5. 根据权利要求3所述的阵列基板，其中所述第一过孔、所述第二过孔和所述第三过孔均为锥形孔，并且所述锥形孔的孔径在远离所述触控连接端的方向上逐渐缩小。
  6. 根据权利要求5所述的阵列基板，其中所述第二过孔的最大孔 径小于或等于所述第三过孔的最小孔径。
  7. 根据权利要求1所述的阵列基板，其中所述触控连接端的一部分与所述触控线不重叠。
  8. 根据权利要求1所述的阵列基板，其中所述触控连接端与所述触控线不相互重叠。
  9. 根据权利要求1所述的阵列基板，还包括数据线，所述数据线与所述触控线同层设置且与所述触控线平行、间隔设置。
  10. 根据权利要求1所述的阵列基板，其中所述薄膜晶体管包括依次层叠设置的栅极、栅绝缘层、有源层以及源漏极，并且所述触控线与所述源漏极同层设置。
  11. 根据权利要求10所述的阵列基板，其中所述触控连接端与所述栅极同层设置。
  12. 根据权利要求11所述的阵列基板，其中所述触控线和所述源漏极采用三层结构，所述三层结构依次采用钛、铝、钛制备。
  13. 根据权利要求11所述的阵列基板，其中所述栅极和所述触控连接端采用钼制备。
  14. 一种触摸屏，包括权利要求1-13中任一所述的阵列基板。
  15. 一种阵列基板的制备方法，包括：
    形成包括触控连接端的图形；
    在所述触控连接端上沉积第一绝缘层，并且在所述第一绝缘层中形成第一过孔和第二过孔；
    在所述第一绝缘层上形成包括触控线和第一连接电极的图形，其中所述第一连接电极设置于所述第一过孔中；
    在形成有所述触控线和所述第一连接电极的图形的所述第一绝缘层上沉积第二绝缘层，并且在所述第二绝缘层中形成第三过孔，其中所述第三过孔与所述第二过孔至少部分重叠；以及
    在所述第二绝缘层上形成包括公共电极层和第二连接电极的图形，其中所述第二连接电极设置于所述第二过孔和所述第三过孔中，并且所述第二连接电极连接所述公共电极层和所述触控连接端。
  16. 根据权利要求15所述的阵列基板的制备方法，其中在所述第一绝缘层上形成包括触控线和第一连接电极的图形的步骤还包括：形成从所述触控线的一侧延伸出的辅助连接端，其中所述辅助连接端的 正投影与所述第一过孔至少部分重叠，所述辅助连接端在所述第一过孔中形成第一连接电极，并且所述辅助连接端通过所述第一连接电极连接到所述触控连接端。
  17. 根据权利要求15所述的阵列基板的制备方法，其中形成包括触控连接端的图形的步骤包括：
    采用同一构图工艺，形成包括触控连接端和栅极的图形。
  18. 根据权利要求15所述的阵列基板的制备方法，其中在所述第一绝缘层上形成包括触控线和第一连接电极的图形的步骤包括：
    采用同一构图工艺，形成包括触控线、第一连接电极和源漏极的图形。
  19. 根据权利要求15所述的阵列基板的制备方法，其中所述第一过孔、所述第二过孔和所述第三过孔均为锥形孔，所述锥形孔的孔径在远离所述触控连接端的方向上逐渐缩小，并且所述第二过孔的最大孔径小于或等于所述第三过孔的最小孔径。
  20. 根据权利要求15-19中任一所述的阵列基板的制备方法，其中所述触控线和所述源漏极采用三层结构，所述三层结构依次采用钛、铝、钛制备，并且所述触控连接端采用钼制备。
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