WO2017193922A1 - 浮点矩阵求逆的并行硬件架构和并行计算方法 - Google Patents

浮点矩阵求逆的并行硬件架构和并行计算方法 Download PDF

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WO2017193922A1
WO2017193922A1 PCT/CN2017/083682 CN2017083682W WO2017193922A1 WO 2017193922 A1 WO2017193922 A1 WO 2017193922A1 CN 2017083682 W CN2017083682 W CN 2017083682W WO 2017193922 A1 WO2017193922 A1 WO 2017193922A1
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matrix
row
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辛遥
梁添才
龚文川
刘道余
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GRG Banking Equipment Co Ltd
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    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization

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  • the present invention relates to the field of digital circuits, and more particularly to a parallel hardware architecture and a parallel computing method for floating-point matrix inversion.
  • Matrix computing is an important aspect in the field of scientific computing.
  • the core problem in scientific computing is often to solve a series of large linear equations.
  • the solution of these linear equations is the basis and core of solving the whole problem, and its calculation amount accounts for the whole system calculation.
  • the proportion of quantity is very high, and it is very common to introduce matrix theory to solve and solve the problem of solving equations in scientific research and engineering technology. It not only opens up a broad research prospect for matrix theory and method, but also makes research on science and engineering technology. New changes have taken place and new research approaches have been opened up.
  • Matrix computing has become a mathematical tool in many subject areas. It has not only important applications in mathematical analysis, optimization methods, mathematical models, etc., but also in scientific fields such as signal processing, image processing, and communication technology.
  • Matrix inversion is an important operation in matrix operations. How to effectively perform matrix inversion is also a hot research in the field of mathematics.
  • the embodiment of the invention provides a parallel hardware architecture and a parallel computing method for inverting the floating-point matrix, which can solve the problem that the matrix dimension is fixed when the existing matrix operation is implemented by hardware.
  • a matrix writing module configured to write matrix data of the augmented matrix into the first memory and the second memory, wherein the first memory stores an inverse matrix to be inquired in the augmented matrix, Writing a unit matrix in the augmented matrix in the second memory, the first memory and the second memory dynamically allocating a storage space for the matrix data;
  • An initial principal positioning module configured to locate an initial principal row of the augmented matrix
  • a row switching module configured to exchange a first row of the augmented matrix with a primary row; when the first exchange, the principal element acts as the initial principal row;
  • a row elimination module configured to perform normalization and row elimination calculation on the augmented matrix after row switching, and locate a next principal row
  • a triggering module configured to repeatedly trigger the row switching module and the row elimination module repeatedly, until the inverse matrix to be inquired stored in the first memory becomes an identity matrix, and output matrix data in the second memory.
  • the method further includes: a dynamic storage allocation module, configured to dynamically allocate a storage space for the matrix data when the matrix write module writes the matrix data of the augmented matrix into the first memory and the second memory;
  • a dynamic storage allocation module configured to dynamically allocate a storage space for the matrix data when the matrix write module writes the matrix data of the augmented matrix into the first memory and the second memory;
  • the dynamic storage allocation module includes:
  • a row allocation unit configured to divide the storage space into m discrete blocks according to the size of the matrix data, each of the discrete blocks storing a row of matrix data, the size of the matrix data being m*n;
  • a column allocation unit for dividing each of the discrete blocks into Row address spaces, each of which stores Dp floating point numbers, and Dp is equal to the degree of parallelism of the operations.
  • the parallel hardware architecture further includes:
  • the storage redistribution module is configured to acquire the changed degree of parallelism if the degree of parallelism of the discovery operation is changed, and dynamically allocate storage space for the matrix data.
  • the initial principal positioning module includes:
  • a first data positioning unit configured to locate a first data of each row of the augmented matrix when writing matrix data of the augmented matrix
  • the main element row determining unit is configured to compare the first data of each row, and determine an initial principal row of the behavior of the augmented matrix in which the first data is the largest.
  • the line elimination module includes:
  • a normalization unit configured to normalize a main element row of the augmented matrix after row exchange
  • a cache unit configured to cache the elements of the normalized primary element row and the elements of the column in which the primary element is located in two third memories;
  • a row elimination calculation unit for performing line elimination calculation on all rows except the principal element row
  • the main element row relocating unit is configured to reposition the row to eliminate the calculated main element row of the augmented matrix.
  • Step 1 Write matrix data of the augmented matrix into the first memory and the second memory, wherein the first memory stores an inverse matrix to be inquired in the augmented matrix, and writes in the second memory Into the unit matrix in the augmented matrix, the first memory and the second memory dynamically allocate storage space for the matrix data;
  • Step 2 locating an initial principal line of the augmented matrix
  • Step 3 exchange the first row of the augmented matrix with the primary row, and when the first exchange, the principal element acts as the initial principal row;
  • Step 4 normalizing and eliminating the augmented matrix after the row exchange, and positioning the next principal row;
  • Step 5 Perform step 3 and step 4 alternately until the matrix to be inquired stored in the first memory becomes an identity matrix, and output matrix data in the second memory.
  • the method for dynamically allocating storage space for the matrix data specifically includes:
  • the parallel computing method further includes:
  • the detection finds that the degree of parallelism of the operation changes, the changed degree of parallelism is acquired, and the storage space is dynamically allocated for the matrix data.
  • the initial principal cell row for locating the augmented matrix specifically includes:
  • performing normalization and row elimination calculation on the augmented matrix after the row exchange, and positioning the next principal row specifically includes:
  • the normalized element of the primary element row and the element of the column of the primary element are respectively cached in two third memories;
  • Repositioning the row eliminates the calculated principal row of the augmented matrix.
  • a parallel hardware architecture for inverting a floating-point matrix includes: a matrix writing module, configured to write matrix data of the augmented matrix into the first memory and the second memory, wherein the first Writing an inverse matrix to be inquired in the augmented matrix in a memory, writing a unit matrix in the augmented matrix in the second memory, the first memory and the second memory dynamically allocating the matrix data a storage space; an initial principal positioning module, configured to locate an initial principal row of the augmented matrix; and a row switching module, configured to exchange a first row of the augmented matrix with a primary row, when the first exchange is performed
  • the principal element acts as the initial principal element row;
  • the row elimination module is configured to perform normalization and row elimination calculation on the augmented matrix after the row exchange, and locate the next principal element row;
  • the trigger module uses The row switching module and the row elimination module are repeatedly triggered alternately until the inverse matrix to be inquired stored in the first memory becomes an identity matrix, and the matrix data in the second memory is output.
  • the parallel hardware architecture is applied to matrix inversion of arbitrary dimensions, which can satisfy large-scale matrix inversion requirements, and between matrix inversions of different dimensions. There is no need to change the hardware settings.
  • the parallel processing method the inversion processing of the matrix of arbitrary dimensions can be realized, and the speed of the inverse operation can be improved.
  • FIG. 1 is a flow chart of an embodiment of a parallel computing method for inverting a floating-point matrix according to an embodiment of the present invention
  • FIG. 2 is a flow chart of another embodiment of a parallel computing method for inverting a floating-point matrix according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a principle of a dynamic storage allocation algorithm according to an embodiment of the present invention.
  • FIG. 4 is a structural diagram of an embodiment of a parallel hardware architecture for inverting a floating-point matrix according to an embodiment of the present invention
  • FIG. 5 is another embodiment of a parallel hardware architecture for inverting a floating-point matrix according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a parallel hardware architecture of a floating-point matrix inversion according to an application scenario of the present invention
  • FIG. 7 is a schematic diagram of an application scenario of a row elimination module of a parallel hardware architecture for inverting a floating-point matrix according to the present invention.
  • the embodiment of the invention provides a parallel hardware architecture and a parallel computing method for inverting a floating-point matrix, which is used to solve the problem that the matrix dimension is fixed when the existing matrix operation is implemented by hardware.
  • an embodiment of a parallel computing method for inverting a floating-point matrix in an embodiment of the present invention includes:
  • the matrix data of the augmented matrix is written into the first memory and the second memory, wherein the first memory stores an inverse matrix to be inquired in the augmented matrix, and the augmentation is written in the second memory
  • the unit matrix in the matrix, the first memory and the second memory dynamically allocate storage space for the matrix data.
  • the initial principal cell row of the augmented matrix can be located.
  • the first row of the augmented matrix can be exchanged with the primary row.
  • the principal element acts on the initial principal row.
  • the normalized and row-cancelled calculations of the augmented matrix after the row exchange can be performed, and the next principal row is located.
  • Step 105 and step 104 are repeatedly performed alternately until the inverse matrix to be inquired stored in the first memory becomes an identity matrix, and the matrix data in the second memory is output.
  • Steps 103 and 104 are alternately executed until the inverse matrix to be inquired stored in the first memory becomes the identity matrix, and the matrix data in the second memory is output.
  • first, matrix data of the augmented matrix is written into the first memory and the second memory, wherein the first memory stores an inverse matrix to be inquired in the augmented matrix, and the second memory
  • the first memory and the second memory dynamically allocate storage space for the matrix data; then, locating the initial principal cell row of the augmented matrix; and then, the first of the augmented matrix
  • the row is exchanged with the main element row.
  • the principal element acts on the initial principal element row; then, the normalized and row elimination calculations are performed on the augmented matrix after the row exchange, and the next main is located.
  • the third step and the fourth step are repeatedly performed until the inverse matrix to be inquired stored in the first memory becomes the identity matrix, and the matrix data in the second memory is output.
  • the parallel computing method is applied to the matrix inversion of an arbitrary dimension, which can satisfy the large-scale matrix inversion requirement, and does not need to be changed between matrix inversions of different dimensions. Hardware settings.
  • FIG. 2 Another implementation of a parallel computing method for inverting a floating-point matrix in an embodiment of the present invention is provided. Examples include:
  • the matrix data of the augmented matrix is written into the first memory and the second memory, wherein the first memory stores an inverse matrix to be inquired in the augmented matrix, and the augmentation is written in the second memory
  • the unit matrix in the matrix, the first memory and the second memory dynamically allocate storage space for the matrix data.
  • the method for dynamically allocating the storage space for the matrix data specifically includes:
  • the storage space is divided into m discrete blocks according to the size of the matrix data, and each of the discrete blocks stores a row of matrix data, and the size of the matrix data is m*n;
  • each row address space stores Dp floating point numbers, Dp is equal to the parallelism of the operation, Indicates the result of rounding up n/Dp.
  • each matrix row space is further divided into A row address space in which each row address space stores Dp floating point numbers (data) such that each matrix row space stores n floating point numbers.
  • the storage space allocation can be adjusted in real time according to the degree of parallelism: if the parallelism of the operation is detected to be changed, the changed parallelism is acquired, and the matrix is re-created. Data dynamically allocates storage space.
  • the first data of each row of the augmented matrix may be located when the matrix data of the augmented matrix is written.
  • the first data of each row may be compared to determine the initial principal row of the behavior of the augmented matrix having the largest initial data. For example, it may be that the first data of each row is located when the data is written, the size comparison is performed between every two rows, and the larger data is stored, and when the writing ends, the stored first data is the largest, so that the maximum can be determined.
  • the behavior of the initial data corresponds to the initial principal row.
  • the first row of the augmented matrix can be exchanged with the primary row. It can be understood that the primary element is exchanged during the first exchange. The behavior of the initial principal row.
  • the normalized and row-cancelled calculations of the augmented matrix after the row exchange can be performed, and the next principal row is located.
  • step 205 may specifically include:
  • the normalization and elimination operations are pure pipeline design, because in step C, They come from three memories, so they can be operated simultaneously (ie, parallel). In fact, there are Dp numbers in each position, and the horizontal scanning operation is adopted, that is, the Dp adjacent elements in the same row participate in the operation until all the elements complete the operation.
  • step 3 and step 4 alternately until the inverse matrix to be inquired stored in the first memory becomes an identity matrix, and output matrix data in the second memory.
  • Steps 3 and 4 are alternately performed until the inverse matrix to be inquired stored in the first memory becomes the identity matrix, and the matrix data in the second memory is output.
  • the first memory stores the inverse matrix to be inquired
  • the second memory stores the identity matrix, after performing the inversion operation, when After the inverse matrix of the original to be the identity matrix, the unit matrix stored in the second memory is the inverse matrix of the inverse matrix to be obtained, and the matrix data in the second memory is output, that is, the inverse matrix required for the output.
  • the memory for storing the inverse matrix and the unit matrix is not fixed. When the inverse matrix to be obtained becomes the unit matrix, the next round of memory is alternately converted, and another memory is used to store the inverse matrix to be obtained.
  • the parallel computing method for inverting the floating-point matrix is mainly described above.
  • the parallel hardware architecture of the inversion of the floating-point matrix is described in detail below. Referring to FIG. 4, a floating-point matrix is obtained in the embodiment of the present invention.
  • One embodiment of the inverse parallel hardware architecture includes:
  • a matrix writing module 401 configured to write matrix data of the augmented matrix into the first memory and the second memory, wherein the first memory stores an inverse matrix to be inquired in the augmented matrix, the second memory Writing into the unit matrix in the augmented matrix, the first memory and the second memory dynamically allocating storage space for the matrix data;
  • An initial principal positioning module 402 is configured to locate an initial principal row of the augmented matrix
  • a row switching module 403 configured to exchange the first row of the augmented matrix with the primary row, the first time In time, the principal element acts on the initial principal row;
  • a row elimination module 404 configured to perform normalization and row elimination calculation on the augmented matrix after the row exchange, and locate the next principal cell row;
  • the triggering module 405 is configured to repeatedly trigger the row switching module 403 and the row eliminating module 404 to repeatedly output the matrix data in the second memory when the inverse matrix to be inquired stored in the first memory becomes an identity matrix.
  • the matrix write module 401 writes the matrix data of the augmented matrix into the first memory and the second memory, wherein the first memory stores the inverse matrix to be inquired in the augmented matrix, the first Writing, in the second memory, the unit matrix in the augmented matrix, the first memory and the second memory dynamically allocate storage space for the matrix data; the initial pivoting module 402 locates the initial principal row of the augmented matrix; The module 403 exchanges the first row of the augmented matrix with the primary row. When the first exchange, the principal acts as the initial principal row; the row elimination module 404 normalizes the apolated matrix after the row is exchanged.
  • the triggering module repeatedly triggers the row switching module 403 and the row elimination module 404 repeatedly until the inverse matrix to be inquired stored in the first memory becomes the identity matrix, and outputs the first Matrix data in two memories.
  • the parallel hardware architecture is applicable to matrix inversion of arbitrary dimensions, which can satisfy large-scale matrix inversion requirements, and does not need to be changed between matrix inversions of different dimensions. Hardware settings.
  • a matrix writing module 501 configured to write matrix data of the augmented matrix into the first memory and the second memory, wherein the first memory stores an inverse matrix to be inquired in the augmented matrix, the second memory Writing into the unit matrix in the augmented matrix, the first memory and the second memory dynamically allocating storage space for the matrix data;
  • a row switching module 503 configured to exchange the first row of the augmented matrix with the primary row; when the first exchange, the principal element acts as the initial principal row;
  • a row elimination module 504 configured to perform normalization and row elimination calculation on the augmented matrix after the row exchange, and locate the next principal cell row;
  • the triggering module 505 is configured to repeatedly trigger the row switching module 503 and the row eliminating module 504 to repeatedly output the matrix data in the second memory when the inverse matrix to be inquired stored in the first memory becomes an identity matrix.
  • the parallel hardware architecture further includes a dynamic storage allocation module 506, configured to dynamically allocate and store the matrix data when the matrix write module writes the matrix data of the augmented matrix into the first memory and the second memory. space;
  • the dynamic storage allocation module 506 includes:
  • the row allocation unit 5061 is configured to divide the storage space into m discrete blocks according to the size of the matrix data, and each of the discrete blocks stores one row of matrix data, and the size of the matrix data is m*n;
  • a column allocating unit 5062 configured to divide each of the discrete blocks into Row address space, each row address space stores Dp floating point numbers, and Dp is equal to the degree of parallelism of the operations.
  • the parallel hardware architecture further includes:
  • the storage re-allocation module 507 is configured to acquire the changed parallelism if the parallelism of the discovery operation is changed, and dynamically allocate the storage space for the matrix data.
  • the initial pivoting module 502 includes:
  • the first data positioning unit 5021 is configured to locate the first data of each row of the augmented matrix when writing the matrix data of the augmented matrix;
  • the principal row determining unit 5022 is configured to compare the first data of each row, and determine an initial principal row of the behavior of the augmented matrix having the largest initial data.
  • the line elimination module 504 includes:
  • the normalization unit 5041 is configured to normalize the main element row of the augmented matrix after the row exchange;
  • the cache unit 5042 is configured to cache the elements of the normalized primary element row and the elements of the column in which the primary element is located in two third memories;
  • a row elimination calculation unit 5043 configured to perform row elimination calculation on all rows except the principal element row
  • the principal row relocation unit 5044 is configured to reposition the row to eliminate the calculated principal row of the augmented matrix.
  • the normalization and elimination operations may be designed as a pure pipeline, because in the row elimination calculation process, They are from three memories (such as the normalized principal memory, the main element column memory and the matrix memory in Figure 7), so they can be operated simultaneously by the scalable floating-point arithmetic unit (that is, parallel computing), and then passed through the comparator after the operation. Compare relocation of the principal row. In fact, there are Dp numbers in each position, and the horizontal scanning operation is adopted, that is, the Dp adjacent elements in the same row participate in the operation until all the elements complete the operation.
  • the parallel hardware architecture of the floating-point matrix inversion in an application scenario is shown in Figure 6.
  • the parallel hardware architecture can encapsulate five interface IO signals:
  • Matrix size indicates the size of the matrix.
  • Write address The storage address of the matrix data that is initially written.
  • Read address The storage address of the matrix data is read after the inverse operation is completed.
  • Read data Read the data of an address space of the memory after the inverse operation is completed.
  • This parallel hardware architecture supports variable matrix size and can perform matrix inversion operations of any size, the only limitation being the capacity and resource size of the first memory and the second memory.
  • the storage space allocation of the memory (the first memory, the second memory or the third memory, etc.) can be adjusted in real time according to the degree of parallelism, and the dynamic storage allocation algorithm of the principle shown in FIG. 3 is embedded in the memory.
  • the hardware architecture is simulated and verified in the FPGA, and the parallelism Dp is set to 4, 8, 16, 32, and the maximum support matrix size is 256 ⁇ 256.
  • the maximum clock operating frequencies are 208 MHz, 222 MHz, 218 MHz, and 169 MHz, respectively.
  • the estimated matrix inversion clock number is calculated as: n is the size of the square matrix, and the computational complexity is reduced from O(n3) to O(n3/Dp).
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or Some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

本发明实施例公开了浮点矩阵求逆的并行硬件架构，用于解决现有矩阵运算通过硬件实现时矩阵维数固定的问题。本发明实施例中一种浮点矩阵求逆的并行硬件架构包括：矩阵写入模块，用于将增广矩阵的矩阵数据写入第一存储器和第二存储器中，第一存储器和第二存储器为矩阵数据动态分配存储空间；初始主元定位模块，用于定位增广矩阵的初始主元行；行交换模块，用于将增广矩阵的首行与主元行进行交换；行消除模块，用于进行归一化和行消除计算，并定位下一主元行；触发模块，用于反复交替触发行交换模块和行消除模块，直到第一存储器中存储的待求逆矩阵成为单位矩阵时，输出第二存储器中的矩阵数据。本发明实施例还提供浮点矩阵求逆的并行计算方法。

Description

浮点矩阵求逆的并行硬件架构和并行计算方法
本申请要求于2016年5月11日提交中国专利局、申请号为201610311399.4、发明名称为“浮点矩阵求逆的并行硬件架构和并行计算方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及数字电路领域，尤其涉及浮点矩阵求逆的并行硬件架构和并行计算方法。
背景技术
矩阵运算是科学计算领域中的一个重要方面，科学计算中的核心问题往往是求解一系列大型线性方程组，这些线性方程组的求解是解决整个问题的基础和核心，其计算量占整个系统计算量的比重很高，而引入矩阵理论来处理和解决科学研究和工程技术上的方程组求解问题已经很普遍，不仅为矩阵理论和方法开辟了广阔的研究前景，也使科学与工程技术的研究发生新的变化，开拓新的研究途径。矩阵运算已成为众多学科领域的数学工具，它不仅在数值分析、最优化方法、数学模型等数学分支上有极其重要的应用，还在信号处理、图像处理、通信技术等科学领域中广泛应用。矩阵求逆是矩阵运算中重要的运算，如何有效的完成矩阵求逆也是数学领域的热点研究。
目前大部分矩阵运算都是利用软件来实现，但是随着矩阵维数的增长，软件处理的速度也会大幅度变慢。矩阵运算的硬件实现能够充分发挥硬件的速度和并行性，目前公开的设计中大部分都是固定维数的矩阵运算，尚无法完成任意维矩阵的硬件实现，尤其是大规模的矩阵求逆的硬件设计。
发明内容
本发明实施例提供了浮点矩阵求逆的并行硬件架构和并行计算方法，能够解决现有矩阵运算通过硬件实现时矩阵维数固定的问题。
本发明实施例提供的一种浮点矩阵求逆的并行硬件架构，包括：
矩阵写入模块，用于将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，所述第一存储器中写入所述增广矩阵中的待求逆矩阵，所述第二存储器中写入所述增广矩阵中的单位矩阵，所述第一存储器和第二存储器为所述矩阵数据动态分配存储空间；
初始主元定位模块，用于定位所述增广矩阵的初始主元行；
行交换模块，用于将所述增广矩阵的首行与主元行进行交换，第一次交换时，所述主元行为所述初始主元行；
行消除模块，用于对行交换后的所述增广矩阵进行归一化和行消除计算，并定位下一主元行；
触发模块，用于反复交替触发所述行交换模块和行消除模块，直到所述第一存储器中存储的所述待求逆矩阵成为单位矩阵时，输出所述第二存储器中的矩阵数据。
可选地，还包括动态存储分配模块，用于在所述矩阵写入模块将增广矩阵的矩阵数据写入第一存储器和第二存储器时，为所述矩阵数据动态分配存储空间；
所述动态存储分配模块包括：
行分配单元，用于根据所述矩阵数据的大小将存储空间划分为m个离散块，每块所述离散块存储一行矩阵数据，所述矩阵数据的大小为m*n；
列分配单元，用于将每块所述离散块划分为
Figure PCTCN2017083682-appb-000001
个行地址空间，每个所述行地址空间存储Dp个浮点数，Dp等于运算的并行度。
可选地，所述并行硬件架构还包括：
存储重分配模块，用于若检测发现运算的并行度发生改变，则获取改变后的并行度，并重新为所述矩阵数据动态分配存储空间。
可选地，所述初始主元定位模块包括：
行首数据定位单元，用于在写入所述增广矩阵的矩阵数据时，定位所述增广矩阵每一行的首数据；
主元行确定单元，用于比较每一行的所述首数据，确定所述首数据最大的所述增广矩阵的所在行为初始主元行。
可选地，所述行消除模块包括：
归一化单元，用于对行交换后的所述增广矩阵的主元行进行归一化；
缓存单元，用于将归一化后的所述主元行的元素与主元所在列的元素分别缓存在两个第三存储器中；
行消除计算单元，用于对所述主元行以外的所有行进行行消除计算；
主元行重定位单元，用于重新定位行消除计算后的所述增广矩阵的主元行。
本发明实施例提供的一种浮点矩阵求逆的并行计算方法，包括：
步骤一、将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，所述第一存储器中写入所述增广矩阵中的待求逆矩阵，所述第二存储器中写入所述增广矩阵中的单位矩阵，所述第一存储器和第二存储器为所述矩阵数据动态分配存储空间；
步骤二、定位所述增广矩阵的初始主元行；
步骤三、将所述增广矩阵的首行与主元行进行交换，第一次交换时，所述主元行为所述初始主元行；
步骤四、对行交换后的所述增广矩阵进行归一化和行消除计算，并定位下一主元行；
步骤五、反复交替执行所述步骤三和步骤四，直到所述第一存储器中存储的所述待求逆矩阵成为单位矩阵时，输出所述第二存储器中的矩阵数据。
可选地，将增广矩阵的矩阵数据写入第一存储器和第二存储器时，为所述矩阵数据动态分配存储空间的方法具体包括：
根据所述矩阵数据的大小将存储空间划分为m个离散块，每块所述离散块存储一行矩阵数据，所述矩阵数据的大小为m*n；
将每块所述离散块划分为
Figure PCTCN2017083682-appb-000002
个行地址空间，每个所述行地址空间存储Dp个浮点数，Dp等于运算的并行度。
可选地，所述并行计算方法还包括：
若检测发现运算的并行度发生改变，则获取改变后的并行度，并重新为所述矩阵数据动态分配存储空间。
可选地，所述定位所述增广矩阵的初始主元行具体包括：
在写入所述增广矩阵的矩阵数据时，定位所述增广矩阵每一行的首数据；
比较每一行的所述首数据，确定所述首数据最大的所述增广矩阵的所在行为初始主元行。
可选地，对行交换后的所述增广矩阵进行归一化和行消除计算，并定位下一主元行具体包括：
对行交换后的所述增广矩阵的主元行进行归一化；
将归一化后的所述主元行的元素与主元所在列的元素分别缓存在两个第三存储器中；
对所述主元行以外的所有行进行行消除计算；
重新定位行消除计算后的所述增广矩阵的主元行。
从以上技术方案可以看出，本发明实施例具有以下优点：
本发明实施例中，一种浮点矩阵求逆的并行硬件架构包括：矩阵写入模块，用于将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，所述第一存储器中写入所述增广矩阵中的待求逆矩阵，所述第二存储器中写入所述增广矩阵中的单位矩阵，所述第一存储器和第二存储器为所述矩阵数据动态分配存储空间；初始主元定位模块，用于定位所述增广矩阵的初始主元行；行交换模块，用于将所述增广矩阵的首行与主元行进行交换，第一次交换时，所述主元行为所述初始主元行；行消除模块，用于对行交换后的所述增广矩阵进行归一化和行消除计算，并定位下一主元行；触发模块，用于反复交替触发所述行交换模块和行消除模块，直到所述第一存储器中存储的所述待求逆矩阵成为单位矩阵时，输出所述第二存储器中的矩阵数据。在本发明实施例中，通过为矩阵数据动态分配存储空间，所述并行硬件构架适用任意维数的矩阵求逆，可以满足大规模的矩阵求逆要求，在不同维数的矩阵求逆之间无需更改硬件设置。同时，配合并行处理方式，可以实现任意维度矩阵的求逆处理，提高求逆运算的速度。
附图说明
图1为本发明实施例中一种浮点矩阵求逆的并行计算方法一个实施例流程图；
图2为本发明实施例中一种浮点矩阵求逆的并行计算方法另一个实施例流程图；
图3为本发明实施例中动态存储分配算法的原理示意图；
图4为本发明实施例中一种浮点矩阵求逆的并行硬件架构一个实施例结构图；
图5为本发明实施例中一种浮点矩阵求逆的并行硬件架构另一个实施例 结构图；
图6为本发明的一种浮点矩阵求逆的并行硬件架构一个应用场景下的结构示意图；
图7为本发明的一种浮点矩阵求逆的并行硬件架构的行消除模块一个应用场景下的原理示意图。
具体实施方式
本发明实施例提供了浮点矩阵求逆的并行硬件架构和并行计算方法，用于解决现有矩阵运算通过硬件实现时矩阵维数固定的问题。
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图1，本发明实施例中一种浮点矩阵求逆的并行计算方法一个实施例包括：
101、将增广矩阵的矩阵数据写入第一存储器和第二存储器中；
首先，将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，该第一存储器中写入该增广矩阵中的待求逆矩阵，该第二存储器中写入该增广矩阵中的单位矩阵，该第一存储器和第二存储器为该矩阵数据动态分配存储空间。
102、定位该增广矩阵的初始主元行；
在将增广矩阵的矩阵数据写入第一存储器和第二存储器中之后，可以定位该增广矩阵的初始主元行。
103、将该增广矩阵的首行与主元行进行交换；
在定位该增广矩阵的初始主元行之后，可以将该增广矩阵的首行与主元行进行交换，第一次交换时，该主元行为该初始主元行。
104、对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行；
在将该增广矩阵的首行与主元行进行交换之后，可以对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行。
105、反复交替执行步骤103和步骤104，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。
反复交替执行步骤103和步骤104，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。
本实施例中，首先，将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，该第一存储器中写入该增广矩阵中的待求逆矩阵，该第二存储器中写入该增广矩阵中的单位矩阵，该第一存储器和第二存储器为该矩阵数据动态分配存储空间；然后，定位该增广矩阵的初始主元行；接着，将该增广矩阵的首行与主元行进行交换，第一次交换时，该主元行为该初始主元行；再之，对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行；最后，反复交替执行该步骤三和步骤四，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。在本实施例中，通过为矩阵数据动态分配存储空间，该并行计算方法适用任意维数的矩阵求逆，可以满足大规模的矩阵求逆要求，在不同维数的矩阵求逆之间无需更改硬件设置。
为便于理解，下面对本发明实施例中的一种浮点矩阵求逆的并行计算方法进行详细描述，请参阅图2，本发明实施例中一种浮点矩阵求逆的并行计算方法另一个实施例包括：
201、将增广矩阵的矩阵数据写入第一存储器和第二存储器中；
首先，将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，该第一存储器中写入该增广矩阵中的待求逆矩阵，该第二存储器中写入该增广矩阵中的单位矩阵，该第一存储器和第二存储器为该矩阵数据动态分配存储空间。
需要说明的是，将增广矩阵的矩阵数据写入第一存储器和第二存储器时，为该矩阵数据动态分配存储空间的方法具体包括：
1、根据该矩阵数据的大小将存储空间划分为m个离散块，每块该离散块存储一行矩阵数据，该矩阵数据的大小为m*n；
2、将每块该离散块划分为
Figure PCTCN2017083682-appb-000003
个行地址空间，每个该行地址空间存储 Dp个浮点数，Dp等于运算的并行度，
Figure PCTCN2017083682-appb-000004
表示向上取整n/Dp的结果。
如图3所示，将一个存储器的空间划分为m个矩阵行空间(也即离散块)，然后每个矩阵行空间又被划分为
Figure PCTCN2017083682-appb-000005
个行地址空间，其中每个行地址空间存储Dp个浮点数(数据)，从而每个矩阵行空间存储n个浮点数。
另外，为了保证动态分配的存储空间与运算的并行度保持匹配，存储空间分配可以根据并行度实时调整：若检测发现运算的并行度发生改变，则获取改变后的并行度，并重新为该矩阵数据动态分配存储空间。
202、在写入该增广矩阵的矩阵数据时，定位该增广矩阵每一行的首数据；
为了定位初始主元行，可以在写入该增广矩阵的矩阵数据时，定位该增广矩阵每一行的首数据。
203、比较每一行的该首数据，确定该首数据最大的该增广矩阵的所在行为初始主元行；
在定位该增广矩阵每一行的首数据之后，可以比较每一行的该首数据，确定该首数据最大的该增广矩阵的所在行为初始主元行。例如可以是，在数据写入时定位每一行的首数据，每两行之间进行大小比较并存储较大的数据，当写入结束后其存储的即为最大的首数据，从而可以确定最大首数据对应的行为初始主元行。
204、将该增广矩阵的首行与主元行进行交换；
在确定初始主元行或定位下一主元行(见步骤205)之后，可以将该增广矩阵的首行与主元行进行交换，可以理解的是，第一次交换时，该主元行为该初始主元行。
205、对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行；
在将该增广矩阵的首行与主元行进行交换之后，可以对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行。
需要说明的是，步骤205具体可以包括：
A、对行交换后的该增广矩阵的主元行进行归一化：举例说明，增广矩阵
Figure PCTCN2017083682-appb-000006
数，首先计算出主元的倒数
Figure PCTCN2017083682-appb-000007
后将主元行元素与倒数一一相乘，这样尽可能避免了除法操作；
B、将归一化后的该主元行的元素
Figure PCTCN2017083682-appb-000008
与主元所在列的元素
Figure PCTCN2017083682-appb-000009
分别缓存在两个第三存储器中；
C、对该主元行以外的所有行进行行消除计算：
Figure PCTCN2017083682-appb-000010
Dp、重新定位行消除计算后的该增广矩阵的主元行。
归一化和消除操作为纯流水线设计，因为步骤C中，
Figure PCTCN2017083682-appb-000011
分别来自三个存储器，所以可以同时进行运算(即并行计算)。实际上每个位置的数有Dp个，采用水平扫描操作，即同一行Dp个相邻元素参与运算，直到所有元素完成运算。
206、反复交替执行该步骤三和步骤四，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。
反复交替执行该步骤三和步骤四，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。由高斯-约当部分主元消除法(Gauss–Jordan Elimination with Partial Pivoting)的原理可知，开始时，第一存储器存储待求逆矩阵，第二存储器存储单位矩阵，在进行求逆运算后，当原待求逆矩阵成为单位矩阵后，第二存储器中存储的单位矩阵即为待求逆矩阵的逆矩阵，输出该第二存储器中的矩阵数据即输出所需的逆矩阵。需要说明的是，所述存储待求逆矩阵和单位矩阵的存储器不是固定的，当待求逆矩阵成为单位矩阵后，下一轮存储器交替转换，由另一个存储器来存放待求逆矩阵。
上面主要描述了一种浮点矩阵求逆的并行计算方法，下面将对一种浮点矩阵求逆的并行硬件架构进行详细描述，请参阅图4，本发明实施例中一种浮点矩阵求逆的并行硬件架构一个实施例包括：
矩阵写入模块401，用于将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，该第一存储器中写入该增广矩阵中的待求逆矩阵，该第二存储器中写入该增广矩阵中的单位矩阵，该第一存储器和第二存储器为该矩阵数据动态分配存储空间；
初始主元定位模块402，用于定位该增广矩阵的初始主元行；
行交换模块403，用于将该增广矩阵的首行与主元行进行交换，第一次交 换时，该主元行为该初始主元行；
行消除模块404，用于对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行；
触发模块405，用于反复交替触发该行交换模块403和行消除模块404，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。
本实施例中，矩阵写入模块401将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，该第一存储器中写入该增广矩阵中的待求逆矩阵，该第二存储器中写入该增广矩阵中的单位矩阵，该第一存储器和第二存储器为该矩阵数据动态分配存储空间；初始主元定位模块402定位该增广矩阵的初始主元行；行交换模块403将该增广矩阵的首行与主元行进行交换，第一次交换时，该主元行为该初始主元行；行消除模块404对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行；触发模块反复交替触发该行交换模块403和行消除模块404，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。在本实施例中，通过为矩阵数据动态分配存储空间，该并行硬件构架适用任意维数的矩阵求逆，可以满足大规模的矩阵求逆要求，在不同维数的矩阵求逆之间无需更改硬件设置。
为便于理解，下面对本发明实施例中的一种浮点矩阵求逆的并行硬件架构进行详细描述，请参阅图5，本发明实施例中一种浮点矩阵求逆的并行硬件架构另一个实施例包括：
矩阵写入模块501，用于将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，该第一存储器中写入该增广矩阵中的待求逆矩阵，该第二存储器中写入该增广矩阵中的单位矩阵，该第一存储器和第二存储器为该矩阵数据动态分配存储空间；
初始主元定位模块502，用于定位该增广矩阵的初始主元行；
行交换模块503，用于将该增广矩阵的首行与主元行进行交换，第一次交换时，该主元行为该初始主元行；
行消除模块504，用于对行交换后的该增广矩阵进行归一化和行消除计算，并定位下一主元行；
触发模块505，用于反复交替触发该行交换模块503和行消除模块504，直到该第一存储器中存储的该待求逆矩阵成为单位矩阵时，输出该第二存储器中的矩阵数据。
本实施例中，该并行硬件架构还包括动态存储分配模块506，用于在该矩阵写入模块将增广矩阵的矩阵数据写入第一存储器和第二存储器时，为该矩阵数据动态分配存储空间；
该动态存储分配模块506包括：
行分配单元5061，用于根据该矩阵数据的大小将存储空间划分为m个离散块，每块该离散块存储一行矩阵数据，该矩阵数据的大小为m*n；
列分配单元5062，用于将每块该离散块划分为
Figure PCTCN2017083682-appb-000012
个行地址空间，每个该行地址空间存储Dp个浮点数，Dp等于运算的并行度。
本实施例中，该并行硬件架构还包括：
存储重分配模块507，用于若检测发现运算的并行度发生改变，则获取改变后的并行度，并重新为该矩阵数据动态分配存储空间。
本实施例中，该初始主元定位模块502包括：
行首数据定位单元5021，用于在写入该增广矩阵的矩阵数据时，定位该增广矩阵每一行的首数据；
主元行确定单元5022，用于比较每一行的该首数据，确定该首数据最大的该增广矩阵的所在行为初始主元行。
本实施例中，该行消除模块504包括：
归一化单元5041，用于对行交换后的该增广矩阵的主元行进行归一化；
缓存单元5042，用于将归一化后的该主元行的元素与主元所在列的元素分别缓存在两个第三存储器中；
行消除计算单元5043，用于对该主元行以外的所有行进行行消除计算；
主元行重定位单元5044，用于重新定位行消除计算后的该增广矩阵的主元行。
需要说明的是，对于本实施例中的行消除模块504，在具体一应用场景下，如图7所示，归一化和消除操可以作为纯流水线设计，因为在行消除计算过程中，
Figure PCTCN2017083682-appb-000013
分别来自三个存储器(如图7中的归一化主元存储器、主 元列存储器和矩阵存储器)，所以可以同时通过可扩展浮点运算单元进行运算(即并行计算)，运算后通过比较器比较重新定位主元行。实际上每个位置的数有Dp个，采用水平扫描操作，即同一行Dp个相邻元素参与运算，直到所有元素完成运算。
为便于理解，一个应用场景中的浮点矩阵求逆的并行硬件架构如图6所示。该并行硬件架构可以封装有5个接口IO信号：
1、矩阵大小：指示矩阵的规模。
2、写地址：初始时写入矩阵数据的存储地址。
3、写数据：初始时写入存储器的一个地址空间的数据。
4、读地址：逆运算完成后读出矩阵数据的存储地址。
5、读数据：逆运算完成后读出存储器的一个地址空间的数据。
此并行硬件架构支持矩阵规模大小可变，可以进行任意大小的矩阵求逆运算，唯一的限制为第一存储器和第二存储器的容量和资源大小。该并行硬件架构中的运算模块可以采用多浮点运算单元并行配置，运算单元数量可以扩展，支持不同并行度设计，加速矩阵运算。如并行度Dp＝4时，同时有四个数据同时进行运算。存储器(第一存储器、第二存储器或第三存储器等)的存储空间分配可以根据并行度实时调整，存储器中内嵌如图3所示原理的动态存储分配算法。
所述硬件架构在FPGA进行仿真验证，分别设置并行度Dp为4，8，16，32，最大支持矩阵大小为256×256，最大时钟工作频率分别为208MHz，222MHz，218MHz，169MHz。完成矩阵求逆时钟数估算为：
Figure PCTCN2017083682-appb-000014
n为方阵的大小，计算复杂度由O(n3)减少为O(n3/Dp)。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或 一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

  1. 一种浮点矩阵求逆的并行硬件架构，其特征在于，包括：
    矩阵写入模块，用于将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，所述第一存储器中写入所述增广矩阵中的待求逆矩阵，所述第二存储器中写入所述增广矩阵中的单位矩阵，所述第一存储器和第二存储器为所述矩阵数据动态分配存储空间；
    初始主元定位模块，用于定位所述增广矩阵的初始主元行；
    行交换模块，用于将所述增广矩阵的首行与主元行进行交换，第一次交换时，所述主元行为所述初始主元行；
    行消除模块，用于对行交换后的所述增广矩阵进行归一化和行消除计算，并定位下一主元行；
    触发模块，用于反复交替触发所述行交换模块和行消除模块，直到所述第一存储器中存储的所述待求逆矩阵成为单位矩阵时，输出所述第二存储器中的矩阵数据。
  2. 根据权利要求1所述的并行硬件架构，其特征在于，还包括动态存储分配模块，用于在所述矩阵写入模块将增广矩阵的矩阵数据写入第一存储器和第二存储器时，为所述矩阵数据动态分配存储空间；
    所述动态存储分配模块包括：
    行分配单元，用于根据所述矩阵数据的大小将存储空间划分为m个离散块，每块所述离散块存储一行矩阵数据，所述矩阵数据的大小为m*n；
    列分配单元，用于将每块所述离散块划分为
    Figure PCTCN2017083682-appb-100001
    个行地址空间，每个所述行地址空间存储Dp个浮点数，Dp等于运算的并行度。
  3. 根据权利要求2所述的并行硬件架构，其特征在于，所述并行硬件架构还包括：
    存储重分配模块，用于若检测发现运算的并行度发生改变，则获取改变后的并行度，并重新为所述矩阵数据动态分配存储空间。
  4. 根据权利要求1所述的并行硬件架构，其特征在于，所述初始主元定位模块包括：
    行首数据定位单元，用于在写入所述增广矩阵的矩阵数据时，定位所述增 广矩阵每一行的首数据；
    主元行确定单元，用于比较每一行的所述首数据，确定所述首数据最大的所述增广矩阵的所在行为初始主元行。
  5. 根据权利要求1所述的并行硬件架构，其特征在于，所述行消除模块包括：
    归一化单元，用于对行交换后的所述增广矩阵的主元行进行归一化；
    缓存单元，用于将归一化后的所述主元行的元素与主元所在列的元素分别缓存在两个第三存储器中；
    行消除计算单元，用于对所述主元行以外的所有行进行行消除计算；
    主元行重定位单元，用于重新定位行消除计算后的所述增广矩阵的主元行。
  6. 一种浮点矩阵求逆的并行计算方法，其特征在于，包括：
    步骤一、将增广矩阵的矩阵数据写入第一存储器和第二存储器中，其中，所述第一存储器中写入所述增广矩阵中的待求逆矩阵，所述第二存储器中写入所述增广矩阵中的单位矩阵，所述第一存储器和第二存储器为所述矩阵数据动态分配存储空间；
    步骤二、定位所述增广矩阵的初始主元行；
    步骤三、将所述增广矩阵的首行与主元行进行交换，第一次交换时，所述主元行为所述初始主元行；
    步骤四、对行交换后的所述增广矩阵进行归一化和行消除计算，并定位下一主元行；
    步骤五、反复交替执行所述步骤三和步骤四，直到所述第一存储器中存储的所述待求逆矩阵成为单位矩阵时，输出所述第二存储器中的矩阵数据。
  7. 根据权利要求6所述的并行计算方法，其特征在于，将增广矩阵的矩阵数据写入第一存储器和第二存储器时，为所述矩阵数据动态分配存储空间的方法具体包括：
    根据所述矩阵数据的大小将存储空间划分为m个离散块，每块所述离散块存储一行矩阵数据，所述矩阵数据的大小为m*n；
    将每块所述离散块划分为
    Figure PCTCN2017083682-appb-100002
    个行地址空间，每个所述行地址空间存储 Dp个浮点数，Dp等于运算的并行度。
  8. 根据权利要求7所述的并行计算方法，其特征在于，所述并行计算方法还包括：
    若检测发现运算的并行度发生改变，则获取改变后的并行度，并重新为所述矩阵数据动态分配存储空间。
  9. 根据权利要求6所述的并行计算方法，其特征在于，所述定位所述增广矩阵的初始主元行具体包括：
    在写入所述增广矩阵的矩阵数据时，定位所述增广矩阵每一行的首数据；
    比较每一行的所述首数据，确定所述首数据最大的所述增广矩阵的所在行为初始主元行。
  10. 根据权利要求6所述的并行计算方法，其特征在于，对行交换后的所述增广矩阵进行归一化和行消除计算，并定位下一主元行具体包括：
    对行交换后的所述增广矩阵的主元行进行归一化；
    将归一化后的所述主元行的元素与主元所在列的元素分别缓存在两个第三存储器中；
    对所述主元行以外的所有行进行行消除计算；
    重新定位行消除计算后的所述增广矩阵的主元行。
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