WO2017193322A1

WO2017193322A1 - Method of manufacturing insulated gate bipolar transistor

Info

Publication number: WO2017193322A1
Application number: PCT/CN2016/081800
Authority: WO
Inventors: 周贤达; 舒小平; 徐远梅
Original assignee: 中山港科半导体科技有限公司
Priority date: 2016-05-12
Filing date: 2016-05-12
Publication date: 2017-11-16

Abstract

Provided is a method of manufacturing an insulated gate bipolar transistor, comprising the following steps: 1. fabricating a lightly doped substrate; 2. forming on the substrate a dielectric layer (333); 3. depositing on the dielectric layer (333) an undoped polycrystalline silicon layer; 4. patterning the undoped polycrystalline silicon layer and the dielectric layer (333) to form a gate channel (541); 5. depositing, on a surface of monocrystalline silicon, silicon, to form monocrystalline silicon, and forming, on a remaining part of the surface of the substrate, polycrystalline silicon; 6. forming gate dielectric (332); 7. forming gate electrode (322); 8. forming a polycrystalline silicon base region (313); 9. forming a heavily doped polycrystalline silicon emitter region (311) and a polycrystalline silicon spreading region (311); 10. depositing an inter-layer dielectric (331); 11. patterning the inter-layer dielectric (331); 12. forming an emitter (321); 13. thinning the substrate to form a drift region (314); 14 forming, by performing ion injection and annealing, a buffer region (315); 15. forming at a back side a collector region (316); and 16. forming at the back side a collector electrode. The device manufactured by the method can in theory produce the lowest conduction voltage drop.

Description

Method for manufacturing insulated gate bipolar transistor

Technical field

The invention discloses a method for manufacturing a power semiconductor device, in particular to a method for manufacturing an insulated gate bipolar transistor.

Background technique

Insulated Gate Bipolar Transistors (IGBTs) have been widely used in high voltage power electronic systems such as variable frequency drives and inverters. The ideal device should have low power loss, the conduction loss of the IGBT is a major component of the power loss, and the conduction loss can be characterized by the on-state voltage of the device.

Referring to the drawings, a cross section of a prior art IGBT device 100 is shown in FIG. The device 100 is a MOS-controlled PNP bipolar junction transistor, and the MOS channel is composed of an n ⁺ emitter region 111, a p-base region 113, an n ^- drift region 114, a gate dielectric 132, and a gate electrode 122. The state is controlled by the MOS channel. In the on state of device 100, holes are injected from the backside p ⁺ collector region 116/n buffer 115 junction and conduct electrons through the MOS channel. The high concentration of plasma formed by the unbalanced electrons and holes in the lightly doped n ^- drift region 114 gives the region a high conductivity, however, due to the presence of a slightly reverse biased n ^- drift region 114/ The p-base region 113 is junction, and the concentration of electron-hole plasma near the junction is relatively low. The concentration of electron-hole plasma in the n ^- drift region 114 as a function of distance is shown in FIG. As shown in the figure, the plasma concentration is almost zero at the junction of the n ^- drift region 114/p base region 113 due to the drift current of the reverse biased pn junction. This reduced concentration causes the on-state voltage drop of device 100 to be relatively larger than the pin diode. If the reverse biased n ^- drift region 114/p base region 113 junction can be eliminated, the on-state voltage drop of device 100 will be the same as the on-state voltage drop of the pin diode [1]. In order to achieve the theoretically lowest on-state voltage drop, an ultra-narrow silicon mesa is required between the trenches. If the mesa width is about 20 nm, two adjacent inversion layers will be merged together, so the p-base region 113 will be completely It is converted to an n ⁺ inversion layer, and then the on-state voltage drop of the device can be the same as the on-state voltage drop of the pin diode. However, a mesa having a width of about 20 nm in device 100 is actually very difficult to manufacture.

Summary of the invention

In view of the disadvantages of high IGBT conduction loss produced by the conventional manufacturing method in the prior art mentioned above, the present invention provides a novel manufacturing method of an insulated gate bipolar transistor, which can be made theoretical by a special manufacturing method. The lowest on-state voltage drop.

The technical solution adopted by the present invention to solve the technical problem thereof is: a manufacturing method of an insulated gate bipolar transistor, the manufacturing method comprising the following steps:

(1) fabricating a lightly doped substrate wafer;

(2) forming a dielectric layer (333) on the wafer;

(3) depositing an undoped polysilicon layer on the dielectric layer (333);

(4), the undoped polysilicon layer and the dielectric layer (333) are patterned to form a gate trench (541);

(5) depositing silicon to form single crystal silicon on the surface of the single crystal silicon, and forming polysilicon on the remaining portion of the surface of the wafer;

(6) forming a gate dielectric (332);

(7) forming a gate electrode (322) by polysilicon deposition and etch back,

(8) forming a polysilicon base region (313) by ion implantation and driving in,

(9) forming a heavily doped polysilicon emitter region (311) and a polysilicon diffusion region (312),

(10) depositing an interlayer dielectric (331);

(11) patterning the interlayer dielectric (331),

(12) forming an emitter (321) by depositing a metal layer and patterning,

(13) thinning the wafer to form a drift region (314),

(14) forming a buffer zone (315) on the back side by ion implantation and annealing,

(15) forming a collector region (316) on the back side by ion implantation and annealing,

(16), forming the collector (323) on the back side by depositing a metal layer and alloying.

The technical solution adopted by the present invention to solve the technical problem thereof further includes:

The gate dielectric (332) is formed by oxidizing the surface of the wafer.

The gate dielectric (332) is formed by oxidizing the surface of the wafer and subsequently depositing a high K dielectric.

The dielectric (333) is silicon oxide or silicon nitride. When the dielectric (333) is silicon oxide, it is formed by deposition or thermal oxidation. When the dielectric (333) is silicon nitride, it is formed by deposition. .

The interlayer dielectric (331) is made of silicon oxide.

In the step (14), the annealing is laser annealing or low temperature annealing.

The beneficial effects of the present invention are that the IGBT produced by the manufacturing method of the present invention can have a theoretically lowest on-state voltage drop.

The invention will be further described with reference to the drawings and specific embodiments.

DRAWINGS

1 is a schematic cross-sectional view of a prior art IGBT device.

2 is a schematic diagram of an electron-hole plasma concentration distribution and an ideal concentration distribution in a drift region of a prior art IGBT device.

FIG. 3 is a schematic structural view of a gate trench formed in the present invention.

4 is a schematic view showing the structure of a channel region in the present invention.

FIG. 5 is a schematic view showing the structure of the gate structure in the present invention.

Figure 6 is a schematic view showing the structure of the p-base region after formation in the present invention.

Figure 7 is a schematic view showing the structure of the n ⁺ emitter region and the p ⁺ diffusion region in the present invention.

Figure 8 is a schematic view showing the structure of an interlayer dielectric and an emitter in the present invention.

Figure 9 is a schematic view showing the structure of the back side structure in the present invention.

Figure 10 is a schematic cross-sectional view of the finished product of the present invention.

Figure 11 is a top plan view of the finished product of the present invention.

detailed description

This embodiment is a preferred embodiment of the present invention, and other principles and basic structures are the same as or similar to those of the present embodiment, and are all within the scope of the present invention.

The present invention will be described using an n-channel device, but it will be understood in the following description that the present invention is equally applicable to a p-channel device having a structure similar to that of an n-channel device except that the doping regions are doped. The impurity type is just the opposite, which is recognized in the industry. Therefore, the present invention only describes the structure by taking the N-channel as an example, and the structural description for the p-channel device is omitted.

The present invention primarily protects a method of fabricating an insulated gate bipolar transistor, the method of manufacture comprising the steps of:

(1) starting with a lightly doped substrate wafer;

(2) forming a dielectric layer 333 on the wafer. In the embodiment, the buried dielectric 333 has a thickness between 3 μm and 10 μm;

(3) depositing an undoped polysilicon layer on the dielectric layer 333;

(4), the undoped polysilicon layer and dielectric layer 333 is patterned to form a gate trench 541;

(5) depositing silicon to form single crystal silicon on the surface of the single crystal silicon and remaining on the surface of the wafer Forming polysilicon thereon;

(6) forming a gate dielectric 332. In the present embodiment, the gate dielectric 332 is formed by oxidizing the surface of the wafer, and may also oxidize the surface of the wafer and subsequently deposit a high-k dielectric. Forming;

(7) forming a gate electrode 322 by polysilicon deposition and etch back,

(8) forming a polysilicon base region 313 by ion implantation and driving, the polysilicon base region 313 having a width of between 5 nm and 20 nm.

(9) forming a heavily doped polysilicon emitter region 311 and a polysilicon diffusion region 312. In this embodiment, the emitter region 311 has a doping concentration of 1×10 ¹⁹ cm ⁻³ to 1×10 ²¹ cm ⁻³ , and a diffusion region 312 has a doping concentration of 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²¹ cm ^-3 ,

(10) depositing an interlayer dielectric 331 (ILD),

(11), performing patterning processing on the ILD 331,

(12) forming an emitter 321 by depositing a metal layer and patterning,

(13) thinning the wafer to form a drift region 314. In the embodiment, the drift region 314 has a doping concentration of 1×10 ¹² cm ⁻³ to 1×10 ¹⁵ cm ⁻³ and a range between 30 μm and 400 μm. length,

(14) Forming a buffer region 315 on the back side by ion implantation and annealing. In this embodiment, the buffer region 315 has a relatively higher doping concentration than the drift region 314 and is relatively shorter than the drift region 314. length,

(15) forming a collector region 316 on the back side by ion implantation and annealing. In this embodiment, the collector region 316 has a doping concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 and a depth between 0.1 μm and 1 μm,

(16) The collector electrode 323 is formed on the back side by depositing a metal layer and alloying.

Please refer to FIG. 3, which is the formation of the gate trench 541. As shown in the figure, the fabrication process begins with an n ^- substrate wafer, and since a portion of the n ^- substrate will become an n ^- drift region 314, the doping concentration of the n ^- substrate should be the same as the n ^- drift region. The target doping concentration in 314 is the same. First, a dielectric layer 333 is formed on the wafer, which is typically silicon oxide or silicon nitride. Silicon oxide can be formed by deposition or thermal oxidation, and silicon nitride can be formed by deposition. Thereafter, an undoped polysilicon layer is deposited over dielectric layer 333, and then undoped polysilicon and dielectric 333 are patterned to form gate trenches 541. In this embodiment, the patterning is typically light. Formed by a combination of engraving and etching. During the etch, an over etch is required to ensure that the dielectric 333 is completely etched. Therefore, a portion of the silicon substrate is also etched away during etching.

Please refer to FIG. 4, which shows the formation of the channel region of the device. As shown in the figure, a thin polysilicon layer is formed on the sidewall of the gate trench 541. In this embodiment, a thin polysilicon layer is formed by silicon deposition, which is usually a chemical vapor deposition. . The deposition will form polysilicon on the sidewalls of the buried dielectric 333 and the surface of the doped polysilicon, while at the same time it will also form single crystal silicon on the surface of the single crystal silicon at the bottom of the gate trench 541. Since the deposited polysilicon is doped in the subsequent steps to form the p-base region 313, the deposition conditions should be well controlled to obtain the target thickness of the p-base region 313.

Please refer to FIG. 5, which shows the formation of a gate structure. First, a gate dielectric 332 is formed on the surface of the gate trench 541 and the remaining portion of the wafer surface. In one embodiment of the invention, gate dielectric 332 is formed by oxidizing the surface of the wafer, and thus gate dielectric 332 is silicon oxide; in another embodiment of the invention, gate dielectric 332 is formed by oxidizing the surface of the wafer. And then deposited by depositing a high K dielectric, and thus gate dielectric 332 is a combination of silicon oxide and high K dielectric. After forming the gate dielectric 332, the gate electrode 322 is formed by in-situ doped polysilicon deposition and etch back. After this step, the gate trench 541 is filled with a gate dielectric 332 and a gate electrode 322.

Please refer to FIG. 6, which shows the formation of the p-base region 313. The p base region 313 is formed by ion implantation and diffusion diffusion. Due to the high density of grain boundaries in the polysilicon, the diffusion coefficient in the polysilicon region is much higher than in the single crystal silicon region. Therefore, after the diffusion is driven, the p-base region 313/n ^- drift 314 junction is located at the boundary between the adjacent polysilicon and the single crystal silicon.

Referring to Figure 7, Figure 7 shows the formation of n ⁺ emitter region 311 and p ⁺ diffusion region 312. Both regions are polysilicon regions, and both regions are doped by ion implantation and annealing. Since the diffusion coefficient in the polysilicon region is much higher than the diffusion coefficient in the single crystal silicon region, the annealing should have a small thermal process. For example, under the premise of controlling the thermal process, a rapid thermal anneal is preferably used to fully activate the dopant. The p ⁺ diffusion region 312 is not shown in the drawing because it is placed in parallel with the n ⁺ emitter region 311, as shown in FIG.

Referring to Figure 8, Figure 8 shows the formation of an interlayer dielectric 331 (ILD) and an emitter 321 . First, an interlayer dielectric 331 is deposited on the surface of the wafer, and the interlayer dielectric 331 is usually made of silicon oxide, but is not limited to silicon oxide. Subsequently, the interlayer dielectric 331 is patterned by photolithography and etching, after which a metal layer is deposited, and then the metal layer is patterned to form the emitter 321 by photolithography and etching.

Please refer to Figure 9, which shows the formation of the back side structure. First, the wafer is thinned from the back side to form an n ^- drift region 314. Then, an n-buffer 315 is formed on the back side of the wafer by ion implantation and annealing. In this embodiment, the annealing is usually laser annealing or low-temperature annealing to avoid melting of the emitter 321 . After that, a p ⁺ collector region 316 is formed on the back side of the wafer by ion implantation and annealing. Then, a collector electrode 323 is formed on the back side of the wafer by metal deposition. Finally, the alloy is alloyed to reduce the contact resistance between the electrode and the semiconductor region. In this embodiment, the alloy is a common step in wafer fabrication by placing the wafer into a furnace tube at about 400 ° C and introducing nitrogen gas. And hydrogen, which causes the metal and silicon to form an alloy at the contact location, the purpose of which is to reduce the contact resistance between the metal and the silicon.

Deposition, patterning treatment, surface oxidation of wafer, etch back, ion implantation and drive-in diffusion, thinning, ion implantation, metal layer alloy, thermal oxidation, photolithography, etching, chemical vapor deposition For the product, laser annealing, and low temperature annealing, the crystal fabrication method in the conventional technology is used.

Claims

A manufacturing method of an insulated gate bipolar transistor, characterized in that the manufacturing method comprises the following steps:

(1) fabricating a lightly doped substrate wafer;

(2) forming a dielectric layer (333) on the wafer;

(3) depositing an undoped polysilicon layer on the dielectric layer (333);

(4), the undoped polysilicon layer and the dielectric layer (333) are patterned to form a gate trench (541);

(5) depositing silicon to form single crystal silicon on the surface of the single crystal silicon, and forming polysilicon on the remaining portion of the surface of the wafer;

(6) forming a gate dielectric (332);

(7) forming a gate electrode (322) by polysilicon deposition and etch back,

(8) forming a polysilicon base region (313) by ion implantation and driving in,

(9) forming a heavily doped polysilicon emitter region (311) and a polysilicon diffusion region (312),

(10) depositing an interlayer dielectric (331);

(11) patterning the interlayer dielectric (331),

(12) forming an emitter (321) by depositing a metal layer and patterning,

(13) thinning the wafer to form a drift region (314),

(14) forming a buffer zone (315) on the back side by ion implantation and annealing,

(15) forming a collector region (316) on the back side by ion implantation and annealing,

(16), forming the collector (323) on the back side by depositing a metal layer and alloying.
The method of fabricating an insulated gate bipolar transistor according to claim 1, wherein said gate dielectric (332) is formed by oxidizing a surface of said wafer.
A method of fabricating an insulated gate bipolar transistor according to claim 1, wherein: The gate dielectric (332) is formed by oxidizing the surface of the wafer and subsequently depositing a high K dielectric.
The method of fabricating an insulated gate bipolar transistor according to claim 1, wherein said dielectric (333) is silicon oxide or silicon nitride, and when dielectric (333) is silicon oxide, it is deposited or heated. It is formed by oxidation, and is formed by deposition when the dielectric (333) is silicon nitride.
The method of fabricating an insulated gate bipolar transistor according to claim 1, wherein said interlayer dielectric (331) is made of silicon oxide.
The method of manufacturing an insulated gate bipolar transistor according to claim 1, wherein in the step (14), the annealing is performed by laser annealing or low temperature annealing.