WO2017160282A1

WO2017160282A1 - Parasitic-aware integrated substrate balanced filter and apparatus to achieve transmission zeros

Info

Publication number: WO2017160282A1
Application number: PCT/US2016/022477
Authority: WO
Inventors: Sidharth Dalmia
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2016-03-15
Filing date: 2016-03-15
Publication date: 2017-09-21
Anticipated expiration: 2018-09-15
Also published as: US20210210442A1; US11469190B2

Abstract

Described is an apparatus which comprises: a first transmission path for a first frequency band; a second transmission path for a second frequency band different from the first frequency band; a node common to the first and second transmission paths, the node to be coupled to an antenna; and a transmission-zero circuit coupled to the common node.

Description

PARASITIC- AWARE INTEGRATED SUBSTRATE BALANCED FILTER AND APPARATUS TO ACHIEVE TRANSMISSION ZEROS

BACKGROUND

[0001] The Radio Frequency (RF) frontend and discrete silicon passive components

(e.g., inductors, antennas, capacitors, etc.) can occupy approximately 50% to 70% area of a platform (e.g., a circuit board of a handheld phone). The frontend can cost approximately 30% to 50% of the total Bill of Materials (BOM), and increase power consumption by approximately 10% to 20%. Currently RF designs use discrete components from commonly made using Low Temperature Co-fired Ceramic (LTCC) processes. However, LTCC is very expensive and challenging for use in space constrained cost sensitive applications.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1 illustrates a cross-section of a computing platform with standalone components of a radio frequency (RF) frontend positioned on the surface of a laminate.

[0004] Fig. 2 illustrates a cross-section of a computing platform with integrated components of a RF frontend within a laminate or substrate, according to some embodiments of the disclosure.

[0005] Fig. 3 illustrates a differential balanced diplexer with integrated balun, diplexer, and bandpass filter, according to some embodiments of the disclosure.

[0006] Fig. 4A illustrates a parasitic-aware differential balanced diplexer with integrated balun, diplexer, and bandpass filter, according to some embodiments of the disclosure.

[0007] Fig. 4B illustrates a parasitic-aware differential balanced multiplexer with multiplexer and bandpass filter, according to some embodiments of the disclosure.

[0008] Figs. 5A-B illustrate three-dimensional (3D) views, respectively, of the parasitic-aware differential balanced diplexer formed in a 4-layer substrate, according to some embodiments of the disclosure. [0009] Fig. 6 illustrates a part of a parasitic-aware differential balanced diplexer with integrated balun, diplexer, and bandpass filter, according to some embodiments of the disclosure.

[0010] Fig. 7 illustrates a plot showing frequency response (e.g., scattering parameters) of the parasitic-aware balanced diplexer of Fig. 4A, according to some embodiments of the disclosure.

[0011] Fig. 8 illustrates part of a differential balanced diplexer which can achieve transmission zeroes using a parasitic-aware approach, according to some embodiments of the disclosure.

[0012] Fig. 9 illustrates a plot showing frequency response (scattering parameters) of the balanced diplexer of Fig. 8, according to some embodiments of the disclosure.

[0013] Fig. 10 illustrates a differential balanced diplexer with apparatus to achieve transmission zeros, according to some embodiments of the disclosure.

[0014] Fig. 11 illustrates a differential balanced diplexer with apparatus to achieve transmission zeros, according to some embodiments of the disclosure.

[0015] Fig. 12 illustrates a differential balanced diplexer with apparatus to achieve transmission zeros, according to some embodiments of the disclosure.

[0016] Fig. 13 illustrates a smart device or a computer system or a SoC (System-on-

Chip) which is partially implemented in the laminate/substrate, according to some embodiments.

DETAILED DESCRIPTION

[0017] Fig. 1 illustrates cross-section 100 of a computing platform (e.g., a circuit board of a handheld phone) with standalone components of a radio frequency (RF) frontend positioned on the surface of a laminate. Cross-section 100 comprises a printed circuit board (PCB) 101, solder balls 102, laminate or substrate 103 with micro-bumps and redistribution layer, RF active and passive devices 104 (e.g., wireless chip), surface mount devices (SMDs) 105 and 106, and mold compound 107. SMDs 105 and 106 may include frontend components such as baluns, antennas, diplexers, multiplexers, filters (e.g., bandpass and low pass filers), etc. These SMDs perform important functions. For example, baluns are used for eliminating common mode noise, diplexers and multiplexers allow for antenna sharing, and bandpass/low-pass filters reject unwanted signals and blockers. As more frequency bands are added to computing platforms to provide additional services, the number of components grows further. These components, however, can occupy approximately 50% to 70% area of the platform and can cost approximately 30% to 50% of the total Bill of Materials (BOM).

[0018] Some embodiments describe an integrated substrate frontend (iSFE) formed by printing the SMDs and other components in the packaging substrates (e.g., laminates) or host PCB. As such, savings in lateral area and height of the platform are realized.

Additionally, a highly integrated computing platform is achieved.

[0019] Some embodiments describe an apparatus (e.g., a computing platform) which comprises a die (e.g., processor die) with a first side and a first set of solder balls coupled to the die along the first side. The apparatus further comprises a laminate based substrate adjacent to the first set of solder balls, where the laminate based substrate includes a parasitic-aware balanced diplexer embedded in it, and where the parasitic-aware balanced diplexer is communicatively coupled to the first die via at least one of the solder balls of the first set. Here, the laminate forms the iSFE.

[0020] In some embodiments, an apparatus is provided which comprises: a first transmission path for a first frequency band and a second transmission path for a second frequency band different from the first frequency band. In some embodiments, the apparatus further comprises a node common to the first and second transmission paths, such that the node is to be coupled to an antenna. In some embodiments, the apparatus comprises a transmission-zero circuit coupled to the common node. In some embodiments, the transmission-zero circuit provides transmission zeros which are frequencies where signal transmission between input and output is stopped. A filter, for example, uses the

transmission zero frequencies together with the passband edge frequencies and passband ripple to form the transfer function between the input and output of the filter, and for shaping the response of the filter. In some embodiments, the apparatus with transmission-zero circuit is part of the iSFE.

[0021] The iSFE of the various embodiments is lower in cost than any known integration schemes such as Low Temperature Co-fired Ceramic (LTCC) processes. The iSFE of various embodiments can be customized to silicon (Si) as standalone component or integrated in Si package or in PCB on which the Si resides.

[0022] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0023] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0024] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0025] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term "scaling" generally also refers to downsizing layout and devices within the same technology node. The term "scaling" may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value.

[0026] Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. [0027] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right," '^"front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0028] Fig. 2 illustrates cross-section 200 of a computing platform with integrated components of a RF frontend within a laminate or substrate, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0029] Cross-section 200 illustrates laminate 203 with integrated SMDs 205 and 206.

Compared to cross-section 100, here BoM is reduced because discrete components 105 and 106 are no longer needed as standalone components and are fully integrated into laminate 203 forming fully iSFE. In some embodiments, laminate 203 uses standard silicon package substrate technology with minimum layer counts (e.g., less than 5 layers) and

integrating/printing the functionality of the entire frontend in substrate 203. Laminate based substrate 203 of the various embodiments is manufactured at low cost using traditional schemes such as core base or coreless substrates. The laminate based substrate 203 of the various embodiments is conducive for silicon package or standalone component with thin core and thin pre-impregnated layers. The laminate based substrate 203 of the various embodiments is also conducive for fan-out and for iSFE. In some embodiments, laminate 203 can have one metal layer as the minimum number of layers or multiple layers depending on the availability of substrate thickness.

[0030] In some embodiments, when using a 1 layer or 1.5 layer laminate or low layer count, solder connections can be used instead of vias and the area underneath the device on main PCB can be used to draw portions of inductors and capacitors too. Although, Fig. 2 shows solder balls on the top side and the bottom side of substrate, it is understood that the solder balls can be replaced with a LGA (Land Grid Array) connection where the solder ball is replaced with regular SMT (Surface Mount Technology) connection. In some

embodiments, Cu (Copper) pillars on top and bottom or one of the planes can use used. In some embodiments, the substrate can have cavity for the die alongside the integrated passive components. [0031] In some embodiments, laminate 203 can be made using convention materials used in commonplace packages and PCBs. In some embodiments, the material permeability (Er) of laminate 203 ranges from 2-30. In some embodiments, the thickness of laminate 203 can range from 2 μηι to 200 μηι depending on density and isolation requirements. In some embodiments, laminate 203 can be made using microvias and through-holes or just one of the interconnects. In some embodiments, laminate 203 can be as minimal as 2 metal layers with one core/prepreg material. In some embodiments, the laminate based substrate is independent of microvias.

[0032] When using minimal number of metal layers or thin packaging substrates, it is understood that the presence of ground locally can add significant parasitics; while such parasitics are very useful in certain instances they can also degrade the coupling between the mutually coupled inductors. In one such embodiment, the main layers of the package may not have locally present ground around in certain areas. Additionally, it is also understood that several of the components in schematics can be implemented using discrete components such as SMT bandpass filters, SMT capacitors and inductors or on Si capacitors and inductors; it is not imperative that all portions are always integrated as printed components on the substrate. Some embodiments can also have an odd number of layers in coreless implementation of such substrate. When using minimal number of layers, the techniques of various embodiments lend themselves extremely well for flexible/bendable electronics.

[0033] By using the right combination of materials, thicknesses, design rules, and architecture, a complete WiFi, BT (Bluetooth), and a global navigation satellite system

(GNSS) frontend can be implemented and integrated in substrate 203. However the embodiments are not limited to the above communication standards. In some instances, hardware associated with other standards such as WiGig (by Wireless Gigabit Alliance) or 5G (fifth generation mobile network or wireless system) signal, which are greater than 10 GHz, can be implemented and integrated in substrate 203. As such, most if not all the standalone components around silicon chip 104 can be completely or near completely eliminated and the package can be made thinner, cheaper, smaller, and better performing. For example, the thickness of mold compound 207 is less than the thickness of mold compound 107, and as such package thickness (e.g., height) is reduced.

[0034] In some embodiments, laminate 203 includes an integrated parasitic-aware balanced filter for each frequency band which can be connected to other balanced filters in other frequency band with minimal circuitry. As such, single-ended antenna sharing or dipole antenna sharing across multiple bands is achieved in accordance with some embodiments. In some embodiments, dominant inductive and dominant parasitic capacitive designs are employed to integrate frontend components in ultra-thin substrate 103 and PCB 101 without additional processing costs and without the need for non-standard PCB/substrate materials. By using parasitic capacitances, minimal number of physical realizable components are used to achieve desired responses in-band and out-of-band. In some embodiments, no physical ground is used in the package itself. Instead, in some

embodiments, the ground of the reference board is used to free up a metal layer of laminate 203 and/or PCB 101.

[0035] Fig. 3 illustrates a differential balanced diplexer with integrated balun, diplexer, and bandpass filter, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0036] In some embodiments, balanced diplexer 300 comprises a first differential path, a second differential path, and a common node coupling the first and second differential paths to antenna 403. In some embodiments, balanced diplexer 300 includes an output impedance (e.g., 50 Ohms) matched to the input impedance of antenna 301. In some embodiments, first differential path comprises differential input impedance Rl (e.g., 50 Ohms), capacitors CI, C2, C3, C3, and C5, and inductors LI and L2.

[0037] In some embodiments, differential input impedance Rl is provided by a resistor having a first terminal coupled to one input port (e.g., '+' port) and another terminal coupled to another input port (e.g., '+' port). In some embodiments, capacitor CI has a first terminal coupled to the input port and the first terminal of resistor Rl . In some embodiments, the second terminal of capacitor CI is coupled to a first terminal of inductor LI . In some embodiments, capacitor C2 has a first terminal coupled to the input port and the second terminal of resistor Rl . In some embodiments, the second terminal of capacitor C2 is coupled to a second terminal of inductor LI . In some embodiments, capacitor C3 is coupled in parallel to inductor LI . In some embodiments, inductor LI is inductively coupled to inductor L2. In some embodiments, a first terminal of inductor L2 is coupled to a first terminal of capacitor C4 and a first terminal of capacitor C5. In some embodiments, a second terminal of inductor L2 is coupled to ground. In some embodiments, capacitor C5 is coupled in parallel to inductor L2. In some embodiments, a second terminal of capacitor C4 is coupled to the common node. In some embodiments, an output impedance (e.g., a 50 Ohms resistor R2) is coupled to the common node.

[0038] In some embodiments, inductors LI and L2 together function as a balun. A balun is a four port device (or effectively a 3-port device because one port is coupled to ground) and is an electrical device that converts between a balanced signal (e.g., two signals working against each other where ground is irrelevant) and an unbalanced signal (e.g., a single signal working against ground or pseudo-ground).

[0039] In some embodiments, the first and second differential paths provide the diplexer function of apparatus 300. A diplexer receives two inputs and diplexes them for antenna 301 coupled to the diplexer. A diplexer is a passive device that implements frequency-domain multiplexing. For example, two ports (e.g., high frequency port and low frequency port) are multiplexed onto an output port. The high frequency port generally provides signals on a first frequency band (e.g., 5 GHz band) while the low frequency port generally provides signals on a second frequency band (e.g., 2.4 GHz), where the first frequency band has a frequency higher than a frequency of the second frequency band. The signals on the low frequency port and the high frequency port occupy disjoint frequency bands. Accordingly, the signals on the low frequency port and the high frequency port can coexist on the output port without interfering with each other. The output port of the diplexer is coupled to antenna 301.

[0040] In some embodiments, antenna 301 is one of: monopole antennas, dipole antennas, loop antennas, patch antennas, microstrip antennas, coplanar wave antennas, or other types of antennas suitable for transmission of Radio Frequency (RF) signals. In some multiple-input multiple-output (MIMO) embodiments, antenna array 305 are separated to take advantage of spatial diversity.

[0041] In some embodiments, the capacitors CI, C2, and C3 together with inductor

LI and resistor Rl provide the bandpass filter (BPF) function. BPF is a filter that passes frequencies within a certain range and rejects or attenuates frequencies outside of that range. In some embodiments, capacitor Ca is provided such that a first terminal of capacitor Ca couples to the second terminal of CI and the first terminal of inductor LI, while a second terminal of capacitor Ca couples to ground. In some embodiments, the capacitance of Ca is much less than the capacitances of capacitors CI, C2, C3, C4, and C5. In some

embodiments, capacitor Cb is provided such that a first terminal of capacitor Cb couples to the second terminal of C2 and the second terminal of inductor LI, while a second terminal of capacitor Cb couples to ground.

[0042] In some embodiments, the capacitance of capacitor Cb is much less than the capacitances of capacitors CI, C2, C3, C4, and C5. In some embodiments, capacitances of capacitors Ca and Cb are the same. In some embodiments, capacitances provided by capacitors Ca and Cb are provided by parasitic capacitances of capacitors CI, C2, and C3. As such, capacitors CI, C2, and C3 are designed to be large so that capacitors Ca and Cb are removed and parasitic capacitances of capacitors CI, C2, and C3 provide the function of capacitors Ca and Cb, in accordance with some embodiments. In some embodiments, all components of the differential balanced filter or balanced diplexer 300 provide band pass function.

[0043] The differential design of Fig. 3 uses coupled inductor topology where inductor L2 (and L2') is single-ended whereas inductor LI (and LI ') provide differential signal, in accordance with some embodiments. In some embodiments, the inductor coupling for each frequency band is tailored to meet the desired bandwidth. In some embodiments, the capacitors C3 and C5 of the first differential path which are parallel to inductors LI and L2, respectively, provide the desired frequency pole for the first differential path. In some embodiments, the capacitors C3' and C5' of the second differential path, which are parallel to inductors LI ' and L2', respectively, provide the desired frequency pole for the second differential path.

[0044] In some embodiments, the series capacitors CI, C2, and C4 for the first differential path match to the desired impedance (e.g., 25 Qs to 100 Qs). In some embodiments, the series capacitors CI ', C2', and C4' for the second differential path match to the desired impedance (e.g., 25 Qs to 100 Qs). In other embodiments, to match Si (Silicon) power amplifiers directly, the differential or single ended impedance can be as low as 1-10 Ohms with some reactance. In some such embodiments, a portion of circuitry may be implemented on the Si (silicon) itself. For example, capacitors and capacitor banks can be implemented in silicon itself where impedance and frequency tenability is also achieved.

[0045] In some embodiments, the filters can connect together without the need for additional matching, phasing, and multiplexing phasors at the common node. In some embodiments, inductors LI, L2, LI ', and L2' are large (e.g., the range can be 0.5nH to 30nH) whereas capacitors (CI, C2, C3, C4, C5, CI ', C2', C3', C4', and C5') are small (e.g., in the range of 0.01 pF to 5 pF) so that diplexer 300 can be realized in a small size using standard PCB and packaging dielectrics.

[0046] In some embodiments, the second differential path has a similar structure and layout (or floorplan) as the first differential path but with different capacitors and inductors (e.g., different values of capacitances and inductances). Here, the second differential path comprises differential input impedance Rl ' (e.g., 50 Ohms), capacitors CI ', C2', C3', Ca', Cb', C4', and C5', and inductors LI ' and L2'.

[0047] In some embodiments, lower frequency band (e.g., 2.4 GHz) produces a very high input impedance at the input ports of the upper band (e.g., 5 GHz) while the upper frequency band (e.g., 5 GHz) provides a very high impedance at the input ports of the lower band (e.g., 2.5 GHz). As such, signals on the first and second differential paths remain separate and avoid interference. The common node provides a single-ended port to a multiband antenna (e.g., antenna 301), in accordance with some embodiments. In some embodiments, antenna 301 is formed in laminate 203. In some embodiments, antenna 301 is formed outside of laminate 203.

[0048] Fig. 4A illustrates a parasitic-aware differential balanced diplexer 400 with integrated balun, diplexer, and bandpass filter, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 4A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig. 4A and Fig. 3 are described.

[0049] In some embodiments, parasitic-aware differential balanced diplexer 400 has fewer components than differential balanced diplexer 300. Here, capacitors C3, Ca, Cb, and C5 of Fig. 3 are eliminated from the first differential path, and capacitors C3', Ca', Cb', and C5' of Fig. 3 are eliminated from the second differential path. Functionally, parasitic-aware differential balanced diplexer 400 and differential balanced diplexer 300 behave the same but for fewer components and thus lower cost.

[0050] In some embodiments, for the first differential path, capacitors CI, C2, and C4 are made large enough to provide the capacitive effects of capacitors C3, Ca, Cb, and C5. For example, parasitic capacitances of capacitors CI, C2, and C4 provide the capacitive effects of capacitors C3, Ca, Cb, and C5 without needing to fabricate capacitors C3, Ca, Cb, and C5. In some embodiments, for the second differential path, capacitors CI ', C2', and C4' are made large enough to provide the capacitive effects of capacitors C3', Ca', Cb', and C5'. For example, parasitic capacitances of capacitors CI ', C2', and C4' provide the capacitive effects of capacitors C3', Ca', Cb', and C5' without needing to fabricate capacitors C3', Ca', Cb', and C5'. As such, fabrication cost is reduced, and parasitic-aware differential balanced diplexer 400 can be integrated in laminate 203, in accordance with some embodiments.

[0051] Fig. 4B illustrates a differential balanced multiplexer or triplexer 420 with multiplexer/triplexer and bandpass filter, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 4B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of the disclosure, differences between Fig. 4A and Fig. 4B and Fig. 3 are described. In some embodiments, a tap to ground is added to inductor LI (and LI '). In some embodiments, capacitors C3 (and C3') of Fig. 3 are placed with a series combination of inductor L3 and capacitor C3 (and L3' and C3'). In some embodiments, this series combination of inductor and capacitor acts as capacitor in band but with a notch at higher frequencies. The parasitic- aware differential balanced multiplexer or triplexer 420 may be the same size of differential balanced multiplexer or triplexer 300, but with additional inductor L3 and capacitor C3 (and L3' and C3'). As such, a higher performing differential balanced multiplexer or triplexer 420 is achieved with little or no increase in area using parasitic-aware design approach.

[0052] Figs. 5A-B illustrates three-dimensional (3D) views 500 and 520, respectively, of the parasitic-aware differential balanced diplexer formed in a 4-layer substrate 203, according to some embodiments of the disclosure. The 3D view 500 illustrates a compact design of Fig. 4A using fewer components than a fabricated design of Fig. 3. The layout of parasitic-aware differential balanced diplexer 400 shown in the 3D view 500 uses two layers of laminate 203, in accordance with some embodiments. As such, an integrated balun, diplexer, and filter is realized using fewer number of components. The 3D view 520 illustrates a compact design of Fig. 4B, in accordance with some embodiments.

[0053] Fig. 6 illustrates a part of a parasitic-aware differential balanced diplexer 600 with integrated balun, diplexer, and bandpass filter, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig. 6 and Fig. 3 are described. Fig. 6 illustrates a first differential path, and it is similar to the first differential path of Fig. 3. Here, an additional capacitor C6 is added in parallel to capacitor C5.

[0054] Fig. 7 illustrates plot 700 showing frequency response (scattering parameters) of the balanced diplexer of Fig. 4A, according to some embodiments of the disclosure. Here, x-axis is frequency in Giga-Hertz (GHz) and y-axis is decibels (dB). Here, curve 701 is the passband for the first differential path (high frequency band) from 5.15 GHz to 5.85 GHz; and curve 702 is the return loss at the antenna port (or common node).

[0055] Fig. 8 illustrates part of a differential balanced diplexer 800 which can achieve transmission zeroes without the need for additional components, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig. 8 and Fig. 3 and Fig. 6 are described.

[0056] In some embodiments, transmission zeros are added by capacitors C7 and C8.

In some embodiments, capacitor C7 has a first terminal coupled to the first terminal of inductor LI, and a second terminal coupled to the first terminal of inductor L2. In some embodiments, capacitor C8 has a first terminal coupled to the second terminal of inductor LI, and a second terminal coupled to the second terminal of inductor L2. Capacitors C7 and C8 are coupling capacitors. In some embodiments, transmission zeros are added by using high inductance inductors for inductors LI and L2. In some embodiments, the coupling capacitors C7 and C8 are parasitic capacitors that occur between high inductance inductors LI and L2.

[0057] In some embodiments, naturally occurring coupling capacitances between inductors resonates with the implied value of mutual inductance to create high side transmission zeros. In some embodiments, the parasitic capacitances Ca, Cb, C7, and C8 may induce some imbalance in the phase and amplitude which can be adjusted for by adding an inductor or capacitor to one leg of the differential arm.

[0058] Fig. 9 illustrates plot 900 showing frequency response (scattering parameters) of the balanced diplexer of Fig. 8, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. Here, x-axis is frequency in GHz while y-axis is decibels. Curve 901 is the passband for the first differential path (high frequency band) from 5.15 GHz to 5.85 GHz; and curve 902 is the return loss at the antenna port (or common node). The transmission zero 903 is caused by capacitors C7 and C8, in accordance with some embodiments. In some embodiments, the line width and line spacing of coupled inductors LI and L2 determine the frequency value of the transmission zero.

[0059] Fig. 10 illustrates differential balanced diplexer 1000 with apparatus to achieve transmission zeros, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig.

10 and Fig. 4A are described. In some embodiments, a third inductor L3 is added in parallel to capacitor C4 for the first differential path. In some embodiments, a fourth inductor L4 is added in parallel to capacitor C4' for the second differential path.

[0060] Fig. 11 illustrates a differential balanced diplexer 1100 with apparatus to achieve transmission zeros, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 11 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig.

11 and Fig. 4A are described.

[0061] In some embodiments, for the first differential path, inductor L4 is coupled in series with capacitor C9, and the series combination is coupled to the common node. In some embodiments, capacitor C9 is coupled to the common node while a terminal of inductor L4 is coupled to ground as shown. In some embodiments, for the second differential path, inductor L4' is coupled in series with capacitor C9', and the series combination is coupled to the common node. In some embodiments, capacitor C9' is coupled to the common node while a terminal of inductor L4' is coupled to ground as shown.

[0062] Fig. 12 illustrates differential balanced diplexer 1200 with apparatus to achieve transmission zeros, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 12 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig.

12 and Fig. 4A and Fig. 11 are described.

[0063] In some embodiments, inductor L5 and capacitors CIO and CI 1 are added to provide higher order filters with transmission zeroes. In some embodiments, for the first differential path, a first terminal of inductor L5 is coupled to the second terminal of capacitor C5 which the second terminal of inductor L5 is coupled to ground (e.g., inductor L5 is parallel to capacitor C5 of Fig. 4A). In some embodiments, a first terminal of capacitor CIO is coupled to the second terminal of capacitor C4, and a second terminal of capacitor CIO is coupled to the common node. In some embodiments, a first terminal of capacitor CI 1 is coupled to the first terminal of inductor L2, and a second terminal of capacitor CI 1 is coupled to the common node. In some embodiments, inductor L5 and capacitors CIO and CI 1 adds a third pole to the band, thus increasing the noise rejection of the first differential path. As such, transmission zero is added at lower frequencies with minimal sized capacitors. In some embodiments, the second differential path is same as the one shown in Fig. 11. In other embodiments, the second differential path is similar to the first differential path of Fig. 12

[0064] Fig. 13 illustrates a smart device or a computer system or a SoC (System-on-

Chip) 2500 which is at least partially implemented in the laminate/substrate, according to some embodiments. Fig. 13 illustrates a smart device or a computer system or a SoC

(System-on-Chip) which is partially implemented in the laminate/substrate, according to some embodiments. It is pointed out that those elements of Fig. 13 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0065] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0066] Fig. 13 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 2500 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 2500.

[0067] In some embodiments, computing device 2500 includes a first processor 2510

(e.g., die 104). The various embodiments of the present disclosure may also comprise a network interface within 2570 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0068] In one embodiment, processor 2510 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 2510 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 2500 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0069] In one embodiment, computing device 2500 includes audio subsystem 2520, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 2500, or connected to the computing device 2500. In one embodiment, a user interacts with the computing device 2500 by providing audio commands that are received and processed by processor 2510.

[0070] Display subsystem 2530 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 2500. Display subsystem 2530 includes display interface 2532, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 2532 includes logic separate from processor 2510 to perform at least some processing related to the display. In one embodiment, display subsystem 2530 includes a touch screen (or touch pad) device that provides both output and input to a user. [0071] I/O controller 2540 represents hardware devices and software components related to interaction with a user. I/O controller 2540 is operable to manage hardware that is part of audio subsystem 2520 and/or display subsystem 2530. Additionally, I/O controller 2540 illustrates a connection point for additional devices that connect to computing device 2500 through which a user might interact with the system. For example, devices that can be attached to the computing device 2500 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0072] As mentioned above, I/O controller 2540 can interact with audio subsystem

2520 and/or display subsystem 2530. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 2500. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 2530 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 2540. There can also be additional buttons or switches on the computing device 2500 to provide I/O functions managed by I/O controller 2540.

[0073] In one embodiment, I/O controller 2540 manages devices such as

accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 2500. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0074] In one embodiment, computing device 2500 includes power management 2550 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 2560 includes memory devices for storing information in computing device 2500. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 2560 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 2500.

[0075] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 2560) for storing the computer-executable instructions. The machine-readable medium (e.g., memory 2560) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0076] Connectivity 2570 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 2500 to communicate with external devices. The computing device 2500 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0077] Connectivity 2570 can include multiple different types of connectivity. To generalize, the computing device 2500 is illustrated with cellular connectivity 2572 and wireless connectivity 2574. Cellular connectivity 2572 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 2574 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication. In some embodiments, various frontend components of the cellular connectivity 2574 such as antennas, baluns, diplexers, triplexers, multiplexers, bandpass filters, low pass filters, etc. are implemented as iSFE as described with reference to various embodiments.

[0078] Peripheral connections 2580 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 2500 could both be a peripheral device ("to" 2582) to other computing devices, as well as have peripheral devices ("from" 2584) connected to it. The computing device 2500 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 2500. Additionally, a docking connector can allow computing device 2500 to connect to certain peripherals that allow the computing device 2500 to control content output, for example, to audiovisual or other systems.

[0079] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 2500 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0080] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0081] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive

[0082] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0083] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0084] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0085] For example, an apparatus is provided which comprises: a first transmission path for a first frequency band; a second transmission path for a second frequency band different from the first frequency band; a node common to the first and second transmission paths, the node to be coupled to an antenna; and a transmission-zero circuit coupled to the common node. In some embodiments, the first or second transmission paths comprise: input ports to be communicatively coupled to a first die; an input termination impedance coupled to the input ports; a first inductor; a first capacitor having one terminal coupled to one of the input ports, and another terminal coupled to a first terminal of the first inductor; and a second capacitor having one terminal coupled to one of the input ports, and another terminal coupled to a second terminal of the first inductor.

[0086] In some embodiments, the first or second transmission paths comprise: a second inductor inductively coupled to the first inductor, the second inductor having a first terminal which is to be coupled to ground; and a third capacitor having a first terminal coupled to a first terminal of the second inductor, and a second terminal coupled to the common node. In some embodiments, the transmission-zero circuit comprises: a third inductor coupled in parallel to the third capacitor of the first transmission path; and a fourth inductor coupled in parallel to the third capacitor of the second transmission path. In some embodiments, the transmission-zero circuit comprises: a fourth capacitor; and a third inductor coupled in series with the fourth capacitor, and coupled to the third capacitor of the first transmission path. In some embodiments, transmission-zero circuit comprises: a fifth capacitor; and a fourth inductor coupled in series with the fifth capacitor, and coupled to the third capacitor of the second transmission path. [0087] In another example, a system is provided which comprises: a memory; a processor coupled to the memory; a first set of solder balls coupled to the processor along a first side of the processor; and a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having an apparatus according to the apparatus described above.

[0088] In another example, an apparatus is provided which comprises: a die with a first side; a first set of solder balls coupled to the die along the first side; and a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having a diplexer embedded in it, wherein the diplexer is communicatively coupled to the first die via at least one of the solder balls of the first set. In some embodiments, the diplexer comprises: a first differential transmission path for a first frequency band; a second differential transmission path for a second frequency band different from the first frequency band; and a node common to the first and second differential transmission paths, the node to be coupled to an antenna. In some embodiments, frequency of the first frequency band is higher than a frequency of the second frequency band.

[0089] In some embodiments, an input impedance of the first differential transmission path is to be higher for the second frequency band than an input impedance of the second differential transmission path at the second frequency band. In some embodiments, an input impedance of the second differential transmission path is to be higher for the first frequency band than an input impedance of the first differential transmission path at the first frequency band. In some embodiments, the first or second differential transmission paths comprise: input ports to be communicatively coupled to the die; an input termination impedance coupled to the input ports; a first inductor; a first capacitor having one terminal coupled to one of the input ports, and another terminal coupled to a first terminal of the first inductor; and a second capacitor having one terminal coupled to one of the input ports, and another terminal coupled to a second terminal of the first inductor.

[0090] In some embodiments, first or second differential transmission paths comprise: a second inductor inductively coupled to the first inductor, the second inductor having a first terminal which is to be coupled to ground; and a third capacitor having a first terminal coupled to a first terminal of the second inductor, and a second terminal coupled to the common node. In some embodiments, the laminate based substrate has less than five layers. In some embodiments, the laminate based substrate has a thickness which is less than 30 μιτι. In some embodiments, the apparatus comprises: a second set of solder balls adjacent to the laminate based substrate. In some embodiments, the apparatus comprises: a printed circuit board (PCB) adjacent to the second set of solder balls. In some embodiments, the PCB has metal lines with spacing less than 50 μηι between the metal lines. In some embodiments, the laminate based substrate is independent of a ground plane.

[0091] In another example, a system is provided which comprises: a memory; a processor coupled to the memory; a first set of solder balls coupled to the processor along a first side of the processor; and a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having an apparatus according to the apparatus described above.

[0092] In another example, a method is provided which comprises: coupling a first set of solder balls to a die along a first side of the die; and positioning a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having a diplexer embedded in it, wherein the diplexer is communicatively coupled to the first die via at least one of the solder balls of the first set. In some embodiments, the diplexer comprises: a first differential transmission path for a first frequency band; a second differential transmission path for a second frequency band different from the first frequency band; and a node common to the first and second differential transmission paths, the node to be coupled to an antenna.

[0093] In another example, an apparatus is provided which comprises: means for coupling a first set of solder balls to a die along a first side of the die; and means for coupling a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having a diplexer embedded in it, wherein the diplexer is communicatively coupled to the first die via at least one of the solder balls of the first set. In some embodiments, the diplexer comprises: means for providing a transmission path for a first frequency band; means for providing a differential transmission path for a second frequency band different from the first frequency band; means for merging the transmission path and the differential transmission path; and coupling the means for merging to an antenna.

[0094] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

CLAIMS What is claimed is:

1. An apparatus comprising:

a first transmission path for a first frequency band;

a second transmission path for a second frequency band different from the first frequency band;

a node common to the first and second transmission paths, the node to be coupled to an antenna; and

a transmission-zero circuit coupled to the common node.

2. The apparatus of claim 1, wherein the first or second transmission paths comprise:

input ports to be communicatively coupled to a first die;

an input termination impedance coupled to the input ports;

a first inductor;

a first capacitor having one terminal coupled to one of the input ports, and another terminal coupled to a first terminal of the first inductor; and

a second capacitor having one terminal coupled to one of the input ports, and another terminal coupled to a second terminal of the first inductor.

3. The apparatus of claim 2, wherein the first or second transmission paths comprise:

a second inductor inductively coupled to the first inductor, the second inductor having a first terminal which is to be coupled to ground; and

a third capacitor having a first terminal coupled to a first terminal of the second inductor, and a second terminal coupled to the common node.

4. The apparatus of claim 3, wherein the transmission-zero circuit comprises:

a third inductor coupled in parallel to the third capacitor of the first transmission path; and

a fourth inductor coupled in parallel to the third capacitor of the second transmission path.

5. The apparatus of claim 3, wherein the transmission-zero circuit comprises: a fourth capacitor; and

a third inductor coupled in series with the fourth capacitor, and coupled to the third capacitor of the first transmission path.

6. The apparatus of claim 5, wherein the transmission-zero circuit comprises:

a fifth capacitor; and

a fourth inductor coupled in series with the fifth capacitor, and coupled to the third capacitor of the second transmission path.

7. An apparatus comprising:

a die with a first side;

a first set of solder balls coupled to the die along the first side; and

a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having a diplexer embedded in it, wherein the diplexer is communicatively coupled to the first die via at least one of the solder balls of the first set.

8. The apparatus of claim 7, wherein the diplexer comprises:

a first differential transmission path for a first frequency band;

a second differential transmission path for a second frequency band different from the first frequency band; and

a node common to the first and second differential transmission paths, the node to be coupled to an antenna.

9. The apparatus of claim 8, wherein frequency of the first frequency band is higher than a frequency of the second frequency band.

10. The apparatus of claim 9, wherein:

an input impedance of the first differential transmission path is to be higher for the second frequency band than an input impedance of the second differential transmission path at the second frequency band; and

an input impedance of the second differential transmission path is to be higher for the first frequency band than an input impedance of the first differential transmission path at the first frequency band.

1 1. The apparatus of claim 10, wherein the first or second differential transmission paths comprise:

input ports to be communicatively coupled to the die;

an input termination impedance coupled to the input ports;

a first inductor;

12. The apparatus of claim 11 , wherein first or second differential transmission paths

comprise:

13. The apparatus of claim 7, wherein the laminate based substrate has less than five layers.

14. The apparatus of claim 7, wherein the laminate based substrate has a thickness which is less than 30 μιτι.

15. The apparatus of claim 7 comprises: a second set of solder balls adjacent to the laminate based substrate.

16. The apparatus of claim 15 comprises: a printed circuit board (PCB) adjacent to the second set of solder balls.

17. The apparatus of claim 16, wherein the PCB has metal lines with spacing less than 50 μιτι between the metal lines.

18. The apparatus of claim 7, wherein the laminate based substrate is independent of a ground plane.

19. A system comprising:

a memory;

a processor coupled to the memory;

a first set of solder balls coupled to the processor along a first side of the processor; and

a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having an apparatus according to any one of claims 1 to 6.

20. A system comprising:

a memory;

a processor coupled to the memory;

a laminate based substrate adjacent to the first set of solder balls, the laminate based substrate having an apparatus according to any one of claims 7 to 18.