WO2017151296A1 - Multi-step voltage for forming resistive random access memory (rram) cell filament - Google Patents
Multi-step voltage for forming resistive random access memory (rram) cell filament Download PDFInfo
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- WO2017151296A1 WO2017151296A1 PCT/US2017/017543 US2017017543W WO2017151296A1 WO 2017151296 A1 WO2017151296 A1 WO 2017151296A1 US 2017017543 W US2017017543 W US 2017017543W WO 2017151296 A1 WO2017151296 A1 WO 2017151296A1
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- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 20
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 8
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 description 35
- 230000015572 biosynthetic process Effects 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 3
- 229910003070 TaOx Inorganic materials 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 229910016553 CuOx Inorganic materials 0.000 description 1
- -1 HfOx Chemical class 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910003087 TiOx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/009—Write using potential difference applied between cell electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Definitions
- the present invention relates to non-volatile memory, and more specifically to resistive random access memory.
- Resistive random access memory is a type of nonvolatile memory.
- RRAM memory cells each include a resistive dielectric material layer sandwiched between two conductive electrodes.
- the dielectric material is normally insulating.
- a conduction path typically referred to as a filament
- the filament can be "reset” (i.e., broken or ruptured, resulting in a high resistance across the RRAM cell) and set (i.e., re-formed, resulting in a lower resistance across the RRAM cell), by applying the appropriate voltages across the dielectric layer.
- the low and high resistance states can be utilized to indicate a digital signal of " 1" or "0" depending upon the resistance state, and thereby provide a reprogrammable non- volatile memory cell that can store a bit of information.
- Figure 1 shows a conventional configuration of an RRAM memory cell 1.
- the memory cell 1 includes a resistive dielectric material layer 2 sandwiched between two conductive material layers that form top and bottom electrodes 3 and 4, respectively.
- Figures 2A-2D show the switching mechanism of the dielectric material layer 2. Specifically, Fig. 2A shows the resistive dielectric material layer 2 in its initial state after fabrication, where the layer 2 exhibits a relatively high resistance.
- Fig. 2B shows the formation of a conductive filament 7 through the layer 2 by applying the appropriate voltage across the layer 2. The filament 7 is a conductive path through the layer 2, such that the layer exhibits a relatively low resistance across it (because of the relatively high conductivity of the filament 7).
- Fig. 1 shows a conventional configuration of an RRAM memory cell 1.
- the memory cell 1 includes a resistive dielectric material layer 2 sandwiched between two conductive material layers that form top and bottom electrodes 3 and 4, respectively.
- Figures 2A-2D show the switching mechanism of the dielectric material layer 2. Specifically, Fig
- FIG. 2C shows the formation of a rupture 8 in filament 7 caused by the application of a "reset” voltage across the layer 2.
- the area of the rupture 8 has a relatively high resistance, so that layer 2 exhibits a relatively high resistance across it.
- Fig. 2D shows the restoration of the filament 7 in the area of the rupture 8 caused by the application of a "set” voltage across layer 2.
- the restored filament 7 means the layer 2 exhibits a relatively low resistance across it.
- the relatively low resistance of layer 2 in the "formation" or “set” states of Figs. 2B and 2D respectively can represent a digital signal state (e.g. a "1"), and the relatively high resistance of layer 2 in the "reset” state of Fig. 2C can represent a different digital signal state (e.g.
- the reset voltage (which breaks the filament) can have a polarity opposite that of the filament formation and the set voltages, but it can also have the same polarity.
- the RRAM cell 1 can repeatedly be “reset” and “set,” so it forms an ideal reprogrammable nonvolatile memory cell.
- One of the most critical operations involves the initial formation of the filament, as it will define the switching characteristics of the memory cell (e.g. operational power, device-to-device resistance variation, etc.).
- the voltage and current needed to form the filament are relatively high (i.e. significantly higher than the voltages needed to set and reset the memory cell).
- Using a filament forming voltage that is too low will not adequately form the filament.
- Using an excessive filament forming voltage could cause uncontrolled filament formation which can damage the device and result in inferior resistance switching behaviors. Therefore, there is a need for a reliable and effective technique for initially forming the filaments in RRAM devices.
- the aforementioned problems and needs are addressed by a method of forming a conductive filament in metal oxide material disposed between and in electrical contact with first and second conductive electrodes.
- the method comprises applying a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
- a memory device comprises a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.
- Fig. 1 is a side cross sectional view of a conventional Resistive Random Access Memory (RRAM) cell.
- RRAM Resistive Random Access Memory
- Fig. 2A is a side cross sectional view of the resistive dielectric layer of the conventional RRAM cell in its initial state.
- Fig. 2B is a side cross sectional view of the resistive dielectric layer of the conventional RRAM cell in its formed state.
- Fig. 2C is a side cross sectional view of the resistive dielectric layer of the conventional RRAM cell in its reset state.
- Fig. 2D is a side cross sectional view of the resistive dielectric layer of the conventional RRAM cell in its set state.
- Fig. 3 is a schematic diagram showing the basic components of the RRAM memory device.
- Fig. 4 is a graph illustrating the waveform of the voltage pulses applied to form the filament in the RRAM cell.
- Fig. 5 is a graph illustrating current limits applied to the voltage pulses of Fig. 4.
- Fig. 6 is a graph illustrating current limits applied to the voltage pulses of Fig. 4.
- Fig. 7 is a graph illustrating an alternate waveform of the voltage pulses applied to form the filament in the RRAM cell.
- Fig. 8 is a graph illustrating current limits applied to the voltage pulses of Fig. 7.
- Fig. 9 is a graph illustrating an alternate waveform of the voltage pulses applied to form the filament in the RRAM cell.
- Fig. 10 is a graph illustrating an alternate waveform of the voltage pulses applied to form the filament in the RRAM cell.
- Fig. 11 is a graph illustrating an alternate waveform of the voltage pulses applied to form the filament in the RRAM cell.
- Fig. 12 is a graph illustrating an alternate waveform of the voltage pulses applied to form the filament in the RRAM cell.
- Fig. 13 is a graph illustrating an alternate waveform of the voltage pulses applied to form the filament in the RRAM cell.
- the present invention is an improved technique for initially forming filaments in RRAM devices.
- the technique involves voltage pulses that combine increasing voltages within each pulse, and increasing the maximum achieved voltage pulse-to-pulse, and in combination with controlling and shaping the forming current in a pre-determined manner, to gently form the filaments without excessive voltages that will damage the memory cell.
- the application of the pulses can end at a preset value, or can end after the cell reaches a desired resistance level.
- Fig. 3 illustrates the high level basic structure of an RRAM memory device, which includes the previously described RRAM cell 1, a voltage source 10 for applying voltages across the memory cell 1 for filament formation, cell reset and cell set.
- a resistance detector 12 can be used to measure the electrical resistance across the RRAM cell 1 for filament formation and determining the state of the RRAM cell 1 (i.e. reading the cell). It should be appreciated that while Fig. 3 illustrates only a single RRAM cell 1, the voltage source 10 and resistance detector 12 are connected to and operate on an array of RRAM cells 1. It should also be appreciated at the voltage source 10 and resistance detector 12 could be formed as a single integrated device.
- the electrodes 3 and 4 are made of a metal material (e.g., Pt, Ti, TiN, Ru, Ni, TaN, W, etc.) and resistive dielectric layer 2 is made of a metal oxide (e.g., HfOx, TaOx, TiOx, WOx, Vox, CuOx, etc.).
- resistive dielectric layer 2 can be a composite of discrete sub-layers (e.g. layer 2 could be multiple layers, such as a Hf layer disposed between a TaOx layer and a HfOx layer).
- Fig. 4 illustrates the voltage pulses P applied across electrodes 3 and 4 by voltage source 10 for forming the filament in the resistive dielectric layer 2.
- the voltage increases in increments (i.e., voltage steps V s ), each with an increment duration T s , in a stair-step fashion.
- Each successive pulse P reaches a higher voltage before ending, and has a longer duration T.
- pulse Pi has a first incremental voltage V s applied for an incremental time T s . Then the applied voltage is increased by an additional V s and this second incremental voltage is applied for incremental time T s . Then the applied voltage is increased again by an additional V s and this third incremental voltage is applied for incremental time T s .
- pulse Pi ends, having a total time duration Ti.
- Pulse P 2 is the same as pulse Pi except it has an additional incremental voltage raised by another V s which is applied for incremental time T s , so that the overall duration T 2 of pulse P 2 is greater than the duration Ti of pulse Pi. This iteration continues until the filament formation is completed.
- the filament forming process ends by reaching a predetermined number of pulses P, or the resistance of the resistive dielectric layer 2 as measured between pulses P by resistance detector 12 reaches a desired value which verifies that the filament has been properly formed (i.e. forming verification), or by sensing that the electrical current during an applied voltage source exceeds a predetermined value (also forming verification), or a combination of the above (i.e. cease the process by reaching the predetermined number of pulses unless the measured resistance drops below a predetermined threshold first or the electrical current exceeds a predetermined value first).
- a maximum electrical current limit I (commonly referred to as an electrical current limit, current limit and current compliance limit) can be implemented by voltage source 10 for each pulse, whereby the electrical current for any given pulse cannot exceed the current limit I should the current reach that limit.
- the current limits I for each pulse can be the same, or can vary (e.g. can increase pulse to pulse). For example, as shown in Fig. 5, each of the voltage pulses in Fig. 4 are limited by corresponding current limits that increase for each successive incremental voltage within each pulse. Alternately, each pulse could have just a single current limit I as shown in Fig. 6, where the current limit increases for each successive pulse. By slowly raising the current limit for each pulse (or within each pulse), excessive electrical currents that could cause uncontrollable filament formation can be avoided.
- the current limit can be determined by a combination of the above approaches.
- Fig. 7 illustrates an alternate waveform of pulses P that can be applied across electrodes 3 and 4 for forming the filament. In this waveform, the voltage amplitudes and duration of each pulse P are the same. But, the current limit I for each pulse P is gradually increased as shown in Fig. 8, until the filament is properly formed.
- Fig. 9 illustrates an alternate waveform of pulses P that can be applied across electrodes 3 and 4 for forming the filament.
- each pulse P includes a gradually increasing voltage starting from zero (as opposed to discrete steps described above).
- Each pulse has the same duration T, but each successive pulse ramps the voltage faster and reaches a higher maximum voltage as compared to the previous pulse P.
- a current limit can be applied to these pulses, which is the same pulse to pulse, or which varies pulse to pulse as described above.
- Fig. 10 illustrates an alternate waveform of pulses P that can be applied across electrodes 3 and 4 for forming the filament.
- each pulse P includes a gradually increasing voltage starting from zero. The rate at which the voltage ramps up is the same for each pulse.
- Each successive pulse has a duration T greater than the previous pulse, so each successive pulse reaches a higher maximum voltage as compared to the previous pulse P.
- a current limit can be applied to these pulses, which is the same pulse to pulse, or which varies pulse to pulse as described above.
- Fig. 11 illustrates an alternate waveform of pulses P that can be applied across electrodes 3 and 4 for forming the filament.
- each pulse P includes a gradually increasing voltage.
- the rate at which the voltage ramps up is the same for each pulse, and preferably each successive pulse begins at the voltage level where the previous pulse ended.
- the pulses in this embodiment all have the same duration T, but this duration time could vary as well.
- a current limit can be applied to these pulses, which is the same pulse to pulse, or which varies pulse to pulse as described above.
- Fig. 12 illustrates an alternate waveform of pulses P that can be applied across electrodes 3 and 4 for forming the filament. In this waveform, each pulse P includes a gradually increasing voltage.
- a current limit can be applied to these pulses, which is the same pulse to pulse, or which varies pulse to pulse as described above.
- Fig. 13 illustrates an alternate waveform of pulses P that can be applied across electrodes 3 and 4 for forming the filament.
- This waveform is similar to that of Fig. 5, but with the addition of a small reverse bias voltage at the end of each pulse P (i.e. a voltage of reverse polarity but smaller amplitude compared to that of most the pulse P).
- the reverse bias helps stabilize the oxygen vacancies that form the filament.
- the reverse bias voltages can vary from pulse to pulse in amplitude and/or duration (e.g. the amplitude of reverse bias voltages can increase from pulse to pulse as shown in Fig. 9).
- the reverse bias voltage of this waveform can be added to any of the previously discussed waveforms.
- a current limit can be applied to these pulses, which is the same pulse to pulse, or which varies pulse to pulse as described above.
- references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims.
- Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims.
- not all method steps need be performed in the exact order illustrated or claimed.
- single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
- the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
- forming an element "over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201780014845.8A CN108886094A (en) | 2016-03-04 | 2017-02-10 | It is used to form the multistage voltage of resistive random access memory (RRAM) unit filament |
KR1020187028526A KR101981911B1 (en) | 2016-03-04 | 2017-02-10 | A multi-step voltage (RRAM) cell for forming resistive random access memory (RRAM) cell filaments |
JP2018544244A JP2019511803A (en) | 2016-03-04 | 2017-02-10 | Multi-step voltage for forming resistive random access memory (RRAM) cell filaments |
EP17760463.4A EP3424087A4 (en) | 2016-03-04 | 2017-02-10 | Multi-step voltage for forming resistive random access memory (rram) cell filament |
TW106106805A TWI621122B (en) | 2016-03-04 | 2017-03-02 | Multi-step voltage for forming resistive random access memory (rram) cell filament |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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SG10201601703UA SG10201601703UA (en) | 2016-03-04 | 2016-03-04 | Multi-step voltage for forming resistive random access memory (rram) cell filament |
SG10201601703U | 2016-03-04 | ||
US15/404,087 US9959927B2 (en) | 2016-03-04 | 2017-01-11 | Multi-step voltage for forming resistive access memory (RRAM) cell filament |
US15/404,087 | 2017-01-11 |
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WO2017151296A1 true WO2017151296A1 (en) | 2017-09-08 |
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PCT/US2017/017543 WO2017151296A1 (en) | 2016-03-04 | 2017-02-10 | Multi-step voltage for forming resistive random access memory (rram) cell filament |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113436664A (en) * | 2021-08-26 | 2021-09-24 | 之江实验室 | Linear symmetrical adjustment method for conductance of resistive random access memory unit |
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US20080084751A1 (en) * | 2006-10-10 | 2008-04-10 | Yan Li | Variable program voltage increment values in non-volatile memory program operations |
US20110051504A1 (en) * | 2009-08-31 | 2011-03-03 | Sandisk 3D Llc | Creating short program pulses in asymmetric memory arrays |
US20110305066A1 (en) * | 2010-06-14 | 2011-12-15 | Crossbar, Inc. | Write and erase scheme for resistive memory device |
US8995169B1 (en) * | 2013-09-12 | 2015-03-31 | Sandisk 3D Llc | Method of operating FET low current 3D Re-RAM |
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2017
- 2017-02-10 WO PCT/US2017/017543 patent/WO2017151296A1/en active Application Filing
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US20080084751A1 (en) * | 2006-10-10 | 2008-04-10 | Yan Li | Variable program voltage increment values in non-volatile memory program operations |
US20110051504A1 (en) * | 2009-08-31 | 2011-03-03 | Sandisk 3D Llc | Creating short program pulses in asymmetric memory arrays |
US20110305066A1 (en) * | 2010-06-14 | 2011-12-15 | Crossbar, Inc. | Write and erase scheme for resistive memory device |
US8995169B1 (en) * | 2013-09-12 | 2015-03-31 | Sandisk 3D Llc | Method of operating FET low current 3D Re-RAM |
Non-Patent Citations (1)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN113436664A (en) * | 2021-08-26 | 2021-09-24 | 之江实验室 | Linear symmetrical adjustment method for conductance of resistive random access memory unit |
CN113436664B (en) * | 2021-08-26 | 2021-12-14 | 之江实验室 | Linear symmetrical adjustment method for conductance of resistive random access memory unit |
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