WO2017131687A1

WO2017131687A1 - Signal integrity measurements

Info

Publication number: WO2017131687A1
Application number: PCT/US2016/015275
Authority: WO
Inventors: Peter Hansen; Patrick Raymond
Original assignee: Hewlett Packard Enterprise Development Lp
Priority date: 2016-01-28
Filing date: 2016-01-28
Publication date: 2017-08-03

Abstract

In one example, a configuration block receives a set of signals via a set of connection lines, a bus controller receives a first portion of the set of signals, a converter receives a second portion of the set of signals, and a controller engine executes an operation based on the first portion of the set of signals and measures a signal integrity based on the second portion of the set of signals.

Description

SIGNAL INTEGRITY MEASUREMENTS

Background

[0001] Computing systems can utilize a set of controllers to perform a set of functions. In some examples, the set of controllers can communicate with other computing devices and/or controllers, in some examples, the set of controllers can utilize a pin connector such as a bus connector to send and receive communication signals between the set of controllers and computing devices. In some examples, noise can affect the quality of the communication signals.

Brief Description of the Drawings

[0002] Figure 1 illustrates a diagram of an example system for signal integrity measurements consistent with the present disclosure.

[0003] Figure 2 illustrates a diagram of an example computing device for signal integrity measurements consistent with the present disclosure.

[0004] Figure 3 illustrates a diagram of an example system for signal integrity measurements consistent with the present disclosure.

[0005] Figure 4 illustrates a diagram of an example system for signal integrity measurements consistent with the present disclosure.

[0006] Figure 5 il!ustrates a flow chart of an example method for signal integrity measurements consistent with the present disclosure. Detailed Description

[0007] Computing devices can utilize a communication architecture (e.g., bus architecture, i2c architecture, SPI, Ethernet, serial lines, etc.) to send and receive communication signals with other computing devices. Communication signals transferred by the communication architecture can be compromised by noise as described further herein. In some examples, the noise can degrade the signal integrity of the communication signals.

[0008] In some examples, the degraded signal integrity can cause

communication errors. In previous solutions, the computing devices are tested in a lab and/or disassembled to determine a cause of the degraded signal integrity. The examples for signal integrity measurements described herein can decrease time spent on determining the cause of the degraded signal integrity. In addition, the examples for signal integrity measurements described herein can be a low cost and integrated solution to determining a cause of degraded signal integrity by switching between an operation mode and a diagnostic mode.

[0009] A set of examples for signal integrity measurements are described herein. In one example, a controller for signal integrity measurements includes a configuration block to receive a set of signals via a set of connection lines, a bus controller coupled to the configuration block to receive a first portion of the set of signals, a converter coupled to the configuration block to receive a second portion of the set of signals, and a controller engine coupled to the bus controller and the converter to: execute an operation based on the first portion of the set of signals, and measure a signal integrity based on the second portion of the set of signals.

[0010] The examples of signal integrity measurements described herein can selectively multiplex communication signals to an analog to digital converter in a diagnostic mode. In some examples, the examples of signal integrity measurements described herein can reduce time and resources associated with troubleshooting signal integrity issues between computing devices. In some examples, the examples of signal integrity measurements described herein can also substantially lower costs associated with signal integrity issues between computing devices. [0011] The figures herein follow a numbering convention in which the first digit corresponds to the drawing figure number and the remaining digits identify an element or component in the drawing. Elements shown in the various figures herein may be capable of being added, exchanged, and/or eliminated so as to provide a set of additional examples of the present disclosure, in addition, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the examples of the present disclosure, and should not be taken in a limiting sense.

[0012] Figures 1 and 2 respectively illustrate an example system 100 and an example computing device 214 consistent with the present disclosure. Figure 1 illustrates a diagram of an example system 100 for signal integrity measurements consistent with the present disclosure. The system 100 can include a database 104, a signal integrity system 102, or a set of engines (e.g., controller engine 106). The signal integrity system 102 can be in communication with the database 104 via a

communication link, and can include the set of engines (e.g., controller engine 106). The signal integrity system 102 can include additional or fewer engines than are illustrated to perform the various functions as will be described in further detail in connection with Figures 3-5.

[0013] The set of engines (e.g., controller engine 106) can include a combination of hardware and programming, but at least hardware, that can perform functions described herein (e.g., execute an operation based on the first portion of the set of signals, measure a signal integrity based on the second portion of the set of signals, measure the signal integrity based on current detection of the second portion of the set of signals, measure the signal integrity based on an impulse response of the second portion of the set of signals, measure a signal to noise ratio of the communication signal, etc.) stored in a memory resource (e.g., computer readable medium, machine readable medium, etc.) as well as hard-wired program (e.g., logic).

[0014] The controller engine 106 can include hardware or a combination of hardware and programming, but at least hardware, to measure a signal integrity based on a set of signals. As used herein, the signal integrity can be the quality of a signal when it is received by a controller. The quality of the signal can be measured using a signal to noise ratio or other metric to provide a value that represents a quality of the signal when the signal is received, in some examples, a relatively lower signal integrity can be more difficult to utilize by the controller. For example, a relatively lower signal integrity can cause lost communication or incorrect miscommunication between controllers.

[0015] In some examples, the controller engine 106 can measure the signal integrity utilizing a portion of the set of communication signals when the controller engine 106 is in a diagnostic mode. For example, the controller engine 106 can utilize a portion of the set of signals to measure the signal integrity with current detection or impulse response during a diagnostic mode. In some examples, the controller engine 106 can utilize a set of other calculations to determine the signal integrity of the portion of the set of communication signals.

[0016] In some examples, the controller engine 106 can receive a set of portions of a set of received communication signals. In some examples, the controller engine 106 can execute an operation based on a portion of the set of signals when the controller engine 106 is in an operation mode. For example, the controller engine 106 can be in an operation mode and execute instructions that are received via the set of received signals.

[0017] Figure 2 illustrates a diagram of an example computing device 214 consistent with the present disclosure. The computing device 214 can utilize software/ hardware (e.g., machine-readable instructions), or logic to perform functions described herein.

[0018] The computing device 214 can be any combination of hardware and program instructions configured to share information. The hardware, for example, can include a processing resource 216 or a memory resource 220 (e.g., computer-readable medium (CRM), machine readable medium (MRM), database, etc.). A processing resource 216, as used herein, can include any set of processors capable of executing instructions stored by a memory resource 220. Processing resource 216 may be implemented in a single device or distributed across multiple devices. The program instructions (e.g., computer readable instructions (CRi)) can include instructions stored on the memory resource 220 and executable by the processing resource 216 to implement a function (e.g., execute an operation based on the first portion of the set of signals, measure a signal integrity based on the second portion of the set of signals, measure the signal integrity based on current detection of the second portion of the set of signals, measure the signal integrity based on an impulse response of the second portion of the set of signals, measure a signal to noise ratio of the communication signal, etc.).

[0019] The memory resource 220 can be in communication with a processing resource 216. A memory resource 220, as used herein, can include any set of memory components capable of storing instructions that can be executed by processing resource 216. Such memory resource 220 can be a non-transitory CRM or MRM.

Memory resource 220 may be integrated in a single device or distributed across multiple devices. Further, memory resource 220 may be fully or partially integrated in the same device as processing resource 216 or it may be separate but accessible to that device and processing resource 216. Thus, it is noted that the computing device 214 may be implemented on a participant device, on a server device, on a collection of server devices, or a combination of the participant device and the server device.

[0020] The memory resource 220 can be in communication with the processing resource 216 via a communication link (e.g., a path) 218. The communication link 218 can be local or remote to a machine (e.g., a computing device) associated with the processing resource 216. Examples of a communication link 218 can include an electronic bus internal to a machine (e.g., a computing device) where the memory resource 220 is one of volatile, non-volatile, fixed, or removable storage medium in communication with the processing resource 216 via the electronic bus.

[0021] A set of modules (e.g., controller module 222) can include CRI that when executed by the processing resource 216 can perform functions. The set of modules (e.g., controller module 222) can be sub-modules of other modules. For example, the controller module 222 and another module can be sub-modules or contained within the same computing device. In another example, the set of modules (e.g., controller module 222) can comprise individual modules at separate and distinct locations (e.g., CRM, etc.).

[0022] As used herein, a set of modules (e.g., controller module 222) can include instructions that when executed by the processing resource 216 can function as a corresponding engine as described herein. For example, the controller module 222 can include instructions that when executed by the processing resource 216 can function as the controller engine 106. In another example, the processing resource 216 can implement and perform the functions of the controller engine 106 as referenced in Figure 1.

[0023] Figure 3 illustrates a diagram of an example system 330 for signal integrity measurements consistent with the present disclosure. In some examples, the system 330 can represent a computing system where a set of computing devices 332, 342 are communicating with a communication architecture (e.g., bus architecture, i2c

architecture, SPI, Ethernet, serial lines, etc.). In some examples, the set of computing devices 332, 342 can utilize a set of communication lines (e.g., bus lines, etc.) that are coupled by a set of pin connectors 340-1 , 340-2. In some examples, a signal integrity of signals transferred over the set of communication lines can be affected by a set of noise sources (e.g., bent pins of the pin connectors 340-1 , 340-2, RFI Noise from a power supply 336, poor connection of the pin connectors 340-1 , 340-2, etc.).

[0024] In some examples, the system 330 can include a computing device 332 with a controller 334. In some examples, the controller 334 can be connected to a set of joints 338-1 via a set of communication lines, in some examples, the set of joints 338-1 can be cold solder joints that can couple the set of communication lines from the controller 334 to an enclosure of the computing device 332. in some examples, the set of joints 338-1 can be coupled to a pin connector 340-1 by a set of communication lines. In some examples, the pin connector 340-1 can be coupled to a corresponding pin connector 340-2. For example, the pin connector 340-1 can be a male bus connector and pin connector 340-2 can be a female bus connector.

[0025] In some examples, the set of pins of the pin connectors 340-1 , 340-2 can each provide a plurality of functions. For example, a pin of the pin connectors 340-1 , 340-2 can provide an operation executed by a processing device and the pin of the pin connectors 340-1 , 340-2 can also measure a signal integrity, in some examples, the same pin of the pin connectors 340-1 , 340-2 can provide a functional operation and a diagnostic feature to measure the signal integrity of communications via the pin. [0026] In some examples, the computing device 342 can include a controller 344 that is coupled to a set of joints 338-2 by a set of communication lines. In some examples, the set of joints 338-2 can be a set of cold solder joints that can couple the set of communication lines from the controller 344 to an enclosure of the computing device 332. In some examples, the set of joints 338-2 can be coupled to the pin connector 340-2. in some examples, the computing device 332 and the computing device 342 can be within the same enclosure and/or the same computing device.

[0027] In some examples, a set of communication signals can be transferred between the set of computing devices 332, 342 via the communication lines coupled by the set of pin connectors 340-2. In some examples, a signal integrity (e.g., signal quality, etc.) of the communication signals being transferred between the set of computing devices 332, 342 can be affected by a set of noise sources. For example, the signal to noise ratio of the communication signals can be affected by noise produced by a power supply 336 (e.g., RFI noise, etc.). In another example, the signal to noise ratio can be affected by noise produced by a set of bent pins within the set of pin connectors 340-1 , 340-2. In some examples, the noise sources can lower the signal integrity of the communication between the set of computing devices 332, 342. As described herein, a relatively lower signal integrity can cause communication errors.

[0028] In some examples, the set of computing devices 332, 342 can switch between an operation mode to execute instructions via the communication signals and a diagnostic mode to measure a signal to noise ratio of the communication signals. In some examples, the communication signals can be muxed with a multiplexor to split the communication signals based on an operation mode (e.g., operation mode, diagnostic mode, etc.).

[0029] Figure 4 illustrates a diagram of an example system 450 for signal integrity measurements consistent with the present disclosure. The system 450 can include a controller 444 that is coupled to a pin connector 440 by a set of communication lines. As described herein, the controller 444 can be a part of a computing device (e.g., computing device 332, computing device 342, etc.) and/or enclosed within a computing device that can be in communication with a set of other computing devices that are coupled to the pin connector 440. As described herein, the pin connector 440 can be a bus connector of a bus architecture (e.g., Ethernet, I2C, SPI, UART, Simple GPIO, etc.).

[0030] In some examples, the set of communication lines coupled to the connector 440 can be coupled to a pin configuration block 452. The pin configuration block 452 can be utilized to split or mux a received communication signal via the set of communication lines. In some examples, the pin configuration block 452 can be utilized to send communication signals to a bus controller 458 via path 454 when the system 450 is in an operation mode. In some examples, the pin configuration block 452 can be utilized to send communication signals to a converter 460 via path 456 when the system 450 is in a diagnostic mode.

[0031] The pin configuration block 452 can be utilized split (e.g., mux, etc.) communication signals for either operation execution and/or communication signal integrity diagnostics. For example, the pin configuration block 452 can include a multiplexor to transfer communication signals between at least one of the bus controller 458 and the converter 460. In some examples, the pin configuration block 452 can utilize a switch to switch the transfer of communication signals between path 454 and path 456. in some examples, the pin configuration block 452 can utilize a particular pin placement that can be muxed by a multiplexor within the pin configuration block 452.

[0032] In some examples, the configuration block 452 can split a communication signal into two identical portions to execute an operation and measure a signal integrity of the communication signal. In these examples, the communication signals can be relatively slow signals. For example, communication signals can be relatively slow signals with a relatively long rise time compared to communication signals that are relatively fast signals with a relatively short rise time. In these examples, the

configuration block 452 can split the communication signal into two identical portions when the communication signal is a relatively slow signal and there is not a detrimental stub. As used herein, a detrimental stub can be approximately one sixth of a length a signal wave travels during the rise time of the communication signal. Thus, so long as there is not a detrimental stub, the configuration block 452 can split the communication into two identical portions to execute an operation and measure the signal integrity. [0033] In some examples the pin configuration block 452 can send

communication signals via path 454 to the bus controller 458 during an operation mode. In some examples, the bus controller 458 can include hardware and/or logic to provide instructions for a processing device 462 (e.g., processor, computer core, etc.). In some examples, the bus controller 458 can include a set of bus lines that can be activated and/or deactivated. In some examples, the set of bus lines can include, but are not limited to: a read line, a write line, a byte enable line, among other bus lines. In some examples, the set of bus lines can be utilized to provide instructions to the processing device 462 based on received communication signals from path 454 of the pin configuration block 452. For example, the bus controller 458 can send instructions to the processing device 462 based on the communication signals to execute a bus operation 464.

[0034] In some examples, the pin configuration block 452 can send

communications via path 456 to the converter 460. In some examples, the converter 460 can be an analog to digital (A/D) converter that can convert a received analog signal to a digital signal, in some examples, the received communication signals from path 456 can be converted to a digital signal and provided to the processing device 462 to measure signal integrity 466 of the received communication signals.

[0035] In some examples, the processing device 462 can utilize the digital signal received from the converter 460 to utilize a connectivity technique such as an impulse response technique (e.g., impulse response function, etc.) to measure the signal integrity 466. In some examples, the impulse response technique can represent the received digital signal integrity 466 as a reaction of the system 450 to the

communication signals over time.

[0036] in some examples, the processing device 462 can utilize the digital signal received from the converter 460 to utilize a connectivity technique, such as a current detection technique, to measure the signal integrity 466. in some examples, the current detection technique can be utilized to compare a current value of the digital signal compared to a threshold value to determine when the signal integrity is above or below the threshold value, in some examples, the threshold value can be utilized to determine whether the signal to noise ratio of the communication signals are above a threshold value. In some examples, the system 450 can determine that current values above the threshold value are acceptable values and that current values below the threshold value are not acceptable values. That is, current values above the threshold value can represent a relatively high signal to noise ratio and current values below the threshold value can represent a relatively low signal to noise ratio.

[0037] The system 450 can be utilized to perform a set of operations based in part on received communication signals and also determine a signal integrity of the received communication signals. The system 450 can be relatively less expensive compared to previous systems and methods of determining signal integrity. In some examples, the same processing device 462 can be utilized to perform bus operations 464 and measure signal integrity 466.

[0038] Figure 5 illustrates a flow chart of an example method 570 for signal integrity measurements consistent with the present disclosure. The method 570 can be executed by a system and/or computing device as described herein. In some examples, the method 570 can be executed by a computing device (e.g., computer, controller, microcontroller, etc.) that is receiving communication signals from a different computing device. In some examples, the computing device that is receiving the communication signals can perform an operation based on the received communication and/or measure signal integrity of the received communication signals.

[0039] At 572, the method 570 can include receiving, at a configuration block, a communication signal from a pin connector coupled to a computing device. As described herein the configuration block can be a pin configuration block that is coupled to a connector (e.g., pin connector, etc.) via a set of communication lines, in some examples, the communication signal can be received from a different computing device via the pin connector. In some examples, the pin connector can be utilized to split or mux the communication signal as described herein.

[0040] At 574, the method 570 can include splitting, at the configuration block, the communication signal into a first portion and a second portion. In some examples, splitting the communication signal into a first portion and a second portion can include sending a first communication signal to a first device and sending a second

communication to a second device. In some examples, the communication signal can be received by the configuration block and the signal can be muxed to send a first portion of the signal to a first device and a second portion of the signal to a second device. As described herein, so long as there is not a detrimental stub, a configuration block can split the communication into two identical portions to execute an operation and measure the signal integrity. In some examples, splitting the communication signal includes selectively multiplexing the communication signal.

[0041] At 576, the method 570 can include providing the first portion to a bus controller to execute an operation, in some examples, the first portion of the

communication signal can be a first portion of a muxed communication signal as described herein, in some examples, the first portion can be provided (e.g., sent) to a bus controller as described herein to provide instructions to a processing device for performing an operation based on the communication signal. In some examples, the first portion of the communication signal can be sent to the bus controller when the computing device is in an operation mode as described herein.

[0042] At 578, the method 570 can include providing the second portion to a converter to measure a signal integrity. In some examples, the second portion of the communication signal can be a second portion of a muxed communication signal as described herein, in some examples, the second portion can be sent to a converter such as an analog to digital converter. In some examples, the converter can convert the received second portion for determining a signal integrity for the received

communication signal. In some examples, the second portion of the communication can be sent to the converter when the computing device is in a diagnostic mode as described herein. In some examples, measuring the signal integrity includes measuring a circuit connectivity between a first controller and a second controller. In some examples, measuring the signal integrity includes measuring a signal to noise ratio of the communication signal.

[0043] As used herein, logic" is an alternative or additional processing resource to perform a particular action or function, etc., described herein, which includes hardware (e.g., various forms of transistor logic, application specific integrated circuits (ASICs), etc.), as opposed to computer executable instructions (e.g., software, firmware, etc.) stored in memory and executable by a processor. Further, as used herein, "a" or "a set of something can refer to one or more such things. For example, "a set of widgets" can refer to one or more widgets.

[0044] The above specification, examples and data provide a description of the method and applications, and use of the system and method of the present disclosure. Since many examples can be made without departing from the spirit and scope of the system and method of the present disclosure, this specification merely sets forth some of the many possible example configurations and implementations.

Claims

Claims What is claimed:

1. A controller, comprising:

a configuration block to receive a set of signals via a set of connection lines;

a bus controller coupled to the configuration block to receive a first portion of the set of signals;

a converter coupled to the configuration block to receive a second portion of the set of signals; and

a controller engine coupled to the bus controller and the converter to: execute an operation based on the first portion of the set of signals; and

measure a signal integrity based on the second portion of the set of signals.

2. The controller of claim 1 , comprising a pin connector coupled to the configuration block.

3. The controller of claim 2, wherein the pin connector couples the controller to a computing device.

4. The controller of claim 2, wherein a set of pins of the pin connector each provide a plurality of functions.

5. The controller of claim 1 , wherein the controller engine measures the signal integrity based on current detection of the second portion of the set of signals.

6. The controller of claim 1 , wherein the controller engine measures the signal integrity based on an impulse response of the second portion of the set of signals.

7. The controller of claim 1 , wherein the configuration block includes a multiplexor to transfer signals between at least one of the bus controller and the converter.

8. A system, comprising:

a first controller comprising a set of connection lines coupled to a set of pins of a first pin connector;

a second controller comprising a set of connection lines coupled to a set of pins of a second pin connector, wherein the first pin connector is coupled to the second pin connector to provide an exchange of communication signals between the first controller and the second controller; and

a configuration block to split the communication signals into a first portion and a second portion of communication signals, wherein the first portion of

communication signals is utilized to execute an operation and the second portion of communication signals is utilized to measure a signal integrity.

9. The system of claim 8, wherein the configuration block sends the first portion of communication signals to a bus controller.

10. The system of claim 8, wherein the configuration block sends the second portion of communication signals to an analog to digital (A D) converter.

11. The system of claim 8, wherein the configuration block splits the communication signals into two identical portions of communication signals.

12. A method, comprising:

receiving, at a configuration block, a communication signal from a pin connector coupled to a computing device;

splitting, at the configuration block, the communication signal into a first portion and a second portion;

providing the first portion to a bus controller to execute an operation; and providing the second portion to a converter to measure a signal integrity.

13. The method of claim 12, wherein splitting the communication signal includes selectively multiplexing the communication signal.

14. The method of claim 12, wherein measuring the signal integrity includes measuring a circuit connectivity between a first controller and a second controller.

15. The method of claim 12, wherein measuring the signal integrity includes measuring a signal to noise ratio of the communication signal.