WO2017123085A1

WO2017123085A1 - Lithographic defined 3d lateral wiring

Info

Publication number: WO2017123085A1
Application number: PCT/NL2017/050009
Authority: WO
Inventors: Zahra Kolahdouz ESFAHANI; Hendrikus Wilhelmus Van Zeijl; Guo Qi ZHANG
Original assignee: Technische Universiteit Delft
Current assignee: Technische Universiteit Delft
Priority date: 2016-01-14
Filing date: 2017-01-09
Publication date: 2017-07-20
Anticipated expiration: 2018-07-14
Also published as: NL2016093B1

Abstract

The present invention is in the field of a semiconductor product having lithographic defined lateral wiring, a process fo making such a product, use of said process, and a chip or a chip in package having such wiring. In semiconductor processes functional electrical elements which need to be connected to an outside world by electrical conducting wires. The process used for lithographic defined lateral metal wiring in a package comprises the steps of providing a chip and a substrate, optionally placing the chip on the substrate, providing a passivation layer covering the chip, and providing openings in the passivation layer to metal pads.

Description

Lithographic defined 3D lateral wiring

FIELD OF THE INVENTION

The present invention is in the field of a semiconductor product having lithographic defined 3D lateral wiring, a process for making such a product, use of said process, and a chip or a chip in package having such wiring.

BACKGROUND OF THE INVENTION

In semiconductor processes functional electrical elements, such as transistors, resistors, and so on are defined typically in activated silicon regions, typically using lithographic techniques, and chemical and physical processes. The functional elements are thereafter electrically connected according to a predefined scheme, typically using various insulating

(dielectric) layers, through which so-called contacts or vias are provided. The contacts are filled with an electrical conductor, typically a metal such as Cu, Al, W, etc. After 3-15 layers the connection scheme is typically completed. Thereafter the

semiconductor product, such as an integrated circuit (IC) , is typically protected from environmental influences by a so-called passivation layer. In order to provide contacts to the outside world, for input and output (I/O), parts of the passivation layer are opened to provide so-called bond pads. At the product side the bond pads are in electrical connection to the predefined scheme. To the bond pads thin electrical conductive wires are connected, through gluing, welding, or the like. This is

typically referred to as the package side, as in addition to the bond wires a physical package is provided to the semiconductor product. To a semiconductor product 2-500 wires may be connected, typically depending on the semiconductor technology used. If various semiconductor products are stacked, or likewise form a package of products, or are integrated in a package, even more bond wires may be required. The wires are typically connected to a construct such as a printed circuit board (PCB, having a further connection scheme for functionally connecting various elements, such as one or more of the semiconductor products or packages, drivers, memories, power supplies, transformers, etc. The wires typically have a thickness of 20-250 μιη, whereas the bond pads are typically somewhat larger. The wire bonding is typically performed by an advanced machine which is capable of bonding wires precisely at relatively high speeds (wires/minute) . Such machines are however inherently limited in precision and speed. Especially with advanced semiconductor processes wire bonding has become a problem.

As mentioned above, wire bonding is the leading

interconnection technique in spite of the rapid developments in chip and wafer level packaging technology because of its

considered high reliability. It is noted that the bond forming process is performed at a relatively high temperature. The increased process temperature of wire bonding may lead to various problems such as oxidation of the bonding pad. There are also other reliability issues like inter metallic compound (IMC} growth, metal pad squeeze and mechanical issues such as stress into the Si active regions. In addition there are various challenges for wire bonding in multi-domain packaging, such as temperature limitations, deep access capability and limited aspect ratio and bonding on sensitive devices and over cavity and cantilever leads.

Different challenges and reliability issues with

conventional interconnect technologies especially with wire bonding, introduce an increasing need for developing new I/O interconnect techniques. Two of the major drives are:

1) the fragile nature of low-k dielectrics and their relatively poor adhesion to the surrounding materials considered critical to minimize the mechanical stresses on the chip.

2} Wire bonding difficulties to obtain fine interconnections with a high density. Figure 1 presents some examples of wire bonding challenges.

Another problem with prior art methods is that feature sizes on ICs are shrinking rapidly, which shrinkage is very difficult to follow on the package side. Figure 2 summarizes packaging trends following Moore's law. With conventional wire bonding there is a major gap between the interconnect size developed on the IC and wiring traces printed on the boards.

For instance, for RF, millimeter wave (MMW) and micro-wave IC applications different problems with wire bonding are

encountered; Wire bond inductance is a big problem for high frequency input and output signals; Wire bonding has a high impedance at GHz ranges and creates matching problems; Due to the impedance of wire bonding, several decoupling capacitors are required close to the chip for supply voltages. Normally, there is not enough space near the chip to place components close by; High number of these extra required decoupling components does not allow to place them close to the chip; In some high frequency application, several different ICs or RF components are required to be placed closely. However, the high number of decoupling components makes this due to limited space at least complex if not impossible; High values of printed circuit board (PCB) trace width and clearance requirements (-100 μιη) do not allow the traces to be located very close to the IC pads. As a consequence it increases a wire bonding length. In other words, wire bonding spacing is very small on IC, but as they come to PCB, they become relatively large.

One of the novel technique recently used for some limited technological areas is the so-called lithographic defined wire bonding, which includes the deposition of metal film and then patterning a wire-like trace through lithography. The proposed interconnect method may be deployed where wire bonding, flip-chip (face-down) and through silicon via (TSV) interconnections are difficult to carry out. This technique offers benefits such as better interconnection reliability due to a low temperature process, less stress introduced into the Si active region and mechanical issues, higher interconnect density (applicable for RF application) . This type of interconnect with TSV performance and on chip passive component is also applicable for LED SiP and 3D integration applications. In most cases this technique was carried out on a tapered Si sidewall. Incidentally CA1227287 (A) recites packaging micro miniature devices and, more particularly, to a packaging assembly and a method in which one or more devices are affixed to and

interconnected on a wafer. In an example silicon-integrated- circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch- resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer using conformal lithographic techniques. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments,

connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics. The

attachments are on a wafer in between various chips.

Some recent publications are mentioned below.

M. Murugesan et al. in "High step coverage Cu lateral interconnections over 100 μη\ thick chips on a polymer substrate; an alternative method to wire bonding"; J. Micromechanics Micro engineering, vol. 22, no. 8, p. 085033, Aug. 2012, recites investigations of a high-step-coverage copper (Cu) -lateral interconnects formed over 100 μκι thick Si chips by an

electroplating method for their microstructure and electrical characteristics. They developed a spin-coating with special parameters for resist which needs to be different for various chip height and does not provide a reliable and uniform coverage. Their litho process is performed with a normal contact exposure which supports limited wire size and pitch and in addition is not precise. It is therefore not applicable for a thicker chip. The above technique covers wiring over a maximum height difference of 100 μπι and the interconnect density (bonds per unit surface area) was not much improved. One of the main challenges is considered to be a lithography step wherein contact exposure is used. Although contact aligners are more cost effective compared with wafer steppers, nowadays, wafer steppers are being used for advanced WLP .

K.-W. Lee et al. in "Novel interconnection technology for heterogeneous integration of MEMS; LSI multi-chip module" in Microsyst. Technol., vol. 16, no. 3, pp. 441-447, Oct. 2009, suggest a method for heterogeneous integration of a MEMS and LSI multi- chip module, in which the MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked on each other. The cavity chip composed of deep Cu TSV- beam lead interconnections was developed for interconnecting MEMS chips with high step height of more than few hundreds micrometer without the degradation of sensing elements. They developed a separate cavity chip for Cu TSV beam lead interconnection. A disadvantage is that this method will add much complexity of micro-machining and TSV formation. They later use contact lithography to define the wires which limits the wire size and pitches .

B. Morgan et al. in "Substrate interconnect technologies for 3-D MEMS packaging"; Microelectron . Eng., vol. 81, no. 1, pp. 106-116, Jul. 2005, developed 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. They presented a process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE) , with an emphasis on achieving positively tapered, smooth side- walls to ease deposition of a seed layer for subsequent Cu electroplating. The gray-scale technology used therein is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 pm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. What is developed is therefore a Si tapered structure with micro-machining in order to subsequently place their flip chip components. They also used a through hole technology which adds more complexity and challenges to the process. It is noted that the gray scale lithography used requires smoothness on the surfaces and hence is often not applicable.

Several documents recite a use of single resist layers and improvements in lithographic imaging therewith.

JP 3 268615 B2 relates to electronic components, a packaging component forming the external connection terminal by a lead to be connected to the electrodes of the electronic component, and a method for producing the same. A distance between the adjacent electrodes to wire bonding is as a consequence necessary to 100 μιη about at a minimum. A single exposure and contact exposure is used (see fig. 15), which is considered not possible with one step projection lithography. The objective of this patent is solving cracks in solder joints of wire bonding.

US 4,657,629 Al recites a bi-level photoresist process that employs a relatively thick photoresist layer deposited over the surface to be patterned. The entirety of this photoresist layer is exposed to actinic ultraviolet radiation and thereafter subjected to a heat treatment so as to effectively desensitize the layer to the action of a developing agent. Because of its thickness the first layer effectively acts as an optical buffer between the second relatively thin layer and any underlying metallic reactive interface, so that optical notching of the second layer of photoresist cannot occur; hence the first layer is just used as anti-reflection coating. It is a thick layer which is firstly exposed with UV {without any lithography) before coating the next layer; effectively therefore only one layer is used for lithography. The process is proposed to overcome limitations of normal lithography for thin line of different layers in an IC production line, which is typically not thicker than 10 microns and hence relates to planar (not high topography) structures. It can also not be used to planarize structures with large height differences. In addition such a thick resist could not be patterned using prior art techniques, at least not with sufficient resolution.

US 6,534,242 B2 recites a method of making an exposure pattern through a dual-beam interference exposure process.

Therein laser light from a laser which comprises parallel light having coherency is divided by a half mirror into two light beams, therewith improving resolution by increasing a depth of focus with multi-exposure on high topography substrates. Such a resolution enhancement technique is considered not applicable to a high topography having different defocusing issues. It is noted that the multi exposure is done on the same focus level,

typically at a top plane of the resist.

US2009/091736 Al recites a calculation method of

calculating, by a computer, a light intensity distribution formed on an image plane of a projection optical system. Integration of such methods to lithographic techniques mentioned above is considered cumbersome.

US 2008/054426 Al recites a reduction in the size of a final semiconductor device and its thinning, and attaining facilitation of a manufacturing process, the semiconductor device includes a circuit chip having a flat mounted surface, a circuit chip smaller in size than the former circuit chip, and a sheet-like support. Such relates to mounting various compounds which is considered totally different from the present invention. In addition it is questionable if these techniques can be combined with other techniques, without running into further problems.

JP 2006/013205 A recites a method of manufacturing a semiconductor device characterized in that the formation of formation and the wiring contact hole is formed by

photolithography and etching techniques, and in the

photolithography for forming a direct drawing apparatus does not use a photomask.

In addition the above developments have a limited

reliability and still a relatively low density and precision of the wire patterning. The present invention therefore relates to an improved process for wire bonding, use of said process, and products obtained thereby, which solve one or more of the above problems and drawbacks of the prior art, providing reliable results, without jeopardizing functionality and advantages.

SUMMARY OF THE INVENTION

The present invention relates to an improved process for wiring according to claim 1, a use of said process according to claims 14-18, and a product obtainable by said process according to claims 19 and 20. The present invention provides various benefits and potentials compared to conventional methods, such as an improved packaging reliability wherein a low temperature and less material is used, interfaces are involved, process stress is reduced due to optimized interconnect lines such as at critical transitions, an improved line density is obtained which relates to a litho defined pitch rather than tooling defined pitch, an enhanced precision, reduction of a bond pad area, provision of heterogeneous integration as it can be used for conventional chips without special requirements (such as restrict design requirements for flip-chip and TSV) which is especially useful when spatial limitation or mechanical consideration are existed, a low-K compatibility used in modern IC technology nodes, a compatibility with ultra-thick metal option interconnect on advanced IC, being an alternative for TSV on smaller ICs, providing RF optimized structures (ground-signal-ground) , providing a reduction of parasitic inductance as the otherwise unescapable wire bonding loop height is replaced by the thickness of wire traces in the present process, and shorter interconnect lengths giving interconnection with minimized resistive- capacitive delay for high frequency applications. Such is especially beneficial for a system in package,

The present process relates lithographic defined lateral metal wiring in a package, typically using a single mask, wherein the metal wiring may relate to a 2D or 3D scheme. It is found that using only one single mask with multi-exposure and

sufficient focus steps is enough for a successful patterning. It was observed that as the difference between min and max of a resist thickness increases, the overall intensity contrast should rise accordingly. To achieve an even higher resolution or to have a generic pattern split masks for each defined focal range may be considered, such as one mask per lithographic step. Wiring relates to providing electrical connections with wire-like structures, i.e. conductive material having a relatively small width and thickness. Typically multiple wires are provided. The metal layer as a 3D metal wiring on the chip and substrate is provided using two or more lithography steps each step at a different height, hence multi exposure is used. Therein use is made of optical image forming using a resist and patterning said resist by exposure using light and thereafter removing non- exposed resist, as is known per se in the field of semiconductor technology. It is however atypical to use a lithographic process for defining wiring, let alone lateral defined wiring; as such the present invention differentiates already over most of the prior art, such as cited above. It is further atypical to use such a process for a package, wherein the package comprises a chip and a substrate. The chip (also referred to as semiconductor device or integrated circuit IC) is typically produced using a semiconductor process, up to a passivation thereof and optionally including a passivation. The present process provides a good step coverage and thick enough resist over high topography of e.g. several hundred microns. The chip as processed may be placed on a substrate; in an alternative the substrate of the chip, typically silicon, may be used.

In a first step of the present invention a passivation layer is applied on the chip and optionally on the substrate. The

passivation layer typically comprises an insulating material. Thereafter connecting openings in the passivation layer are provided. In view of the present process it may be possible to reduce a number of dielectric and metal layers of the chip, as such layer (s) may become redundant in view of the present, in a way additional, lithographic defined wiring. If certain layers would be considered redundant, than the present connecting openings may at east functionally resemble vias (once filled with metal) . The vias would provide connection to conducting

structures, typically metallic structures. For sake of

readability the term "metal pads" also encompasses such

underlying metal structures. The metal pads are typically present on a top most layer of the chip, which top most layer may subsequently covered by the passivation layer. In a next step a metal layer is deposited, forming an electrical connection with the metal pads. In order to provide a predetermined wiring scheme a next step involves patterning the metal layer on the chip and substrate using lithography, preferably high aspect ratio lithography.

It has been found that a multi-step imaging (MSI)

functionality, such as developed by ASML for MEMS industry, allows increasing a global focus offset range from the standard specification of ± 30 μπι up to ±200 μπι when additional measures are taken. Additionally, a local focus offset of ±5 um can be added to each die to the global focus offset to adapt to a by a process induced thickness. In an example a local focus offset relates to the height difference in high topography substrate, which in each exposure step is applied to eliminate a possible defocus issue in case of applying a typical exposure with a focus at a top plane. In addition high aspect ratio lithography may be used for lithographically defined SiP interconnects. Typically a multistep approach is used, such as two steps or more therewith providing two or more resist layers.

Lithographic Defined Wiring (LDWB) - shown in Fig. 3) generally consists of the following steps: Passivation layer deposition; Making contact opening in passivation layer,

optionally tapering layer deposition; which is both for tapering the sidewall and passivation; Metal deposition; Patterning through high aspect ratio (H.A.R) lithography. The non-uniformity of the wafers is noted in that they typically have a relatively high topographic height variation (±1-25 μπι) . As there typically is a significant height difference between a top surface of a chip and a substrate, e.g. more than 100 μπι, therewith a 3D metal wiring scheme is provided.

This kind of wiring provides benefits compared to prior art methods such as an improved reliability with less material interfaces, a reduced stress due to optimized interconnect lines at critical transitions, an increased bond wire line density, an improved precision, heterogeneous integration, improved yield, an improved process, optionally providing different wire dimensions such as in view of functionality and current density, improved design flexibility and design freedom, and a low-K compatibility. Figure 3 schematically shows the concept.

The present Litho-defined wiring provides many further advantages, such as a litho defined pitch rather than a by a tool defined pitch, a better match from CMOS level interconnect to package level interconnect (Compatible with ULK interconnect on advanced CMOS), an alternative for TSV on smaller IC's, RF optimized structures (ground-signal-ground) , improved matching power and signal requirements, and a reduction of parasitic inductance .

Thereby the present invention provides a solution to one or more of the above mentioned problems and drawbacks.

Advantages of the present description are detailed

throughout the description.

DETAILED DESCRIPTION OF THE INVENTION

Certain details of the present process are detailed below.

Various materials can be used for tapering and passivation of the semiconductor product or component, such as various polymers, underfills and thick photoresists. In prior art underfill processing, a controlled amount of liquid underfill is dispensed along the edges of the component/substrate joint.

Figure 4 presents an example of underfill dispensing.

To lithographically pattern a high aspect ratio wire structure over a step height of hundreds of microns a complete process is developed for different phases, such as a resist application having a good resist coverage over the typically present high topographic variable surfaces, especially on convex corners, an exposure of the resist solving a defocusing problem and different leveling requirements due to the topography, and a resist development which may have different resist thickness over a topography of the semiconductor product that in addition may need a different time to react in a development solution.

Spray coating can be used to apply the resist to have a good coverage over the topography instead of conventional spin coating. Figure 5 shows spray coating schematically. The spray coating experiments are performed on an EVG 101 spray coater on 4 inch wafers. A diluted positive resist solution can be used in this experiment and it is necessary in order to get a proper droplet size of resist distribution. Spin rate, spray nozzle scanning speed and profile, spray pressure and resist dispense volume are relevant parameters and are adjusted to optimize the deposition of thick resist layer on topographic wafers. The coating is done in multiple steps of multi-layer spraying over the whole wafer to get sure of having conformal coverage all over the topographies. To increase the resist coherency, some baking steps can be added during thick coating processes. The spray coating process could be optimized for different aspect ratios of cavities and topographies. For wider and shallower cavities, the resist thickness has better uniformity and the layer is thicker. Considering the reflection of light in exposure step on cavity sidewall for target mask pattern, both negative and positive resists might be used. For negative and positive tone resists, diluted AZ® nLOF 2070 and AZ® 9260 could be used, respectively.

The resist may be developed using a manual process. For a negative resist, after exposure a crosslink baking was done at 115°C for 3 min. Then, it was developed in a pure MF322 solution for 2 min. For a positive resist, it was developed in diluted AZ400K (diluted with 2 parts of DI water) for 1-2 min.

In comparison to contact aligner, multi-step imaging (MSI) is more flexible for imaging over high topographies. While the depth of focus for nominal projection system is +/-2um, MSI extends it to +/-200 μηι. The exposure dose with MSI can be controlled at different focus levels. It has the potential to adapt the dose in the aerial image at different focus levels to better match local resist thickness and compensate thickness variation of spray coated resist. The aerial image is typically used for optimization of a number of exposures in a z-direction (height) . On the contrary the constant dose of exposure in contact aligner causes problem in developing patterns for

different resist thickness. For example considering a thick resist present at the bottom corner of dies where it attaches to the substrate, the exposure dose and developing time are

preferably increased which may as a consequence cause over exposure and loosing features for thinner part of resist layer.

To make features just at the top of the dies, the average height of the dies may be considered in the global focus offset. The focal plane is thus at the same level as the top of the dies. To keep the same resolution all over the wafer, several issues are preferably taken into account: 1) non-uniformity and

roughness of different involved surfaces due to chemical nature of process, 2) spray-coated resist is not uniform all over the wafer and also in different place of the topographies. These types of issues can be addressed in the local focus offset.

Aerial image calculation can help to do exploration and get a better vision of defocus effect over the topography. It is also useful in optimization of multi-step imaging. Such a procedure typically involves steps as aerial image calculation, identifying a defocus effect, adapting a resist thickness profile if

applicable, adapting a resist contrast and sensitivity

respectively if applicable, and making a final model. Calculation of aerial image for projection exposure can be done based on Fraunhofer diffraction equations. Light intensity over the structures in different depth from top to the bottom may be calculated and a 3D color map image can be plotted. These calculation can be done for masks including lines with different line parameters and can be used as a reference for designing the masks and number of MSI focal plane.

Based on calculation and wiring requirements the mask can be designed. For a simple method, taking into account the pitches and feature sizes, the topography height is divided in multiple sections. Each section may have a different focal plane at the middle. So the mask could be split for each section and later exposed with a focus at the middle of the section.

Using multi step imaging on an ASM PAS 5500/80 projection aligner (NA = 0.48), inventors realized a resolution down to 2 μπι for a given topography of 200 μπι height. Figure 6 shows some example of patterning with MSI for 200 μιτι deep cavities. The wires typically have a width of 0.1-250 μια, preferably 1-100 um, more preferably 5-50 μπι, even more preferably 10-50 um, such as 30-40 μπι, and a thickness of 0.3 nm-20 μιη, preferably 1 nm-10 pi, more preferably 10 nm-5 um, even more preferably 100 nm-5 um, such as 0.25-4 um or as 0.5-2 as 0.25-4 μπι. For metal wires typically a PVD process can be used, providing thicknesses in the order of 0.1-10 μπι, whereas if for instance graphene would be used mono-atomic layers, or atomic multi layers could be used, having a thickness in the order of nm's. An important advantage is that the present process provides a large degree of freedom in developing wiring, wherein in principle each individual wire can be optimized e.g. in terms of electrical impedance, current density, conductance, material, etc. As such also a layout of an electrical connection scheme can be optimized.

To get an even better pattern quality and resolution at tapered sidewalls one can add more imaging steps, each step with a focal plane at a different height level of chip sidewalls.

For different wiring structures an optimized imaging steps can be calculated. Comparing different applications there is a trade-off between imaging step numbers (i.e. proportional to the lithography time) and pattern sharpness. There is also some space for mask engineering for less imaging steps.

In an example of the present process the step of providing a passivation layer is performed by deposition, such as LPCVD, CVD, spray coating, and dip coating.

In an example of the present process the tapering layer tapers at least one sidewall, typically a sidewall of the chip, and/or typically all sidewalls of the chip, in so far as applicable. The side all tapering can be provided in an additional step, such as underfill dispensing and polymer spray coating step.

In an example of the present process the passivation layer is formed of an inorganic dielectric, a polymer, a photoresist, a resin and combinations thereof.

In an example of the present process photo resist is applied using at least one of a rotating wafer, a spray nozzle, a spray pressure, a spray rate, a resist volume, and a moving arm

attached to a nozzle.

In an example of the present process photo resist is applied in a sequence, the sequence comprising (i) applying the

photoresist in multilayers, such as 2-12 multilayers, (ii) heating and/or baking the photoresist multilayers, and repeating steps {i} and (ii) 1-5 times, such as 1-2 times.

In an example of the present process a photoresist exposure dose is varied locally, depending on a light source (wavelength) , a resist type and thickness thereof. Typically a dose of 800-1200 mJ/cm² is applied, such as 900-1000 mJ/cm² for an i-line stepper (λ= 248 nm) .

In an example of the present process a local focus offset is provided during exposure of the photoresist, such as from 2-200 urn, depending on the height of the chip and number of steps. For instance a chip height of 200 μιη may be divided into five (extra) steps of 40 μιη each. A local focus offset would then be 40 μπι per step and may start at a non-zero offset, e.g. 0 μιιι for a top plane, followed by 20 urn, 60 μπι, 100 μιτι, 140 um, 180 μιη, and finally a bottom plane at 200 μπι. As such a full height of a high topography surface can be covered.

In an example of the present process aerial image

calculation is used to determine local lithographic patterning boundary conditions for optimizing a mask design, preferably using Fraunhofer diffraction.

In an example of the present process patterning of the metal layers is performed over a height exceeding 100 μπι, typically exceeding 200 μπι, such as up to 500 um. In other words, patterning of the metal layers can be performed over functional surface levels of a chip and substrate and connecting those levels can be over a height exceeding 100 μιη. A functional surface level can relate to a height level, e.g. the top of a chip comprising bond bands, a substrate level comprising

connections to an outside world, a structure in a chip, such as a cavity, a MEMS, etc.

In an example of the present process the chip is placed on the substrate, such as in a case wherein a chip and a substrate are separate items. The chip may be attached to the substrate such as by gluing.

In an example of the present process patterning of the metal layers is done in a multi-step approach, such as a 3-50 step approach .

In a second aspect the present invention relates to a use of the present process for heterogeneous integration of a chip on a package .

In an alternative the use is for providing an electrical interconnecting wiring between two or more functional levels for a chip on a package.

In an alternative the use is for providing an electrical interconnecting wiring between the front side and backside of a chip .

In an alternative the use is for full formation of wiring from a (supporting) substrate to one or more chips.

In an alternative the use is for a lateral 3D metal wiring for a MEMS, an optical application, an RF application, a high temperature package, a solid state lighting package, a LED package .

In addition two or more of the uses above may be combined.

In a third aspect the present invention relates to a chip or chip in package comprising lithographic defined wiring obtainable by the present process.

In a fourth aspect the present invention relates to a product obtainable by the present process. The invention is further detailed by the accompanying examples, which are exemplary and explanatory of nature and are not limiting the scope of the invention. The one or more of the above examples and embodiments may be combined, falling within the scope of the invention.

EXAMPLES

The below relates to examples, which are not limiting in nature .

The details provided below specifically relate to Figure 6d and are illustrative for the process steps of forming a 3D connecting wire structure. Firstly a 200 μπι deep cavity was formed on a Si substrate (4 inch wafer) through 33% KOH wet etching during sufficient time at 85°C. Thereafter a 300 nm

Aluminum layer was deposited at 50°C in a PVD sputtering tool (TRIKON SIGMA machine) . Typically a deposition rate at room temperature is about 3 μπι/h or about 50 nm/min. In order to have a good coverage over the whole topography, which is often not available with conventional spin coating, the spray coating was performed on an EVG 101 spray coater on the 4 inch wafer. A diluted positive AZ9260 resist solution was used in this

experiment. The coating was done in multiple steps:

An HMDS vapor treatment for 1 minute on a hotplate at 403 °K (130 °C) to enhance resist adhesion;

thereafter spraying the photoresist eight times at a spraying pressure of 10⁵ Pa (1000 mbar) ;

- thereafter baking the resist during 1 minute at 388 °K (115 °C) ;

thereafter again spraying the photoresist eight times at pressure of 10⁵ Pa (1000 mbar);

- and thereafter baking the resist during 5 minute at 388

° (115 °C) .

The exposure was done using multi step imaging on an ASM PAS 5500/80 stepper (NA = 0.48). In view of previously performed simulations the mask was split to several layers (having a different height with respect to e.g. a substrate surface) including a top plane, several sidewall segments, and a bottom plane of the cavities formed above. A local offset and a local exposure dose were used for each above layer. For top layers the exposure doses were 1000 mJ/cm² and for the bottom layers 1100 mJ/ cm² due to different thickness of the resist. The developing was done in an AZ400k: water 1:2 solution for 1 minute. The aluminum later was etched using a typical wet etching process step suited thereto, typically at a slightly increased

temperature of 300-320 °K, such as mixtures of 1-5 % HN0₃ (for Al oxidation), 65-75 % H₃P0₄ (to dissolve the A1₂0₃) , 5-10 % CH₃COOH (for wetting and buffering) and H20 dilution to define the etch rate at given temperature.

In view of reduction of reflection from sidewalls of the cavities, a diluted negative AZ® nLOF 2070 resist was coated in 2 steps of 4-layer spraying. Each step was followed by baking at 100°C hotplate for 1 and 5 min, respectively. Although there was a considerable thickness difference between top and bottom corners of cavities (few micrometers) , the good coverage over top corner resolves the problem of pattern splitting. For wire pitches less than 20 um, the lines are merged together. For pitches bigger than 20 μπι, lines with a minimum width of 10 μπ\ were successfully developed and etched with a wet etch process.

A similar process as above, including forming a 200 μιη deep cavity, may be used to obtain wiring schemes as shown in figures 6a-c. In fig. 6a four metal wires are shown having a thickness of about 10 μπι and a width of about 20 μπι. In fig. 6b the two top wires have a width of about 50 μπι, the three middle wires have a width of about 20 μιη, whereas the three bottom wires have a width of about 10 um. A thickness of all of the wires is about 3 μπι. In figure 3c metal pad type structure of 50*50 μιη² are shown, connected by wires of about 20 μχα having a thickness of about 6 μπι. A high resolution up to 2 μπι from top to bottom of 200 m cavities is provided.

In an example imaging is done in several steps at different focus levels. The exposure dose with multi step imaging (MSI) can be controlled at different focus levels. It has the potential to adapt the dose in the aerial image at different focus levels to match well with local resist thickness. Therefore, it can

compensate for thickness variations of spray coated resist. The constant dose of exposure in contact aligner causes problems in developing patterns for different resist thicknesses. For

example, considering thick resist at the bottom corner of the cavity, the exposure dose and developing time should be

increased. This may cause over-exposure and loosing features for thinner part of resist layer at the edges.

For MSI, exposure may be done using a pre-defined single leveling point. In this case, leveling takes place in 2 steps:

Global leveling: determine height reference points; and field by field leveling: red level sensor measurement at a given location. An exposure takes the closest measurement point as a reference (max. 200 points) . It gives the flexibility to define the locations for leveling that are used to determine the nominal focus plane.

Due to our design parameters for lateral features on the sidewall and interconnects, the maximum focus range which could at present be achieved with an acceptable pattern resolution from focus plane is ± 18 μπι. Such is referred to as a focus layer. In a next phase, the mask was split to different segments for each focus layer. Thus, 35 μιη as focus layer depth is taken and the center of this interval could be determined as the focus plane. Subsequently, for the 200 μη cavities, 8 multi-step images are defined, which are from top plane (focus offset is 0 μπι} to bottom plane (focus offset is 200 μηα) . The final interconnect mask was split into 8 layers, each two neighbor layer has 1 μηι overlap to ensure pattern integrity. The mask layers are shown in Figure 7(b) . The predefined focus offsets were 0, 18, 53, 88, 124, 159, 188 and 199 μιη for the 8 imaging steps from the top to the bottom of the cavities. Front to backside alignment (FTBA) is preferred. In this way, the overlay error is less than 200 nm (3σ) . Therein some embedded optics in an XY wafer stage are provided. For this option, alignment markers were exposed and etched on both side of wafers in the former steps. Using the capabilities of MSI, different exposure dose can be used for defined layers considering the local resist thickness profile. The bottom and the sixth layers were provided with a relative higher energy, while layer 1 due to thin resist coverage over the top corner is provided with less . To optimize pattern quality, different tests were done. In a SEM image all the exposed focus layers and all the features were found to be successfully realized. In the last part, the whole layers where exposed.

Thanks to the 35 um focus depth for individual layers, lateral structures were also successfully developed. The wave like features on resist sidewall represent different imaging steps. Final results show a very well patterned Al layer after a wet etching .

In conclusion lithographic defined lateral wire bonding was used a new approach to overcome limitations and challenges of conventional wire bonding for special applications. It includes metal film deposition and patterning the wire trace preferably through high aspect ratio lithography, which is a key for such a method. Two sets of experiments were done to make various line structures over KOH cavities of different depths up to 200 μιη. Multilayer spray-coating was used to have a good resist coverage over deep cavities. Exposure was done with EVG 420 mask aligner and multistep imaging on an ASML PAS5500/80 projection aligner. Aluminum interconnect lines with different parameters were achieved after etching process. For sidewall imaging of wires using MSI on stepper, a simulation method was proposed to predict 3D aerial image projected on the resist. As experimental results showed, only the aerial image was typically not enough and other parameters such as resist thickness profile and its sensitivity are considered. Including these, the final simulation methodology was able to predict the final resist profile on 3D structures. The MSI with single mask was also experimentally investigated, and was found very challenging for high resolution features and a pattern depending method. Lastly, MSI with split masking was developed. It showed promising results for high resolution and generic patterns. This method can be applied for heterogeneous integration area where a reliable and flexible interconnection method is critical. It also demonstrates integration beyond wire bonding capabilities such as monolithically implementation of 3D devices .

The invention is further detailed by the accompanying figures, which are exemplary and explanatory of nature and are not limiting the scope of the invention. To the person skilled in the art it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, defined by the present claims.

SUMMARY OF THE FIGURES

Figure la-c: Examples of wire bonding interconnect

challenges (a) Complexity (b) Crosstalk [Yang Kun, ICEPT-HDP 2011] (c) Reliability [C. J. Vath, ICEPT-HDP 2011]

Figure 2 shows the development of a minimum frame size over time.

Figure 3a-c shows a schematic of wiring on a side of a chip.

Figure 4 shows gluing a chip on a substrate and dispensing underfill as tapering material (prior art) .

Figure 5 shows schematics of applying a photoresist.

Figure 6a-d shows SEM picture of present litho defined wiring .

Figures 7a-b show present layouts.

Figures 8a-e show an example of an aerial image simulation. Figures 9a-e show an example of resist thickness profile simulation.

The invention although described in detailed explanatory context may be best understood in conjunction with the

accompanying figures.

DETAILED DESCRIPTION OF THE FIGURES

Figures 1-4 have been detailed throughout the description.

Figure 5 shows schematics of applying a resist. Therein a spray nozzle 10 is shown. The spray nozzle is attached to an arm 11. The arm can move freely around a virtual axis. The wafer is rotated around its axis (see arrow 14).

Figure 6a-d shows SEM picture of present litho defined wiring. In fig. 6a a side wall of a chip is shown having four lateral wire bonds. In fig. 6b a side wall of a chip is shown having eight 3D litho defined lateral wires, three of these have a relatively small width, three have a medium width and two have a larger width. In fig. 6c lateral wires are shown between bonds pads forming electrical measurement structures for varying linewidths. The wires are partly interconnected at a left side thereof. Fig. 6d shows a complex wiring scheme connecting several devices in different functional levels, with bonds pads, a large cavity in the left middle section and parts of a cavity in the bottom and top section.

Fig. 7a shows a different layer definition for multi (6) step lithography in a 200 μιη deep cavity, and (b) split mask layers for each imaging step (different colors on the sidewalls indicated with arrows represent 6 focus layers) .

Figures 8a-e show an example of an aerial image simulation.

Light intensity simulated plots over 200 μπι cavity for mask of lines with 10 μπι width and 20 um pitch for, (a) one step exposure focusing at top, (b) focusing at mid-level of sidewall, (c) focusing at bottom, (d) double exposure focusing at both top and bottom, and (d) triple exposure focusing at top, bottom and, mid- level of sidewall. The arrows point to the focal plane positions. In multi-exposure parts, light intensity of more than 2 is clipped and saturated. The light intensity amount is scaled to its nominal value (dose to clear) . To have a better vision over how resist thickness changes over cavity sidewall, sets of SEM cross-section images were taken. The thickness was measured. The cavity depth in this case is 410 μηα. Starting from nominal thickness at the top (x>310 um) , resist thickness suddenly drops to its minimum value at the top edge (x=290 μπι) . This occurs due to flowing the resist from the edge down to the sidewall.

Consequently, top side of the sidewall becomes thicker than the nominal value (the maximum at x=260 μπι) . The thickness gradually drops, until a local peak happens at the bottom corner (x=0 μιτι) . At the bottom plain (x<0 μπι) , the thickness initially drops and then returns to the nominal value of the top plane. Figures 9a-e show an example of resist thickness profile simulation. Resist thickness profile simulated plots over 200 μπι cavity for mask of lines of 10 μπι width/20 μηα pitch for, (a) one step exposure focusing at top, (b) focusing at mid-level of sidewall, (c) focusing at bottom, (d) same structure with double exposure focusing at top and bottom, (d) with triple exposure focusing at top, bottom and mid-level of sidewall.

Claims

1. Process for lithographic defined lateral 3D metal wiring in a package comprising the steps of

providing a chip and a substrate,

providing a passivation layer covering the chip,

providing connection openings in the passivation layer, depositing a metal layer,

providing a resist layer in two or more steps,

patterning the metal layer as a 3D metal wiring on the chip and substrate, preferably using a single mask, using two or more lithography steps each step at a different height, preferably high aspect ratio lithography, and

etching the metal layer.

2. Process according to claim 1, wherein the step of providing a passivation layer is performed by deposition, such as LPCVD, CVD, spray coating, and dip coating.

3. Process according to any of the preceding claims, wherein the tapering layer tapers at least one sidewall, such as wherein the sidewall tapering is provided in an additional step, such as underfill dispensing and polymer spray coating.

4. Process according to claim 3 wherein the passivation layer is formed of an inorganic dielectric, a polymer, a

photoresist, a resin and combinations thereof.

5. Process according to any of the preceding claims, wherein photo resist is applied using at least one of a rotating wafer, a spray nozzle, a spray pressure, a spray rate, a resist volume, and a moving arm attached to a nozzle.

6. Process according to any of the preceding claims, wherein photo resist is applied in three or more steps, such as 5-12 steps .

7. Process according to claim 6, wherein the photo resist is applied in a sequence, the sequence comprising (i) applying the photoresist in multilayers, such as 2-12 multilayers, (ii) heating and/or baking the photoresist multilayers, and repeating steps (i) and (ii) 1-5 times, such as 1-2 times.

8. Process according to any of the preceding claims, wherein a resist exposure dose is varied locally.

9. Process according to any of the preceding claims, wherein a local focus offset is provided.

10. Process according to any of the preceding claims, wherein aerial image calculation is used to determine local lithographic patterning boundary conditions for optimizing a mask design, such as far field diffraction pattern calculation, preferably using Fraunhofer diffraction.

11. Process according to any of the preceding claims, wherein patterning of the metal layers is performed over a height exceeding 100 μιτι, typically exceeding 200 μιη, such as up to 500 μπι.

12. Process according to any of the preceding claims, wherein the chip is placed on the substrate.

13. Process according to any of the preceding claims, wherein patterning of the metal layers is done in a multi-step approach each step at a different height, such as a 3-50 step approach, preferably wherein a height difference between

subsequent steps is from 5-100 μιη.

14. Use of a process according to any of the preceding claims for heterogeneous integration of a chip on a package.

15. Use of a process according to any of the preceding claims for providing an electrical interconnecting wiring between two or more functional levels for a chip on a package.

16. Use of a process according to any of the preceding claims for providing an electrical interconnecting wiring between the front side and backside of a chip.

17. Use of a process according to any of the preceding claims for providing full formation of wiring from a (supporting) substrate to one or more chips.

18. Use of a process according to any of claims 1-13 for a lateral 3D metal wiring for a MEMS, an optical application, an RF application, a high temperature package, a solid state lighting package, or a LED package.

19. Chip or chip in package comprising lithographic defined wiring obtainable by a process according to any of claims 1-13.

20. Product obtainable by a process according to any of claims 1-13.